drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/pkt_sched.h>
  39 #include <linux/ipv6.h>
  40 #include <linux/slab.h>
  41 #include <net/checksum.h>
  42 #include <net/ip6_checksum.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/if_vlan.h>
  45 #include <linux/prefetch.h>
  46 #include <scsi/fc/fc_fcoe.h>
  47
  48 #include "ixgbe.h"
  49 #include "ixgbe_common.h"
  50 #include "ixgbe_dcb_82599.h"
  51 #include "ixgbe_sriov.h"
  52
  53 char ixgbe_driver_name[] = "ixgbe";
  54 static const char ixgbe_driver_string[] =
  55                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  56 #define MAJ 3
  57 #define MIN 3
  58 #define BUILD 8
  59 #define KFIX 2
  60 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  61         __stringify(BUILD) "-k" __stringify(KFIX)
  62 const char ixgbe_driver_version[] = DRV_VERSION;
  63 static const char ixgbe_copyright[] =
  64                                 "Copyright (c) 1999-2011 Intel Corporation.";
  65
  66 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  67         [board_82598] = &ixgbe_82598_info,
  68         [board_82599] = &ixgbe_82599_info,
  69         [board_X540] = &ixgbe_X540_info,
  70 };
  71
  72 /* ixgbe_pci_tbl - PCI Device ID Table
  73  *
  74  * Wildcard entries (PCI_ANY_ID) should come last
  75  * Last entry must be all 0s
  76  *
  77  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  78  *   Class, Class Mask, private data (not used) }
  79  */
  80 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  98          board_82598 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
 100          board_82598 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
 102          board_82598 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
 104          board_82598 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 114          board_82599 },
 115         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 116          board_82599 },
 117         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 118          board_82599 },
 119         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
 120          board_82599 },
 121         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
 122          board_82599 },
 123         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 124          board_82599 },
 125         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 126          board_82599 },
 127         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
 128          board_X540 },
 129         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
 130          board_82599 },
 131         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
 132          board_82599 },
 133
 134         /* required last entry */
 135         {0, }
 136 };
 137 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 138
 139 #ifdef CONFIG_IXGBE_DCA
 140 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 141                             void *p);
 142 static struct notifier_block dca_notifier = {
 143         .notifier_call = ixgbe_notify_dca,
 144         .next          = NULL,
 145         .priority      = 0
 146 };
 147 #endif
 148
 149 #ifdef CONFIG_PCI_IOV
 150 static unsigned int max_vfs;
 151 module_param(max_vfs, uint, 0);
 152 MODULE_PARM_DESC(max_vfs,
 153                  "Maximum number of virtual functions to allocate per physical function");
 154 #endif /* CONFIG_PCI_IOV */
 155
 156 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 157 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 158 MODULE_LICENSE("GPL");
 159 MODULE_VERSION(DRV_VERSION);
 160
 161 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 162
 163 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 164 {
 165         struct ixgbe_hw *hw = &adapter->hw;
 166         u32 gcr;
 167         u32 gpie;
 168         u32 vmdctl;
 169
 170 #ifdef CONFIG_PCI_IOV
 171         /* disable iov and allow time for transactions to clear */
 172         pci_disable_sriov(adapter->pdev);
 173 #endif
 174
 175         /* turn off device IOV mode */
 176         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 177         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 178         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 179         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 180         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 181         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 182
 183         /* set default pool back to 0 */
 184         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 185         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 186         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 187
 188         /* take a breather then clean up driver data */
 189         msleep(100);
 190
 191         kfree(adapter->vfinfo);
 192         adapter->vfinfo = NULL;
 193
 194         adapter->num_vfs = 0;
 195         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 196 }
 197
 198 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 199 {
 200         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 201             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 202                 schedule_work(&adapter->service_task);
 203 }
 204
 205 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 206 {
 207         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 208
 209         /* flush memory to make sure state is correct before next watchog */
 210         smp_mb__before_clear_bit();
 211         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 212 }
 213
 214 struct ixgbe_reg_info {
 215         u32 ofs;
 216         char *name;
 217 };
 218
 219 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 220
 221         /* General Registers */
 222         {IXGBE_CTRL, "CTRL"},
 223         {IXGBE_STATUS, "STATUS"},
 224         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 225
 226         /* Interrupt Registers */
 227         {IXGBE_EICR, "EICR"},
 228
 229         /* RX Registers */
 230         {IXGBE_SRRCTL(0), "SRRCTL"},
 231         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 232         {IXGBE_RDLEN(0), "RDLEN"},
 233         {IXGBE_RDH(0), "RDH"},
 234         {IXGBE_RDT(0), "RDT"},
 235         {IXGBE_RXDCTL(0), "RXDCTL"},
 236         {IXGBE_RDBAL(0), "RDBAL"},
 237         {IXGBE_RDBAH(0), "RDBAH"},
 238
 239         /* TX Registers */
 240         {IXGBE_TDBAL(0), "TDBAL"},
 241         {IXGBE_TDBAH(0), "TDBAH"},
 242         {IXGBE_TDLEN(0), "TDLEN"},
 243         {IXGBE_TDH(0), "TDH"},
 244         {IXGBE_TDT(0), "TDT"},
 245         {IXGBE_TXDCTL(0), "TXDCTL"},
 246
 247         /* List Terminator */
 248         {}
 249 };
 250
 251
 252 /*
 253  * ixgbe_regdump - register printout routine
 254  */
 255 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 256 {
 257         int i = 0, j = 0;
 258         char rname[16];
 259         u32 regs[64];
 260
 261         switch (reginfo->ofs) {
 262         case IXGBE_SRRCTL(0):
 263                 for (i = 0; i < 64; i++)
 264                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 265                 break;
 266         case IXGBE_DCA_RXCTRL(0):
 267                 for (i = 0; i < 64; i++)
 268                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 269                 break;
 270         case IXGBE_RDLEN(0):
 271                 for (i = 0; i < 64; i++)
 272                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 273                 break;
 274         case IXGBE_RDH(0):
 275                 for (i = 0; i < 64; i++)
 276                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 277                 break;
 278         case IXGBE_RDT(0):
 279                 for (i = 0; i < 64; i++)
 280                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 281                 break;
 282         case IXGBE_RXDCTL(0):
 283                 for (i = 0; i < 64; i++)
 284                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 285                 break;
 286         case IXGBE_RDBAL(0):
 287                 for (i = 0; i < 64; i++)
 288                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 289                 break;
 290         case IXGBE_RDBAH(0):
 291                 for (i = 0; i < 64; i++)
 292                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 293                 break;
 294         case IXGBE_TDBAL(0):
 295                 for (i = 0; i < 64; i++)
 296                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 297                 break;
 298         case IXGBE_TDBAH(0):
 299                 for (i = 0; i < 64; i++)
 300                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 301                 break;
 302         case IXGBE_TDLEN(0):
 303                 for (i = 0; i < 64; i++)
 304                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 305                 break;
 306         case IXGBE_TDH(0):
 307                 for (i = 0; i < 64; i++)
 308                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 309                 break;
 310         case IXGBE_TDT(0):
 311                 for (i = 0; i < 64; i++)
 312                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 313                 break;
 314         case IXGBE_TXDCTL(0):
 315                 for (i = 0; i < 64; i++)
 316                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 317                 break;
 318         default:
 319                 pr_info("%-15s %08x\n", reginfo->name,
 320                         IXGBE_READ_REG(hw, reginfo->ofs));
 321                 return;
 322         }
 323
 324         for (i = 0; i < 8; i++) {
 325                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 326                 pr_err("%-15s", rname);
 327                 for (j = 0; j < 8; j++)
 328                         pr_cont(" %08x", regs[i*8+j]);
 329                 pr_cont("\n");
 330         }
 331
 332 }
 333
 334 /*
 335  * ixgbe_dump - Print registers, tx-rings and rx-rings
 336  */
 337 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 338 {
 339         struct net_device *netdev = adapter->netdev;
 340         struct ixgbe_hw *hw = &adapter->hw;
 341         struct ixgbe_reg_info *reginfo;
 342         int n = 0;
 343         struct ixgbe_ring *tx_ring;
 344         struct ixgbe_tx_buffer *tx_buffer_info;
 345         union ixgbe_adv_tx_desc *tx_desc;
 346         struct my_u0 { u64 a; u64 b; } *u0;
 347         struct ixgbe_ring *rx_ring;
 348         union ixgbe_adv_rx_desc *rx_desc;
 349         struct ixgbe_rx_buffer *rx_buffer_info;
 350         u32 staterr;
 351         int i = 0;
 352
 353         if (!netif_msg_hw(adapter))
 354                 return;
 355
 356         /* Print netdevice Info */
 357         if (netdev) {
 358                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 359                 pr_info("Device Name     state            "
 360                         "trans_start      last_rx\n");
 361                 pr_info("%-15s %016lX %016lX %016lX\n",
 362                         netdev->name,
 363                         netdev->state,
 364                         netdev->trans_start,
 365                         netdev->last_rx);
 366         }
 367
 368         /* Print Registers */
 369         dev_info(&adapter->pdev->dev, "Register Dump\n");
 370         pr_info(" Register Name   Value\n");
 371         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 372              reginfo->name; reginfo++) {
 373                 ixgbe_regdump(hw, reginfo);
 374         }
 375
 376         /* Print TX Ring Summary */
 377         if (!netdev || !netif_running(netdev))
 378                 goto exit;
 379
 380         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 381         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 382         for (n = 0; n < adapter->num_tx_queues; n++) {
 383                 tx_ring = adapter->tx_ring[n];
 384                 tx_buffer_info =
 385                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 386                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 387                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 388                            (u64)tx_buffer_info->dma,
 389                            tx_buffer_info->length,
 390                            tx_buffer_info->next_to_watch,
 391                            (u64)tx_buffer_info->time_stamp);
 392         }
 393
 394         /* Print TX Rings */
 395         if (!netif_msg_tx_done(adapter))
 396                 goto rx_ring_summary;
 397
 398         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 399
 400         /* Transmit Descriptor Formats
 401          *
 402          * Advanced Transmit Descriptor
 403          *   +--------------------------------------------------------------+
 404          * 0 |         Buffer Address [63:0]                                |
 405          *   +--------------------------------------------------------------+
 406          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 407          *   +--------------------------------------------------------------+
 408          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 409          */
 410
 411         for (n = 0; n < adapter->num_tx_queues; n++) {
 412                 tx_ring = adapter->tx_ring[n];
 413                 pr_info("------------------------------------\n");
 414                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 415                 pr_info("------------------------------------\n");
 416                 pr_info("T [desc]     [address 63:0  ] "
 417                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 418                         "leng  ntw timestamp        bi->skb\n");
 419
 420                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 421                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 422                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 423                         u0 = (struct my_u0 *)tx_desc;
 424                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 425                                 " %04X  %3X %016llX %p", i,
 426                                 le64_to_cpu(u0->a),
 427                                 le64_to_cpu(u0->b),
 428                                 (u64)tx_buffer_info->dma,
 429                                 tx_buffer_info->length,
 430                                 tx_buffer_info->next_to_watch,
 431                                 (u64)tx_buffer_info->time_stamp,
 432                                 tx_buffer_info->skb);
 433                         if (i == tx_ring->next_to_use &&
 434                                 i == tx_ring->next_to_clean)
 435                                 pr_cont(" NTC/U\n");
 436                         else if (i == tx_ring->next_to_use)
 437                                 pr_cont(" NTU\n");
 438                         else if (i == tx_ring->next_to_clean)
 439                                 pr_cont(" NTC\n");
 440                         else
 441                                 pr_cont("\n");
 442
 443                         if (netif_msg_pktdata(adapter) &&
 444                                 tx_buffer_info->dma != 0)
 445                                 print_hex_dump(KERN_INFO, "",
 446                                         DUMP_PREFIX_ADDRESS, 16, 1,
 447                                         phys_to_virt(tx_buffer_info->dma),
 448                                         tx_buffer_info->length, true);
 449                 }
 450         }
 451
 452         /* Print RX Rings Summary */
 453 rx_ring_summary:
 454         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 455         pr_info("Queue [NTU] [NTC]\n");
 456         for (n = 0; n < adapter->num_rx_queues; n++) {
 457                 rx_ring = adapter->rx_ring[n];
 458                 pr_info("%5d %5X %5X\n",
 459                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 460         }
 461
 462         /* Print RX Rings */
 463         if (!netif_msg_rx_status(adapter))
 464                 goto exit;
 465
 466         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 467
 468         /* Advanced Receive Descriptor (Read) Format
 469          *    63                                           1        0
 470          *    +-----------------------------------------------------+
 471          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 472          *    +----------------------------------------------+------+
 473          *  8 |       Header Buffer Address [63:1]           |  DD  |
 474          *    +-----------------------------------------------------+
 475          *
 476          *
 477          * Advanced Receive Descriptor (Write-Back) Format
 478          *
 479          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 480          *   +------------------------------------------------------+
 481          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 482          *   | Checksum   Ident  |   |           |    | Type | Type |
 483          *   +------------------------------------------------------+
 484          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 485          *   +------------------------------------------------------+
 486          *   63       48 47    32 31            20 19               0
 487          */
 488         for (n = 0; n < adapter->num_rx_queues; n++) {
 489                 rx_ring = adapter->rx_ring[n];
 490                 pr_info("------------------------------------\n");
 491                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 492                 pr_info("------------------------------------\n");
 493                 pr_info("R  [desc]      [ PktBuf     A0] "
 494                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 495                         "<-- Adv Rx Read format\n");
 496                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 497                         "[vl er S cks ln] ---------------- [bi->skb] "
 498                         "<-- Adv Rx Write-Back format\n");
 499
 500                 for (i = 0; i < rx_ring->count; i++) {
 501                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 502                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 503                         u0 = (struct my_u0 *)rx_desc;
 504                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 505                         if (staterr & IXGBE_RXD_STAT_DD) {
 506                                 /* Descriptor Done */
 507                                 pr_info("RWB[0x%03X]     %016llX "
 508                                         "%016llX ---------------- %p", i,
 509                                         le64_to_cpu(u0->a),
 510                                         le64_to_cpu(u0->b),
 511                                         rx_buffer_info->skb);
 512                         } else {
 513                                 pr_info("R  [0x%03X]     %016llX "
 514                                         "%016llX %016llX %p", i,
 515                                         le64_to_cpu(u0->a),
 516                                         le64_to_cpu(u0->b),
 517                                         (u64)rx_buffer_info->dma,
 518                                         rx_buffer_info->skb);
 519
 520                                 if (netif_msg_pktdata(adapter)) {
 521                                         print_hex_dump(KERN_INFO, "",
 522                                            DUMP_PREFIX_ADDRESS, 16, 1,
 523                                            phys_to_virt(rx_buffer_info->dma),
 524                                            rx_ring->rx_buf_len, true);
 525
 526                                         if (rx_ring->rx_buf_len
 527                                                 < IXGBE_RXBUFFER_2048)
 528                                                 print_hex_dump(KERN_INFO, "",
 529                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 530                                                   phys_to_virt(
 531                                                     rx_buffer_info->page_dma +
 532                                                     rx_buffer_info->page_offset
 533                                                   ),
 534                                                   PAGE_SIZE/2, true);
 535                                 }
 536                         }
 537
 538                         if (i == rx_ring->next_to_use)
 539                                 pr_cont(" NTU\n");
 540                         else if (i == rx_ring->next_to_clean)
 541                                 pr_cont(" NTC\n");
 542                         else
 543                                 pr_cont("\n");
 544
 545                 }
 546         }
 547
 548 exit:
 549         return;
 550 }
 551
 552 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 553 {
 554         u32 ctrl_ext;
 555
 556         /* Let firmware take over control of h/w */
 557         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 558         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 559                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 560 }
 561
 562 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 563 {
 564         u32 ctrl_ext;
 565
 566         /* Let firmware know the driver has taken over */
 567         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 568         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 569                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 570 }
 571
 572 /*
 573  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 574  * @adapter: pointer to adapter struct
 575  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 576  * @queue: queue to map the corresponding interrupt to
 577  * @msix_vector: the vector to map to the corresponding queue
 578  *
 579  */
 580 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 581                            u8 queue, u8 msix_vector)
 582 {
 583         u32 ivar, index;
 584         struct ixgbe_hw *hw = &adapter->hw;
 585         switch (hw->mac.type) {
 586         case ixgbe_mac_82598EB:
 587                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 588                 if (direction == -1)
 589                         direction = 0;
 590                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 591                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 592                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 593                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 594                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 595                 break;
 596         case ixgbe_mac_82599EB:
 597         case ixgbe_mac_X540:
 598                 if (direction == -1) {
 599                         /* other causes */
 600                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 601                         index = ((queue & 1) * 8);
 602                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 603                         ivar &= ~(0xFF << index);
 604                         ivar |= (msix_vector << index);
 605                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 606                         break;
 607                 } else {
 608                         /* tx or rx causes */
 609                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 610                         index = ((16 * (queue & 1)) + (8 * direction));
 611                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 612                         ivar &= ~(0xFF << index);
 613                         ivar |= (msix_vector << index);
 614                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 615                         break;
 616                 }
 617         default:
 618                 break;
 619         }
 620 }
 621
 622 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 623                                           u64 qmask)
 624 {
 625         u32 mask;
 626
 627         switch (adapter->hw.mac.type) {
 628         case ixgbe_mac_82598EB:
 629                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 630                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 631                 break;
 632         case ixgbe_mac_82599EB:
 633         case ixgbe_mac_X540:
 634                 mask = (qmask & 0xFFFFFFFF);
 635                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 636                 mask = (qmask >> 32);
 637                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 638                 break;
 639         default:
 640                 break;
 641         }
 642 }
 643
 644 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 645                                       struct ixgbe_tx_buffer *tx_buffer_info)
 646 {
 647         if (tx_buffer_info->dma) {
 648                 if (tx_buffer_info->mapped_as_page)
 649                         dma_unmap_page(tx_ring->dev,
 650                                        tx_buffer_info->dma,
 651                                        tx_buffer_info->length,
 652                                        DMA_TO_DEVICE);
 653                 else
 654                         dma_unmap_single(tx_ring->dev,
 655                                          tx_buffer_info->dma,
 656                                          tx_buffer_info->length,
 657                                          DMA_TO_DEVICE);
 658                 tx_buffer_info->dma = 0;
 659         }
 660         if (tx_buffer_info->skb) {
 661                 dev_kfree_skb_any(tx_buffer_info->skb);
 662                 tx_buffer_info->skb = NULL;
 663         }
 664         tx_buffer_info->time_stamp = 0;
 665         /* tx_buffer_info must be completely set up in the transmit path */
 666 }
 667
 668 /**
 669  * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
 670  * @adapter: driver private struct
 671  * @index: reg idx of queue to query (0-127)
 672  *
 673  * Helper function to determine the traffic index for a particular
 674  * register index.
 675  *
 676  * Returns : a tc index for use in range 0-7, or 0-3
 677  */
 678 static u8 ixgbe_dcb_txq_to_tc(struct ixgbe_adapter *adapter, u8 reg_idx)
 679 {
 680         int tc = -1;
 681         int dcb_i = netdev_get_num_tc(adapter->netdev);
 682
 683         /* if DCB is not enabled the queues have no TC */
 684         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
 685                 return tc;
 686
 687         /* check valid range */
 688         if (reg_idx >= adapter->hw.mac.max_tx_queues)
 689                 return tc;
 690
 691         switch (adapter->hw.mac.type) {
 692         case ixgbe_mac_82598EB:
 693                 tc = reg_idx >> 2;
 694                 break;
 695         default:
 696                 if (dcb_i != 4 && dcb_i != 8)
 697                         break;
 698
 699                 /* if VMDq is enabled the lowest order bits determine TC */
 700                 if (adapter->flags & (IXGBE_FLAG_SRIOV_ENABLED |
 701                                       IXGBE_FLAG_VMDQ_ENABLED)) {
 702                         tc = reg_idx & (dcb_i - 1);
 703                         break;
 704                 }
 705
 706                 /*
 707                  * Convert the reg_idx into the correct TC. This bitmask
 708                  * targets the last full 32 ring traffic class and assigns
 709                  * it a value of 1. From there the rest of the rings are
 710                  * based on shifting the mask further up to include the
 711                  * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
 712                  * will only ever be 8 or 4 and that reg_idx will never
 713                  * be greater then 128. The code without the power of 2
 714                  * optimizations would be:
 715                  * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
 716                  */
 717                 tc = ((reg_idx & 0X1F) + 0x20) * dcb_i;
 718                 tc >>= 9 - (reg_idx >> 5);
 719         }
 720
 721         return tc;
 722 }
 723
 724 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 725 {
 726         struct ixgbe_hw *hw = &adapter->hw;
 727         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 728         u32 data = 0;
 729         u32 xoff[8] = {0};
 730         int i;
 731
 732         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 733             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 734                 switch (hw->mac.type) {
 735                 case ixgbe_mac_82598EB:
 736                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 737                         break;
 738                 default:
 739                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 740                 }
 741                 hwstats->lxoffrxc += data;
 742
 743                 /* refill credits (no tx hang) if we received xoff */
 744                 if (!data)
 745                         return;
 746
 747                 for (i = 0; i < adapter->num_tx_queues; i++)
 748                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 749                                   &adapter->tx_ring[i]->state);
 750                 return;
 751         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 752                 return;
 753
 754         /* update stats for each tc, only valid with PFC enabled */
 755         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 756                 switch (hw->mac.type) {
 757                 case ixgbe_mac_82598EB:
 758                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 759                         break;
 760                 default:
 761                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 762                 }
 763                 hwstats->pxoffrxc[i] += xoff[i];
 764         }
 765
 766         /* disarm tx queues that have received xoff frames */
 767         for (i = 0; i < adapter->num_tx_queues; i++) {
 768                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 769                 u32 tc = ixgbe_dcb_txq_to_tc(adapter, tx_ring->reg_idx);
 770
 771                 if (xoff[tc])
 772                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 773         }
 774 }
 775
 776 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 777 {
 778         return ring->tx_stats.completed;
 779 }
 780
 781 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 782 {
 783         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 784         struct ixgbe_hw *hw = &adapter->hw;
 785
 786         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 787         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 788
 789         if (head != tail)
 790                 return (head < tail) ?
 791                         tail - head : (tail + ring->count - head);
 792
 793         return 0;
 794 }
 795
 796 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 797 {
 798         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 799         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 800         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 801         bool ret = false;
 802
 803         clear_check_for_tx_hang(tx_ring);
 804
 805         /*
 806          * Check for a hung queue, but be thorough. This verifies
 807          * that a transmit has been completed since the previous
 808          * check AND there is at least one packet pending. The
 809          * ARMED bit is set to indicate a potential hang. The
 810          * bit is cleared if a pause frame is received to remove
 811          * false hang detection due to PFC or 802.3x frames. By
 812          * requiring this to fail twice we avoid races with
 813          * pfc clearing the ARMED bit and conditions where we
 814          * run the check_tx_hang logic with a transmit completion
 815          * pending but without time to complete it yet.
 816          */
 817         if ((tx_done_old == tx_done) && tx_pending) {
 818                 /* make sure it is true for two checks in a row */
 819                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 820                                        &tx_ring->state);
 821         } else {
 822                 /* update completed stats and continue */
 823                 tx_ring->tx_stats.tx_done_old = tx_done;
 824                 /* reset the countdown */
 825                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 826         }
 827
 828         return ret;
 829 }
 830
 831 #define IXGBE_MAX_TXD_PWR       14
 832 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 833
 834 /* Tx Descriptors needed, worst case */
 835 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 836                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 837 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 838         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 839
 840 /**
 841  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 842  * @adapter: driver private struct
 843  **/
 844 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 845 {
 846
 847         /* Do the reset outside of interrupt context */
 848         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 849                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 850                 ixgbe_service_event_schedule(adapter);
 851         }
 852 }
 853
 854 /**
 855  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 856  * @q_vector: structure containing interrupt and ring information
 857  * @tx_ring: tx ring to clean
 858  **/
 859 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 860                                struct ixgbe_ring *tx_ring)
 861 {
 862         struct ixgbe_adapter *adapter = q_vector->adapter;
 863         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 864         struct ixgbe_tx_buffer *tx_buffer_info;
 865         unsigned int total_bytes = 0, total_packets = 0;
 866         u16 i, eop, count = 0;
 867
 868         i = tx_ring->next_to_clean;
 869         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 870         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 871
 872         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 873                (count < tx_ring->work_limit)) {
 874                 bool cleaned = false;
 875                 rmb(); /* read buffer_info after eop_desc */
 876                 for ( ; !cleaned; count++) {
 877                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 878                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 879
 880                         tx_desc->wb.status = 0;
 881                         cleaned = (i == eop);
 882
 883                         i++;
 884                         if (i == tx_ring->count)
 885                                 i = 0;
 886
 887                         if (cleaned && tx_buffer_info->skb) {
 888                                 total_bytes += tx_buffer_info->bytecount;
 889                                 total_packets += tx_buffer_info->gso_segs;
 890                         }
 891
 892                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 893                                                          tx_buffer_info);
 894                 }
 895
 896                 tx_ring->tx_stats.completed++;
 897                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 898                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 899         }
 900
 901         tx_ring->next_to_clean = i;
 902         tx_ring->total_bytes += total_bytes;
 903         tx_ring->total_packets += total_packets;
 904         u64_stats_update_begin(&tx_ring->syncp);
 905         tx_ring->stats.packets += total_packets;
 906         tx_ring->stats.bytes += total_bytes;
 907         u64_stats_update_end(&tx_ring->syncp);
 908
 909         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 910                 /* schedule immediate reset if we believe we hung */
 911                 struct ixgbe_hw *hw = &adapter->hw;
 912                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 913                 e_err(drv, "Detected Tx Unit Hang\n"
 914                         "  Tx Queue             <%d>\n"
 915                         "  TDH, TDT             <%x>, <%x>\n"
 916                         "  next_to_use          <%x>\n"
 917                         "  next_to_clean        <%x>\n"
 918                         "tx_buffer_info[next_to_clean]\n"
 919                         "  time_stamp           <%lx>\n"
 920                         "  jiffies              <%lx>\n",
 921                         tx_ring->queue_index,
 922                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 923                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 924                         tx_ring->next_to_use, eop,
 925                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 926
 927                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 928
 929                 e_info(probe,
 930                        "tx hang %d detected on queue %d, resetting adapter\n",
 931                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 932
 933                 /* schedule immediate reset if we believe we hung */
 934                 ixgbe_tx_timeout_reset(adapter);
 935
 936                 /* the adapter is about to reset, no point in enabling stuff */
 937                 return true;
 938         }
 939
 940 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 941         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 942                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 943                 /* Make sure that anybody stopping the queue after this
 944                  * sees the new next_to_clean.
 945                  */
 946                 smp_mb();
 947                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 948                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 949                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 950                         ++tx_ring->tx_stats.restart_queue;
 951                 }
 952         }
 953
 954         return count < tx_ring->work_limit;
 955 }
 956
 957 #ifdef CONFIG_IXGBE_DCA
 958 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 959                                 struct ixgbe_ring *rx_ring,
 960                                 int cpu)
 961 {
 962         struct ixgbe_hw *hw = &adapter->hw;
 963         u32 rxctrl;
 964         u8 reg_idx = rx_ring->reg_idx;
 965
 966         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 967         switch (hw->mac.type) {
 968         case ixgbe_mac_82598EB:
 969                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 970                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 971                 break;
 972         case ixgbe_mac_82599EB:
 973         case ixgbe_mac_X540:
 974                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 975                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 976                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 977                 break;
 978         default:
 979                 break;
 980         }
 981         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 982         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 983         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 984         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 985 }
 986
 987 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 988                                 struct ixgbe_ring *tx_ring,
 989                                 int cpu)
 990 {
 991         struct ixgbe_hw *hw = &adapter->hw;
 992         u32 txctrl;
 993         u8 reg_idx = tx_ring->reg_idx;
 994
 995         switch (hw->mac.type) {
 996         case ixgbe_mac_82598EB:
 997                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 998                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 999                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
1000                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1001                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
1002                 break;
1003         case ixgbe_mac_82599EB:
1004         case ixgbe_mac_X540:
1005                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
1006                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
1007                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
1008                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
1009                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1010                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
1011                 break;
1012         default:
1013                 break;
1014         }
1015 }
1016
1017 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1018 {
1019         struct ixgbe_adapter *adapter = q_vector->adapter;
1020         int cpu = get_cpu();
1021         long r_idx;
1022         int i;
1023
1024         if (q_vector->cpu == cpu)
1025                 goto out_no_update;
1026
1027         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1028         for (i = 0; i < q_vector->txr_count; i++) {
1029                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
1030                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1031                                       r_idx + 1);
1032         }
1033
1034         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1035         for (i = 0; i < q_vector->rxr_count; i++) {
1036                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
1037                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1038                                       r_idx + 1);
1039         }
1040
1041         q_vector->cpu = cpu;
1042 out_no_update:
1043         put_cpu();
1044 }
1045
1046 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1047 {
1048         int num_q_vectors;
1049         int i;
1050
1051         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1052                 return;
1053
1054         /* always use CB2 mode, difference is masked in the CB driver */
1055         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1056
1057         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1058                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1059         else
1060                 num_q_vectors = 1;
1061
1062         for (i = 0; i < num_q_vectors; i++) {
1063                 adapter->q_vector[i]->cpu = -1;
1064                 ixgbe_update_dca(adapter->q_vector[i]);
1065         }
1066 }
1067
1068 static int __ixgbe_notify_dca(struct device *dev, void *data)
1069 {
1070         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1071         unsigned long event = *(unsigned long *)data;
1072
1073         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1074                 return 0;
1075
1076         switch (event) {
1077         case DCA_PROVIDER_ADD:
1078                 /* if we're already enabled, don't do it again */
1079                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1080                         break;
1081                 if (dca_add_requester(dev) == 0) {
1082                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1083                         ixgbe_setup_dca(adapter);
1084                         break;
1085                 }
1086                 /* Fall Through since DCA is disabled. */
1087         case DCA_PROVIDER_REMOVE:
1088                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1089                         dca_remove_requester(dev);
1090                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1091                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1092                 }
1093                 break;
1094         }
1095
1096         return 0;
1097 }
1098 #endif /* CONFIG_IXGBE_DCA */
1099
1100 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1101                                  struct sk_buff *skb)
1102 {
1103         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1104 }
1105
1106 /**
1107  * ixgbe_receive_skb - Send a completed packet up the stack
1108  * @adapter: board private structure
1109  * @skb: packet to send up
1110  * @status: hardware indication of status of receive
1111  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1112  * @rx_desc: rx descriptor
1113  **/
1114 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1115                               struct sk_buff *skb, u8 status,
1116                               struct ixgbe_ring *ring,
1117                               union ixgbe_adv_rx_desc *rx_desc)
1118 {
1119         struct ixgbe_adapter *adapter = q_vector->adapter;
1120         struct napi_struct *napi = &q_vector->napi;
1121         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1122         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1123
1124         if (is_vlan && (tag & VLAN_VID_MASK))
1125                 __vlan_hwaccel_put_tag(skb, tag);
1126
1127         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1128                 napi_gro_receive(napi, skb);
1129         else
1130                 netif_rx(skb);
1131 }
1132
1133 /**
1134  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1135  * @adapter: address of board private structure
1136  * @status_err: hardware indication of status of receive
1137  * @skb: skb currently being received and modified
1138  **/
1139 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1140                                      union ixgbe_adv_rx_desc *rx_desc,
1141                                      struct sk_buff *skb)
1142 {
1143         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1144
1145         skb_checksum_none_assert(skb);
1146
1147         /* Rx csum disabled */
1148         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1149                 return;
1150
1151         /* if IP and error */
1152         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1153             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1154                 adapter->hw_csum_rx_error++;
1155                 return;
1156         }
1157
1158         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1159                 return;
1160
1161         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1162                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1163
1164                 /*
1165                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1166                  * checksum errors.
1167                  */
1168                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1169                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1170                         return;
1171
1172                 adapter->hw_csum_rx_error++;
1173                 return;
1174         }
1175
1176         /* It must be a TCP or UDP packet with a valid checksum */
1177         skb->ip_summed = CHECKSUM_UNNECESSARY;
1178 }
1179
1180 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1181 {
1182         /*
1183          * Force memory writes to complete before letting h/w
1184          * know there are new descriptors to fetch.  (Only
1185          * applicable for weak-ordered memory model archs,
1186          * such as IA-64).
1187          */
1188         wmb();
1189         writel(val, rx_ring->tail);
1190 }
1191
1192 /**
1193  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1194  * @rx_ring: ring to place buffers on
1195  * @cleaned_count: number of buffers to replace
1196  **/
1197 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1198 {
1199         union ixgbe_adv_rx_desc *rx_desc;
1200         struct ixgbe_rx_buffer *bi;
1201         struct sk_buff *skb;
1202         u16 i = rx_ring->next_to_use;
1203
1204         /* do nothing if no valid netdev defined */
1205         if (!rx_ring->netdev)
1206                 return;
1207
1208         while (cleaned_count--) {
1209                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1210                 bi = &rx_ring->rx_buffer_info[i];
1211                 skb = bi->skb;
1212
1213                 if (!skb) {
1214                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1215                                                         rx_ring->rx_buf_len);
1216                         if (!skb) {
1217                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1218                                 goto no_buffers;
1219                         }
1220                         /* initialize queue mapping */
1221                         skb_record_rx_queue(skb, rx_ring->queue_index);
1222                         bi->skb = skb;
1223                 }
1224
1225                 if (!bi->dma) {
1226                         bi->dma = dma_map_single(rx_ring->dev,
1227                                                  skb->data,
1228                                                  rx_ring->rx_buf_len,
1229                                                  DMA_FROM_DEVICE);
1230                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1231                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1232                                 bi->dma = 0;
1233                                 goto no_buffers;
1234                         }
1235                 }
1236
1237                 if (ring_is_ps_enabled(rx_ring)) {
1238                         if (!bi->page) {
1239                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1240                                 if (!bi->page) {
1241                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1242                                         goto no_buffers;
1243                                 }
1244                         }
1245
1246                         if (!bi->page_dma) {
1247                                 /* use a half page if we're re-using */
1248                                 bi->page_offset ^= PAGE_SIZE / 2;
1249                                 bi->page_dma = dma_map_page(rx_ring->dev,
1250                                                             bi->page,
1251                                                             bi->page_offset,
1252                                                             PAGE_SIZE / 2,
1253                                                             DMA_FROM_DEVICE);
1254                                 if (dma_mapping_error(rx_ring->dev,
1255                                                       bi->page_dma)) {
1256                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1257                                         bi->page_dma = 0;
1258                                         goto no_buffers;
1259                                 }
1260                         }
1261
1262                         /* Refresh the desc even if buffer_addrs didn't change
1263                          * because each write-back erases this info. */
1264                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1265                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1266                 } else {
1267                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1268                         rx_desc->read.hdr_addr = 0;
1269                 }
1270
1271                 i++;
1272                 if (i == rx_ring->count)
1273                         i = 0;
1274         }
1275
1276 no_buffers:
1277         if (rx_ring->next_to_use != i) {
1278                 rx_ring->next_to_use = i;
1279                 ixgbe_release_rx_desc(rx_ring, i);
1280         }
1281 }
1282
1283 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1284 {
1285         /* HW will not DMA in data larger than the given buffer, even if it
1286          * parses the (NFS, of course) header to be larger.  In that case, it
1287          * fills the header buffer and spills the rest into the page.
1288          */
1289         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1290         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1291                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1292         if (hlen > IXGBE_RX_HDR_SIZE)
1293                 hlen = IXGBE_RX_HDR_SIZE;
1294         return hlen;
1295 }
1296
1297 /**
1298  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1299  * @skb: pointer to the last skb in the rsc queue
1300  *
1301  * This function changes a queue full of hw rsc buffers into a completed
1302  * packet.  It uses the ->prev pointers to find the first packet and then
1303  * turns it into the frag list owner.
1304  **/
1305 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1306 {
1307         unsigned int frag_list_size = 0;
1308         unsigned int skb_cnt = 1;
1309
1310         while (skb->prev) {
1311                 struct sk_buff *prev = skb->prev;
1312                 frag_list_size += skb->len;
1313                 skb->prev = NULL;
1314                 skb = prev;
1315                 skb_cnt++;
1316         }
1317
1318         skb_shinfo(skb)->frag_list = skb->next;
1319         skb->next = NULL;
1320         skb->len += frag_list_size;
1321         skb->data_len += frag_list_size;
1322         skb->truesize += frag_list_size;
1323         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1324
1325         return skb;
1326 }
1327
1328 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1329 {
1330         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1331                 IXGBE_RXDADV_RSCCNT_MASK);
1332 }
1333
1334 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1335                                struct ixgbe_ring *rx_ring,
1336                                int *work_done, int work_to_do)
1337 {
1338         struct ixgbe_adapter *adapter = q_vector->adapter;
1339         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1340         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1341         struct sk_buff *skb;
1342         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1343         const int current_node = numa_node_id();
1344 #ifdef IXGBE_FCOE
1345         int ddp_bytes = 0;
1346 #endif /* IXGBE_FCOE */
1347         u32 staterr;
1348         u16 i;
1349         u16 cleaned_count = 0;
1350         bool pkt_is_rsc = false;
1351
1352         i = rx_ring->next_to_clean;
1353         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1354         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1355
1356         while (staterr & IXGBE_RXD_STAT_DD) {
1357                 u32 upper_len = 0;
1358
1359                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1360
1361                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1362
1363                 skb = rx_buffer_info->skb;
1364                 rx_buffer_info->skb = NULL;
1365                 prefetch(skb->data);
1366
1367                 if (ring_is_rsc_enabled(rx_ring))
1368                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1369
1370                 /* if this is a skb from previous receive DMA will be 0 */
1371                 if (rx_buffer_info->dma) {
1372                         u16 hlen;
1373                         if (pkt_is_rsc &&
1374                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1375                             !skb->prev) {
1376                                 /*
1377                                  * When HWRSC is enabled, delay unmapping
1378                                  * of the first packet. It carries the
1379                                  * header information, HW may still
1380                                  * access the header after the writeback.
1381                                  * Only unmap it when EOP is reached
1382                                  */
1383                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1384                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1385                         } else {
1386                                 dma_unmap_single(rx_ring->dev,
1387                                                  rx_buffer_info->dma,
1388                                                  rx_ring->rx_buf_len,
1389                                                  DMA_FROM_DEVICE);
1390                         }
1391                         rx_buffer_info->dma = 0;
1392
1393                         if (ring_is_ps_enabled(rx_ring)) {
1394                                 hlen = ixgbe_get_hlen(rx_desc);
1395                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1396                         } else {
1397                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1398                         }
1399
1400                         skb_put(skb, hlen);
1401                 } else {
1402                         /* assume packet split since header is unmapped */
1403                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1404                 }
1405
1406                 if (upper_len) {
1407                         dma_unmap_page(rx_ring->dev,
1408                                        rx_buffer_info->page_dma,
1409                                        PAGE_SIZE / 2,
1410                                        DMA_FROM_DEVICE);
1411                         rx_buffer_info->page_dma = 0;
1412                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1413                                            rx_buffer_info->page,
1414                                            rx_buffer_info->page_offset,
1415                                            upper_len);
1416
1417                         if ((page_count(rx_buffer_info->page) == 1) &&
1418                             (page_to_nid(rx_buffer_info->page) == current_node))
1419                                 get_page(rx_buffer_info->page);
1420                         else
1421                                 rx_buffer_info->page = NULL;
1422
1423                         skb->len += upper_len;
1424                         skb->data_len += upper_len;
1425                         skb->truesize += upper_len;
1426                 }
1427
1428                 i++;
1429                 if (i == rx_ring->count)
1430                         i = 0;
1431
1432                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1433                 prefetch(next_rxd);
1434                 cleaned_count++;
1435
1436                 if (pkt_is_rsc) {
1437                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1438                                      IXGBE_RXDADV_NEXTP_SHIFT;
1439                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1440                 } else {
1441                         next_buffer = &rx_ring->rx_buffer_info[i];
1442                 }
1443
1444                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1445                         if (ring_is_ps_enabled(rx_ring)) {
1446                                 rx_buffer_info->skb = next_buffer->skb;
1447                                 rx_buffer_info->dma = next_buffer->dma;
1448                                 next_buffer->skb = skb;
1449                                 next_buffer->dma = 0;
1450                         } else {
1451                                 skb->next = next_buffer->skb;
1452                                 skb->next->prev = skb;
1453                         }
1454                         rx_ring->rx_stats.non_eop_descs++;
1455                         goto next_desc;
1456                 }
1457
1458                 if (skb->prev) {
1459                         skb = ixgbe_transform_rsc_queue(skb);
1460                         /* if we got here without RSC the packet is invalid */
1461                         if (!pkt_is_rsc) {
1462                                 __pskb_trim(skb, 0);
1463                                 rx_buffer_info->skb = skb;
1464                                 goto next_desc;
1465                         }
1466                 }
1467
1468                 if (ring_is_rsc_enabled(rx_ring)) {
1469                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1470                                 dma_unmap_single(rx_ring->dev,
1471                                                  IXGBE_RSC_CB(skb)->dma,
1472                                                  rx_ring->rx_buf_len,
1473                                                  DMA_FROM_DEVICE);
1474                                 IXGBE_RSC_CB(skb)->dma = 0;
1475                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1476                         }
1477                 }
1478                 if (pkt_is_rsc) {
1479                         if (ring_is_ps_enabled(rx_ring))
1480                                 rx_ring->rx_stats.rsc_count +=
1481                                         skb_shinfo(skb)->nr_frags;
1482                         else
1483                                 rx_ring->rx_stats.rsc_count +=
1484                                         IXGBE_RSC_CB(skb)->skb_cnt;
1485                         rx_ring->rx_stats.rsc_flush++;
1486                 }
1487
1488                 /* ERR_MASK will only have valid bits if EOP set */
1489                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1490                         /* trim packet back to size 0 and recycle it */
1491                         __pskb_trim(skb, 0);
1492                         rx_buffer_info->skb = skb;
1493                         goto next_desc;
1494                 }
1495
1496                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1497                 if (adapter->netdev->features & NETIF_F_RXHASH)
1498                         ixgbe_rx_hash(rx_desc, skb);
1499
1500                 /* probably a little skewed due to removing CRC */
1501                 total_rx_bytes += skb->len;
1502                 total_rx_packets++;
1503
1504                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1505 #ifdef IXGBE_FCOE
1506                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1507                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1508                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1509                         if (!ddp_bytes)
1510                                 goto next_desc;
1511                 }
1512 #endif /* IXGBE_FCOE */
1513                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1514
1515 next_desc:
1516                 rx_desc->wb.upper.status_error = 0;
1517
1518                 (*work_done)++;
1519                 if (*work_done >= work_to_do)
1520                         break;
1521
1522                 /* return some buffers to hardware, one at a time is too slow */
1523                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1524                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1525                         cleaned_count = 0;
1526                 }
1527
1528                 /* use prefetched values */
1529                 rx_desc = next_rxd;
1530                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1531         }
1532
1533         rx_ring->next_to_clean = i;
1534         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1535
1536         if (cleaned_count)
1537                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1538
1539 #ifdef IXGBE_FCOE
1540         /* include DDPed FCoE data */
1541         if (ddp_bytes > 0) {
1542                 unsigned int mss;
1543
1544                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1545                         sizeof(struct fc_frame_header) -
1546                         sizeof(struct fcoe_crc_eof);
1547                 if (mss > 512)
1548                         mss &= ~511;
1549                 total_rx_bytes += ddp_bytes;
1550                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1551         }
1552 #endif /* IXGBE_FCOE */
1553
1554         rx_ring->total_packets += total_rx_packets;
1555         rx_ring->total_bytes += total_rx_bytes;
1556         u64_stats_update_begin(&rx_ring->syncp);
1557         rx_ring->stats.packets += total_rx_packets;
1558         rx_ring->stats.bytes += total_rx_bytes;
1559         u64_stats_update_end(&rx_ring->syncp);
1560 }
1561
1562 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1563 /**
1564  * ixgbe_configure_msix - Configure MSI-X hardware
1565  * @adapter: board private structure
1566  *
1567  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1568  * interrupts.
1569  **/
1570 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1571 {
1572         struct ixgbe_q_vector *q_vector;
1573         int i, q_vectors, v_idx, r_idx;
1574         u32 mask;
1575
1576         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1577
1578         /*
1579          * Populate the IVAR table and set the ITR values to the
1580          * corresponding register.
1581          */
1582         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1583                 q_vector = adapter->q_vector[v_idx];
1584                 /* XXX for_each_set_bit(...) */
1585                 r_idx = find_first_bit(q_vector->rxr_idx,
1586                                        adapter->num_rx_queues);
1587
1588                 for (i = 0; i < q_vector->rxr_count; i++) {
1589                         u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1590                         ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1591                         r_idx = find_next_bit(q_vector->rxr_idx,
1592                                               adapter->num_rx_queues,
1593                                               r_idx + 1);
1594                 }
1595                 r_idx = find_first_bit(q_vector->txr_idx,
1596                                        adapter->num_tx_queues);
1597
1598                 for (i = 0; i < q_vector->txr_count; i++) {
1599                         u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1600                         ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1601                         r_idx = find_next_bit(q_vector->txr_idx,
1602                                               adapter->num_tx_queues,
1603                                               r_idx + 1);
1604                 }
1605
1606                 if (q_vector->txr_count && !q_vector->rxr_count)
1607                         /* tx only */
1608                         q_vector->eitr = adapter->tx_eitr_param;
1609                 else if (q_vector->rxr_count)
1610                         /* rx or mixed */
1611                         q_vector->eitr = adapter->rx_eitr_param;
1612
1613                 ixgbe_write_eitr(q_vector);
1614                 /* If Flow Director is enabled, set interrupt affinity */
1615                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1616                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1617                         /*
1618                          * Allocate the affinity_hint cpumask, assign the mask
1619                          * for this vector, and set our affinity_hint for
1620                          * this irq.
1621                          */
1622                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1623                                                GFP_KERNEL))
1624                                 return;
1625                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1626                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1627                                               q_vector->affinity_mask);
1628                 }
1629         }
1630
1631         switch (adapter->hw.mac.type) {
1632         case ixgbe_mac_82598EB:
1633                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1634                                v_idx);
1635                 break;
1636         case ixgbe_mac_82599EB:
1637         case ixgbe_mac_X540:
1638                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1639                 break;
1640
1641         default:
1642                 break;
1643         }
1644         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1645
1646         /* set up to autoclear timer, and the vectors */
1647         mask = IXGBE_EIMS_ENABLE_MASK;
1648         if (adapter->num_vfs)
1649                 mask &= ~(IXGBE_EIMS_OTHER |
1650                           IXGBE_EIMS_MAILBOX |
1651                           IXGBE_EIMS_LSC);
1652         else
1653                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1654         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1655 }
1656
1657 enum latency_range {
1658         lowest_latency = 0,
1659         low_latency = 1,
1660         bulk_latency = 2,
1661         latency_invalid = 255
1662 };
1663
1664 /**
1665  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1666  * @adapter: pointer to adapter
1667  * @eitr: eitr setting (ints per sec) to give last timeslice
1668  * @itr_setting: current throttle rate in ints/second
1669  * @packets: the number of packets during this measurement interval
1670  * @bytes: the number of bytes during this measurement interval
1671  *
1672  *      Stores a new ITR value based on packets and byte
1673  *      counts during the last interrupt.  The advantage of per interrupt
1674  *      computation is faster updates and more accurate ITR for the current
1675  *      traffic pattern.  Constants in this function were computed
1676  *      based on theoretical maximum wire speed and thresholds were set based
1677  *      on testing data as well as attempting to minimize response time
1678  *      while increasing bulk throughput.
1679  *      this functionality is controlled by the InterruptThrottleRate module
1680  *      parameter (see ixgbe_param.c)
1681  **/
1682 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1683                            u32 eitr, u8 itr_setting,
1684                            int packets, int bytes)
1685 {
1686         unsigned int retval = itr_setting;
1687         u32 timepassed_us;
1688         u64 bytes_perint;
1689
1690         if (packets == 0)
1691                 goto update_itr_done;
1692
1693
1694         /* simple throttlerate management
1695          *    0-20MB/s lowest (100000 ints/s)
1696          *   20-100MB/s low   (20000 ints/s)
1697          *  100-1249MB/s bulk (8000 ints/s)
1698          */
1699         /* what was last interrupt timeslice? */
1700         timepassed_us = 1000000/eitr;
1701         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1702
1703         switch (itr_setting) {
1704         case lowest_latency:
1705                 if (bytes_perint > adapter->eitr_low)
1706                         retval = low_latency;
1707                 break;
1708         case low_latency:
1709                 if (bytes_perint > adapter->eitr_high)
1710                         retval = bulk_latency;
1711                 else if (bytes_perint <= adapter->eitr_low)
1712                         retval = lowest_latency;
1713                 break;
1714         case bulk_latency:
1715                 if (bytes_perint <= adapter->eitr_high)
1716                         retval = low_latency;
1717                 break;
1718         }
1719
1720 update_itr_done:
1721         return retval;
1722 }
1723
1724 /**
1725  * ixgbe_write_eitr - write EITR register in hardware specific way
1726  * @q_vector: structure containing interrupt and ring information
1727  *
1728  * This function is made to be called by ethtool and by the driver
1729  * when it needs to update EITR registers at runtime.  Hardware
1730  * specific quirks/differences are taken care of here.
1731  */
1732 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1733 {
1734         struct ixgbe_adapter *adapter = q_vector->adapter;
1735         struct ixgbe_hw *hw = &adapter->hw;
1736         int v_idx = q_vector->v_idx;
1737         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1738
1739         switch (adapter->hw.mac.type) {
1740         case ixgbe_mac_82598EB:
1741                 /* must write high and low 16 bits to reset counter */
1742                 itr_reg |= (itr_reg << 16);
1743                 break;
1744         case ixgbe_mac_82599EB:
1745         case ixgbe_mac_X540:
1746                 /*
1747                  * 82599 and X540 can support a value of zero, so allow it for
1748                  * max interrupt rate, but there is an errata where it can
1749                  * not be zero with RSC
1750                  */
1751                 if (itr_reg == 8 &&
1752                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1753                         itr_reg = 0;
1754
1755                 /*
1756                  * set the WDIS bit to not clear the timer bits and cause an
1757                  * immediate assertion of the interrupt
1758                  */
1759                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1760                 break;
1761         default:
1762                 break;
1763         }
1764         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1765 }
1766
1767 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1768 {
1769         struct ixgbe_adapter *adapter = q_vector->adapter;
1770         int i, r_idx;
1771         u32 new_itr;
1772         u8 current_itr, ret_itr;
1773
1774         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1775         for (i = 0; i < q_vector->txr_count; i++) {
1776                 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1777                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1778                                            q_vector->tx_itr,
1779                                            tx_ring->total_packets,
1780                                            tx_ring->total_bytes);
1781                 /* if the result for this queue would decrease interrupt
1782                  * rate for this vector then use that result */
1783                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1784                                     q_vector->tx_itr - 1 : ret_itr);
1785                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1786                                       r_idx + 1);
1787         }
1788
1789         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1790         for (i = 0; i < q_vector->rxr_count; i++) {
1791                 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1792                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1793                                            q_vector->rx_itr,
1794                                            rx_ring->total_packets,
1795                                            rx_ring->total_bytes);
1796                 /* if the result for this queue would decrease interrupt
1797                  * rate for this vector then use that result */
1798                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1799                                     q_vector->rx_itr - 1 : ret_itr);
1800                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1801                                       r_idx + 1);
1802         }
1803
1804         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1805
1806         switch (current_itr) {
1807         /* counts and packets in update_itr are dependent on these numbers */
1808         case lowest_latency:
1809                 new_itr = 100000;
1810                 break;
1811         case low_latency:
1812                 new_itr = 20000; /* aka hwitr = ~200 */
1813                 break;
1814         case bulk_latency:
1815         default:
1816                 new_itr = 8000;
1817                 break;
1818         }
1819
1820         if (new_itr != q_vector->eitr) {
1821                 /* do an exponential smoothing */
1822                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1823
1824                 /* save the algorithm value here, not the smoothed one */
1825                 q_vector->eitr = new_itr;
1826
1827                 ixgbe_write_eitr(q_vector);
1828         }
1829 }
1830
1831 /**
1832  * ixgbe_check_overtemp_subtask - check for over tempurature
1833  * @adapter: pointer to adapter
1834  **/
1835 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1836 {
1837         struct ixgbe_hw *hw = &adapter->hw;
1838         u32 eicr = adapter->interrupt_event;
1839
1840         if (test_bit(__IXGBE_DOWN, &adapter->state))
1841                 return;
1842
1843         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1844             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1845                 return;
1846
1847         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1848
1849         switch (hw->device_id) {
1850         case IXGBE_DEV_ID_82599_T3_LOM:
1851                 /*
1852                  * Since the warning interrupt is for both ports
1853                  * we don't have to check if:
1854                  *  - This interrupt wasn't for our port.
1855                  *  - We may have missed the interrupt so always have to
1856                  *    check if we  got a LSC
1857                  */
1858                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1859                     !(eicr & IXGBE_EICR_LSC))
1860                         return;
1861
1862                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1863                         u32 autoneg;
1864                         bool link_up = false;
1865
1866                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1867
1868                         if (link_up)
1869                                 return;
1870                 }
1871
1872                 /* Check if this is not due to overtemp */
1873                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1874                         return;
1875
1876                 break;
1877         default:
1878                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1879                         return;
1880                 break;
1881         }
1882         e_crit(drv,
1883                "Network adapter has been stopped because it has over heated. "
1884                "Restart the computer. If the problem persists, "
1885                "power off the system and replace the adapter\n");
1886
1887         adapter->interrupt_event = 0;
1888 }
1889
1890 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1891 {
1892         struct ixgbe_hw *hw = &adapter->hw;
1893
1894         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1895             (eicr & IXGBE_EICR_GPI_SDP1)) {
1896                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1897                 /* write to clear the interrupt */
1898                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1899         }
1900 }
1901
1902 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1903 {
1904         struct ixgbe_hw *hw = &adapter->hw;
1905
1906         if (eicr & IXGBE_EICR_GPI_SDP2) {
1907                 /* Clear the interrupt */
1908                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1909                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1910                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1911                         ixgbe_service_event_schedule(adapter);
1912                 }
1913         }
1914
1915         if (eicr & IXGBE_EICR_GPI_SDP1) {
1916                 /* Clear the interrupt */
1917                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1918                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1919                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1920                         ixgbe_service_event_schedule(adapter);
1921                 }
1922         }
1923 }
1924
1925 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1926 {
1927         struct ixgbe_hw *hw = &adapter->hw;
1928
1929         adapter->lsc_int++;
1930         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1931         adapter->link_check_timeout = jiffies;
1932         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1933                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1934                 IXGBE_WRITE_FLUSH(hw);
1935                 ixgbe_service_event_schedule(adapter);
1936         }
1937 }
1938
1939 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1940 {
1941         struct net_device *netdev = data;
1942         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1943         struct ixgbe_hw *hw = &adapter->hw;
1944         u32 eicr;
1945
1946         /*
1947          * Workaround for Silicon errata.  Use clear-by-write instead
1948          * of clear-by-read.  Reading with EICS will return the
1949          * interrupt causes without clearing, which later be done
1950          * with the write to EICR.
1951          */
1952         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1953         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1954
1955         if (eicr & IXGBE_EICR_LSC)
1956                 ixgbe_check_lsc(adapter);
1957
1958         if (eicr & IXGBE_EICR_MAILBOX)
1959                 ixgbe_msg_task(adapter);
1960
1961         switch (hw->mac.type) {
1962         case ixgbe_mac_82599EB:
1963         case ixgbe_mac_X540:
1964                 /* Handle Flow Director Full threshold interrupt */
1965                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1966                         int reinit_count = 0;
1967                         int i;
1968                         for (i = 0; i < adapter->num_tx_queues; i++) {
1969                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
1970                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1971                                                        &ring->state))
1972                                         reinit_count++;
1973                         }
1974                         if (reinit_count) {
1975                                 /* no more flow director interrupts until after init */
1976                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1977                                 eicr &= ~IXGBE_EICR_FLOW_DIR;
1978                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1979                                 ixgbe_service_event_schedule(adapter);
1980                         }
1981                 }
1982                 ixgbe_check_sfp_event(adapter, eicr);
1983                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1984                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1985                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1986                                 adapter->interrupt_event = eicr;
1987                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1988                                 ixgbe_service_event_schedule(adapter);
1989                         }
1990                 }
1991                 break;
1992         default:
1993                 break;
1994         }
1995
1996         ixgbe_check_fan_failure(adapter, eicr);
1997
1998         /* re-enable the original interrupt state, no lsc, no queues */
1999         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2000                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
2001                                 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
2002
2003         return IRQ_HANDLED;
2004 }
2005
2006 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2007                                            u64 qmask)
2008 {
2009         u32 mask;
2010         struct ixgbe_hw *hw = &adapter->hw;
2011
2012         switch (hw->mac.type) {
2013         case ixgbe_mac_82598EB:
2014                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2015                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2016                 break;
2017         case ixgbe_mac_82599EB:
2018         case ixgbe_mac_X540:
2019                 mask = (qmask & 0xFFFFFFFF);
2020                 if (mask)
2021                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2022                 mask = (qmask >> 32);
2023                 if (mask)
2024                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2025                 break;
2026         default:
2027                 break;
2028         }
2029         /* skip the flush */
2030 }
2031
2032 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
2033                                             u64 qmask)
2034 {
2035         u32 mask;
2036         struct ixgbe_hw *hw = &adapter->hw;
2037
2038         switch (hw->mac.type) {
2039         case ixgbe_mac_82598EB:
2040                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2041                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2042                 break;
2043         case ixgbe_mac_82599EB:
2044         case ixgbe_mac_X540:
2045                 mask = (qmask & 0xFFFFFFFF);
2046                 if (mask)
2047                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
2048                 mask = (qmask >> 32);
2049                 if (mask)
2050                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2051                 break;
2052         default:
2053                 break;
2054         }
2055         /* skip the flush */
2056 }
2057
2058 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
2059 {
2060         struct ixgbe_q_vector *q_vector = data;
2061         struct ixgbe_adapter  *adapter = q_vector->adapter;
2062         struct ixgbe_ring     *tx_ring;
2063         int i, r_idx;
2064
2065         if (!q_vector->txr_count)
2066                 return IRQ_HANDLED;
2067
2068         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2069         for (i = 0; i < q_vector->txr_count; i++) {
2070                 tx_ring = adapter->tx_ring[r_idx];
2071                 tx_ring->total_bytes = 0;
2072                 tx_ring->total_packets = 0;
2073                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2074                                       r_idx + 1);
2075         }
2076
2077         /* EIAM disabled interrupts (on this vector) for us */
2078         napi_schedule(&q_vector->napi);
2079
2080         return IRQ_HANDLED;
2081 }
2082
2083 /**
2084  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2085  * @irq: unused
2086  * @data: pointer to our q_vector struct for this interrupt vector
2087  **/
2088 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2089 {
2090         struct ixgbe_q_vector *q_vector = data;
2091         struct ixgbe_adapter  *adapter = q_vector->adapter;
2092         struct ixgbe_ring  *rx_ring;
2093         int r_idx;
2094         int i;
2095
2096 #ifdef CONFIG_IXGBE_DCA
2097         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2098                 ixgbe_update_dca(q_vector);
2099 #endif
2100
2101         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2102         for (i = 0; i < q_vector->rxr_count; i++) {
2103                 rx_ring = adapter->rx_ring[r_idx];
2104                 rx_ring->total_bytes = 0;
2105                 rx_ring->total_packets = 0;
2106                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2107                                       r_idx + 1);
2108         }
2109
2110         if (!q_vector->rxr_count)
2111                 return IRQ_HANDLED;
2112
2113         /* EIAM disabled interrupts (on this vector) for us */
2114         napi_schedule(&q_vector->napi);
2115
2116         return IRQ_HANDLED;
2117 }
2118
2119 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2120 {
2121         struct ixgbe_q_vector *q_vector = data;
2122         struct ixgbe_adapter  *adapter = q_vector->adapter;
2123         struct ixgbe_ring  *ring;
2124         int r_idx;
2125         int i;
2126
2127         if (!q_vector->txr_count && !q_vector->rxr_count)
2128                 return IRQ_HANDLED;
2129
2130         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2131         for (i = 0; i < q_vector->txr_count; i++) {
2132                 ring = adapter->tx_ring[r_idx];
2133                 ring->total_bytes = 0;
2134                 ring->total_packets = 0;
2135                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2136                                       r_idx + 1);
2137         }
2138
2139         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2140         for (i = 0; i < q_vector->rxr_count; i++) {
2141                 ring = adapter->rx_ring[r_idx];
2142                 ring->total_bytes = 0;
2143                 ring->total_packets = 0;
2144                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2145                                       r_idx + 1);
2146         }
2147
2148         /* EIAM disabled interrupts (on this vector) for us */
2149         napi_schedule(&q_vector->napi);
2150
2151         return IRQ_HANDLED;
2152 }
2153
2154 /**
2155  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2156  * @napi: napi struct with our devices info in it
2157  * @budget: amount of work driver is allowed to do this pass, in packets
2158  *
2159  * This function is optimized for cleaning one queue only on a single
2160  * q_vector!!!
2161  **/
2162 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2163 {
2164         struct ixgbe_q_vector *q_vector =
2165                                container_of(napi, struct ixgbe_q_vector, napi);
2166         struct ixgbe_adapter *adapter = q_vector->adapter;
2167         struct ixgbe_ring *rx_ring = NULL;
2168         int work_done = 0;
2169         long r_idx;
2170
2171 #ifdef CONFIG_IXGBE_DCA
2172         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2173                 ixgbe_update_dca(q_vector);
2174 #endif
2175
2176         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2177         rx_ring = adapter->rx_ring[r_idx];
2178
2179         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2180
2181         /* If all Rx work done, exit the polling mode */
2182         if (work_done < budget) {
2183                 napi_complete(napi);
2184                 if (adapter->rx_itr_setting & 1)
2185                         ixgbe_set_itr_msix(q_vector);
2186                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2187                         ixgbe_irq_enable_queues(adapter,
2188                                                 ((u64)1 << q_vector->v_idx));
2189         }
2190
2191         return work_done;
2192 }
2193
2194 /**
2195  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2196  * @napi: napi struct with our devices info in it
2197  * @budget: amount of work driver is allowed to do this pass, in packets
2198  *
2199  * This function will clean more than one rx queue associated with a
2200  * q_vector.
2201  **/
2202 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2203 {
2204         struct ixgbe_q_vector *q_vector =
2205                                container_of(napi, struct ixgbe_q_vector, napi);
2206         struct ixgbe_adapter *adapter = q_vector->adapter;
2207         struct ixgbe_ring *ring = NULL;
2208         int work_done = 0, i;
2209         long r_idx;
2210         bool tx_clean_complete = true;
2211
2212 #ifdef CONFIG_IXGBE_DCA
2213         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2214                 ixgbe_update_dca(q_vector);
2215 #endif
2216
2217         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2218         for (i = 0; i < q_vector->txr_count; i++) {
2219                 ring = adapter->tx_ring[r_idx];
2220                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2221                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2222                                       r_idx + 1);
2223         }
2224
2225         /* attempt to distribute budget to each queue fairly, but don't allow
2226          * the budget to go below 1 because we'll exit polling */
2227         budget /= (q_vector->rxr_count ?: 1);
2228         budget = max(budget, 1);
2229         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2230         for (i = 0; i < q_vector->rxr_count; i++) {
2231                 ring = adapter->rx_ring[r_idx];
2232                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2233                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2234                                       r_idx + 1);
2235         }
2236
2237         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2238         ring = adapter->rx_ring[r_idx];
2239         /* If all Rx work done, exit the polling mode */
2240         if (work_done < budget) {
2241                 napi_complete(napi);
2242                 if (adapter->rx_itr_setting & 1)
2243                         ixgbe_set_itr_msix(q_vector);
2244                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2245                         ixgbe_irq_enable_queues(adapter,
2246                                                 ((u64)1 << q_vector->v_idx));
2247                 return 0;
2248         }
2249
2250         return work_done;
2251 }
2252
2253 /**
2254  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2255  * @napi: napi struct with our devices info in it
2256  * @budget: amount of work driver is allowed to do this pass, in packets
2257  *
2258  * This function is optimized for cleaning one queue only on a single
2259  * q_vector!!!
2260  **/
2261 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2262 {
2263         struct ixgbe_q_vector *q_vector =
2264                                container_of(napi, struct ixgbe_q_vector, napi);
2265         struct ixgbe_adapter *adapter = q_vector->adapter;
2266         struct ixgbe_ring *tx_ring = NULL;
2267         int work_done = 0;
2268         long r_idx;
2269
2270 #ifdef CONFIG_IXGBE_DCA
2271         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2272                 ixgbe_update_dca(q_vector);
2273 #endif
2274
2275         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2276         tx_ring = adapter->tx_ring[r_idx];
2277
2278         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2279                 work_done = budget;
2280
2281         /* If all Tx work done, exit the polling mode */
2282         if (work_done < budget) {
2283                 napi_complete(napi);
2284                 if (adapter->tx_itr_setting & 1)
2285                         ixgbe_set_itr_msix(q_vector);
2286                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2287                         ixgbe_irq_enable_queues(adapter,
2288                                                 ((u64)1 << q_vector->v_idx));
2289         }
2290
2291         return work_done;
2292 }
2293
2294 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2295                                      int r_idx)
2296 {
2297         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2298         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2299
2300         set_bit(r_idx, q_vector->rxr_idx);
2301         q_vector->rxr_count++;
2302         rx_ring->q_vector = q_vector;
2303 }
2304
2305 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2306                                      int t_idx)
2307 {
2308         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2309         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2310
2311         set_bit(t_idx, q_vector->txr_idx);
2312         q_vector->txr_count++;
2313         tx_ring->q_vector = q_vector;
2314 }
2315
2316 /**
2317  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2318  * @adapter: board private structure to initialize
2319  *
2320  * This function maps descriptor rings to the queue-specific vectors
2321  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2322  * one vector per ring/queue, but on a constrained vector budget, we
2323  * group the rings as "efficiently" as possible.  You would add new
2324  * mapping configurations in here.
2325  **/
2326 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2327 {
2328         int q_vectors;
2329         int v_start = 0;
2330         int rxr_idx = 0, txr_idx = 0;
2331         int rxr_remaining = adapter->num_rx_queues;
2332         int txr_remaining = adapter->num_tx_queues;
2333         int i, j;
2334         int rqpv, tqpv;
2335         int err = 0;
2336
2337         /* No mapping required if MSI-X is disabled. */
2338         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2339                 goto out;
2340
2341         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2342
2343         /*
2344          * The ideal configuration...
2345          * We have enough vectors to map one per queue.
2346          */
2347         if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2348                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2349                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2350
2351                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2352                         map_vector_to_txq(adapter, v_start, txr_idx);
2353
2354                 goto out;
2355         }
2356
2357         /*
2358          * If we don't have enough vectors for a 1-to-1
2359          * mapping, we'll have to group them so there are
2360          * multiple queues per vector.
2361          */
2362         /* Re-adjusting *qpv takes care of the remainder. */
2363         for (i = v_start; i < q_vectors; i++) {
2364                 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2365                 for (j = 0; j < rqpv; j++) {
2366                         map_vector_to_rxq(adapter, i, rxr_idx);
2367                         rxr_idx++;
2368                         rxr_remaining--;
2369                 }
2370                 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2371                 for (j = 0; j < tqpv; j++) {
2372                         map_vector_to_txq(adapter, i, txr_idx);
2373                         txr_idx++;
2374                         txr_remaining--;
2375                 }
2376         }
2377 out:
2378         return err;
2379 }
2380
2381 /**
2382  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2383  * @adapter: board private structure
2384  *
2385  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2386  * interrupts from the kernel.
2387  **/
2388 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2389 {
2390         struct net_device *netdev = adapter->netdev;
2391         irqreturn_t (*handler)(int, void *);
2392         int i, vector, q_vectors, err;
2393         int ri = 0, ti = 0;
2394
2395         /* Decrement for Other and TCP Timer vectors */
2396         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2397
2398         err = ixgbe_map_rings_to_vectors(adapter);
2399         if (err)
2400                 return err;
2401
2402 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count)        \
2403                                           ? &ixgbe_msix_clean_many : \
2404                           (_v)->rxr_count ? &ixgbe_msix_clean_rx   : \
2405                           (_v)->txr_count ? &ixgbe_msix_clean_tx   : \
2406                           NULL)
2407         for (vector = 0; vector < q_vectors; vector++) {
2408                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2409                 handler = SET_HANDLER(q_vector);
2410
2411                 if (handler == &ixgbe_msix_clean_rx) {
2412                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2413                                  "%s-%s-%d", netdev->name, "rx", ri++);
2414                 } else if (handler == &ixgbe_msix_clean_tx) {
2415                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2416                                  "%s-%s-%d", netdev->name, "tx", ti++);
2417                 } else if (handler == &ixgbe_msix_clean_many) {
2418                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2419                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2420                         ti++;
2421                 } else {
2422                         /* skip this unused q_vector */
2423                         continue;
2424                 }
2425                 err = request_irq(adapter->msix_entries[vector].vector,
2426                                   handler, 0, q_vector->name,
2427                                   q_vector);
2428                 if (err) {
2429                         e_err(probe, "request_irq failed for MSIX interrupt "
2430                               "Error: %d\n", err);
2431                         goto free_queue_irqs;
2432                 }
2433         }
2434
2435         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2436         err = request_irq(adapter->msix_entries[vector].vector,
2437                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2438         if (err) {
2439                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2440                 goto free_queue_irqs;
2441         }
2442
2443         return 0;
2444
2445 free_queue_irqs:
2446         for (i = vector - 1; i >= 0; i--)
2447                 free_irq(adapter->msix_entries[--vector].vector,
2448                          adapter->q_vector[i]);
2449         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2450         pci_disable_msix(adapter->pdev);
2451         kfree(adapter->msix_entries);
2452         adapter->msix_entries = NULL;
2453         return err;
2454 }
2455
2456 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2457 {
2458         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2459         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2460         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2461         u32 new_itr = q_vector->eitr;
2462         u8 current_itr;
2463
2464         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2465                                             q_vector->tx_itr,
2466                                             tx_ring->total_packets,
2467                                             tx_ring->total_bytes);
2468         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2469                                             q_vector->rx_itr,
2470                                             rx_ring->total_packets,
2471                                             rx_ring->total_bytes);
2472
2473         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2474
2475         switch (current_itr) {
2476         /* counts and packets in update_itr are dependent on these numbers */
2477         case lowest_latency:
2478                 new_itr = 100000;
2479                 break;
2480         case low_latency:
2481                 new_itr = 20000; /* aka hwitr = ~200 */
2482                 break;
2483         case bulk_latency:
2484                 new_itr = 8000;
2485                 break;
2486         default:
2487                 break;
2488         }
2489
2490         if (new_itr != q_vector->eitr) {
2491                 /* do an exponential smoothing */
2492                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2493
2494                 /* save the algorithm value here */
2495                 q_vector->eitr = new_itr;
2496
2497                 ixgbe_write_eitr(q_vector);
2498         }
2499 }
2500
2501 /**
2502  * ixgbe_irq_enable - Enable default interrupt generation settings
2503  * @adapter: board private structure
2504  **/
2505 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2506                                     bool flush)
2507 {
2508         u32 mask;
2509
2510         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2511         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2512                 mask |= IXGBE_EIMS_GPI_SDP0;
2513         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2514                 mask |= IXGBE_EIMS_GPI_SDP1;
2515         switch (adapter->hw.mac.type) {
2516         case ixgbe_mac_82599EB:
2517         case ixgbe_mac_X540:
2518                 mask |= IXGBE_EIMS_ECC;
2519                 mask |= IXGBE_EIMS_GPI_SDP1;
2520                 mask |= IXGBE_EIMS_GPI_SDP2;
2521                 if (adapter->num_vfs)
2522                         mask |= IXGBE_EIMS_MAILBOX;
2523                 break;
2524         default:
2525                 break;
2526         }
2527         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2528             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2529                 mask |= IXGBE_EIMS_FLOW_DIR;
2530
2531         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2532         if (queues)
2533                 ixgbe_irq_enable_queues(adapter, ~0);
2534         if (flush)
2535                 IXGBE_WRITE_FLUSH(&adapter->hw);
2536
2537         if (adapter->num_vfs > 32) {
2538                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2539                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2540         }
2541 }
2542
2543 /**
2544  * ixgbe_intr - legacy mode Interrupt Handler
2545  * @irq: interrupt number
2546  * @data: pointer to a network interface device structure
2547  **/
2548 static irqreturn_t ixgbe_intr(int irq, void *data)
2549 {
2550         struct net_device *netdev = data;
2551         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2552         struct ixgbe_hw *hw = &adapter->hw;
2553         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2554         u32 eicr;
2555
2556         /*
2557          * Workaround for silicon errata on 82598.  Mask the interrupts
2558          * before the read of EICR.
2559          */
2560         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2561
2562         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2563          * therefore no explict interrupt disable is necessary */
2564         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2565         if (!eicr) {
2566                 /*
2567                  * shared interrupt alert!
2568                  * make sure interrupts are enabled because the read will
2569                  * have disabled interrupts due to EIAM
2570                  * finish the workaround of silicon errata on 82598.  Unmask
2571                  * the interrupt that we masked before the EICR read.
2572                  */
2573                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2574                         ixgbe_irq_enable(adapter, true, true);
2575                 return IRQ_NONE;        /* Not our interrupt */
2576         }
2577
2578         if (eicr & IXGBE_EICR_LSC)
2579                 ixgbe_check_lsc(adapter);
2580
2581         switch (hw->mac.type) {
2582         case ixgbe_mac_82599EB:
2583                 ixgbe_check_sfp_event(adapter, eicr);
2584                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2585                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2586                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2587                                 adapter->interrupt_event = eicr;
2588                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2589                                 ixgbe_service_event_schedule(adapter);
2590                         }
2591                 }
2592                 break;
2593         default:
2594                 break;
2595         }
2596
2597         ixgbe_check_fan_failure(adapter, eicr);
2598
2599         if (napi_schedule_prep(&(q_vector->napi))) {
2600                 adapter->tx_ring[0]->total_packets = 0;
2601                 adapter->tx_ring[0]->total_bytes = 0;
2602                 adapter->rx_ring[0]->total_packets = 0;
2603                 adapter->rx_ring[0]->total_bytes = 0;
2604                 /* would disable interrupts here but EIAM disabled it */
2605                 __napi_schedule(&(q_vector->napi));
2606         }
2607
2608         /*
2609          * re-enable link(maybe) and non-queue interrupts, no flush.
2610          * ixgbe_poll will re-enable the queue interrupts
2611          */
2612
2613         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2614                 ixgbe_irq_enable(adapter, false, false);
2615
2616         return IRQ_HANDLED;
2617 }
2618
2619 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2620 {
2621         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2622
2623         for (i = 0; i < q_vectors; i++) {
2624                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2625                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2626                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2627                 q_vector->rxr_count = 0;
2628                 q_vector->txr_count = 0;
2629         }
2630 }
2631
2632 /**
2633  * ixgbe_request_irq - initialize interrupts
2634  * @adapter: board private structure
2635  *
2636  * Attempts to configure interrupts using the best available
2637  * capabilities of the hardware and kernel.
2638  **/
2639 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2640 {
2641         struct net_device *netdev = adapter->netdev;
2642         int err;
2643
2644         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2645                 err = ixgbe_request_msix_irqs(adapter);
2646         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2647                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2648                                   netdev->name, netdev);
2649         } else {
2650                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2651                                   netdev->name, netdev);
2652         }
2653
2654         if (err)
2655                 e_err(probe, "request_irq failed, Error %d\n", err);
2656
2657         return err;
2658 }
2659
2660 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2661 {
2662         struct net_device *netdev = adapter->netdev;
2663
2664         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2665                 int i, q_vectors;
2666
2667                 q_vectors = adapter->num_msix_vectors;
2668
2669                 i = q_vectors - 1;
2670                 free_irq(adapter->msix_entries[i].vector, netdev);
2671
2672                 i--;
2673                 for (; i >= 0; i--) {
2674                         /* free only the irqs that were actually requested */
2675                         if (!adapter->q_vector[i]->rxr_count &&
2676                             !adapter->q_vector[i]->txr_count)
2677                                 continue;
2678
2679                         free_irq(adapter->msix_entries[i].vector,
2680                                  adapter->q_vector[i]);
2681                 }
2682
2683                 ixgbe_reset_q_vectors(adapter);
2684         } else {
2685                 free_irq(adapter->pdev->irq, netdev);
2686         }
2687 }
2688
2689 /**
2690  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2691  * @adapter: board private structure
2692  **/
2693 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2694 {
2695         switch (adapter->hw.mac.type) {
2696         case ixgbe_mac_82598EB:
2697                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2698                 break;
2699         case ixgbe_mac_82599EB:
2700         case ixgbe_mac_X540:
2701                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2702                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2703                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2704                 if (adapter->num_vfs > 32)
2705                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2706                 break;
2707         default:
2708                 break;
2709         }
2710         IXGBE_WRITE_FLUSH(&adapter->hw);
2711         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2712                 int i;
2713                 for (i = 0; i < adapter->num_msix_vectors; i++)
2714                         synchronize_irq(adapter->msix_entries[i].vector);
2715         } else {
2716                 synchronize_irq(adapter->pdev->irq);
2717         }
2718 }
2719
2720 /**
2721  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2722  *
2723  **/
2724 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2725 {
2726         struct ixgbe_hw *hw = &adapter->hw;
2727
2728         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2729                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2730
2731         ixgbe_set_ivar(adapter, 0, 0, 0);
2732         ixgbe_set_ivar(adapter, 1, 0, 0);
2733
2734         map_vector_to_rxq(adapter, 0, 0);
2735         map_vector_to_txq(adapter, 0, 0);
2736
2737         e_info(hw, "Legacy interrupt IVAR setup done\n");
2738 }
2739
2740 /**
2741  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2742  * @adapter: board private structure
2743  * @ring: structure containing ring specific data
2744  *
2745  * Configure the Tx descriptor ring after a reset.
2746  **/
2747 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2748                              struct ixgbe_ring *ring)
2749 {
2750         struct ixgbe_hw *hw = &adapter->hw;
2751         u64 tdba = ring->dma;
2752         int wait_loop = 10;
2753         u32 txdctl;
2754         u8 reg_idx = ring->reg_idx;
2755
2756         /* disable queue to avoid issues while updating state */
2757         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2758         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2759                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2760         IXGBE_WRITE_FLUSH(hw);
2761
2762         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2763                         (tdba & DMA_BIT_MASK(32)));
2764         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2765         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2766                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2767         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2768         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2769         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2770
2771         /* configure fetching thresholds */
2772         if (adapter->rx_itr_setting == 0) {
2773                 /* cannot set wthresh when itr==0 */
2774                 txdctl &= ~0x007F0000;
2775         } else {
2776                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2777                 txdctl |= (8 << 16);
2778         }
2779         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2780                 /* PThresh workaround for Tx hang with DFP enabled. */
2781                 txdctl |= 32;
2782         }
2783
2784         /* reinitialize flowdirector state */
2785         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2786             adapter->atr_sample_rate) {
2787                 ring->atr_sample_rate = adapter->atr_sample_rate;
2788                 ring->atr_count = 0;
2789                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2790         } else {
2791                 ring->atr_sample_rate = 0;
2792         }
2793
2794         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2795
2796         /* enable queue */
2797         txdctl |= IXGBE_TXDCTL_ENABLE;
2798         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2799
2800         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2801         if (hw->mac.type == ixgbe_mac_82598EB &&
2802             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2803                 return;
2804
2805         /* poll to verify queue is enabled */
2806         do {
2807                 usleep_range(1000, 2000);
2808                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2809         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2810         if (!wait_loop)
2811                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2812 }
2813
2814 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2815 {
2816         struct ixgbe_hw *hw = &adapter->hw;
2817         u32 rttdcs;
2818         u32 mask;
2819
2820         if (hw->mac.type == ixgbe_mac_82598EB)
2821                 return;
2822
2823         /* disable the arbiter while setting MTQC */
2824         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2825         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2826         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2827
2828         /* set transmit pool layout */
2829         mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2830         switch (adapter->flags & mask) {
2831
2832         case (IXGBE_FLAG_SRIOV_ENABLED):
2833                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2834                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2835                 break;
2836
2837         case (IXGBE_FLAG_DCB_ENABLED):
2838                 /* We enable 8 traffic classes, DCB only */
2839                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2840                               (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2841                 break;
2842
2843         default:
2844                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2845                 break;
2846         }
2847
2848         /* re-enable the arbiter */
2849         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2850         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2851 }
2852
2853 /**
2854  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2855  * @adapter: board private structure
2856  *
2857  * Configure the Tx unit of the MAC after a reset.
2858  **/
2859 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2860 {
2861         struct ixgbe_hw *hw = &adapter->hw;
2862         u32 dmatxctl;
2863         u32 i;
2864
2865         ixgbe_setup_mtqc(adapter);
2866
2867         if (hw->mac.type != ixgbe_mac_82598EB) {
2868                 /* DMATXCTL.EN must be before Tx queues are enabled */
2869                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2870                 dmatxctl |= IXGBE_DMATXCTL_TE;
2871                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2872         }
2873
2874         /* Setup the HW Tx Head and Tail descriptor pointers */
2875         for (i = 0; i < adapter->num_tx_queues; i++)
2876                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2877 }
2878
2879 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2880
2881 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2882                                    struct ixgbe_ring *rx_ring)
2883 {
2884         u32 srrctl;
2885         u8 reg_idx = rx_ring->reg_idx;
2886
2887         switch (adapter->hw.mac.type) {
2888         case ixgbe_mac_82598EB: {
2889                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2890                 const int mask = feature[RING_F_RSS].mask;
2891                 reg_idx = reg_idx & mask;
2892         }
2893                 break;
2894         case ixgbe_mac_82599EB:
2895         case ixgbe_mac_X540:
2896         default:
2897                 break;
2898         }
2899
2900         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2901
2902         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2903         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2904         if (adapter->num_vfs)
2905                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2906
2907         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2908                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2909
2910         if (ring_is_ps_enabled(rx_ring)) {
2911 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2912                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2913 #else
2914                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2915 #endif
2916                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2917         } else {
2918                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2919                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2920                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2921         }
2922
2923         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2924 }
2925
2926 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2927 {
2928         struct ixgbe_hw *hw = &adapter->hw;
2929         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2930                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2931                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2932         u32 mrqc = 0, reta = 0;
2933         u32 rxcsum;
2934         int i, j;
2935         int mask;
2936
2937         /* Fill out hash function seeds */
2938         for (i = 0; i < 10; i++)
2939                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2940
2941         /* Fill out redirection table */
2942         for (i = 0, j = 0; i < 128; i++, j++) {
2943                 if (j == adapter->ring_feature[RING_F_RSS].indices)
2944                         j = 0;
2945                 /* reta = 4-byte sliding window of
2946                  * 0x00..(indices-1)(indices-1)00..etc. */
2947                 reta = (reta << 8) | (j * 0x11);
2948                 if ((i & 3) == 3)
2949                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2950         }
2951
2952         /* Disable indicating checksum in descriptor, enables RSS hash */
2953         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2954         rxcsum |= IXGBE_RXCSUM_PCSD;
2955         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2956
2957         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2958                 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2959         else
2960                 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2961 #ifdef CONFIG_IXGBE_DCB
2962                                          | IXGBE_FLAG_DCB_ENABLED
2963 #endif
2964                                          | IXGBE_FLAG_SRIOV_ENABLED
2965                                         );
2966
2967         switch (mask) {
2968 #ifdef CONFIG_IXGBE_DCB
2969         case (IXGBE_FLAG_DCB_ENABLED | IXGBE_FLAG_RSS_ENABLED):
2970                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2971                 break;
2972         case (IXGBE_FLAG_DCB_ENABLED):
2973                 mrqc = IXGBE_MRQC_RT8TCEN;
2974                 break;
2975 #endif /* CONFIG_IXGBE_DCB */
2976         case (IXGBE_FLAG_RSS_ENABLED):
2977                 mrqc = IXGBE_MRQC_RSSEN;
2978                 break;
2979         case (IXGBE_FLAG_SRIOV_ENABLED):
2980                 mrqc = IXGBE_MRQC_VMDQEN;
2981                 break;
2982         default:
2983                 break;
2984         }
2985
2986         /* Perform hash on these packet types */
2987         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2988               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2989               | IXGBE_MRQC_RSS_FIELD_IPV6
2990               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2991
2992         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2993 }
2994
2995 /**
2996  * ixgbe_clear_rscctl - disable RSC for the indicated ring
2997  * @adapter: address of board private structure
2998  * @ring: structure containing ring specific data
2999  **/
3000 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
3001                         struct ixgbe_ring *ring)
3002 {
3003         struct ixgbe_hw *hw = &adapter->hw;
3004         u32 rscctrl;
3005         u8 reg_idx = ring->reg_idx;
3006
3007         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3008         rscctrl &= ~IXGBE_RSCCTL_RSCEN;
3009         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3010 }
3011
3012 /**
3013  * ixgbe_configure_rscctl - enable RSC for the indicated ring
3014  * @adapter:    address of board private structure
3015  * @index:      index of ring to set
3016  **/
3017 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
3018                                    struct ixgbe_ring *ring)
3019 {
3020         struct ixgbe_hw *hw = &adapter->hw;
3021         u32 rscctrl;
3022         int rx_buf_len;
3023         u8 reg_idx = ring->reg_idx;
3024
3025         if (!ring_is_rsc_enabled(ring))
3026                 return;
3027
3028         rx_buf_len = ring->rx_buf_len;
3029         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
3030         rscctrl |= IXGBE_RSCCTL_RSCEN;
3031         /*
3032          * we must limit the number of descriptors so that the
3033          * total size of max desc * buf_len is not greater
3034          * than 65535
3035          */
3036         if (ring_is_ps_enabled(ring)) {
3037 #if (MAX_SKB_FRAGS > 16)
3038                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3039 #elif (MAX_SKB_FRAGS > 8)
3040                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3041 #elif (MAX_SKB_FRAGS > 4)
3042                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3043 #else
3044                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
3045 #endif
3046         } else {
3047                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
3048                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
3049                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
3050                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
3051                 else
3052                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3053         }
3054         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3055 }
3056
3057 /**
3058  *  ixgbe_set_uta - Set unicast filter table address
3059  *  @adapter: board private structure
3060  *
3061  *  The unicast table address is a register array of 32-bit registers.
3062  *  The table is meant to be used in a way similar to how the MTA is used
3063  *  however due to certain limitations in the hardware it is necessary to
3064  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
3065  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
3066  **/
3067 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
3068 {
3069         struct ixgbe_hw *hw = &adapter->hw;
3070         int i;
3071
3072         /* The UTA table only exists on 82599 hardware and newer */
3073         if (hw->mac.type < ixgbe_mac_82599EB)
3074                 return;
3075
3076         /* we only need to do this if VMDq is enabled */
3077         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3078                 return;
3079
3080         for (i = 0; i < 128; i++)
3081                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3082 }
3083
3084 #define IXGBE_MAX_RX_DESC_POLL 10
3085 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3086                                        struct ixgbe_ring *ring)
3087 {
3088         struct ixgbe_hw *hw = &adapter->hw;
3089         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3090         u32 rxdctl;
3091         u8 reg_idx = ring->reg_idx;
3092
3093         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3094         if (hw->mac.type == ixgbe_mac_82598EB &&
3095             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3096                 return;
3097
3098         do {
3099                 usleep_range(1000, 2000);
3100                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3101         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3102
3103         if (!wait_loop) {
3104                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3105                       "the polling period\n", reg_idx);
3106         }
3107 }
3108
3109 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3110                             struct ixgbe_ring *ring)
3111 {
3112         struct ixgbe_hw *hw = &adapter->hw;
3113         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3114         u32 rxdctl;
3115         u8 reg_idx = ring->reg_idx;
3116
3117         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3118         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3119
3120         /* write value back with RXDCTL.ENABLE bit cleared */
3121         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3122
3123         if (hw->mac.type == ixgbe_mac_82598EB &&
3124             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3125                 return;
3126
3127         /* the hardware may take up to 100us to really disable the rx queue */
3128         do {
3129                 udelay(10);
3130                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3131         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3132
3133         if (!wait_loop) {
3134                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3135                       "the polling period\n", reg_idx);
3136         }
3137 }
3138
3139 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3140                              struct ixgbe_ring *ring)
3141 {
3142         struct ixgbe_hw *hw = &adapter->hw;
3143         u64 rdba = ring->dma;
3144         u32 rxdctl;
3145         u8 reg_idx = ring->reg_idx;
3146
3147         /* disable queue to avoid issues while updating state */
3148         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3149         ixgbe_disable_rx_queue(adapter, ring);
3150
3151         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3152         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3153         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3154                         ring->count * sizeof(union ixgbe_adv_rx_desc));
3155         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3156         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3157         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3158
3159         ixgbe_configure_srrctl(adapter, ring);
3160         ixgbe_configure_rscctl(adapter, ring);
3161
3162         /* If operating in IOV mode set RLPML for X540 */
3163         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3164             hw->mac.type == ixgbe_mac_X540) {
3165                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3166                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3167                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3168         }
3169
3170         if (hw->mac.type == ixgbe_mac_82598EB) {
3171                 /*
3172                  * enable cache line friendly hardware writes:
3173                  * PTHRESH=32 descriptors (half the internal cache),
3174                  * this also removes ugly rx_no_buffer_count increment
3175                  * HTHRESH=4 descriptors (to minimize latency on fetch)
3176                  * WTHRESH=8 burst writeback up to two cache lines
3177                  */
3178                 rxdctl &= ~0x3FFFFF;
3179                 rxdctl |=  0x080420;
3180         }
3181
3182         /* enable receive descriptor ring */
3183         rxdctl |= IXGBE_RXDCTL_ENABLE;
3184         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3185
3186         ixgbe_rx_desc_queue_enable(adapter, ring);
3187         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3188 }
3189
3190 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3191 {
3192         struct ixgbe_hw *hw = &adapter->hw;
3193         int p;
3194
3195         /* PSRTYPE must be initialized in non 82598 adapters */
3196         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3197                       IXGBE_PSRTYPE_UDPHDR |
3198                       IXGBE_PSRTYPE_IPV4HDR |
3199                       IXGBE_PSRTYPE_L2HDR |
3200                       IXGBE_PSRTYPE_IPV6HDR;
3201
3202         if (hw->mac.type == ixgbe_mac_82598EB)
3203                 return;
3204
3205         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3206                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3207
3208         for (p = 0; p < adapter->num_rx_pools; p++)
3209                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3210                                 psrtype);
3211 }
3212
3213 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3214 {
3215         struct ixgbe_hw *hw = &adapter->hw;
3216         u32 gcr_ext;
3217         u32 vt_reg_bits;
3218         u32 reg_offset, vf_shift;
3219         u32 vmdctl;
3220
3221         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3222                 return;
3223
3224         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3225         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3226         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3227         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3228
3229         vf_shift = adapter->num_vfs % 32;
3230         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3231
3232         /* Enable only the PF's pool for Tx/Rx */
3233         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3234         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3235         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3236         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3237         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3238
3239         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3240         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3241
3242         /*
3243          * Set up VF register offsets for selected VT Mode,
3244          * i.e. 32 or 64 VFs for SR-IOV
3245          */
3246         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3247         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3248         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3249         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3250
3251         /* enable Tx loopback for VF/PF communication */
3252         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3253         /* Enable MAC Anti-Spoofing */
3254         hw->mac.ops.set_mac_anti_spoofing(hw,
3255                                           (adapter->antispoofing_enabled =
3256                                            (adapter->num_vfs != 0)),
3257                                           adapter->num_vfs);
3258 }
3259
3260 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3261 {
3262         struct ixgbe_hw *hw = &adapter->hw;
3263         struct net_device *netdev = adapter->netdev;
3264         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3265         int rx_buf_len;
3266         struct ixgbe_ring *rx_ring;
3267         int i;
3268         u32 mhadd, hlreg0;
3269
3270         /* Decide whether to use packet split mode or not */
3271         /* On by default */
3272         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3273
3274         /* Do not use packet split if we're in SR-IOV Mode */
3275         if (adapter->num_vfs)
3276                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3277
3278         /* Disable packet split due to 82599 erratum #45 */
3279         if (hw->mac.type == ixgbe_mac_82599EB)
3280                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3281
3282         /* Set the RX buffer length according to the mode */
3283         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3284                 rx_buf_len = IXGBE_RX_HDR_SIZE;
3285         } else {
3286                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3287                     (netdev->mtu <= ETH_DATA_LEN))
3288                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3289                 else
3290                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3291         }
3292
3293 #ifdef IXGBE_FCOE
3294         /* adjust max frame to be able to do baby jumbo for FCoE */
3295         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3296             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3297                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3298
3299 #endif /* IXGBE_FCOE */
3300         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3301         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3302                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3303                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3304
3305                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3306         }
3307
3308         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3309         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3310         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3311         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3312
3313         /*
3314          * Setup the HW Rx Head and Tail Descriptor Pointers and
3315          * the Base and Length of the Rx Descriptor Ring
3316          */
3317         for (i = 0; i < adapter->num_rx_queues; i++) {
3318                 rx_ring = adapter->rx_ring[i];
3319                 rx_ring->rx_buf_len = rx_buf_len;
3320
3321                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3322                         set_ring_ps_enabled(rx_ring);
3323                 else
3324                         clear_ring_ps_enabled(rx_ring);
3325
3326                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3327                         set_ring_rsc_enabled(rx_ring);
3328                 else
3329                         clear_ring_rsc_enabled(rx_ring);
3330
3331 #ifdef IXGBE_FCOE
3332                 if (netdev->features & NETIF_F_FCOE_MTU) {
3333                         struct ixgbe_ring_feature *f;
3334                         f = &adapter->ring_feature[RING_F_FCOE];
3335                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3336                                 clear_ring_ps_enabled(rx_ring);
3337                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3338                                         rx_ring->rx_buf_len =
3339                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3340                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3341                                    !ring_is_ps_enabled(rx_ring)) {
3342                                 rx_ring->rx_buf_len =
3343                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3344                         }
3345                 }
3346 #endif /* IXGBE_FCOE */
3347         }
3348 }
3349
3350 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3351 {
3352         struct ixgbe_hw *hw = &adapter->hw;
3353         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3354
3355         switch (hw->mac.type) {
3356         case ixgbe_mac_82598EB:
3357                 /*
3358                  * For VMDq support of different descriptor types or
3359                  * buffer sizes through the use of multiple SRRCTL
3360                  * registers, RDRXCTL.MVMEN must be set to 1
3361                  *
3362                  * also, the manual doesn't mention it clearly but DCA hints
3363                  * will only use queue 0's tags unless this bit is set.  Side
3364                  * effects of setting this bit are only that SRRCTL must be
3365                  * fully programmed [0..15]
3366                  */
3367                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3368                 break;
3369         case ixgbe_mac_82599EB:
3370         case ixgbe_mac_X540:
3371                 /* Disable RSC for ACK packets */
3372                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3373                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3374                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3375                 /* hardware requires some bits to be set by default */
3376                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3377                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3378                 break;
3379         default:
3380                 /* We should do nothing since we don't know this hardware */
3381                 return;
3382         }
3383
3384         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3385 }
3386
3387 /**
3388  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3389  * @adapter: board private structure
3390  *
3391  * Configure the Rx unit of the MAC after a reset.
3392  **/
3393 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3394 {
3395         struct ixgbe_hw *hw = &adapter->hw;
3396         int i;
3397         u32 rxctrl;
3398
3399         /* disable receives while setting up the descriptors */
3400         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3401         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3402
3403         ixgbe_setup_psrtype(adapter);
3404         ixgbe_setup_rdrxctl(adapter);
3405
3406         /* Program registers for the distribution of queues */
3407         ixgbe_setup_mrqc(adapter);
3408
3409         ixgbe_set_uta(adapter);
3410
3411         /* set_rx_buffer_len must be called before ring initialization */
3412         ixgbe_set_rx_buffer_len(adapter);
3413
3414         /*
3415          * Setup the HW Rx Head and Tail Descriptor Pointers and
3416          * the Base and Length of the Rx Descriptor Ring
3417          */
3418         for (i = 0; i < adapter->num_rx_queues; i++)
3419                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3420
3421         /* disable drop enable for 82598 parts */
3422         if (hw->mac.type == ixgbe_mac_82598EB)
3423                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3424
3425         /* enable all receives */
3426         rxctrl |= IXGBE_RXCTRL_RXEN;
3427         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3428 }
3429
3430 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3431 {
3432         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3433         struct ixgbe_hw *hw = &adapter->hw;
3434         int pool_ndx = adapter->num_vfs;
3435
3436         /* add VID to filter table */
3437         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3438         set_bit(vid, adapter->active_vlans);
3439 }
3440
3441 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3442 {
3443         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3444         struct ixgbe_hw *hw = &adapter->hw;
3445         int pool_ndx = adapter->num_vfs;
3446
3447         /* remove VID from filter table */
3448         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3449         clear_bit(vid, adapter->active_vlans);
3450 }
3451
3452 /**
3453  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3454  * @adapter: driver data
3455  */
3456 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3457 {
3458         struct ixgbe_hw *hw = &adapter->hw;
3459         u32 vlnctrl;
3460
3461         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3462         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3463         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3464 }
3465
3466 /**
3467  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3468  * @adapter: driver data
3469  */
3470 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3471 {
3472         struct ixgbe_hw *hw = &adapter->hw;
3473         u32 vlnctrl;
3474
3475         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3476         vlnctrl |= IXGBE_VLNCTRL_VFE;
3477         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3478         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3479 }
3480
3481 /**
3482  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3483  * @adapter: driver data
3484  */
3485 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3486 {
3487         struct ixgbe_hw *hw = &adapter->hw;
3488         u32 vlnctrl;
3489         int i, j;
3490
3491         switch (hw->mac.type) {
3492         case ixgbe_mac_82598EB:
3493                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3494                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3495                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3496                 break;
3497         case ixgbe_mac_82599EB:
3498         case ixgbe_mac_X540:
3499                 for (i = 0; i < adapter->num_rx_queues; i++) {
3500                         j = adapter->rx_ring[i]->reg_idx;
3501                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3502                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3503                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3504                 }
3505                 break;
3506         default:
3507                 break;
3508         }
3509 }
3510
3511 /**
3512  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3513  * @adapter: driver data
3514  */
3515 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3516 {
3517         struct ixgbe_hw *hw = &adapter->hw;
3518         u32 vlnctrl;
3519         int i, j;
3520
3521         switch (hw->mac.type) {
3522         case ixgbe_mac_82598EB:
3523                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3524                 vlnctrl |= IXGBE_VLNCTRL_VME;
3525                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3526                 break;
3527         case ixgbe_mac_82599EB:
3528         case ixgbe_mac_X540:
3529                 for (i = 0; i < adapter->num_rx_queues; i++) {
3530                         j = adapter->rx_ring[i]->reg_idx;
3531                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3532                         vlnctrl |= IXGBE_RXDCTL_VME;
3533                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3534                 }
3535                 break;
3536         default:
3537                 break;
3538         }
3539 }
3540
3541 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3542 {
3543         u16 vid;
3544
3545         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3546
3547         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3548                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3549 }
3550
3551 /**
3552  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3553  * @netdev: network interface device structure
3554  *
3555  * Writes unicast address list to the RAR table.
3556  * Returns: -ENOMEM on failure/insufficient address space
3557  *                0 on no addresses written
3558  *                X on writing X addresses to the RAR table
3559  **/
3560 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3561 {
3562         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3563         struct ixgbe_hw *hw = &adapter->hw;
3564         unsigned int vfn = adapter->num_vfs;
3565         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3566         int count = 0;
3567
3568         /* return ENOMEM indicating insufficient memory for addresses */
3569         if (netdev_uc_count(netdev) > rar_entries)
3570                 return -ENOMEM;
3571
3572         if (!netdev_uc_empty(netdev) && rar_entries) {
3573                 struct netdev_hw_addr *ha;
3574                 /* return error if we do not support writing to RAR table */
3575                 if (!hw->mac.ops.set_rar)
3576                         return -ENOMEM;
3577
3578                 netdev_for_each_uc_addr(ha, netdev) {
3579                         if (!rar_entries)
3580                                 break;
3581                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3582                                             vfn, IXGBE_RAH_AV);
3583                         count++;
3584                 }
3585         }
3586         /* write the addresses in reverse order to avoid write combining */
3587         for (; rar_entries > 0 ; rar_entries--)
3588                 hw->mac.ops.clear_rar(hw, rar_entries);
3589
3590         return count;
3591 }
3592
3593 /**
3594  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3595  * @netdev: network interface device structure
3596  *
3597  * The set_rx_method entry point is called whenever the unicast/multicast
3598  * address list or the network interface flags are updated.  This routine is
3599  * responsible for configuring the hardware for proper unicast, multicast and
3600  * promiscuous mode.
3601  **/
3602 void ixgbe_set_rx_mode(struct net_device *netdev)
3603 {
3604         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3605         struct ixgbe_hw *hw = &adapter->hw;
3606         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3607         int count;
3608
3609         /* Check for Promiscuous and All Multicast modes */
3610
3611         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3612
3613         /* set all bits that we expect to always be set */
3614         fctrl |= IXGBE_FCTRL_BAM;
3615         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3616         fctrl |= IXGBE_FCTRL_PMCF;
3617
3618         /* clear the bits we are changing the status of */
3619         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3620
3621         if (netdev->flags & IFF_PROMISC) {
3622                 hw->addr_ctrl.user_set_promisc = true;
3623                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3624                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3625                 /* don't hardware filter vlans in promisc mode */
3626                 ixgbe_vlan_filter_disable(adapter);
3627         } else {
3628                 if (netdev->flags & IFF_ALLMULTI) {
3629                         fctrl |= IXGBE_FCTRL_MPE;
3630                         vmolr |= IXGBE_VMOLR_MPE;
3631                 } else {
3632                         /*
3633                          * Write addresses to the MTA, if the attempt fails
3634                          * then we should just turn on promiscuous mode so
3635                          * that we can at least receive multicast traffic
3636                          */
3637                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3638                         vmolr |= IXGBE_VMOLR_ROMPE;
3639                 }
3640                 ixgbe_vlan_filter_enable(adapter);
3641                 hw->addr_ctrl.user_set_promisc = false;
3642                 /*
3643                  * Write addresses to available RAR registers, if there is not
3644                  * sufficient space to store all the addresses then enable
3645                  * unicast promiscuous mode
3646                  */
3647                 count = ixgbe_write_uc_addr_list(netdev);
3648                 if (count < 0) {
3649                         fctrl |= IXGBE_FCTRL_UPE;
3650                         vmolr |= IXGBE_VMOLR_ROPE;
3651                 }
3652         }
3653
3654         if (adapter->num_vfs) {
3655                 ixgbe_restore_vf_multicasts(adapter);
3656                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3657                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3658                            IXGBE_VMOLR_ROPE);
3659                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3660         }
3661
3662         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3663
3664         if (netdev->features & NETIF_F_HW_VLAN_RX)
3665                 ixgbe_vlan_strip_enable(adapter);
3666         else
3667                 ixgbe_vlan_strip_disable(adapter);
3668 }
3669
3670 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3671 {
3672         int q_idx;
3673         struct ixgbe_q_vector *q_vector;
3674         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3675
3676         /* legacy and MSI only use one vector */
3677         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3678                 q_vectors = 1;
3679
3680         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3681                 struct napi_struct *napi;
3682                 q_vector = adapter->q_vector[q_idx];
3683                 napi = &q_vector->napi;
3684                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3685                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3686                                 if (q_vector->txr_count == 1)
3687                                         napi->poll = &ixgbe_clean_txonly;
3688                                 else if (q_vector->rxr_count == 1)
3689                                         napi->poll = &ixgbe_clean_rxonly;
3690                         }
3691                 }
3692
3693                 napi_enable(napi);
3694         }
3695 }
3696
3697 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3698 {
3699         int q_idx;
3700         struct ixgbe_q_vector *q_vector;
3701         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3702
3703         /* legacy and MSI only use one vector */
3704         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3705                 q_vectors = 1;
3706
3707         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3708                 q_vector = adapter->q_vector[q_idx];
3709                 napi_disable(&q_vector->napi);
3710         }
3711 }
3712
3713 #ifdef CONFIG_IXGBE_DCB
3714 /*
3715  * ixgbe_configure_dcb - Configure DCB hardware
3716  * @adapter: ixgbe adapter struct
3717  *
3718  * This is called by the driver on open to configure the DCB hardware.
3719  * This is also called by the gennetlink interface when reconfiguring
3720  * the DCB state.
3721  */
3722 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3723 {
3724         struct ixgbe_hw *hw = &adapter->hw;
3725         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3726
3727         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3728                 if (hw->mac.type == ixgbe_mac_82598EB)
3729                         netif_set_gso_max_size(adapter->netdev, 65536);
3730                 return;
3731         }
3732
3733         if (hw->mac.type == ixgbe_mac_82598EB)
3734                 netif_set_gso_max_size(adapter->netdev, 32768);
3735
3736
3737         /* Enable VLAN tag insert/strip */
3738         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3739
3740         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3741
3742         /* reconfigure the hardware */
3743         if (adapter->dcbx_cap & (DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE)) {
3744 #ifdef CONFIG_FCOE
3745                 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3746                         max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3747 #endif
3748                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3749                                                 DCB_TX_CONFIG);
3750                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3751                                                 DCB_RX_CONFIG);
3752                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3753         } else {
3754                 struct net_device *dev = adapter->netdev;
3755
3756                 if (adapter->ixgbe_ieee_ets)
3757                         dev->dcbnl_ops->ieee_setets(dev,
3758                                                     adapter->ixgbe_ieee_ets);
3759                 if (adapter->ixgbe_ieee_pfc)
3760                         dev->dcbnl_ops->ieee_setpfc(dev,
3761                                                     adapter->ixgbe_ieee_pfc);
3762         }
3763
3764         /* Enable RSS Hash per TC */
3765         if (hw->mac.type != ixgbe_mac_82598EB) {
3766                 int i;
3767                 u32 reg = 0;
3768
3769                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3770                         u8 msb = 0;
3771                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3772
3773                         while (cnt >>= 1)
3774                                 msb++;
3775
3776                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3777                 }
3778                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3779         }
3780 }
3781
3782 #endif
3783 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3784 {
3785         struct net_device *netdev = adapter->netdev;
3786         struct ixgbe_hw *hw = &adapter->hw;
3787         int i;
3788
3789 #ifdef CONFIG_IXGBE_DCB
3790         ixgbe_configure_dcb(adapter);
3791 #endif
3792
3793         ixgbe_set_rx_mode(netdev);
3794         ixgbe_restore_vlan(adapter);
3795
3796 #ifdef IXGBE_FCOE
3797         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3798                 ixgbe_configure_fcoe(adapter);
3799
3800 #endif /* IXGBE_FCOE */
3801         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3802                 for (i = 0; i < adapter->num_tx_queues; i++)
3803                         adapter->tx_ring[i]->atr_sample_rate =
3804                                                        adapter->atr_sample_rate;
3805                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3806         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3807                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3808         }
3809         ixgbe_configure_virtualization(adapter);
3810
3811         ixgbe_configure_tx(adapter);
3812         ixgbe_configure_rx(adapter);
3813 }
3814
3815 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3816 {
3817         switch (hw->phy.type) {
3818         case ixgbe_phy_sfp_avago:
3819         case ixgbe_phy_sfp_ftl:
3820         case ixgbe_phy_sfp_intel:
3821         case ixgbe_phy_sfp_unknown:
3822         case ixgbe_phy_sfp_passive_tyco:
3823         case ixgbe_phy_sfp_passive_unknown:
3824         case ixgbe_phy_sfp_active_unknown:
3825         case ixgbe_phy_sfp_ftl_active:
3826                 return true;
3827         default:
3828                 return false;
3829         }
3830 }
3831
3832 /**
3833  * ixgbe_sfp_link_config - set up SFP+ link
3834  * @adapter: pointer to private adapter struct
3835  **/
3836 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3837 {
3838         /*
3839          * We are assuming the worst case scenerio here, and that
3840          * is that an SFP was inserted/removed after the reset
3841          * but before SFP detection was enabled.  As such the best
3842          * solution is to just start searching as soon as we start
3843          */
3844         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3845                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3846
3847         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3848 }
3849
3850 /**
3851  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3852  * @hw: pointer to private hardware struct
3853  *
3854  * Returns 0 on success, negative on failure
3855  **/
3856 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3857 {
3858         u32 autoneg;
3859         bool negotiation, link_up = false;
3860         u32 ret = IXGBE_ERR_LINK_SETUP;
3861
3862         if (hw->mac.ops.check_link)
3863                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3864
3865         if (ret)
3866                 goto link_cfg_out;
3867
3868         autoneg = hw->phy.autoneg_advertised;
3869         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3870                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3871                                                         &negotiation);
3872         if (ret)
3873                 goto link_cfg_out;
3874
3875         if (hw->mac.ops.setup_link)
3876                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3877 link_cfg_out:
3878         return ret;
3879 }
3880
3881 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3882 {
3883         struct ixgbe_hw *hw = &adapter->hw;
3884         u32 gpie = 0;
3885
3886         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3887                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3888                        IXGBE_GPIE_OCD;
3889                 gpie |= IXGBE_GPIE_EIAME;
3890                 /*
3891                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3892                  * this saves a register write for every interrupt
3893                  */
3894                 switch (hw->mac.type) {
3895                 case ixgbe_mac_82598EB:
3896                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3897                         break;
3898                 case ixgbe_mac_82599EB:
3899                 case ixgbe_mac_X540:
3900                 default:
3901                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3902                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3903                         break;
3904                 }
3905         } else {
3906                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3907                  * specifically only auto mask tx and rx interrupts */
3908                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3909         }
3910
3911         /* XXX: to interrupt immediately for EICS writes, enable this */
3912         /* gpie |= IXGBE_GPIE_EIMEN; */
3913
3914         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3915                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3916                 gpie |= IXGBE_GPIE_VTMODE_64;
3917         }
3918
3919         /* Enable fan failure interrupt */
3920         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3921                 gpie |= IXGBE_SDP1_GPIEN;
3922
3923         if (hw->mac.type == ixgbe_mac_82599EB) {
3924                 gpie |= IXGBE_SDP1_GPIEN;
3925                 gpie |= IXGBE_SDP2_GPIEN;
3926         }
3927
3928         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3929 }
3930
3931 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3932 {
3933         struct ixgbe_hw *hw = &adapter->hw;
3934         int err;
3935         u32 ctrl_ext;
3936
3937         ixgbe_get_hw_control(adapter);
3938         ixgbe_setup_gpie(adapter);
3939
3940         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3941                 ixgbe_configure_msix(adapter);
3942         else
3943                 ixgbe_configure_msi_and_legacy(adapter);
3944
3945         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3946         if (hw->mac.ops.enable_tx_laser &&
3947             ((hw->phy.multispeed_fiber) ||
3948              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3949               (hw->mac.type == ixgbe_mac_82599EB))))
3950                 hw->mac.ops.enable_tx_laser(hw);
3951
3952         clear_bit(__IXGBE_DOWN, &adapter->state);
3953         ixgbe_napi_enable_all(adapter);
3954
3955         if (ixgbe_is_sfp(hw)) {
3956                 ixgbe_sfp_link_config(adapter);
3957         } else {
3958                 err = ixgbe_non_sfp_link_config(hw);
3959                 if (err)
3960                         e_err(probe, "link_config FAILED %d\n", err);
3961         }
3962
3963         /* clear any pending interrupts, may auto mask */
3964         IXGBE_READ_REG(hw, IXGBE_EICR);
3965         ixgbe_irq_enable(adapter, true, true);
3966
3967         /*
3968          * If this adapter has a fan, check to see if we had a failure
3969          * before we enabled the interrupt.
3970          */
3971         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3972                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3973                 if (esdp & IXGBE_ESDP_SDP1)
3974                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3975         }
3976
3977         /* enable transmits */
3978         netif_tx_start_all_queues(adapter->netdev);
3979
3980         /* bring the link up in the watchdog, this could race with our first
3981          * link up interrupt but shouldn't be a problem */
3982         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3983         adapter->link_check_timeout = jiffies;
3984         mod_timer(&adapter->service_timer, jiffies);
3985
3986         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3987         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3988         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3989         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3990
3991         return 0;
3992 }
3993
3994 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3995 {
3996         WARN_ON(in_interrupt());
3997         /* put off any impending NetWatchDogTimeout */
3998         adapter->netdev->trans_start = jiffies;
3999
4000         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
4001                 usleep_range(1000, 2000);
4002         ixgbe_down(adapter);
4003         /*
4004          * If SR-IOV enabled then wait a bit before bringing the adapter
4005          * back up to give the VFs time to respond to the reset.  The
4006          * two second wait is based upon the watchdog timer cycle in
4007          * the VF driver.
4008          */
4009         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4010                 msleep(2000);
4011         ixgbe_up(adapter);
4012         clear_bit(__IXGBE_RESETTING, &adapter->state);
4013 }
4014
4015 int ixgbe_up(struct ixgbe_adapter *adapter)
4016 {
4017         /* hardware has been reset, we need to reload some things */
4018         ixgbe_configure(adapter);
4019
4020         return ixgbe_up_complete(adapter);
4021 }
4022
4023 void ixgbe_reset(struct ixgbe_adapter *adapter)
4024 {
4025         struct ixgbe_hw *hw = &adapter->hw;
4026         int err;
4027
4028         /* lock SFP init bit to prevent race conditions with the watchdog */
4029         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4030                 usleep_range(1000, 2000);
4031
4032         /* clear all SFP and link config related flags while holding SFP_INIT */
4033         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4034                              IXGBE_FLAG2_SFP_NEEDS_RESET);
4035         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4036
4037         err = hw->mac.ops.init_hw(hw);
4038         switch (err) {
4039         case 0:
4040         case IXGBE_ERR_SFP_NOT_PRESENT:
4041         case IXGBE_ERR_SFP_NOT_SUPPORTED:
4042                 break;
4043         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4044                 e_dev_err("master disable timed out\n");
4045                 break;
4046         case IXGBE_ERR_EEPROM_VERSION:
4047                 /* We are running on a pre-production device, log a warning */
4048                 e_dev_warn("This device is a pre-production adapter/LOM. "
4049                            "Please be aware there may be issuesassociated with "
4050                            "your hardware.  If you are experiencing problems "
4051                            "please contact your Intel or hardware "
4052                            "representative who provided you with this "
4053                            "hardware.\n");
4054                 break;
4055         default:
4056                 e_dev_err("Hardware Error: %d\n", err);
4057         }
4058
4059         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4060
4061         /* reprogram the RAR[0] in case user changed it. */
4062         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4063                             IXGBE_RAH_AV);
4064 }
4065
4066 /**
4067  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4068  * @rx_ring: ring to free buffers from
4069  **/
4070 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4071 {
4072         struct device *dev = rx_ring->dev;
4073         unsigned long size;
4074         u16 i;
4075
4076         /* ring already cleared, nothing to do */
4077         if (!rx_ring->rx_buffer_info)
4078                 return;
4079
4080         /* Free all the Rx ring sk_buffs */
4081         for (i = 0; i < rx_ring->count; i++) {
4082                 struct ixgbe_rx_buffer *rx_buffer_info;
4083
4084                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4085                 if (rx_buffer_info->dma) {
4086                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
4087                                          rx_ring->rx_buf_len,
4088                                          DMA_FROM_DEVICE);
4089                         rx_buffer_info->dma = 0;
4090                 }
4091                 if (rx_buffer_info->skb) {
4092                         struct sk_buff *skb = rx_buffer_info->skb;
4093                         rx_buffer_info->skb = NULL;
4094                         do {
4095                                 struct sk_buff *this = skb;
4096                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
4097                                         dma_unmap_single(dev,
4098                                                          IXGBE_RSC_CB(this)->dma,
4099                                                          rx_ring->rx_buf_len,
4100                                                          DMA_FROM_DEVICE);
4101                                         IXGBE_RSC_CB(this)->dma = 0;
4102                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
4103                                 }
4104                                 skb = skb->prev;
4105                                 dev_kfree_skb(this);
4106                         } while (skb);
4107                 }
4108                 if (!rx_buffer_info->page)
4109                         continue;
4110                 if (rx_buffer_info->page_dma) {
4111                         dma_unmap_page(dev, rx_buffer_info->page_dma,
4112                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
4113                         rx_buffer_info->page_dma = 0;
4114                 }
4115                 put_page(rx_buffer_info->page);
4116                 rx_buffer_info->page = NULL;
4117                 rx_buffer_info->page_offset = 0;
4118         }
4119
4120         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4121         memset(rx_ring->rx_buffer_info, 0, size);
4122
4123         /* Zero out the descriptor ring */
4124         memset(rx_ring->desc, 0, rx_ring->size);
4125
4126         rx_ring->next_to_clean = 0;
4127         rx_ring->next_to_use = 0;
4128 }
4129
4130 /**
4131  * ixgbe_clean_tx_ring - Free Tx Buffers
4132  * @tx_ring: ring to be cleaned
4133  **/
4134 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4135 {
4136         struct ixgbe_tx_buffer *tx_buffer_info;
4137         unsigned long size;
4138         u16 i;
4139
4140         /* ring already cleared, nothing to do */
4141         if (!tx_ring->tx_buffer_info)
4142                 return;
4143
4144         /* Free all the Tx ring sk_buffs */
4145         for (i = 0; i < tx_ring->count; i++) {
4146                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4147                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4148         }
4149
4150         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4151         memset(tx_ring->tx_buffer_info, 0, size);
4152
4153         /* Zero out the descriptor ring */
4154         memset(tx_ring->desc, 0, tx_ring->size);
4155
4156         tx_ring->next_to_use = 0;
4157         tx_ring->next_to_clean = 0;
4158 }
4159
4160 /**
4161  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4162  * @adapter: board private structure
4163  **/
4164 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4165 {
4166         int i;
4167
4168         for (i = 0; i < adapter->num_rx_queues; i++)
4169                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4170 }
4171
4172 /**
4173  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4174  * @adapter: board private structure
4175  **/
4176 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4177 {
4178         int i;
4179
4180         for (i = 0; i < adapter->num_tx_queues; i++)
4181                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4182 }
4183
4184 void ixgbe_down(struct ixgbe_adapter *adapter)
4185 {
4186         struct net_device *netdev = adapter->netdev;
4187         struct ixgbe_hw *hw = &adapter->hw;
4188         u32 rxctrl;
4189         int i;
4190         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4191
4192         /* signal that we are down to the interrupt handler */
4193         set_bit(__IXGBE_DOWN, &adapter->state);
4194
4195         /* disable receives */
4196         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4197         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4198
4199         /* disable all enabled rx queues */
4200         for (i = 0; i < adapter->num_rx_queues; i++)
4201                 /* this call also flushes the previous write */
4202                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4203
4204         usleep_range(10000, 20000);
4205
4206         netif_tx_stop_all_queues(netdev);
4207
4208         /* call carrier off first to avoid false dev_watchdog timeouts */
4209         netif_carrier_off(netdev);
4210         netif_tx_disable(netdev);
4211
4212         ixgbe_irq_disable(adapter);
4213
4214         ixgbe_napi_disable_all(adapter);
4215
4216         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4217                              IXGBE_FLAG2_RESET_REQUESTED);
4218         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4219
4220         del_timer_sync(&adapter->service_timer);
4221
4222         /* disable receive for all VFs and wait one second */
4223         if (adapter->num_vfs) {
4224                 /* ping all the active vfs to let them know we are going down */
4225                 ixgbe_ping_all_vfs(adapter);
4226
4227                 /* Disable all VFTE/VFRE TX/RX */
4228                 ixgbe_disable_tx_rx(adapter);
4229
4230                 /* Mark all the VFs as inactive */
4231                 for (i = 0 ; i < adapter->num_vfs; i++)
4232                         adapter->vfinfo[i].clear_to_send = 0;
4233         }
4234
4235         /* Cleanup the affinity_hint CPU mask memory and callback */
4236         for (i = 0; i < num_q_vectors; i++) {
4237                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4238                 /* clear the affinity_mask in the IRQ descriptor */
4239                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4240                 /* release the CPU mask memory */
4241                 free_cpumask_var(q_vector->affinity_mask);
4242         }
4243
4244         /* disable transmits in the hardware now that interrupts are off */
4245         for (i = 0; i < adapter->num_tx_queues; i++) {
4246                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4247                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4248         }
4249
4250         /* Disable the Tx DMA engine on 82599 and X540 */
4251         switch (hw->mac.type) {
4252         case ixgbe_mac_82599EB:
4253         case ixgbe_mac_X540:
4254                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4255                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4256                                  ~IXGBE_DMATXCTL_TE));
4257                 break;
4258         default:
4259                 break;
4260         }
4261
4262         if (!pci_channel_offline(adapter->pdev))
4263                 ixgbe_reset(adapter);
4264
4265         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4266         if (hw->mac.ops.disable_tx_laser &&
4267             ((hw->phy.multispeed_fiber) ||
4268              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4269               (hw->mac.type == ixgbe_mac_82599EB))))
4270                 hw->mac.ops.disable_tx_laser(hw);
4271
4272         ixgbe_clean_all_tx_rings(adapter);
4273         ixgbe_clean_all_rx_rings(adapter);
4274
4275 #ifdef CONFIG_IXGBE_DCA
4276         /* since we reset the hardware DCA settings were cleared */
4277         ixgbe_setup_dca(adapter);
4278 #endif
4279 }
4280
4281 /**
4282  * ixgbe_poll - NAPI Rx polling callback
4283  * @napi: structure for representing this polling device
4284  * @budget: how many packets driver is allowed to clean
4285  *
4286  * This function is used for legacy and MSI, NAPI mode
4287  **/
4288 static int ixgbe_poll(struct napi_struct *napi, int budget)
4289 {
4290         struct ixgbe_q_vector *q_vector =
4291                                 container_of(napi, struct ixgbe_q_vector, napi);
4292         struct ixgbe_adapter *adapter = q_vector->adapter;
4293         int tx_clean_complete, work_done = 0;
4294
4295 #ifdef CONFIG_IXGBE_DCA
4296         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4297                 ixgbe_update_dca(q_vector);
4298 #endif
4299
4300         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4301         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4302
4303         if (!tx_clean_complete)
4304                 work_done = budget;
4305
4306         /* If budget not fully consumed, exit the polling mode */
4307         if (work_done < budget) {
4308                 napi_complete(napi);
4309                 if (adapter->rx_itr_setting & 1)
4310                         ixgbe_set_itr(adapter);
4311                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4312                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4313         }
4314         return work_done;
4315 }
4316
4317 /**
4318  * ixgbe_tx_timeout - Respond to a Tx Hang
4319  * @netdev: network interface device structure
4320  **/
4321 static void ixgbe_tx_timeout(struct net_device *netdev)
4322 {
4323         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4324
4325         /* Do the reset outside of interrupt context */
4326         ixgbe_tx_timeout_reset(adapter);
4327 }
4328
4329 /**
4330  * ixgbe_set_rss_queues: Allocate queues for RSS
4331  * @adapter: board private structure to initialize
4332  *
4333  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4334  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4335  *
4336  **/
4337 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4338 {
4339         bool ret = false;
4340         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4341
4342         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4343                 f->mask = 0xF;
4344                 adapter->num_rx_queues = f->indices;
4345                 adapter->num_tx_queues = f->indices;
4346                 ret = true;
4347         } else {
4348                 ret = false;
4349         }
4350
4351         return ret;
4352 }
4353
4354 /**
4355  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4356  * @adapter: board private structure to initialize
4357  *
4358  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4359  * to the original CPU that initiated the Tx session.  This runs in addition
4360  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4361  * Rx load across CPUs using RSS.
4362  *
4363  **/
4364 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4365 {
4366         bool ret = false;
4367         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4368
4369         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4370         f_fdir->mask = 0;
4371
4372         /* Flow Director must have RSS enabled */
4373         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4374             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4375              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4376                 adapter->num_tx_queues = f_fdir->indices;
4377                 adapter->num_rx_queues = f_fdir->indices;
4378                 ret = true;
4379         } else {
4380                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4381                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4382         }
4383         return ret;
4384 }
4385
4386 #ifdef IXGBE_FCOE
4387 /**
4388  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4389  * @adapter: board private structure to initialize
4390  *
4391  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4392  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4393  * rx queues out of the max number of rx queues, instead, it is used as the
4394  * index of the first rx queue used by FCoE.
4395  *
4396  **/
4397 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4398 {
4399         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4400
4401         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4402                 return false;
4403
4404         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4405 #ifdef CONFIG_IXGBE_DCB
4406                 int tc;
4407                 struct net_device *dev = adapter->netdev;
4408
4409                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4410                 f->indices = dev->tc_to_txq[tc].count;
4411                 f->mask = dev->tc_to_txq[tc].offset;
4412 #endif
4413         } else {
4414                 f->indices = min((int)num_online_cpus(), f->indices);
4415
4416                 adapter->num_rx_queues = 1;
4417                 adapter->num_tx_queues = 1;
4418
4419                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4420                         e_info(probe, "FCoE enabled with RSS\n");
4421                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4422                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4423                                 ixgbe_set_fdir_queues(adapter);
4424                         else
4425                                 ixgbe_set_rss_queues(adapter);
4426                 }
4427                 /* adding FCoE rx rings to the end */
4428                 f->mask = adapter->num_rx_queues;
4429                 adapter->num_rx_queues += f->indices;
4430                 adapter->num_tx_queues += f->indices;
4431         }
4432
4433         return true;
4434 }
4435 #endif /* IXGBE_FCOE */
4436
4437 #ifdef CONFIG_IXGBE_DCB
4438 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4439 {
4440         bool ret = false;
4441         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
4442         int i, q;
4443
4444         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4445                 return ret;
4446
4447         f->indices = 0;
4448         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
4449                 q = min((int)num_online_cpus(), MAX_TRAFFIC_CLASS);
4450                 f->indices += q;
4451         }
4452
4453         f->mask = 0x7 << 3;
4454         adapter->num_rx_queues = f->indices;
4455         adapter->num_tx_queues = f->indices;
4456         ret = true;
4457
4458 #ifdef IXGBE_FCOE
4459         /* FCoE enabled queues require special configuration done through
4460          * configure_fcoe() and others. Here we map FCoE indices onto the
4461          * DCB queue pairs allowing FCoE to own configuration later.
4462          */
4463         ixgbe_set_fcoe_queues(adapter);
4464 #endif
4465
4466         return ret;
4467 }
4468 #endif
4469
4470 /**
4471  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4472  * @adapter: board private structure to initialize
4473  *
4474  * IOV doesn't actually use anything, so just NAK the
4475  * request for now and let the other queue routines
4476  * figure out what to do.
4477  */
4478 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4479 {
4480         return false;
4481 }
4482
4483 /*
4484  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4485  * @adapter: board private structure to initialize
4486  *
4487  * This is the top level queue allocation routine.  The order here is very
4488  * important, starting with the "most" number of features turned on at once,
4489  * and ending with the smallest set of features.  This way large combinations
4490  * can be allocated if they're turned on, and smaller combinations are the
4491  * fallthrough conditions.
4492  *
4493  **/
4494 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4495 {
4496         /* Start with base case */
4497         adapter->num_rx_queues = 1;
4498         adapter->num_tx_queues = 1;
4499         adapter->num_rx_pools = adapter->num_rx_queues;
4500         adapter->num_rx_queues_per_pool = 1;
4501
4502         if (ixgbe_set_sriov_queues(adapter))
4503                 goto done;
4504
4505 #ifdef CONFIG_IXGBE_DCB
4506         if (ixgbe_set_dcb_queues(adapter))
4507                 goto done;
4508
4509 #endif
4510 #ifdef IXGBE_FCOE
4511         if (ixgbe_set_fcoe_queues(adapter))
4512                 goto done;
4513
4514 #endif /* IXGBE_FCOE */
4515         if (ixgbe_set_fdir_queues(adapter))
4516                 goto done;
4517
4518         if (ixgbe_set_rss_queues(adapter))
4519                 goto done;
4520
4521         /* fallback to base case */
4522         adapter->num_rx_queues = 1;
4523         adapter->num_tx_queues = 1;
4524
4525 done:
4526         /* Notify the stack of the (possibly) reduced queue counts. */
4527         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4528         return netif_set_real_num_rx_queues(adapter->netdev,
4529                                             adapter->num_rx_queues);
4530 }
4531
4532 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4533                                        int vectors)
4534 {
4535         int err, vector_threshold;
4536
4537         /* We'll want at least 3 (vector_threshold):
4538          * 1) TxQ[0] Cleanup
4539          * 2) RxQ[0] Cleanup
4540          * 3) Other (Link Status Change, etc.)
4541          * 4) TCP Timer (optional)
4542          */
4543         vector_threshold = MIN_MSIX_COUNT;
4544
4545         /* The more we get, the more we will assign to Tx/Rx Cleanup
4546          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4547          * Right now, we simply care about how many we'll get; we'll
4548          * set them up later while requesting irq's.
4549          */
4550         while (vectors >= vector_threshold) {
4551                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4552                                       vectors);
4553                 if (!err) /* Success in acquiring all requested vectors. */
4554                         break;
4555                 else if (err < 0)
4556                         vectors = 0; /* Nasty failure, quit now */
4557                 else /* err == number of vectors we should try again with */
4558                         vectors = err;
4559         }
4560
4561         if (vectors < vector_threshold) {
4562                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4563                  * This just means we'll go with either a single MSI
4564                  * vector or fall back to legacy interrupts.
4565                  */
4566                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4567                              "Unable to allocate MSI-X interrupts\n");
4568                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4569                 kfree(adapter->msix_entries);
4570                 adapter->msix_entries = NULL;
4571         } else {
4572                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4573                 /*
4574                  * Adjust for only the vectors we'll use, which is minimum
4575                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4576                  * vectors we were allocated.
4577                  */
4578                 adapter->num_msix_vectors = min(vectors,
4579                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4580         }
4581 }
4582
4583 /**
4584  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4585  * @adapter: board private structure to initialize
4586  *
4587  * Cache the descriptor ring offsets for RSS to the assigned rings.
4588  *
4589  **/
4590 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4591 {
4592         int i;
4593
4594         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4595                 return false;
4596
4597         for (i = 0; i < adapter->num_rx_queues; i++)
4598                 adapter->rx_ring[i]->reg_idx = i;
4599         for (i = 0; i < adapter->num_tx_queues; i++)
4600                 adapter->tx_ring[i]->reg_idx = i;
4601
4602         return true;
4603 }
4604
4605 #ifdef CONFIG_IXGBE_DCB
4606
4607 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4608 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4609                                     unsigned int *tx, unsigned int *rx)
4610 {
4611         struct net_device *dev = adapter->netdev;
4612         struct ixgbe_hw *hw = &adapter->hw;
4613         u8 num_tcs = netdev_get_num_tc(dev);
4614
4615         *tx = 0;
4616         *rx = 0;
4617
4618         switch (hw->mac.type) {
4619         case ixgbe_mac_82598EB:
4620                 *tx = tc << 3;
4621                 *rx = tc << 2;
4622                 break;
4623         case ixgbe_mac_82599EB:
4624         case ixgbe_mac_X540:
4625                 if (num_tcs == 8) {
4626                         if (tc < 3) {
4627                                 *tx = tc << 5;
4628                                 *rx = tc << 4;
4629                         } else if (tc <  5) {
4630                                 *tx = ((tc + 2) << 4);
4631                                 *rx = tc << 4;
4632                         } else if (tc < num_tcs) {
4633                                 *tx = ((tc + 8) << 3);
4634                                 *rx = tc << 4;
4635                         }
4636                 } else if (num_tcs == 4) {
4637                         *rx =  tc << 5;
4638                         switch (tc) {
4639                         case 0:
4640                                 *tx =  0;
4641                                 break;
4642                         case 1:
4643                                 *tx = 64;
4644                                 break;
4645                         case 2:
4646                                 *tx = 96;
4647                                 break;
4648                         case 3:
4649                                 *tx = 112;
4650                                 break;
4651                         default:
4652                                 break;
4653                         }
4654                 }
4655                 break;
4656         default:
4657                 break;
4658         }
4659 }
4660
4661 #define IXGBE_MAX_Q_PER_TC      (IXGBE_MAX_DCB_INDICES / MAX_TRAFFIC_CLASS)
4662
4663 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
4664  * classes.
4665  *
4666  * @netdev: net device to configure
4667  * @tc: number of traffic classes to enable
4668  */
4669 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
4670 {
4671         int i;
4672         unsigned int q, offset = 0;
4673
4674         if (!tc) {
4675                 netdev_reset_tc(dev);
4676         } else {
4677                 struct ixgbe_adapter *adapter = netdev_priv(dev);
4678
4679                 /* Hardware supports up to 8 traffic classes */
4680                 if (tc > MAX_TRAFFIC_CLASS || netdev_set_num_tc(dev, tc))
4681                         return -EINVAL;
4682
4683                 /* Partition Tx queues evenly amongst traffic classes */
4684                 for (i = 0; i < tc; i++) {
4685                         q = min((int)num_online_cpus(), IXGBE_MAX_Q_PER_TC);
4686                         netdev_set_prio_tc_map(dev, i, i);
4687                         netdev_set_tc_queue(dev, i, q, offset);
4688                         offset += q;
4689                 }
4690
4691                 /* This enables multiple traffic class support in the hardware
4692                  * which defaults to strict priority transmission by default.
4693                  * If traffic classes are already enabled perhaps through DCB
4694                  * code path then existing configuration will be used.
4695                  */
4696                 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
4697                     dev->dcbnl_ops && dev->dcbnl_ops->setdcbx) {
4698                         struct ieee_ets ets = {
4699                                         .prio_tc = {0, 1, 2, 3, 4, 5, 6, 7},
4700                                               };
4701                         u8 mode = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
4702
4703                         dev->dcbnl_ops->setdcbx(dev, mode);
4704                         dev->dcbnl_ops->ieee_setets(dev, &ets);
4705                 }
4706         }
4707         return 0;
4708 }
4709
4710 /**
4711  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4712  * @adapter: board private structure to initialize
4713  *
4714  * Cache the descriptor ring offsets for DCB to the assigned rings.
4715  *
4716  **/
4717 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4718 {
4719         struct net_device *dev = adapter->netdev;
4720         int i, j, k;
4721         u8 num_tcs = netdev_get_num_tc(dev);
4722
4723         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
4724                 return false;
4725
4726         for (i = 0, k = 0; i < num_tcs; i++) {
4727                 unsigned int tx_s, rx_s;
4728                 u16 count = dev->tc_to_txq[i].count;
4729
4730                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4731                 for (j = 0; j < count; j++, k++) {
4732                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4733                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4734                         adapter->tx_ring[k]->dcb_tc = i;
4735                         adapter->rx_ring[k]->dcb_tc = i;
4736                 }
4737         }
4738
4739         return true;
4740 }
4741 #endif
4742
4743 /**
4744  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4745  * @adapter: board private structure to initialize
4746  *
4747  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4748  *
4749  **/
4750 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4751 {
4752         int i;
4753         bool ret = false;
4754
4755         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4756             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4757              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4758                 for (i = 0; i < adapter->num_rx_queues; i++)
4759                         adapter->rx_ring[i]->reg_idx = i;
4760                 for (i = 0; i < adapter->num_tx_queues; i++)
4761                         adapter->tx_ring[i]->reg_idx = i;
4762                 ret = true;
4763         }
4764
4765         return ret;
4766 }
4767
4768 #ifdef IXGBE_FCOE
4769 /**
4770  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4771  * @adapter: board private structure to initialize
4772  *
4773  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4774  *
4775  */
4776 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4777 {
4778         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4779         int i;
4780         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4781
4782         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4783                 return false;
4784
4785         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4786                 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4787                     (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4788                         ixgbe_cache_ring_fdir(adapter);
4789                 else
4790                         ixgbe_cache_ring_rss(adapter);
4791
4792                 fcoe_rx_i = f->mask;
4793                 fcoe_tx_i = f->mask;
4794         }
4795         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4796                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4797                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4798         }
4799         return true;
4800 }
4801
4802 #endif /* IXGBE_FCOE */
4803 /**
4804  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4805  * @adapter: board private structure to initialize
4806  *
4807  * SR-IOV doesn't use any descriptor rings but changes the default if
4808  * no other mapping is used.
4809  *
4810  */
4811 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4812 {
4813         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4814         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4815         if (adapter->num_vfs)
4816                 return true;
4817         else
4818                 return false;
4819 }
4820
4821 /**
4822  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4823  * @adapter: board private structure to initialize
4824  *
4825  * Once we know the feature-set enabled for the device, we'll cache
4826  * the register offset the descriptor ring is assigned to.
4827  *
4828  * Note, the order the various feature calls is important.  It must start with
4829  * the "most" features enabled at the same time, then trickle down to the
4830  * least amount of features turned on at once.
4831  **/
4832 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4833 {
4834         /* start with default case */
4835         adapter->rx_ring[0]->reg_idx = 0;
4836         adapter->tx_ring[0]->reg_idx = 0;
4837
4838         if (ixgbe_cache_ring_sriov(adapter))
4839                 return;
4840
4841 #ifdef CONFIG_IXGBE_DCB
4842         if (ixgbe_cache_ring_dcb(adapter))
4843                 return;
4844 #endif
4845
4846 #ifdef IXGBE_FCOE
4847         if (ixgbe_cache_ring_fcoe(adapter))
4848                 return;
4849 #endif /* IXGBE_FCOE */
4850
4851         if (ixgbe_cache_ring_fdir(adapter))
4852                 return;
4853
4854         if (ixgbe_cache_ring_rss(adapter))
4855                 return;
4856 }
4857
4858 /**
4859  * ixgbe_alloc_queues - Allocate memory for all rings
4860  * @adapter: board private structure to initialize
4861  *
4862  * We allocate one ring per queue at run-time since we don't know the
4863  * number of queues at compile-time.  The polling_netdev array is
4864  * intended for Multiqueue, but should work fine with a single queue.
4865  **/
4866 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4867 {
4868         int rx = 0, tx = 0, nid = adapter->node;
4869
4870         if (nid < 0 || !node_online(nid))
4871                 nid = first_online_node;
4872
4873         for (; tx < adapter->num_tx_queues; tx++) {
4874                 struct ixgbe_ring *ring;
4875
4876                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4877                 if (!ring)
4878                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4879                 if (!ring)
4880                         goto err_allocation;
4881                 ring->count = adapter->tx_ring_count;
4882                 ring->queue_index = tx;
4883                 ring->numa_node = nid;
4884                 ring->dev = &adapter->pdev->dev;
4885                 ring->netdev = adapter->netdev;
4886
4887                 adapter->tx_ring[tx] = ring;
4888         }
4889
4890         for (; rx < adapter->num_rx_queues; rx++) {
4891                 struct ixgbe_ring *ring;
4892
4893                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4894                 if (!ring)
4895                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4896                 if (!ring)
4897                         goto err_allocation;
4898                 ring->count = adapter->rx_ring_count;
4899                 ring->queue_index = rx;
4900                 ring->numa_node = nid;
4901                 ring->dev = &adapter->pdev->dev;
4902                 ring->netdev = adapter->netdev;
4903
4904                 adapter->rx_ring[rx] = ring;
4905         }
4906
4907         ixgbe_cache_ring_register(adapter);
4908
4909         return 0;
4910
4911 err_allocation:
4912         while (tx)
4913                 kfree(adapter->tx_ring[--tx]);
4914
4915         while (rx)
4916                 kfree(adapter->rx_ring[--rx]);
4917         return -ENOMEM;
4918 }
4919
4920 /**
4921  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4922  * @adapter: board private structure to initialize
4923  *
4924  * Attempt to configure the interrupts using the best available
4925  * capabilities of the hardware and the kernel.
4926  **/
4927 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4928 {
4929         struct ixgbe_hw *hw = &adapter->hw;
4930         int err = 0;
4931         int vector, v_budget;
4932
4933         /*
4934          * It's easy to be greedy for MSI-X vectors, but it really
4935          * doesn't do us much good if we have a lot more vectors
4936          * than CPU's.  So let's be conservative and only ask for
4937          * (roughly) the same number of vectors as there are CPU's.
4938          */
4939         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4940                        (int)num_online_cpus()) + NON_Q_VECTORS;
4941
4942         /*
4943          * At the same time, hardware can only support a maximum of
4944          * hw.mac->max_msix_vectors vectors.  With features
4945          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4946          * descriptor queues supported by our device.  Thus, we cap it off in
4947          * those rare cases where the cpu count also exceeds our vector limit.
4948          */
4949         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4950
4951         /* A failure in MSI-X entry allocation isn't fatal, but it does
4952          * mean we disable MSI-X capabilities of the adapter. */
4953         adapter->msix_entries = kcalloc(v_budget,
4954                                         sizeof(struct msix_entry), GFP_KERNEL);
4955         if (adapter->msix_entries) {
4956                 for (vector = 0; vector < v_budget; vector++)
4957                         adapter->msix_entries[vector].entry = vector;
4958
4959                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4960
4961                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4962                         goto out;
4963         }
4964
4965         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4966         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4967         if (adapter->flags & (IXGBE_FLAG_FDIR_HASH_CAPABLE |
4968                               IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
4969                 e_err(probe,
4970                       "Flow Director is not supported while multiple "
4971                       "queues are disabled.  Disabling Flow Director\n");
4972         }
4973         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4974         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4975         adapter->atr_sample_rate = 0;
4976         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4977                 ixgbe_disable_sriov(adapter);
4978
4979         err = ixgbe_set_num_queues(adapter);
4980         if (err)
4981                 return err;
4982
4983         err = pci_enable_msi(adapter->pdev);
4984         if (!err) {
4985                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4986         } else {
4987                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4988                              "Unable to allocate MSI interrupt, "
4989                              "falling back to legacy.  Error: %d\n", err);
4990                 /* reset err */
4991                 err = 0;
4992         }
4993
4994 out:
4995         return err;
4996 }
4997
4998 /**
4999  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
5000  * @adapter: board private structure to initialize
5001  *
5002  * We allocate one q_vector per queue interrupt.  If allocation fails we
5003  * return -ENOMEM.
5004  **/
5005 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
5006 {
5007         int q_idx, num_q_vectors;
5008         struct ixgbe_q_vector *q_vector;
5009         int (*poll)(struct napi_struct *, int);
5010
5011         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5012                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5013                 poll = &ixgbe_clean_rxtx_many;
5014         } else {
5015                 num_q_vectors = 1;
5016                 poll = &ixgbe_poll;
5017         }
5018
5019         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5020                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
5021                                         GFP_KERNEL, adapter->node);
5022                 if (!q_vector)
5023                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
5024                                            GFP_KERNEL);
5025                 if (!q_vector)
5026                         goto err_out;
5027                 q_vector->adapter = adapter;
5028                 if (q_vector->txr_count && !q_vector->rxr_count)
5029                         q_vector->eitr = adapter->tx_eitr_param;
5030                 else
5031                         q_vector->eitr = adapter->rx_eitr_param;
5032                 q_vector->v_idx = q_idx;
5033                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
5034                 adapter->q_vector[q_idx] = q_vector;
5035         }
5036
5037         return 0;
5038
5039 err_out:
5040         while (q_idx) {
5041                 q_idx--;
5042                 q_vector = adapter->q_vector[q_idx];
5043                 netif_napi_del(&q_vector->napi);
5044                 kfree(q_vector);
5045                 adapter->q_vector[q_idx] = NULL;
5046         }
5047         return -ENOMEM;
5048 }
5049
5050 /**
5051  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5052  * @adapter: board private structure to initialize
5053  *
5054  * This function frees the memory allocated to the q_vectors.  In addition if
5055  * NAPI is enabled it will delete any references to the NAPI struct prior
5056  * to freeing the q_vector.
5057  **/
5058 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5059 {
5060         int q_idx, num_q_vectors;
5061
5062         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5063                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5064         else
5065                 num_q_vectors = 1;
5066
5067         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5068                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
5069                 adapter->q_vector[q_idx] = NULL;
5070                 netif_napi_del(&q_vector->napi);
5071                 kfree(q_vector);
5072         }
5073 }
5074
5075 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
5076 {
5077         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5078                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5079                 pci_disable_msix(adapter->pdev);
5080                 kfree(adapter->msix_entries);
5081                 adapter->msix_entries = NULL;
5082         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5083                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5084                 pci_disable_msi(adapter->pdev);
5085         }
5086 }
5087
5088 /**
5089  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5090  * @adapter: board private structure to initialize
5091  *
5092  * We determine which interrupt scheme to use based on...
5093  * - Kernel support (MSI, MSI-X)
5094  *   - which can be user-defined (via MODULE_PARAM)
5095  * - Hardware queue count (num_*_queues)
5096  *   - defined by miscellaneous hardware support/features (RSS, etc.)
5097  **/
5098 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
5099 {
5100         int err;
5101
5102         /* Number of supported queues */
5103         err = ixgbe_set_num_queues(adapter);
5104         if (err)
5105                 return err;
5106
5107         err = ixgbe_set_interrupt_capability(adapter);
5108         if (err) {
5109                 e_dev_err("Unable to setup interrupt capabilities\n");
5110                 goto err_set_interrupt;
5111         }
5112
5113         err = ixgbe_alloc_q_vectors(adapter);
5114         if (err) {
5115                 e_dev_err("Unable to allocate memory for queue vectors\n");
5116                 goto err_alloc_q_vectors;
5117         }
5118
5119         err = ixgbe_alloc_queues(adapter);
5120         if (err) {
5121                 e_dev_err("Unable to allocate memory for queues\n");
5122                 goto err_alloc_queues;
5123         }
5124
5125         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5126                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5127                    adapter->num_rx_queues, adapter->num_tx_queues);
5128
5129         set_bit(__IXGBE_DOWN, &adapter->state);
5130
5131         return 0;
5132
5133 err_alloc_queues:
5134         ixgbe_free_q_vectors(adapter);
5135 err_alloc_q_vectors:
5136         ixgbe_reset_interrupt_capability(adapter);
5137 err_set_interrupt:
5138         return err;
5139 }
5140
5141 /**
5142  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5143  * @adapter: board private structure to clear interrupt scheme on
5144  *
5145  * We go through and clear interrupt specific resources and reset the structure
5146  * to pre-load conditions
5147  **/
5148 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5149 {
5150         int i;
5151
5152         for (i = 0; i < adapter->num_tx_queues; i++) {
5153                 kfree(adapter->tx_ring[i]);
5154                 adapter->tx_ring[i] = NULL;
5155         }
5156         for (i = 0; i < adapter->num_rx_queues; i++) {
5157                 struct ixgbe_ring *ring = adapter->rx_ring[i];
5158
5159                 /* ixgbe_get_stats64() might access this ring, we must wait
5160                  * a grace period before freeing it.
5161                  */
5162                 kfree_rcu(ring, rcu);
5163                 adapter->rx_ring[i] = NULL;
5164         }
5165
5166         adapter->num_tx_queues = 0;
5167         adapter->num_rx_queues = 0;
5168
5169         ixgbe_free_q_vectors(adapter);
5170         ixgbe_reset_interrupt_capability(adapter);
5171 }
5172
5173 /**
5174  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5175  * @adapter: board private structure to initialize
5176  *
5177  * ixgbe_sw_init initializes the Adapter private data structure.
5178  * Fields are initialized based on PCI device information and
5179  * OS network device settings (MTU size).
5180  **/
5181 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5182 {
5183         struct ixgbe_hw *hw = &adapter->hw;
5184         struct pci_dev *pdev = adapter->pdev;
5185         struct net_device *dev = adapter->netdev;
5186         unsigned int rss;
5187 #ifdef CONFIG_IXGBE_DCB
5188         int j;
5189         struct tc_configuration *tc;
5190 #endif
5191         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5192
5193         /* PCI config space info */
5194
5195         hw->vendor_id = pdev->vendor;
5196         hw->device_id = pdev->device;
5197         hw->revision_id = pdev->revision;
5198         hw->subsystem_vendor_id = pdev->subsystem_vendor;
5199         hw->subsystem_device_id = pdev->subsystem_device;
5200
5201         /* Set capability flags */
5202         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5203         adapter->ring_feature[RING_F_RSS].indices = rss;
5204         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5205         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
5206         switch (hw->mac.type) {
5207         case ixgbe_mac_82598EB:
5208                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5209                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5210                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5211                 break;
5212         case ixgbe_mac_82599EB:
5213         case ixgbe_mac_X540:
5214                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5215                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5216                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5217                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5218                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5219                 /* n-tuple support exists, always init our spinlock */
5220                 spin_lock_init(&adapter->fdir_perfect_lock);
5221                 /* Flow Director hash filters enabled */
5222                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5223                 adapter->atr_sample_rate = 20;
5224                 adapter->ring_feature[RING_F_FDIR].indices =
5225                                                          IXGBE_MAX_FDIR_INDICES;
5226                 adapter->fdir_pballoc = 0;
5227 #ifdef IXGBE_FCOE
5228                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5229                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5230                 adapter->ring_feature[RING_F_FCOE].indices = 0;
5231 #ifdef CONFIG_IXGBE_DCB
5232                 /* Default traffic class to use for FCoE */
5233                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5234                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5235 #endif
5236 #endif /* IXGBE_FCOE */
5237                 break;
5238         default:
5239                 break;
5240         }
5241
5242 #ifdef CONFIG_IXGBE_DCB
5243         /* Configure DCB traffic classes */
5244         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5245                 tc = &adapter->dcb_cfg.tc_config[j];
5246                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5247                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5248                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5249                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5250                 tc->dcb_pfc = pfc_disabled;
5251         }
5252         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5253         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5254         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
5255         adapter->dcb_cfg.pfc_mode_enable = false;
5256         adapter->dcb_set_bitmap = 0x00;
5257         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5258         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5259                            MAX_TRAFFIC_CLASS);
5260
5261 #endif
5262
5263         /* default flow control settings */
5264         hw->fc.requested_mode = ixgbe_fc_full;
5265         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5266 #ifdef CONFIG_DCB
5267         adapter->last_lfc_mode = hw->fc.current_mode;
5268 #endif
5269         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5270         hw->fc.low_water = FC_LOW_WATER(max_frame);
5271         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5272         hw->fc.send_xon = true;
5273         hw->fc.disable_fc_autoneg = false;
5274
5275         /* enable itr by default in dynamic mode */
5276         adapter->rx_itr_setting = 1;
5277         adapter->rx_eitr_param = 20000;
5278         adapter->tx_itr_setting = 1;
5279         adapter->tx_eitr_param = 10000;
5280
5281         /* set defaults for eitr in MegaBytes */
5282         adapter->eitr_low = 10;
5283         adapter->eitr_high = 20;
5284
5285         /* set default ring sizes */
5286         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5287         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5288
5289         /* initialize eeprom parameters */
5290         if (ixgbe_init_eeprom_params_generic(hw)) {
5291                 e_dev_err("EEPROM initialization failed\n");
5292                 return -EIO;
5293         }
5294
5295         /* enable rx csum by default */
5296         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5297
5298         /* get assigned NUMA node */
5299         adapter->node = dev_to_node(&pdev->dev);
5300
5301         set_bit(__IXGBE_DOWN, &adapter->state);
5302
5303         return 0;
5304 }
5305
5306 /**
5307  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5308  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5309  *
5310  * Return 0 on success, negative on failure
5311  **/
5312 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5313 {
5314         struct device *dev = tx_ring->dev;
5315         int size;
5316
5317         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5318         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5319         if (!tx_ring->tx_buffer_info)
5320                 tx_ring->tx_buffer_info = vzalloc(size);
5321         if (!tx_ring->tx_buffer_info)
5322                 goto err;
5323
5324         /* round up to nearest 4K */
5325         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5326         tx_ring->size = ALIGN(tx_ring->size, 4096);
5327
5328         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5329                                            &tx_ring->dma, GFP_KERNEL);
5330         if (!tx_ring->desc)
5331                 goto err;
5332
5333         tx_ring->next_to_use = 0;
5334         tx_ring->next_to_clean = 0;
5335         tx_ring->work_limit = tx_ring->count;
5336         return 0;
5337
5338 err:
5339         vfree(tx_ring->tx_buffer_info);
5340         tx_ring->tx_buffer_info = NULL;
5341         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5342         return -ENOMEM;
5343 }
5344
5345 /**
5346  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5347  * @adapter: board private structure
5348  *
5349  * If this function returns with an error, then it's possible one or
5350  * more of the rings is populated (while the rest are not).  It is the
5351  * callers duty to clean those orphaned rings.
5352  *
5353  * Return 0 on success, negative on failure
5354  **/
5355 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5356 {
5357         int i, err = 0;
5358
5359         for (i = 0; i < adapter->num_tx_queues; i++) {
5360                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5361                 if (!err)
5362                         continue;
5363                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5364                 break;
5365         }
5366
5367         return err;
5368 }
5369
5370 /**
5371  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5372  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5373  *
5374  * Returns 0 on success, negative on failure
5375  **/
5376 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5377 {
5378         struct device *dev = rx_ring->dev;
5379         int size;
5380
5381         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5382         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5383         if (!rx_ring->rx_buffer_info)
5384                 rx_ring->rx_buffer_info = vzalloc(size);
5385         if (!rx_ring->rx_buffer_info)
5386                 goto err;
5387
5388         /* Round up to nearest 4K */
5389         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5390         rx_ring->size = ALIGN(rx_ring->size, 4096);
5391
5392         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5393                                            &rx_ring->dma, GFP_KERNEL);
5394
5395         if (!rx_ring->desc)
5396                 goto err;
5397
5398         rx_ring->next_to_clean = 0;
5399         rx_ring->next_to_use = 0;
5400
5401         return 0;
5402 err:
5403         vfree(rx_ring->rx_buffer_info);
5404         rx_ring->rx_buffer_info = NULL;
5405         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5406         return -ENOMEM;
5407 }
5408
5409 /**
5410  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5411  * @adapter: board private structure
5412  *
5413  * If this function returns with an error, then it's possible one or
5414  * more of the rings is populated (while the rest are not).  It is the
5415  * callers duty to clean those orphaned rings.
5416  *
5417  * Return 0 on success, negative on failure
5418  **/
5419 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5420 {
5421         int i, err = 0;
5422
5423         for (i = 0; i < adapter->num_rx_queues; i++) {
5424                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5425                 if (!err)
5426                         continue;
5427                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5428                 break;
5429         }
5430
5431         return err;
5432 }
5433
5434 /**
5435  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5436  * @tx_ring: Tx descriptor ring for a specific queue
5437  *
5438  * Free all transmit software resources
5439  **/
5440 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5441 {
5442         ixgbe_clean_tx_ring(tx_ring);
5443
5444         vfree(tx_ring->tx_buffer_info);
5445         tx_ring->tx_buffer_info = NULL;
5446
5447         /* if not set, then don't free */
5448         if (!tx_ring->desc)
5449                 return;
5450
5451         dma_free_coherent(tx_ring->dev, tx_ring->size,
5452                           tx_ring->desc, tx_ring->dma);
5453
5454         tx_ring->desc = NULL;
5455 }
5456
5457 /**
5458  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5459  * @adapter: board private structure
5460  *
5461  * Free all transmit software resources
5462  **/
5463 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5464 {
5465         int i;
5466
5467         for (i = 0; i < adapter->num_tx_queues; i++)
5468                 if (adapter->tx_ring[i]->desc)
5469                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5470 }
5471
5472 /**
5473  * ixgbe_free_rx_resources - Free Rx Resources
5474  * @rx_ring: ring to clean the resources from
5475  *
5476  * Free all receive software resources
5477  **/
5478 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5479 {
5480         ixgbe_clean_rx_ring(rx_ring);
5481
5482         vfree(rx_ring->rx_buffer_info);
5483         rx_ring->rx_buffer_info = NULL;
5484
5485         /* if not set, then don't free */
5486         if (!rx_ring->desc)
5487                 return;
5488
5489         dma_free_coherent(rx_ring->dev, rx_ring->size,
5490                           rx_ring->desc, rx_ring->dma);
5491
5492         rx_ring->desc = NULL;
5493 }
5494
5495 /**
5496  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5497  * @adapter: board private structure
5498  *
5499  * Free all receive software resources
5500  **/
5501 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5502 {
5503         int i;
5504
5505         for (i = 0; i < adapter->num_rx_queues; i++)
5506                 if (adapter->rx_ring[i]->desc)
5507                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5508 }
5509
5510 /**
5511  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5512  * @netdev: network interface device structure
5513  * @new_mtu: new value for maximum frame size
5514  *
5515  * Returns 0 on success, negative on failure
5516  **/
5517 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5518 {
5519         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5520         struct ixgbe_hw *hw = &adapter->hw;
5521         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5522
5523         /* MTU < 68 is an error and causes problems on some kernels */
5524         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5525             hw->mac.type != ixgbe_mac_X540) {
5526                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5527                         return -EINVAL;
5528         } else {
5529                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5530                         return -EINVAL;
5531         }
5532
5533         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5534         /* must set new MTU before calling down or up */
5535         netdev->mtu = new_mtu;
5536
5537         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5538         hw->fc.low_water = FC_LOW_WATER(max_frame);
5539
5540         if (netif_running(netdev))
5541                 ixgbe_reinit_locked(adapter);
5542
5543         return 0;
5544 }
5545
5546 /**
5547  * ixgbe_open - Called when a network interface is made active
5548  * @netdev: network interface device structure
5549  *
5550  * Returns 0 on success, negative value on failure
5551  *
5552  * The open entry point is called when a network interface is made
5553  * active by the system (IFF_UP).  At this point all resources needed
5554  * for transmit and receive operations are allocated, the interrupt
5555  * handler is registered with the OS, the watchdog timer is started,
5556  * and the stack is notified that the interface is ready.
5557  **/
5558 static int ixgbe_open(struct net_device *netdev)
5559 {
5560         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5561         int err;
5562
5563         /* disallow open during test */
5564         if (test_bit(__IXGBE_TESTING, &adapter->state))
5565                 return -EBUSY;
5566
5567         netif_carrier_off(netdev);
5568
5569         /* allocate transmit descriptors */
5570         err = ixgbe_setup_all_tx_resources(adapter);
5571         if (err)
5572                 goto err_setup_tx;
5573
5574         /* allocate receive descriptors */
5575         err = ixgbe_setup_all_rx_resources(adapter);
5576         if (err)
5577                 goto err_setup_rx;
5578
5579         ixgbe_configure(adapter);
5580
5581         err = ixgbe_request_irq(adapter);
5582         if (err)
5583                 goto err_req_irq;
5584
5585         err = ixgbe_up_complete(adapter);
5586         if (err)
5587                 goto err_up;
5588
5589         netif_tx_start_all_queues(netdev);
5590
5591         return 0;
5592
5593 err_up:
5594         ixgbe_release_hw_control(adapter);
5595         ixgbe_free_irq(adapter);
5596 err_req_irq:
5597 err_setup_rx:
5598         ixgbe_free_all_rx_resources(adapter);
5599 err_setup_tx:
5600         ixgbe_free_all_tx_resources(adapter);
5601         ixgbe_reset(adapter);
5602
5603         return err;
5604 }
5605
5606 /**
5607  * ixgbe_close - Disables a network interface
5608  * @netdev: network interface device structure
5609  *
5610  * Returns 0, this is not allowed to fail
5611  *
5612  * The close entry point is called when an interface is de-activated
5613  * by the OS.  The hardware is still under the drivers control, but
5614  * needs to be disabled.  A global MAC reset is issued to stop the
5615  * hardware, and all transmit and receive resources are freed.
5616  **/
5617 static int ixgbe_close(struct net_device *netdev)
5618 {
5619         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5620
5621         ixgbe_down(adapter);
5622         ixgbe_free_irq(adapter);
5623
5624         ixgbe_free_all_tx_resources(adapter);
5625         ixgbe_free_all_rx_resources(adapter);
5626
5627         ixgbe_release_hw_control(adapter);
5628
5629         return 0;
5630 }
5631
5632 #ifdef CONFIG_PM
5633 static int ixgbe_resume(struct pci_dev *pdev)
5634 {
5635         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5636         struct net_device *netdev = adapter->netdev;
5637         u32 err;
5638
5639         pci_set_power_state(pdev, PCI_D0);
5640         pci_restore_state(pdev);
5641         /*
5642          * pci_restore_state clears dev->state_saved so call
5643          * pci_save_state to restore it.
5644          */
5645         pci_save_state(pdev);
5646
5647         err = pci_enable_device_mem(pdev);
5648         if (err) {
5649                 e_dev_err("Cannot enable PCI device from suspend\n");
5650                 return err;
5651         }
5652         pci_set_master(pdev);
5653
5654         pci_wake_from_d3(pdev, false);
5655
5656         err = ixgbe_init_interrupt_scheme(adapter);
5657         if (err) {
5658                 e_dev_err("Cannot initialize interrupts for device\n");
5659                 return err;
5660         }
5661
5662         ixgbe_reset(adapter);
5663
5664         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5665
5666         if (netif_running(netdev)) {
5667                 err = ixgbe_open(netdev);
5668                 if (err)
5669                         return err;
5670         }
5671
5672         netif_device_attach(netdev);
5673
5674         return 0;
5675 }
5676 #endif /* CONFIG_PM */
5677
5678 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5679 {
5680         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5681         struct net_device *netdev = adapter->netdev;
5682         struct ixgbe_hw *hw = &adapter->hw;
5683         u32 ctrl, fctrl;
5684         u32 wufc = adapter->wol;
5685 #ifdef CONFIG_PM
5686         int retval = 0;
5687 #endif
5688
5689         netif_device_detach(netdev);
5690
5691         if (netif_running(netdev)) {
5692                 ixgbe_down(adapter);
5693                 ixgbe_free_irq(adapter);
5694                 ixgbe_free_all_tx_resources(adapter);
5695                 ixgbe_free_all_rx_resources(adapter);
5696         }
5697
5698         ixgbe_clear_interrupt_scheme(adapter);
5699 #ifdef CONFIG_DCB
5700         kfree(adapter->ixgbe_ieee_pfc);
5701         kfree(adapter->ixgbe_ieee_ets);
5702 #endif
5703
5704 #ifdef CONFIG_PM
5705         retval = pci_save_state(pdev);
5706         if (retval)
5707                 return retval;
5708
5709 #endif
5710         if (wufc) {
5711                 ixgbe_set_rx_mode(netdev);
5712
5713                 /* turn on all-multi mode if wake on multicast is enabled */
5714                 if (wufc & IXGBE_WUFC_MC) {
5715                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5716                         fctrl |= IXGBE_FCTRL_MPE;
5717                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5718                 }
5719
5720                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5721                 ctrl |= IXGBE_CTRL_GIO_DIS;
5722                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5723
5724                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5725         } else {
5726                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5727                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5728         }
5729
5730         switch (hw->mac.type) {
5731         case ixgbe_mac_82598EB:
5732                 pci_wake_from_d3(pdev, false);
5733                 break;
5734         case ixgbe_mac_82599EB:
5735         case ixgbe_mac_X540:
5736                 pci_wake_from_d3(pdev, !!wufc);
5737                 break;
5738         default:
5739                 break;
5740         }
5741
5742         *enable_wake = !!wufc;
5743
5744         ixgbe_release_hw_control(adapter);
5745
5746         pci_disable_device(pdev);
5747
5748         return 0;
5749 }
5750
5751 #ifdef CONFIG_PM
5752 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5753 {
5754         int retval;
5755         bool wake;
5756
5757         retval = __ixgbe_shutdown(pdev, &wake);
5758         if (retval)
5759                 return retval;
5760
5761         if (wake) {
5762                 pci_prepare_to_sleep(pdev);
5763         } else {
5764                 pci_wake_from_d3(pdev, false);
5765                 pci_set_power_state(pdev, PCI_D3hot);
5766         }
5767
5768         return 0;
5769 }
5770 #endif /* CONFIG_PM */
5771
5772 static void ixgbe_shutdown(struct pci_dev *pdev)
5773 {
5774         bool wake;
5775
5776         __ixgbe_shutdown(pdev, &wake);
5777
5778         if (system_state == SYSTEM_POWER_OFF) {
5779                 pci_wake_from_d3(pdev, wake);
5780                 pci_set_power_state(pdev, PCI_D3hot);
5781         }
5782 }
5783
5784 /**
5785  * ixgbe_update_stats - Update the board statistics counters.
5786  * @adapter: board private structure
5787  **/
5788 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5789 {
5790         struct net_device *netdev = adapter->netdev;
5791         struct ixgbe_hw *hw = &adapter->hw;
5792         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5793         u64 total_mpc = 0;
5794         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5795         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5796         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5797         u64 bytes = 0, packets = 0;
5798
5799         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5800             test_bit(__IXGBE_RESETTING, &adapter->state))
5801                 return;
5802
5803         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5804                 u64 rsc_count = 0;
5805                 u64 rsc_flush = 0;
5806                 for (i = 0; i < 16; i++)
5807                         adapter->hw_rx_no_dma_resources +=
5808                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5809                 for (i = 0; i < adapter->num_rx_queues; i++) {
5810                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5811                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5812                 }
5813                 adapter->rsc_total_count = rsc_count;
5814                 adapter->rsc_total_flush = rsc_flush;
5815         }
5816
5817         for (i = 0; i < adapter->num_rx_queues; i++) {
5818                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5819                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5820                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5821                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5822                 bytes += rx_ring->stats.bytes;
5823                 packets += rx_ring->stats.packets;
5824         }
5825         adapter->non_eop_descs = non_eop_descs;
5826         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5827         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5828         netdev->stats.rx_bytes = bytes;
5829         netdev->stats.rx_packets = packets;
5830
5831         bytes = 0;
5832         packets = 0;
5833         /* gather some stats to the adapter struct that are per queue */
5834         for (i = 0; i < adapter->num_tx_queues; i++) {
5835                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5836                 restart_queue += tx_ring->tx_stats.restart_queue;
5837                 tx_busy += tx_ring->tx_stats.tx_busy;
5838                 bytes += tx_ring->stats.bytes;
5839                 packets += tx_ring->stats.packets;
5840         }
5841         adapter->restart_queue = restart_queue;
5842         adapter->tx_busy = tx_busy;
5843         netdev->stats.tx_bytes = bytes;
5844         netdev->stats.tx_packets = packets;
5845
5846         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5847         for (i = 0; i < 8; i++) {
5848                 /* for packet buffers not used, the register should read 0 */
5849                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5850                 missed_rx += mpc;
5851                 hwstats->mpc[i] += mpc;
5852                 total_mpc += hwstats->mpc[i];
5853                 if (hw->mac.type == ixgbe_mac_82598EB)
5854                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5855                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5856                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5857                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5858                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5859                 switch (hw->mac.type) {
5860                 case ixgbe_mac_82598EB:
5861                         hwstats->pxonrxc[i] +=
5862                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5863                         break;
5864                 case ixgbe_mac_82599EB:
5865                 case ixgbe_mac_X540:
5866                         hwstats->pxonrxc[i] +=
5867                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5868                         break;
5869                 default:
5870                         break;
5871                 }
5872                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5873                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5874         }
5875         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5876         /* work around hardware counting issue */
5877         hwstats->gprc -= missed_rx;
5878
5879         ixgbe_update_xoff_received(adapter);
5880
5881         /* 82598 hardware only has a 32 bit counter in the high register */
5882         switch (hw->mac.type) {
5883         case ixgbe_mac_82598EB:
5884                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5885                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5886                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5887                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5888                 break;
5889         case ixgbe_mac_X540:
5890                 /* OS2BMC stats are X540 only*/
5891                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5892                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5893                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5894                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5895         case ixgbe_mac_82599EB:
5896                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5897                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5898                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5899                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5900                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5901                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5902                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5903                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5904                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5905 #ifdef IXGBE_FCOE
5906                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5907                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5908                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5909                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5910                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5911                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5912 #endif /* IXGBE_FCOE */
5913                 break;
5914         default:
5915                 break;
5916         }
5917         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5918         hwstats->bprc += bprc;
5919         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5920         if (hw->mac.type == ixgbe_mac_82598EB)
5921                 hwstats->mprc -= bprc;
5922         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5923         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5924         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5925         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5926         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5927         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5928         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5929         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5930         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5931         hwstats->lxontxc += lxon;
5932         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5933         hwstats->lxofftxc += lxoff;
5934         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5935         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5936         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5937         /*
5938          * 82598 errata - tx of flow control packets is included in tx counters
5939          */
5940         xon_off_tot = lxon + lxoff;
5941         hwstats->gptc -= xon_off_tot;
5942         hwstats->mptc -= xon_off_tot;
5943         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5944         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5945         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5946         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5947         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5948         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5949         hwstats->ptc64 -= xon_off_tot;
5950         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5951         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5952         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5953         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5954         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5955         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5956
5957         /* Fill out the OS statistics structure */
5958         netdev->stats.multicast = hwstats->mprc;
5959
5960         /* Rx Errors */
5961         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5962         netdev->stats.rx_dropped = 0;
5963         netdev->stats.rx_length_errors = hwstats->rlec;
5964         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5965         netdev->stats.rx_missed_errors = total_mpc;
5966 }
5967
5968 /**
5969  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5970  * @adapter - pointer to the device adapter structure
5971  **/
5972 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5973 {
5974         struct ixgbe_hw *hw = &adapter->hw;
5975         int i;
5976
5977         if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5978                 return;
5979
5980         adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5981
5982         /* if interface is down do nothing */
5983         if (test_bit(__IXGBE_DOWN, &adapter->state))
5984                 return;
5985
5986         /* do nothing if we are not using signature filters */
5987         if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5988                 return;
5989
5990         adapter->fdir_overflow++;
5991
5992         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5993                 for (i = 0; i < adapter->num_tx_queues; i++)
5994                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5995                                 &(adapter->tx_ring[i]->state));
5996                 /* re-enable flow director interrupts */
5997                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5998         } else {
5999                 e_err(probe, "failed to finish FDIR re-initialization, "
6000                       "ignored adding FDIR ATR filters\n");
6001         }
6002 }
6003
6004 /**
6005  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6006  * @adapter - pointer to the device adapter structure
6007  *
6008  * This function serves two purposes.  First it strobes the interrupt lines
6009  * in order to make certain interrupts are occuring.  Secondly it sets the
6010  * bits needed to check for TX hangs.  As a result we should immediately
6011  * determine if a hang has occured.
6012  */
6013 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
6014 {
6015         struct ixgbe_hw *hw = &adapter->hw;
6016         u64 eics = 0;
6017         int i;
6018
6019         /* If we're down or resetting, just bail */
6020         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6021             test_bit(__IXGBE_RESETTING, &adapter->state))
6022                 return;
6023
6024         /* Force detection of hung controller */
6025         if (netif_carrier_ok(adapter->netdev)) {
6026                 for (i = 0; i < adapter->num_tx_queues; i++)
6027                         set_check_for_tx_hang(adapter->tx_ring[i]);
6028         }
6029
6030         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6031                 /*
6032                  * for legacy and MSI interrupts don't set any bits
6033                  * that are enabled for EIAM, because this operation
6034                  * would set *both* EIMS and EICS for any bit in EIAM
6035                  */
6036                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6037                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
6038         } else {
6039                 /* get one bit for every active tx/rx interrupt vector */
6040                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6041                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
6042                         if (qv->rxr_count || qv->txr_count)
6043                                 eics |= ((u64)1 << i);
6044                 }
6045         }
6046
6047         /* Cause software interrupt to ensure rings are cleaned */
6048         ixgbe_irq_rearm_queues(adapter, eics);
6049
6050 }
6051
6052 /**
6053  * ixgbe_watchdog_update_link - update the link status
6054  * @adapter - pointer to the device adapter structure
6055  * @link_speed - pointer to a u32 to store the link_speed
6056  **/
6057 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
6058 {
6059         struct ixgbe_hw *hw = &adapter->hw;
6060         u32 link_speed = adapter->link_speed;
6061         bool link_up = adapter->link_up;
6062         int i;
6063
6064         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6065                 return;
6066
6067         if (hw->mac.ops.check_link) {
6068                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6069         } else {
6070                 /* always assume link is up, if no check link function */
6071                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6072                 link_up = true;
6073         }
6074         if (link_up) {
6075                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6076                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6077                                 hw->mac.ops.fc_enable(hw, i);
6078                 } else {
6079                         hw->mac.ops.fc_enable(hw, 0);
6080                 }
6081         }
6082
6083         if (link_up ||
6084             time_after(jiffies, (adapter->link_check_timeout +
6085                                  IXGBE_TRY_LINK_TIMEOUT))) {
6086                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6087                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6088                 IXGBE_WRITE_FLUSH(hw);
6089         }
6090
6091         adapter->link_up = link_up;
6092         adapter->link_speed = link_speed;
6093 }
6094
6095 /**
6096  * ixgbe_watchdog_link_is_up - update netif_carrier status and
6097  *                             print link up message
6098  * @adapter - pointer to the device adapter structure
6099  **/
6100 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6101 {
6102         struct net_device *netdev = adapter->netdev;
6103         struct ixgbe_hw *hw = &adapter->hw;
6104         u32 link_speed = adapter->link_speed;
6105         bool flow_rx, flow_tx;
6106
6107         /* only continue if link was previously down */
6108         if (netif_carrier_ok(netdev))
6109                 return;
6110
6111         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6112
6113         switch (hw->mac.type) {
6114         case ixgbe_mac_82598EB: {
6115                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6116                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6117                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6118                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6119         }
6120                 break;
6121         case ixgbe_mac_X540:
6122         case ixgbe_mac_82599EB: {
6123                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6124                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6125                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6126                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6127         }
6128                 break;
6129         default:
6130                 flow_tx = false;
6131                 flow_rx = false;
6132                 break;
6133         }
6134         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6135                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6136                "10 Gbps" :
6137                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6138                "1 Gbps" :
6139                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6140                "100 Mbps" :
6141                "unknown speed"))),
6142                ((flow_rx && flow_tx) ? "RX/TX" :
6143                (flow_rx ? "RX" :
6144                (flow_tx ? "TX" : "None"))));
6145
6146         netif_carrier_on(netdev);
6147 #ifdef HAVE_IPLINK_VF_CONFIG
6148         ixgbe_check_vf_rate_limit(adapter);
6149 #endif /* HAVE_IPLINK_VF_CONFIG */
6150 }
6151
6152 /**
6153  * ixgbe_watchdog_link_is_down - update netif_carrier status and
6154  *                               print link down message
6155  * @adapter - pointer to the adapter structure
6156  **/
6157 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6158 {
6159         struct net_device *netdev = adapter->netdev;
6160         struct ixgbe_hw *hw = &adapter->hw;
6161
6162         adapter->link_up = false;
6163         adapter->link_speed = 0;
6164
6165         /* only continue if link was up previously */
6166         if (!netif_carrier_ok(netdev))
6167                 return;
6168
6169         /* poll for SFP+ cable when link is down */
6170         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6171                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6172
6173         e_info(drv, "NIC Link is Down\n");
6174         netif_carrier_off(netdev);
6175 }
6176
6177 /**
6178  * ixgbe_watchdog_flush_tx - flush queues on link down
6179  * @adapter - pointer to the device adapter structure
6180  **/
6181 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6182 {
6183         int i;
6184         int some_tx_pending = 0;
6185
6186         if (!netif_carrier_ok(adapter->netdev)) {
6187                 for (i = 0; i < adapter->num_tx_queues; i++) {
6188                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6189                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6190                                 some_tx_pending = 1;
6191                                 break;
6192                         }
6193                 }
6194
6195                 if (some_tx_pending) {
6196                         /* We've lost link, so the controller stops DMA,
6197                          * but we've got queued Tx work that's never going
6198                          * to get done, so reset controller to flush Tx.
6199                          * (Do the reset outside of interrupt context).
6200                          */
6201                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6202                 }
6203         }
6204 }
6205
6206 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6207 {
6208         u32 ssvpc;
6209
6210         /* Do not perform spoof check for 82598 */
6211         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6212                 return;
6213
6214         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6215
6216         /*
6217          * ssvpc register is cleared on read, if zero then no
6218          * spoofed packets in the last interval.
6219          */
6220         if (!ssvpc)
6221                 return;
6222
6223         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6224 }
6225
6226 /**
6227  * ixgbe_watchdog_subtask - check and bring link up
6228  * @adapter - pointer to the device adapter structure
6229  **/
6230 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6231 {
6232         /* if interface is down do nothing */
6233         if (test_bit(__IXGBE_DOWN, &adapter->state))
6234                 return;
6235
6236         ixgbe_watchdog_update_link(adapter);
6237
6238         if (adapter->link_up)
6239                 ixgbe_watchdog_link_is_up(adapter);
6240         else
6241                 ixgbe_watchdog_link_is_down(adapter);
6242
6243         ixgbe_spoof_check(adapter);
6244         ixgbe_update_stats(adapter);
6245
6246         ixgbe_watchdog_flush_tx(adapter);
6247 }
6248
6249 /**
6250  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6251  * @adapter - the ixgbe adapter structure
6252  **/
6253 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6254 {
6255         struct ixgbe_hw *hw = &adapter->hw;
6256         s32 err;
6257
6258         /* not searching for SFP so there is nothing to do here */
6259         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6260             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6261                 return;
6262
6263         /* someone else is in init, wait until next service event */
6264         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6265                 return;
6266
6267         err = hw->phy.ops.identify_sfp(hw);
6268         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6269                 goto sfp_out;
6270
6271         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6272                 /* If no cable is present, then we need to reset
6273                  * the next time we find a good cable. */
6274                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6275         }
6276
6277         /* exit on error */
6278         if (err)
6279                 goto sfp_out;
6280
6281         /* exit if reset not needed */
6282         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6283                 goto sfp_out;
6284
6285         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6286
6287         /*
6288          * A module may be identified correctly, but the EEPROM may not have
6289          * support for that module.  setup_sfp() will fail in that case, so
6290          * we should not allow that module to load.
6291          */
6292         if (hw->mac.type == ixgbe_mac_82598EB)
6293                 err = hw->phy.ops.reset(hw);
6294         else
6295                 err = hw->mac.ops.setup_sfp(hw);
6296
6297         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6298                 goto sfp_out;
6299
6300         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6301         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6302
6303 sfp_out:
6304         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6305
6306         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6307             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6308                 e_dev_err("failed to initialize because an unsupported "
6309                           "SFP+ module type was detected.\n");
6310                 e_dev_err("Reload the driver after installing a "
6311                           "supported module.\n");
6312                 unregister_netdev(adapter->netdev);
6313         }
6314 }
6315
6316 /**
6317  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6318  * @adapter - the ixgbe adapter structure
6319  **/
6320 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6321 {
6322         struct ixgbe_hw *hw = &adapter->hw;
6323         u32 autoneg;
6324         bool negotiation;
6325
6326         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6327                 return;
6328
6329         /* someone else is in init, wait until next service event */
6330         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6331                 return;
6332
6333         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6334
6335         autoneg = hw->phy.autoneg_advertised;
6336         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6337                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6338         hw->mac.autotry_restart = false;
6339         if (hw->mac.ops.setup_link)
6340                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6341
6342         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6343         adapter->link_check_timeout = jiffies;
6344         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6345 }
6346
6347 /**
6348  * ixgbe_service_timer - Timer Call-back
6349  * @data: pointer to adapter cast into an unsigned long
6350  **/
6351 static void ixgbe_service_timer(unsigned long data)
6352 {
6353         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6354         unsigned long next_event_offset;
6355
6356         /* poll faster when waiting for link */
6357         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6358                 next_event_offset = HZ / 10;
6359         else
6360                 next_event_offset = HZ * 2;
6361
6362         /* Reset the timer */
6363         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6364
6365         ixgbe_service_event_schedule(adapter);
6366 }
6367
6368 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6369 {
6370         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6371                 return;
6372
6373         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6374
6375         /* If we're already down or resetting, just bail */
6376         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6377             test_bit(__IXGBE_RESETTING, &adapter->state))
6378                 return;
6379
6380         ixgbe_dump(adapter);
6381         netdev_err(adapter->netdev, "Reset adapter\n");
6382         adapter->tx_timeout_count++;
6383
6384         ixgbe_reinit_locked(adapter);
6385 }
6386
6387 /**
6388  * ixgbe_service_task - manages and runs subtasks
6389  * @work: pointer to work_struct containing our data
6390  **/
6391 static void ixgbe_service_task(struct work_struct *work)
6392 {
6393         struct ixgbe_adapter *adapter = container_of(work,
6394                                                      struct ixgbe_adapter,
6395                                                      service_task);
6396
6397         ixgbe_reset_subtask(adapter);
6398         ixgbe_sfp_detection_subtask(adapter);
6399         ixgbe_sfp_link_config_subtask(adapter);
6400         ixgbe_check_overtemp_subtask(adapter);
6401         ixgbe_watchdog_subtask(adapter);
6402         ixgbe_fdir_reinit_subtask(adapter);
6403         ixgbe_check_hang_subtask(adapter);
6404
6405         ixgbe_service_event_complete(adapter);
6406 }
6407
6408 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6409                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6410                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
6411 {
6412         struct ixgbe_adv_tx_context_desc *context_desc;
6413         unsigned int i;
6414         int err;
6415         struct ixgbe_tx_buffer *tx_buffer_info;
6416         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6417         u32 mss_l4len_idx, l4len;
6418
6419         if (skb_is_gso(skb)) {
6420                 if (skb_header_cloned(skb)) {
6421                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6422                         if (err)
6423                                 return err;
6424                 }
6425                 l4len = tcp_hdrlen(skb);
6426                 *hdr_len += l4len;
6427
6428                 if (protocol == htons(ETH_P_IP)) {
6429                         struct iphdr *iph = ip_hdr(skb);
6430                         iph->tot_len = 0;
6431                         iph->check = 0;
6432                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6433                                                                  iph->daddr, 0,
6434                                                                  IPPROTO_TCP,
6435                                                                  0);
6436                 } else if (skb_is_gso_v6(skb)) {
6437                         ipv6_hdr(skb)->payload_len = 0;
6438                         tcp_hdr(skb)->check =
6439                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6440                                              &ipv6_hdr(skb)->daddr,
6441                                              0, IPPROTO_TCP, 0);
6442                 }
6443
6444                 i = tx_ring->next_to_use;
6445
6446                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6447                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6448
6449                 /* VLAN MACLEN IPLEN */
6450                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6451                         vlan_macip_lens |=
6452                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6453                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6454                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6455                 *hdr_len += skb_network_offset(skb);
6456                 vlan_macip_lens |=
6457                     (skb_transport_header(skb) - skb_network_header(skb));
6458                 *hdr_len +=
6459                     (skb_transport_header(skb) - skb_network_header(skb));
6460                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6461                 context_desc->seqnum_seed = 0;
6462
6463                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6464                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6465                                    IXGBE_ADVTXD_DTYP_CTXT);
6466
6467                 if (protocol == htons(ETH_P_IP))
6468                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6469                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6470                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6471
6472                 /* MSS L4LEN IDX */
6473                 mss_l4len_idx =
6474                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6475                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6476                 /* use index 1 for TSO */
6477                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6478                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6479
6480                 tx_buffer_info->time_stamp = jiffies;
6481                 tx_buffer_info->next_to_watch = i;
6482
6483                 i++;
6484                 if (i == tx_ring->count)
6485                         i = 0;
6486                 tx_ring->next_to_use = i;
6487
6488                 return true;
6489         }
6490         return false;
6491 }
6492
6493 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6494                       __be16 protocol)
6495 {
6496         u32 rtn = 0;
6497
6498         switch (protocol) {
6499         case cpu_to_be16(ETH_P_IP):
6500                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6501                 switch (ip_hdr(skb)->protocol) {
6502                 case IPPROTO_TCP:
6503                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6504                         break;
6505                 case IPPROTO_SCTP:
6506                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6507                         break;
6508                 }
6509                 break;
6510         case cpu_to_be16(ETH_P_IPV6):
6511                 /* XXX what about other V6 headers?? */
6512                 switch (ipv6_hdr(skb)->nexthdr) {
6513                 case IPPROTO_TCP:
6514                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6515                         break;
6516                 case IPPROTO_SCTP:
6517                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6518                         break;
6519                 }
6520                 break;
6521         default:
6522                 if (unlikely(net_ratelimit()))
6523                         e_warn(probe, "partial checksum but proto=%x!\n",
6524                                protocol);
6525                 break;
6526         }
6527
6528         return rtn;
6529 }
6530
6531 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6532                           struct ixgbe_ring *tx_ring,
6533                           struct sk_buff *skb, u32 tx_flags,
6534                           __be16 protocol)
6535 {
6536         struct ixgbe_adv_tx_context_desc *context_desc;
6537         unsigned int i;
6538         struct ixgbe_tx_buffer *tx_buffer_info;
6539         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6540
6541         if (skb->ip_summed == CHECKSUM_PARTIAL ||
6542             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6543                 i = tx_ring->next_to_use;
6544                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6545                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6546
6547                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6548                         vlan_macip_lens |=
6549                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6550                 vlan_macip_lens |= (skb_network_offset(skb) <<
6551                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6552                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6553                         vlan_macip_lens |= (skb_transport_header(skb) -
6554                                             skb_network_header(skb));
6555
6556                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6557                 context_desc->seqnum_seed = 0;
6558
6559                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6560                                     IXGBE_ADVTXD_DTYP_CTXT);
6561
6562                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6563                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6564
6565                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6566                 /* use index zero for tx checksum offload */
6567                 context_desc->mss_l4len_idx = 0;
6568
6569                 tx_buffer_info->time_stamp = jiffies;
6570                 tx_buffer_info->next_to_watch = i;
6571
6572                 i++;
6573                 if (i == tx_ring->count)
6574                         i = 0;
6575                 tx_ring->next_to_use = i;
6576
6577                 return true;
6578         }
6579
6580         return false;
6581 }
6582
6583 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6584                         struct ixgbe_ring *tx_ring,
6585                         struct sk_buff *skb, u32 tx_flags,
6586                         unsigned int first, const u8 hdr_len)
6587 {
6588         struct device *dev = tx_ring->dev;
6589         struct ixgbe_tx_buffer *tx_buffer_info;
6590         unsigned int len;
6591         unsigned int total = skb->len;
6592         unsigned int offset = 0, size, count = 0, i;
6593         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6594         unsigned int f;
6595         unsigned int bytecount = skb->len;
6596         u16 gso_segs = 1;
6597
6598         i = tx_ring->next_to_use;
6599
6600         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6601                 /* excluding fcoe_crc_eof for FCoE */
6602                 total -= sizeof(struct fcoe_crc_eof);
6603
6604         len = min(skb_headlen(skb), total);
6605         while (len) {
6606                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6607                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6608
6609                 tx_buffer_info->length = size;
6610                 tx_buffer_info->mapped_as_page = false;
6611                 tx_buffer_info->dma = dma_map_single(dev,
6612                                                      skb->data + offset,
6613                                                      size, DMA_TO_DEVICE);
6614                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6615                         goto dma_error;
6616                 tx_buffer_info->time_stamp = jiffies;
6617                 tx_buffer_info->next_to_watch = i;
6618
6619                 len -= size;
6620                 total -= size;
6621                 offset += size;
6622                 count++;
6623
6624                 if (len) {
6625                         i++;
6626                         if (i == tx_ring->count)
6627                                 i = 0;
6628                 }
6629         }
6630
6631         for (f = 0; f < nr_frags; f++) {
6632                 struct skb_frag_struct *frag;
6633
6634                 frag = &skb_shinfo(skb)->frags[f];
6635                 len = min((unsigned int)frag->size, total);
6636                 offset = frag->page_offset;
6637
6638                 while (len) {
6639                         i++;
6640                         if (i == tx_ring->count)
6641                                 i = 0;
6642
6643                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6644                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6645
6646                         tx_buffer_info->length = size;
6647                         tx_buffer_info->dma = dma_map_page(dev,
6648                                                            frag->page,
6649                                                            offset, size,
6650                                                            DMA_TO_DEVICE);
6651                         tx_buffer_info->mapped_as_page = true;
6652                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6653                                 goto dma_error;
6654                         tx_buffer_info->time_stamp = jiffies;
6655                         tx_buffer_info->next_to_watch = i;
6656
6657                         len -= size;
6658                         total -= size;
6659                         offset += size;
6660                         count++;
6661                 }
6662                 if (total == 0)
6663                         break;
6664         }
6665
6666         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6667                 gso_segs = skb_shinfo(skb)->gso_segs;
6668 #ifdef IXGBE_FCOE
6669         /* adjust for FCoE Sequence Offload */
6670         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6671                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6672                                         skb_shinfo(skb)->gso_size);
6673 #endif /* IXGBE_FCOE */
6674         bytecount += (gso_segs - 1) * hdr_len;
6675
6676         /* multiply data chunks by size of headers */
6677         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6678         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6679         tx_ring->tx_buffer_info[i].skb = skb;
6680         tx_ring->tx_buffer_info[first].next_to_watch = i;
6681
6682         return count;
6683
6684 dma_error:
6685         e_dev_err("TX DMA map failed\n");
6686
6687         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6688         tx_buffer_info->dma = 0;
6689         tx_buffer_info->time_stamp = 0;
6690         tx_buffer_info->next_to_watch = 0;
6691         if (count)
6692                 count--;
6693
6694         /* clear timestamp and dma mappings for remaining portion of packet */
6695         while (count--) {
6696                 if (i == 0)
6697                         i += tx_ring->count;
6698                 i--;
6699                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6700                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6701         }
6702
6703         return 0;
6704 }
6705
6706 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6707                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6708 {
6709         union ixgbe_adv_tx_desc *tx_desc = NULL;
6710         struct ixgbe_tx_buffer *tx_buffer_info;
6711         u32 olinfo_status = 0, cmd_type_len = 0;
6712         unsigned int i;
6713         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6714
6715         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6716
6717         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6718
6719         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6720                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6721
6722         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6723                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6724
6725                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6726                                  IXGBE_ADVTXD_POPTS_SHIFT;
6727
6728                 /* use index 1 context for tso */
6729                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6730                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6731                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6732                                          IXGBE_ADVTXD_POPTS_SHIFT;
6733
6734         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6735                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6736                                  IXGBE_ADVTXD_POPTS_SHIFT;
6737
6738         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6739                 olinfo_status |= IXGBE_ADVTXD_CC;
6740                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6741                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6742                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6743         }
6744
6745         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6746
6747         i = tx_ring->next_to_use;
6748         while (count--) {
6749                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6750                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6751                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6752                 tx_desc->read.cmd_type_len =
6753                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6754                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6755                 i++;
6756                 if (i == tx_ring->count)
6757                         i = 0;
6758         }
6759
6760         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6761
6762         /*
6763          * Force memory writes to complete before letting h/w
6764          * know there are new descriptors to fetch.  (Only
6765          * applicable for weak-ordered memory model archs,
6766          * such as IA-64).
6767          */
6768         wmb();
6769
6770         tx_ring->next_to_use = i;
6771         writel(i, tx_ring->tail);
6772 }
6773
6774 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6775                       u32 tx_flags, __be16 protocol)
6776 {
6777         struct ixgbe_q_vector *q_vector = ring->q_vector;
6778         union ixgbe_atr_hash_dword input = { .dword = 0 };
6779         union ixgbe_atr_hash_dword common = { .dword = 0 };
6780         union {
6781                 unsigned char *network;
6782                 struct iphdr *ipv4;
6783                 struct ipv6hdr *ipv6;
6784         } hdr;
6785         struct tcphdr *th;
6786         __be16 vlan_id;
6787
6788         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6789         if (!q_vector)
6790                 return;
6791
6792         /* do nothing if sampling is disabled */
6793         if (!ring->atr_sample_rate)
6794                 return;
6795
6796         ring->atr_count++;
6797
6798         /* snag network header to get L4 type and address */
6799         hdr.network = skb_network_header(skb);
6800
6801         /* Currently only IPv4/IPv6 with TCP is supported */
6802         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6803              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6804             (protocol != __constant_htons(ETH_P_IP) ||
6805              hdr.ipv4->protocol != IPPROTO_TCP))
6806                 return;
6807
6808         th = tcp_hdr(skb);
6809
6810         /* skip this packet since the socket is closing */
6811         if (th->fin)
6812                 return;
6813
6814         /* sample on all syn packets or once every atr sample count */
6815         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6816                 return;
6817
6818         /* reset sample count */
6819         ring->atr_count = 0;
6820
6821         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6822
6823         /*
6824          * src and dst are inverted, think how the receiver sees them
6825          *
6826          * The input is broken into two sections, a non-compressed section
6827          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6828          * is XORed together and stored in the compressed dword.
6829          */
6830         input.formatted.vlan_id = vlan_id;
6831
6832         /*
6833          * since src port and flex bytes occupy the same word XOR them together
6834          * and write the value to source port portion of compressed dword
6835          */
6836         if (vlan_id)
6837                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6838         else
6839                 common.port.src ^= th->dest ^ protocol;
6840         common.port.dst ^= th->source;
6841
6842         if (protocol == __constant_htons(ETH_P_IP)) {
6843                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6844                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6845         } else {
6846                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6847                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6848                              hdr.ipv6->saddr.s6_addr32[1] ^
6849                              hdr.ipv6->saddr.s6_addr32[2] ^
6850                              hdr.ipv6->saddr.s6_addr32[3] ^
6851                              hdr.ipv6->daddr.s6_addr32[0] ^
6852                              hdr.ipv6->daddr.s6_addr32[1] ^
6853                              hdr.ipv6->daddr.s6_addr32[2] ^
6854                              hdr.ipv6->daddr.s6_addr32[3];
6855         }
6856
6857         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6858         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6859                                               input, common, ring->queue_index);
6860 }
6861
6862 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6863 {
6864         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6865         /* Herbert's original patch had:
6866          *  smp_mb__after_netif_stop_queue();
6867          * but since that doesn't exist yet, just open code it. */
6868         smp_mb();
6869
6870         /* We need to check again in a case another CPU has just
6871          * made room available. */
6872         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6873                 return -EBUSY;
6874
6875         /* A reprieve! - use start_queue because it doesn't call schedule */
6876         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6877         ++tx_ring->tx_stats.restart_queue;
6878         return 0;
6879 }
6880
6881 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6882 {
6883         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6884                 return 0;
6885         return __ixgbe_maybe_stop_tx(tx_ring, size);
6886 }
6887
6888 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6889 {
6890         struct ixgbe_adapter *adapter = netdev_priv(dev);
6891         int txq = smp_processor_id();
6892 #ifdef IXGBE_FCOE
6893         __be16 protocol;
6894
6895         protocol = vlan_get_protocol(skb);
6896
6897         if (((protocol == htons(ETH_P_FCOE)) ||
6898             (protocol == htons(ETH_P_FIP))) &&
6899             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6900                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6901                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6902                 return txq;
6903         }
6904 #endif
6905
6906         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6907                 while (unlikely(txq >= dev->real_num_tx_queues))
6908                         txq -= dev->real_num_tx_queues;
6909                 return txq;
6910         }
6911
6912         return skb_tx_hash(dev, skb);
6913 }
6914
6915 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6916                           struct ixgbe_adapter *adapter,
6917                           struct ixgbe_ring *tx_ring)
6918 {
6919         unsigned int first;
6920         unsigned int tx_flags = 0;
6921         u8 hdr_len = 0;
6922         int tso;
6923         int count = 0;
6924         unsigned int f;
6925         __be16 protocol;
6926
6927         protocol = vlan_get_protocol(skb);
6928
6929         if (vlan_tx_tag_present(skb)) {
6930                 tx_flags |= vlan_tx_tag_get(skb);
6931                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6932                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6933                         tx_flags |= tx_ring->dcb_tc << 13;
6934                 }
6935                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6936                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6937         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6938                    skb->priority != TC_PRIO_CONTROL) {
6939                 tx_flags |= tx_ring->dcb_tc << 13;
6940                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6941                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6942         }
6943
6944 #ifdef IXGBE_FCOE
6945         /* for FCoE with DCB, we force the priority to what
6946          * was specified by the switch */
6947         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6948             (protocol == htons(ETH_P_FCOE)))
6949                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6950 #endif
6951
6952         /* four things can cause us to need a context descriptor */
6953         if (skb_is_gso(skb) ||
6954             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6955             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6956             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6957                 count++;
6958
6959         count += TXD_USE_COUNT(skb_headlen(skb));
6960         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6961                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6962
6963         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6964                 tx_ring->tx_stats.tx_busy++;
6965                 return NETDEV_TX_BUSY;
6966         }
6967
6968         first = tx_ring->next_to_use;
6969         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6970 #ifdef IXGBE_FCOE
6971                 /* setup tx offload for FCoE */
6972                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6973                 if (tso < 0) {
6974                         dev_kfree_skb_any(skb);
6975                         return NETDEV_TX_OK;
6976                 }
6977                 if (tso)
6978                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6979 #endif /* IXGBE_FCOE */
6980         } else {
6981                 if (protocol == htons(ETH_P_IP))
6982                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6983                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6984                                 protocol);
6985                 if (tso < 0) {
6986                         dev_kfree_skb_any(skb);
6987                         return NETDEV_TX_OK;
6988                 }
6989
6990                 if (tso)
6991                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6992                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6993                                        protocol) &&
6994                          (skb->ip_summed == CHECKSUM_PARTIAL))
6995                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6996         }
6997
6998         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6999         if (count) {
7000                 /* add the ATR filter if ATR is on */
7001                 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7002                         ixgbe_atr(tx_ring, skb, tx_flags, protocol);
7003                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
7004                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7005
7006         } else {
7007                 dev_kfree_skb_any(skb);
7008                 tx_ring->tx_buffer_info[first].time_stamp = 0;
7009                 tx_ring->next_to_use = first;
7010         }
7011
7012         return NETDEV_TX_OK;
7013 }
7014
7015 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
7016 {
7017         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7018         struct ixgbe_ring *tx_ring;
7019
7020         tx_ring = adapter->tx_ring[skb->queue_mapping];
7021         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
7022 }
7023
7024 /**
7025  * ixgbe_set_mac - Change the Ethernet Address of the NIC
7026  * @netdev: network interface device structure
7027  * @p: pointer to an address structure
7028  *
7029  * Returns 0 on success, negative on failure
7030  **/
7031 static int ixgbe_set_mac(struct net_device *netdev, void *p)
7032 {
7033         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7034         struct ixgbe_hw *hw = &adapter->hw;
7035         struct sockaddr *addr = p;
7036
7037         if (!is_valid_ether_addr(addr->sa_data))
7038                 return -EADDRNOTAVAIL;
7039
7040         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
7041         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
7042
7043         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
7044                             IXGBE_RAH_AV);
7045
7046         return 0;
7047 }
7048
7049 static int
7050 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7051 {
7052         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7053         struct ixgbe_hw *hw = &adapter->hw;
7054         u16 value;
7055         int rc;
7056
7057         if (prtad != hw->phy.mdio.prtad)
7058                 return -EINVAL;
7059         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7060         if (!rc)
7061                 rc = value;
7062         return rc;
7063 }
7064
7065 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7066                             u16 addr, u16 value)
7067 {
7068         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7069         struct ixgbe_hw *hw = &adapter->hw;
7070
7071         if (prtad != hw->phy.mdio.prtad)
7072                 return -EINVAL;
7073         return hw->phy.ops.write_reg(hw, addr, devad, value);
7074 }
7075
7076 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7077 {
7078         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7079
7080         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7081 }
7082
7083 /**
7084  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7085  * netdev->dev_addrs
7086  * @netdev: network interface device structure
7087  *
7088  * Returns non-zero on failure
7089  **/
7090 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7091 {
7092         int err = 0;
7093         struct ixgbe_adapter *adapter = netdev_priv(dev);
7094         struct ixgbe_mac_info *mac = &adapter->hw.mac;
7095
7096         if (is_valid_ether_addr(mac->san_addr)) {
7097                 rtnl_lock();
7098                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7099                 rtnl_unlock();
7100         }
7101         return err;
7102 }
7103
7104 /**
7105  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7106  * netdev->dev_addrs
7107  * @netdev: network interface device structure
7108  *
7109  * Returns non-zero on failure
7110  **/
7111 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7112 {
7113         int err = 0;
7114         struct ixgbe_adapter *adapter = netdev_priv(dev);
7115         struct ixgbe_mac_info *mac = &adapter->hw.mac;
7116
7117         if (is_valid_ether_addr(mac->san_addr)) {
7118                 rtnl_lock();
7119                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7120                 rtnl_unlock();
7121         }
7122         return err;
7123 }
7124
7125 #ifdef CONFIG_NET_POLL_CONTROLLER
7126 /*
7127  * Polling 'interrupt' - used by things like netconsole to send skbs
7128  * without having to re-enable interrupts. It's not called while
7129  * the interrupt routine is executing.
7130  */
7131 static void ixgbe_netpoll(struct net_device *netdev)
7132 {
7133         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7134         int i;
7135
7136         /* if interface is down do nothing */
7137         if (test_bit(__IXGBE_DOWN, &adapter->state))
7138                 return;
7139
7140         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7141         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7142                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7143                 for (i = 0; i < num_q_vectors; i++) {
7144                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7145                         ixgbe_msix_clean_many(0, q_vector);
7146                 }
7147         } else {
7148                 ixgbe_intr(adapter->pdev->irq, netdev);
7149         }
7150         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7151 }
7152 #endif
7153
7154 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7155                                                    struct rtnl_link_stats64 *stats)
7156 {
7157         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7158         int i;
7159
7160         rcu_read_lock();
7161         for (i = 0; i < adapter->num_rx_queues; i++) {
7162                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7163                 u64 bytes, packets;
7164                 unsigned int start;
7165
7166                 if (ring) {
7167                         do {
7168                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7169                                 packets = ring->stats.packets;
7170                                 bytes   = ring->stats.bytes;
7171                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7172                         stats->rx_packets += packets;
7173                         stats->rx_bytes   += bytes;
7174                 }
7175         }
7176
7177         for (i = 0; i < adapter->num_tx_queues; i++) {
7178                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7179                 u64 bytes, packets;
7180                 unsigned int start;
7181
7182                 if (ring) {
7183                         do {
7184                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7185                                 packets = ring->stats.packets;
7186                                 bytes   = ring->stats.bytes;
7187                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7188                         stats->tx_packets += packets;
7189                         stats->tx_bytes   += bytes;
7190                 }
7191         }
7192         rcu_read_unlock();
7193         /* following stats updated by ixgbe_watchdog_task() */
7194         stats->multicast        = netdev->stats.multicast;
7195         stats->rx_errors        = netdev->stats.rx_errors;
7196         stats->rx_length_errors = netdev->stats.rx_length_errors;
7197         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
7198         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7199         return stats;
7200 }
7201
7202
7203 static const struct net_device_ops ixgbe_netdev_ops = {
7204         .ndo_open               = ixgbe_open,
7205         .ndo_stop               = ixgbe_close,
7206         .ndo_start_xmit         = ixgbe_xmit_frame,
7207         .ndo_select_queue       = ixgbe_select_queue,
7208         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7209         .ndo_set_multicast_list = ixgbe_set_rx_mode,
7210         .ndo_validate_addr      = eth_validate_addr,
7211         .ndo_set_mac_address    = ixgbe_set_mac,
7212         .ndo_change_mtu         = ixgbe_change_mtu,
7213         .ndo_tx_timeout         = ixgbe_tx_timeout,
7214         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7215         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7216         .ndo_do_ioctl           = ixgbe_ioctl,
7217         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7218         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7219         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7220         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7221         .ndo_get_stats64        = ixgbe_get_stats64,
7222 #ifdef CONFIG_IXGBE_DCB
7223         .ndo_setup_tc           = ixgbe_setup_tc,
7224 #endif
7225 #ifdef CONFIG_NET_POLL_CONTROLLER
7226         .ndo_poll_controller    = ixgbe_netpoll,
7227 #endif
7228 #ifdef IXGBE_FCOE
7229         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7230         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7231         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7232         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7233         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7234         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7235 #endif /* IXGBE_FCOE */
7236 };
7237
7238 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7239                            const struct ixgbe_info *ii)
7240 {
7241 #ifdef CONFIG_PCI_IOV
7242         struct ixgbe_hw *hw = &adapter->hw;
7243         int err;
7244         int num_vf_macvlans, i;
7245         struct vf_macvlans *mv_list;
7246
7247         if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7248                 return;
7249
7250         /* The 82599 supports up to 64 VFs per physical function
7251          * but this implementation limits allocation to 63 so that
7252          * basic networking resources are still available to the
7253          * physical function
7254          */
7255         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7256         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7257         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7258         if (err) {
7259                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7260                 goto err_novfs;
7261         }
7262
7263         num_vf_macvlans = hw->mac.num_rar_entries -
7264                 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7265
7266         adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7267                                              sizeof(struct vf_macvlans),
7268                                              GFP_KERNEL);
7269         if (mv_list) {
7270                 /* Initialize list of VF macvlans */
7271                 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7272                 for (i = 0; i < num_vf_macvlans; i++) {
7273                         mv_list->vf = -1;
7274                         mv_list->free = true;
7275                         mv_list->rar_entry = hw->mac.num_rar_entries -
7276                                 (i + adapter->num_vfs + 1);
7277                         list_add(&mv_list->l, &adapter->vf_mvs.l);
7278                         mv_list++;
7279                 }
7280         }
7281
7282         /* If call to enable VFs succeeded then allocate memory
7283          * for per VF control structures.
7284          */
7285         adapter->vfinfo =
7286                 kcalloc(adapter->num_vfs,
7287                         sizeof(struct vf_data_storage), GFP_KERNEL);
7288         if (adapter->vfinfo) {
7289                 /* Now that we're sure SR-IOV is enabled
7290                  * and memory allocated set up the mailbox parameters
7291                  */
7292                 ixgbe_init_mbx_params_pf(hw);
7293                 memcpy(&hw->mbx.ops, ii->mbx_ops,
7294                        sizeof(hw->mbx.ops));
7295
7296                 /* Disable RSC when in SR-IOV mode */
7297                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7298                                      IXGBE_FLAG2_RSC_ENABLED);
7299                 return;
7300         }
7301
7302         /* Oh oh */
7303         e_err(probe, "Unable to allocate memory for VF Data Storage - "
7304               "SRIOV disabled\n");
7305         pci_disable_sriov(adapter->pdev);
7306
7307 err_novfs:
7308         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7309         adapter->num_vfs = 0;
7310 #endif /* CONFIG_PCI_IOV */
7311 }
7312
7313 /**
7314  * ixgbe_probe - Device Initialization Routine
7315  * @pdev: PCI device information struct
7316  * @ent: entry in ixgbe_pci_tbl
7317  *
7318  * Returns 0 on success, negative on failure
7319  *
7320  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7321  * The OS initialization, configuring of the adapter private structure,
7322  * and a hardware reset occur.
7323  **/
7324 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7325                                  const struct pci_device_id *ent)
7326 {
7327         struct net_device *netdev;
7328         struct ixgbe_adapter *adapter = NULL;
7329         struct ixgbe_hw *hw;
7330         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7331         static int cards_found;
7332         int i, err, pci_using_dac;
7333         u8 part_str[IXGBE_PBANUM_LENGTH];
7334         unsigned int indices = num_possible_cpus();
7335 #ifdef IXGBE_FCOE
7336         u16 device_caps;
7337 #endif
7338         u32 eec;
7339
7340         /* Catch broken hardware that put the wrong VF device ID in
7341          * the PCIe SR-IOV capability.
7342          */
7343         if (pdev->is_virtfn) {
7344                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7345                      pci_name(pdev), pdev->vendor, pdev->device);
7346                 return -EINVAL;
7347         }
7348
7349         err = pci_enable_device_mem(pdev);
7350         if (err)
7351                 return err;
7352
7353         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7354             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7355                 pci_using_dac = 1;
7356         } else {
7357                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7358                 if (err) {
7359                         err = dma_set_coherent_mask(&pdev->dev,
7360                                                     DMA_BIT_MASK(32));
7361                         if (err) {
7362                                 dev_err(&pdev->dev,
7363                                         "No usable DMA configuration, aborting\n");
7364                                 goto err_dma;
7365                         }
7366                 }
7367                 pci_using_dac = 0;
7368         }
7369
7370         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7371                                            IORESOURCE_MEM), ixgbe_driver_name);
7372         if (err) {
7373                 dev_err(&pdev->dev,
7374                         "pci_request_selected_regions failed 0x%x\n", err);
7375                 goto err_pci_reg;
7376         }
7377
7378         pci_enable_pcie_error_reporting(pdev);
7379
7380         pci_set_master(pdev);
7381         pci_save_state(pdev);
7382
7383         if (ii->mac == ixgbe_mac_82598EB)
7384                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7385         else
7386                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7387
7388 #if defined(CONFIG_DCB)
7389         indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
7390 #elif defined(IXGBE_FCOE)
7391         indices += min_t(unsigned int, num_possible_cpus(),
7392                          IXGBE_MAX_FCOE_INDICES);
7393 #endif
7394         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7395         if (!netdev) {
7396                 err = -ENOMEM;
7397                 goto err_alloc_etherdev;
7398         }
7399
7400         SET_NETDEV_DEV(netdev, &pdev->dev);
7401
7402         adapter = netdev_priv(netdev);
7403         pci_set_drvdata(pdev, adapter);
7404
7405         adapter->netdev = netdev;
7406         adapter->pdev = pdev;
7407         hw = &adapter->hw;
7408         hw->back = adapter;
7409         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7410
7411         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7412                               pci_resource_len(pdev, 0));
7413         if (!hw->hw_addr) {
7414                 err = -EIO;
7415                 goto err_ioremap;
7416         }
7417
7418         for (i = 1; i <= 5; i++) {
7419                 if (pci_resource_len(pdev, i) == 0)
7420                         continue;
7421         }
7422
7423         netdev->netdev_ops = &ixgbe_netdev_ops;
7424         ixgbe_set_ethtool_ops(netdev);
7425         netdev->watchdog_timeo = 5 * HZ;
7426         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7427
7428         adapter->bd_number = cards_found;
7429
7430         /* Setup hw api */
7431         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7432         hw->mac.type  = ii->mac;
7433
7434         /* EEPROM */
7435         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7436         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7437         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7438         if (!(eec & (1 << 8)))
7439                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7440
7441         /* PHY */
7442         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7443         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7444         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7445         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7446         hw->phy.mdio.mmds = 0;
7447         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7448         hw->phy.mdio.dev = netdev;
7449         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7450         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7451
7452         ii->get_invariants(hw);
7453
7454         /* setup the private structure */
7455         err = ixgbe_sw_init(adapter);
7456         if (err)
7457                 goto err_sw_init;
7458
7459         /* Make it possible the adapter to be woken up via WOL */
7460         switch (adapter->hw.mac.type) {
7461         case ixgbe_mac_82599EB:
7462         case ixgbe_mac_X540:
7463                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7464                 break;
7465         default:
7466                 break;
7467         }
7468
7469         /*
7470          * If there is a fan on this device and it has failed log the
7471          * failure.
7472          */
7473         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7474                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7475                 if (esdp & IXGBE_ESDP_SDP1)
7476                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7477         }
7478
7479         /* reset_hw fills in the perm_addr as well */
7480         hw->phy.reset_if_overtemp = true;
7481         err = hw->mac.ops.reset_hw(hw);
7482         hw->phy.reset_if_overtemp = false;
7483         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7484             hw->mac.type == ixgbe_mac_82598EB) {
7485                 err = 0;
7486         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7487                 e_dev_err("failed to load because an unsupported SFP+ "
7488                           "module type was detected.\n");
7489                 e_dev_err("Reload the driver after installing a supported "
7490                           "module.\n");
7491                 goto err_sw_init;
7492         } else if (err) {
7493                 e_dev_err("HW Init failed: %d\n", err);
7494                 goto err_sw_init;
7495         }
7496
7497         ixgbe_probe_vf(adapter, ii);
7498
7499         netdev->features = NETIF_F_SG |
7500                            NETIF_F_IP_CSUM |
7501                            NETIF_F_HW_VLAN_TX |
7502                            NETIF_F_HW_VLAN_RX |
7503                            NETIF_F_HW_VLAN_FILTER;
7504
7505         netdev->features |= NETIF_F_IPV6_CSUM;
7506         netdev->features |= NETIF_F_TSO;
7507         netdev->features |= NETIF_F_TSO6;
7508         netdev->features |= NETIF_F_GRO;
7509         netdev->features |= NETIF_F_RXHASH;
7510
7511         switch (adapter->hw.mac.type) {
7512         case ixgbe_mac_82599EB:
7513         case ixgbe_mac_X540:
7514                 netdev->features |= NETIF_F_SCTP_CSUM;
7515                 break;
7516         default:
7517                 break;
7518         }
7519
7520         netdev->vlan_features |= NETIF_F_TSO;
7521         netdev->vlan_features |= NETIF_F_TSO6;
7522         netdev->vlan_features |= NETIF_F_IP_CSUM;
7523         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7524         netdev->vlan_features |= NETIF_F_SG;
7525
7526         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7527                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7528                                     IXGBE_FLAG_DCB_ENABLED);
7529
7530 #ifdef CONFIG_IXGBE_DCB
7531         netdev->dcbnl_ops = &dcbnl_ops;
7532 #endif
7533
7534 #ifdef IXGBE_FCOE
7535         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7536                 if (hw->mac.ops.get_device_caps) {
7537                         hw->mac.ops.get_device_caps(hw, &device_caps);
7538                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7539                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7540                 }
7541         }
7542         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7543                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7544                 netdev->vlan_features |= NETIF_F_FSO;
7545                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7546         }
7547 #endif /* IXGBE_FCOE */
7548         if (pci_using_dac) {
7549                 netdev->features |= NETIF_F_HIGHDMA;
7550                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7551         }
7552
7553         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7554                 netdev->features |= NETIF_F_LRO;
7555
7556         /* make sure the EEPROM is good */
7557         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7558                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7559                 err = -EIO;
7560                 goto err_eeprom;
7561         }
7562
7563         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7564         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7565
7566         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7567                 e_dev_err("invalid MAC address\n");
7568                 err = -EIO;
7569                 goto err_eeprom;
7570         }
7571
7572         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7573         if (hw->mac.ops.disable_tx_laser &&
7574             ((hw->phy.multispeed_fiber) ||
7575              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7576               (hw->mac.type == ixgbe_mac_82599EB))))
7577                 hw->mac.ops.disable_tx_laser(hw);
7578
7579         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7580                     (unsigned long) adapter);
7581
7582         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7583         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7584
7585         err = ixgbe_init_interrupt_scheme(adapter);
7586         if (err)
7587                 goto err_sw_init;
7588
7589         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7590                 netdev->features &= ~NETIF_F_RXHASH;
7591
7592         switch (pdev->device) {
7593         case IXGBE_DEV_ID_82599_SFP:
7594                 /* Only this subdevice supports WOL */
7595                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7596                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7597                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7598                 break;
7599         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7600                 /* All except this subdevice support WOL */
7601                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7602                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7603                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7604                 break;
7605         case IXGBE_DEV_ID_82599_KX4:
7606                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7607                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7608                 break;
7609         default:
7610                 adapter->wol = 0;
7611                 break;
7612         }
7613         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7614
7615         /* pick up the PCI bus settings for reporting later */
7616         hw->mac.ops.get_bus_info(hw);
7617
7618         /* print bus type/speed/width info */
7619         e_dev_info("(PCI Express:%s:%s) %pM\n",
7620                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7621                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7622                     "Unknown"),
7623                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7624                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7625                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7626                     "Unknown"),
7627                    netdev->dev_addr);
7628
7629         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7630         if (err)
7631                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7632         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7633                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7634                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7635                            part_str);
7636         else
7637                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7638                            hw->mac.type, hw->phy.type, part_str);
7639
7640         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7641                 e_dev_warn("PCI-Express bandwidth available for this card is "
7642                            "not sufficient for optimal performance.\n");
7643                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7644                            "is required.\n");
7645         }
7646
7647         /* save off EEPROM version number */
7648         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7649
7650         /* reset the hardware with the new settings */
7651         err = hw->mac.ops.start_hw(hw);
7652
7653         if (err == IXGBE_ERR_EEPROM_VERSION) {
7654                 /* We are running on a pre-production device, log a warning */
7655                 e_dev_warn("This device is a pre-production adapter/LOM. "
7656                            "Please be aware there may be issues associated "
7657                            "with your hardware.  If you are experiencing "
7658                            "problems please contact your Intel or hardware "
7659                            "representative who provided you with this "
7660                            "hardware.\n");
7661         }
7662         strcpy(netdev->name, "eth%d");
7663         err = register_netdev(netdev);
7664         if (err)
7665                 goto err_register;
7666
7667         /* carrier off reporting is important to ethtool even BEFORE open */
7668         netif_carrier_off(netdev);
7669
7670 #ifdef CONFIG_IXGBE_DCA
7671         if (dca_add_requester(&pdev->dev) == 0) {
7672                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7673                 ixgbe_setup_dca(adapter);
7674         }
7675 #endif
7676         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7677                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7678                 for (i = 0; i < adapter->num_vfs; i++)
7679                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7680         }
7681
7682         /* add san mac addr to netdev */
7683         ixgbe_add_sanmac_netdev(netdev);
7684
7685         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7686         cards_found++;
7687         return 0;
7688
7689 err_register:
7690         ixgbe_release_hw_control(adapter);
7691         ixgbe_clear_interrupt_scheme(adapter);
7692 err_sw_init:
7693 err_eeprom:
7694         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7695                 ixgbe_disable_sriov(adapter);
7696         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7697         iounmap(hw->hw_addr);
7698 err_ioremap:
7699         free_netdev(netdev);
7700 err_alloc_etherdev:
7701         pci_release_selected_regions(pdev,
7702                                      pci_select_bars(pdev, IORESOURCE_MEM));
7703 err_pci_reg:
7704 err_dma:
7705         pci_disable_device(pdev);
7706         return err;
7707 }
7708
7709 /**
7710  * ixgbe_remove - Device Removal Routine
7711  * @pdev: PCI device information struct
7712  *
7713  * ixgbe_remove is called by the PCI subsystem to alert the driver
7714  * that it should release a PCI device.  The could be caused by a
7715  * Hot-Plug event, or because the driver is going to be removed from
7716  * memory.
7717  **/
7718 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7719 {
7720         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7721         struct net_device *netdev = adapter->netdev;
7722
7723         set_bit(__IXGBE_DOWN, &adapter->state);
7724         cancel_work_sync(&adapter->service_task);
7725
7726 #ifdef CONFIG_IXGBE_DCA
7727         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7728                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7729                 dca_remove_requester(&pdev->dev);
7730                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7731         }
7732
7733 #endif
7734 #ifdef IXGBE_FCOE
7735         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7736                 ixgbe_cleanup_fcoe(adapter);
7737
7738 #endif /* IXGBE_FCOE */
7739
7740         /* remove the added san mac */
7741         ixgbe_del_sanmac_netdev(netdev);
7742
7743         if (netdev->reg_state == NETREG_REGISTERED)
7744                 unregister_netdev(netdev);
7745
7746         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7747                 ixgbe_disable_sriov(adapter);
7748
7749         ixgbe_clear_interrupt_scheme(adapter);
7750
7751         ixgbe_release_hw_control(adapter);
7752
7753         iounmap(adapter->hw.hw_addr);
7754         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7755                                      IORESOURCE_MEM));
7756
7757         e_dev_info("complete\n");
7758
7759         free_netdev(netdev);
7760
7761         pci_disable_pcie_error_reporting(pdev);
7762
7763         pci_disable_device(pdev);
7764 }
7765
7766 /**
7767  * ixgbe_io_error_detected - called when PCI error is detected
7768  * @pdev: Pointer to PCI device
7769  * @state: The current pci connection state
7770  *
7771  * This function is called after a PCI bus error affecting
7772  * this device has been detected.
7773  */
7774 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7775                                                 pci_channel_state_t state)
7776 {
7777         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7778         struct net_device *netdev = adapter->netdev;
7779
7780         netif_device_detach(netdev);
7781
7782         if (state == pci_channel_io_perm_failure)
7783                 return PCI_ERS_RESULT_DISCONNECT;
7784
7785         if (netif_running(netdev))
7786                 ixgbe_down(adapter);
7787         pci_disable_device(pdev);
7788
7789         /* Request a slot reset. */
7790         return PCI_ERS_RESULT_NEED_RESET;
7791 }
7792
7793 /**
7794  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7795  * @pdev: Pointer to PCI device
7796  *
7797  * Restart the card from scratch, as if from a cold-boot.
7798  */
7799 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7800 {
7801         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7802         pci_ers_result_t result;
7803         int err;
7804
7805         if (pci_enable_device_mem(pdev)) {
7806                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7807                 result = PCI_ERS_RESULT_DISCONNECT;
7808         } else {
7809                 pci_set_master(pdev);
7810                 pci_restore_state(pdev);
7811                 pci_save_state(pdev);
7812
7813                 pci_wake_from_d3(pdev, false);
7814
7815                 ixgbe_reset(adapter);
7816                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7817                 result = PCI_ERS_RESULT_RECOVERED;
7818         }
7819
7820         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7821         if (err) {
7822                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7823                           "failed 0x%0x\n", err);
7824                 /* non-fatal, continue */
7825         }
7826
7827         return result;
7828 }
7829
7830 /**
7831  * ixgbe_io_resume - called when traffic can start flowing again.
7832  * @pdev: Pointer to PCI device
7833  *
7834  * This callback is called when the error recovery driver tells us that
7835  * its OK to resume normal operation.
7836  */
7837 static void ixgbe_io_resume(struct pci_dev *pdev)
7838 {
7839         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7840         struct net_device *netdev = adapter->netdev;
7841
7842         if (netif_running(netdev)) {
7843                 if (ixgbe_up(adapter)) {
7844                         e_info(probe, "ixgbe_up failed after reset\n");
7845                         return;
7846                 }
7847         }
7848
7849         netif_device_attach(netdev);
7850 }
7851
7852 static struct pci_error_handlers ixgbe_err_handler = {
7853         .error_detected = ixgbe_io_error_detected,
7854         .slot_reset = ixgbe_io_slot_reset,
7855         .resume = ixgbe_io_resume,
7856 };
7857
7858 static struct pci_driver ixgbe_driver = {
7859         .name     = ixgbe_driver_name,
7860         .id_table = ixgbe_pci_tbl,
7861         .probe    = ixgbe_probe,
7862         .remove   = __devexit_p(ixgbe_remove),
7863 #ifdef CONFIG_PM
7864         .suspend  = ixgbe_suspend,
7865         .resume   = ixgbe_resume,
7866 #endif
7867         .shutdown = ixgbe_shutdown,
7868         .err_handler = &ixgbe_err_handler
7869 };
7870
7871 /**
7872  * ixgbe_init_module - Driver Registration Routine
7873  *
7874  * ixgbe_init_module is the first routine called when the driver is
7875  * loaded. All it does is register with the PCI subsystem.
7876  **/
7877 static int __init ixgbe_init_module(void)
7878 {
7879         int ret;
7880         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7881         pr_info("%s\n", ixgbe_copyright);
7882
7883 #ifdef CONFIG_IXGBE_DCA
7884         dca_register_notify(&dca_notifier);
7885 #endif
7886
7887         ret = pci_register_driver(&ixgbe_driver);
7888         return ret;
7889 }
7890
7891 module_init(ixgbe_init_module);
7892
7893 /**
7894  * ixgbe_exit_module - Driver Exit Cleanup Routine
7895  *
7896  * ixgbe_exit_module is called just before the driver is removed
7897  * from memory.
7898  **/
7899 static void __exit ixgbe_exit_module(void)
7900 {
7901 #ifdef CONFIG_IXGBE_DCA
7902         dca_unregister_notify(&dca_notifier);
7903 #endif
7904         pci_unregister_driver(&ixgbe_driver);
7905         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7906 }
7907
7908 #ifdef CONFIG_IXGBE_DCA
7909 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7910                             void *p)
7911 {
7912         int ret_val;
7913
7914         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7915                                          __ixgbe_notify_dca);
7916
7917         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7918 }
7919
7920 #endif /* CONFIG_IXGBE_DCA */
7921
7922 module_exit(ixgbe_exit_module);
7923
7924 /* ixgbe_main.c */