1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31 #include <linux/list.h>
32 #include <linux/netdevice.h>
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw);
39 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
40 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
41 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
42 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
43 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
44 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
46 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
47 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
48 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
50 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw);
52 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index);
53 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index);
54 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
55 static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq);
58 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
59 * @hw: pointer to hardware structure
61 * Starts the hardware by filling the bus info structure and media type, clears
62 * all on chip counters, initializes receive address registers, multicast
63 * table, VLAN filter table, calls routine to set up link and flow control
64 * settings, and leaves transmit and receive units disabled and uninitialized
66 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
70 /* Set the media type */
71 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
73 /* Identify the PHY */
74 hw->phy.ops.identify(hw);
76 /* Clear the VLAN filter table */
77 hw->mac.ops.clear_vfta(hw);
79 /* Clear statistics registers */
80 hw->mac.ops.clear_hw_cntrs(hw);
82 /* Set No Snoop Disable */
83 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
84 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
85 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
86 IXGBE_WRITE_FLUSH(hw);
88 /* Setup flow control */
89 ixgbe_setup_fc(hw, 0);
91 /* Clear adapter stopped flag */
92 hw->adapter_stopped = false;
98 * ixgbe_init_hw_generic - Generic hardware initialization
99 * @hw: pointer to hardware structure
101 * Initialize the hardware by resetting the hardware, filling the bus info
102 * structure and media type, clears all on chip counters, initializes receive
103 * address registers, multicast table, VLAN filter table, calls routine to set
104 * up link and flow control settings, and leaves transmit and receive units
105 * disabled and uninitialized
107 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
109 /* Reset the hardware */
110 hw->mac.ops.reset_hw(hw);
113 hw->mac.ops.start_hw(hw);
119 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
120 * @hw: pointer to hardware structure
122 * Clears all hardware statistics counters by reading them from the hardware
123 * Statistics counters are clear on read.
125 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
129 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
130 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
131 IXGBE_READ_REG(hw, IXGBE_ERRBC);
132 IXGBE_READ_REG(hw, IXGBE_MSPDC);
133 for (i = 0; i < 8; i++)
134 IXGBE_READ_REG(hw, IXGBE_MPC(i));
136 IXGBE_READ_REG(hw, IXGBE_MLFC);
137 IXGBE_READ_REG(hw, IXGBE_MRFC);
138 IXGBE_READ_REG(hw, IXGBE_RLEC);
139 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
140 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
141 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
142 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
144 for (i = 0; i < 8; i++) {
145 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
146 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
147 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
148 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
151 IXGBE_READ_REG(hw, IXGBE_PRC64);
152 IXGBE_READ_REG(hw, IXGBE_PRC127);
153 IXGBE_READ_REG(hw, IXGBE_PRC255);
154 IXGBE_READ_REG(hw, IXGBE_PRC511);
155 IXGBE_READ_REG(hw, IXGBE_PRC1023);
156 IXGBE_READ_REG(hw, IXGBE_PRC1522);
157 IXGBE_READ_REG(hw, IXGBE_GPRC);
158 IXGBE_READ_REG(hw, IXGBE_BPRC);
159 IXGBE_READ_REG(hw, IXGBE_MPRC);
160 IXGBE_READ_REG(hw, IXGBE_GPTC);
161 IXGBE_READ_REG(hw, IXGBE_GORCL);
162 IXGBE_READ_REG(hw, IXGBE_GORCH);
163 IXGBE_READ_REG(hw, IXGBE_GOTCL);
164 IXGBE_READ_REG(hw, IXGBE_GOTCH);
165 for (i = 0; i < 8; i++)
166 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
167 IXGBE_READ_REG(hw, IXGBE_RUC);
168 IXGBE_READ_REG(hw, IXGBE_RFC);
169 IXGBE_READ_REG(hw, IXGBE_ROC);
170 IXGBE_READ_REG(hw, IXGBE_RJC);
171 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
172 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
173 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
174 IXGBE_READ_REG(hw, IXGBE_TORL);
175 IXGBE_READ_REG(hw, IXGBE_TORH);
176 IXGBE_READ_REG(hw, IXGBE_TPR);
177 IXGBE_READ_REG(hw, IXGBE_TPT);
178 IXGBE_READ_REG(hw, IXGBE_PTC64);
179 IXGBE_READ_REG(hw, IXGBE_PTC127);
180 IXGBE_READ_REG(hw, IXGBE_PTC255);
181 IXGBE_READ_REG(hw, IXGBE_PTC511);
182 IXGBE_READ_REG(hw, IXGBE_PTC1023);
183 IXGBE_READ_REG(hw, IXGBE_PTC1522);
184 IXGBE_READ_REG(hw, IXGBE_MPTC);
185 IXGBE_READ_REG(hw, IXGBE_BPTC);
186 for (i = 0; i < 16; i++) {
187 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
188 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
189 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
190 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
197 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
198 * @hw: pointer to hardware structure
199 * @pba_num: stores the part number from the EEPROM
201 * Reads the part number from the EEPROM.
203 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
208 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
210 hw_dbg(hw, "NVM Read Error\n");
213 *pba_num = (u32)(data << 16);
215 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
217 hw_dbg(hw, "NVM Read Error\n");
226 * ixgbe_get_mac_addr_generic - Generic get MAC address
227 * @hw: pointer to hardware structure
228 * @mac_addr: Adapter MAC address
230 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
231 * A reset of the adapter must be performed prior to calling this function
232 * in order for the MAC address to have been loaded from the EEPROM into RAR0
234 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
240 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
241 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
243 for (i = 0; i < 4; i++)
244 mac_addr[i] = (u8)(rar_low >> (i*8));
246 for (i = 0; i < 2; i++)
247 mac_addr[i+4] = (u8)(rar_high >> (i*8));
253 * ixgbe_get_bus_info_generic - Generic set PCI bus info
254 * @hw: pointer to hardware structure
256 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
258 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
260 struct ixgbe_adapter *adapter = hw->back;
261 struct ixgbe_mac_info *mac = &hw->mac;
264 hw->bus.type = ixgbe_bus_type_pci_express;
266 /* Get the negotiated link width and speed from PCI config space */
267 pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
270 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
271 case IXGBE_PCI_LINK_WIDTH_1:
272 hw->bus.width = ixgbe_bus_width_pcie_x1;
274 case IXGBE_PCI_LINK_WIDTH_2:
275 hw->bus.width = ixgbe_bus_width_pcie_x2;
277 case IXGBE_PCI_LINK_WIDTH_4:
278 hw->bus.width = ixgbe_bus_width_pcie_x4;
280 case IXGBE_PCI_LINK_WIDTH_8:
281 hw->bus.width = ixgbe_bus_width_pcie_x8;
284 hw->bus.width = ixgbe_bus_width_unknown;
288 switch (link_status & IXGBE_PCI_LINK_SPEED) {
289 case IXGBE_PCI_LINK_SPEED_2500:
290 hw->bus.speed = ixgbe_bus_speed_2500;
292 case IXGBE_PCI_LINK_SPEED_5000:
293 hw->bus.speed = ixgbe_bus_speed_5000;
296 hw->bus.speed = ixgbe_bus_speed_unknown;
300 mac->ops.set_lan_id(hw);
306 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
307 * @hw: pointer to the HW structure
309 * Determines the LAN function id by reading memory-mapped registers
310 * and swaps the port value if requested.
312 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
314 struct ixgbe_bus_info *bus = &hw->bus;
317 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
318 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
319 bus->lan_id = bus->func;
321 /* check for a port swap */
322 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
323 if (reg & IXGBE_FACTPS_LFS)
328 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
329 * @hw: pointer to hardware structure
331 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
332 * disables transmit and receive units. The adapter_stopped flag is used by
333 * the shared code and drivers to determine if the adapter is in a stopped
334 * state and should not touch the hardware.
336 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
338 u32 number_of_queues;
343 * Set the adapter_stopped flag so other driver functions stop touching
346 hw->adapter_stopped = true;
348 /* Disable the receive unit */
349 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
350 reg_val &= ~(IXGBE_RXCTRL_RXEN);
351 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val);
352 IXGBE_WRITE_FLUSH(hw);
355 /* Clear interrupt mask to stop from interrupts being generated */
356 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
358 /* Clear any pending interrupts */
359 IXGBE_READ_REG(hw, IXGBE_EICR);
361 /* Disable the transmit unit. Each queue must be disabled. */
362 number_of_queues = hw->mac.max_tx_queues;
363 for (i = 0; i < number_of_queues; i++) {
364 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
365 if (reg_val & IXGBE_TXDCTL_ENABLE) {
366 reg_val &= ~IXGBE_TXDCTL_ENABLE;
367 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val);
372 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
373 * access and verify no pending requests
375 if (ixgbe_disable_pcie_master(hw) != 0)
376 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
382 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
383 * @hw: pointer to hardware structure
384 * @index: led number to turn on
386 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
388 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
390 /* To turn on the LED, set mode to ON. */
391 led_reg &= ~IXGBE_LED_MODE_MASK(index);
392 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
393 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
394 IXGBE_WRITE_FLUSH(hw);
400 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
401 * @hw: pointer to hardware structure
402 * @index: led number to turn off
404 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
406 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
408 /* To turn off the LED, set mode to OFF. */
409 led_reg &= ~IXGBE_LED_MODE_MASK(index);
410 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
411 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
412 IXGBE_WRITE_FLUSH(hw);
418 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
419 * @hw: pointer to hardware structure
421 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
422 * ixgbe_hw struct in order to set up EEPROM access.
424 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
426 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
430 if (eeprom->type == ixgbe_eeprom_uninitialized) {
431 eeprom->type = ixgbe_eeprom_none;
432 /* Set default semaphore delay to 10ms which is a well
434 eeprom->semaphore_delay = 10;
437 * Check for EEPROM present first.
438 * If not present leave as none
440 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
441 if (eec & IXGBE_EEC_PRES) {
442 eeprom->type = ixgbe_eeprom_spi;
445 * SPI EEPROM is assumed here. This code would need to
446 * change if a future EEPROM is not SPI.
448 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
449 IXGBE_EEC_SIZE_SHIFT);
450 eeprom->word_size = 1 << (eeprom_size +
451 IXGBE_EEPROM_WORD_SIZE_SHIFT);
454 if (eec & IXGBE_EEC_ADDR_SIZE)
455 eeprom->address_bits = 16;
457 eeprom->address_bits = 8;
458 hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
459 "%d\n", eeprom->type, eeprom->word_size,
460 eeprom->address_bits);
467 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
468 * @hw: pointer to hardware structure
469 * @offset: offset within the EEPROM to be written to
470 * @data: 16 bit word to be written to the EEPROM
472 * If ixgbe_eeprom_update_checksum is not called after this function, the
473 * EEPROM will most likely contain an invalid checksum.
475 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
478 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
480 hw->eeprom.ops.init_params(hw);
482 if (offset >= hw->eeprom.word_size) {
483 status = IXGBE_ERR_EEPROM;
487 /* Prepare the EEPROM for writing */
488 status = ixgbe_acquire_eeprom(hw);
491 if (ixgbe_ready_eeprom(hw) != 0) {
492 ixgbe_release_eeprom(hw);
493 status = IXGBE_ERR_EEPROM;
498 ixgbe_standby_eeprom(hw);
500 /* Send the WRITE ENABLE command (8 bit opcode ) */
501 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI,
502 IXGBE_EEPROM_OPCODE_BITS);
504 ixgbe_standby_eeprom(hw);
507 * Some SPI eeproms use the 8th address bit embedded in the
510 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
511 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
513 /* Send the Write command (8-bit opcode + addr) */
514 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
515 IXGBE_EEPROM_OPCODE_BITS);
516 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
517 hw->eeprom.address_bits);
520 data = (data >> 8) | (data << 8);
521 ixgbe_shift_out_eeprom_bits(hw, data, 16);
522 ixgbe_standby_eeprom(hw);
524 msleep(hw->eeprom.semaphore_delay);
525 /* Done with writing - release the EEPROM */
526 ixgbe_release_eeprom(hw);
534 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
535 * @hw: pointer to hardware structure
536 * @offset: offset within the EEPROM to be read
537 * @data: read 16 bit value from EEPROM
539 * Reads 16 bit value from EEPROM through bit-bang method
541 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
546 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
548 hw->eeprom.ops.init_params(hw);
550 if (offset >= hw->eeprom.word_size) {
551 status = IXGBE_ERR_EEPROM;
555 /* Prepare the EEPROM for reading */
556 status = ixgbe_acquire_eeprom(hw);
559 if (ixgbe_ready_eeprom(hw) != 0) {
560 ixgbe_release_eeprom(hw);
561 status = IXGBE_ERR_EEPROM;
566 ixgbe_standby_eeprom(hw);
569 * Some SPI eeproms use the 8th address bit embedded in the
572 if ((hw->eeprom.address_bits == 8) && (offset >= 128))
573 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
575 /* Send the READ command (opcode + addr) */
576 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
577 IXGBE_EEPROM_OPCODE_BITS);
578 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2),
579 hw->eeprom.address_bits);
582 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
583 *data = (word_in >> 8) | (word_in << 8);
585 /* End this read operation */
586 ixgbe_release_eeprom(hw);
594 * ixgbe_read_eeprom_generic - Read EEPROM word using EERD
595 * @hw: pointer to hardware structure
596 * @offset: offset of word in the EEPROM to read
597 * @data: word read from the EEPROM
599 * Reads a 16 bit word from the EEPROM using the EERD register.
601 s32 ixgbe_read_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
606 hw->eeprom.ops.init_params(hw);
608 if (offset >= hw->eeprom.word_size) {
609 status = IXGBE_ERR_EEPROM;
613 eerd = (offset << IXGBE_EEPROM_READ_ADDR_SHIFT) +
614 IXGBE_EEPROM_READ_REG_START;
616 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
617 status = ixgbe_poll_eeprom_eerd_done(hw);
620 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
621 IXGBE_EEPROM_READ_REG_DATA);
623 hw_dbg(hw, "Eeprom read timed out\n");
630 * ixgbe_poll_eeprom_eerd_done - Poll EERD status
631 * @hw: pointer to hardware structure
633 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
635 static s32 ixgbe_poll_eeprom_eerd_done(struct ixgbe_hw *hw)
639 s32 status = IXGBE_ERR_EEPROM;
641 for (i = 0; i < IXGBE_EERD_ATTEMPTS; i++) {
642 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
643 if (reg & IXGBE_EEPROM_READ_REG_DONE) {
653 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
654 * @hw: pointer to hardware structure
656 * Prepares EEPROM for access using bit-bang method. This function should
657 * be called before issuing a command to the EEPROM.
659 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
665 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
666 status = IXGBE_ERR_SWFW_SYNC;
669 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
671 /* Request EEPROM Access */
672 eec |= IXGBE_EEC_REQ;
673 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
675 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
676 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
677 if (eec & IXGBE_EEC_GNT)
682 /* Release if grant not acquired */
683 if (!(eec & IXGBE_EEC_GNT)) {
684 eec &= ~IXGBE_EEC_REQ;
685 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
686 hw_dbg(hw, "Could not acquire EEPROM grant\n");
688 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
689 status = IXGBE_ERR_EEPROM;
693 /* Setup EEPROM for Read/Write */
695 /* Clear CS and SK */
696 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
697 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
698 IXGBE_WRITE_FLUSH(hw);
705 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
706 * @hw: pointer to hardware structure
708 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
710 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
712 s32 status = IXGBE_ERR_EEPROM;
717 /* Set timeout value based on size of EEPROM */
718 timeout = hw->eeprom.word_size + 1;
720 /* Get SMBI software semaphore between device drivers first */
721 for (i = 0; i < timeout; i++) {
723 * If the SMBI bit is 0 when we read it, then the bit will be
724 * set and we have the semaphore
726 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
727 if (!(swsm & IXGBE_SWSM_SMBI)) {
734 /* Now get the semaphore between SW/FW through the SWESMBI bit */
736 for (i = 0; i < timeout; i++) {
737 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
739 /* Set the SW EEPROM semaphore bit to request access */
740 swsm |= IXGBE_SWSM_SWESMBI;
741 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
744 * If we set the bit successfully then we got the
747 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
748 if (swsm & IXGBE_SWSM_SWESMBI)
755 * Release semaphores and return error if SW EEPROM semaphore
756 * was not granted because we don't have access to the EEPROM
759 hw_dbg(hw, "Driver can't access the Eeprom - Semaphore "
761 ixgbe_release_eeprom_semaphore(hw);
762 status = IXGBE_ERR_EEPROM;
770 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
771 * @hw: pointer to hardware structure
773 * This function clears hardware semaphore bits.
775 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
779 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
781 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
782 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
783 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
784 IXGBE_WRITE_FLUSH(hw);
788 * ixgbe_ready_eeprom - Polls for EEPROM ready
789 * @hw: pointer to hardware structure
791 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
798 * Read "Status Register" repeatedly until the LSB is cleared. The
799 * EEPROM will signal that the command has been completed by clearing
800 * bit 0 of the internal status register. If it's not cleared within
801 * 5 milliseconds, then error out.
803 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
804 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
805 IXGBE_EEPROM_OPCODE_BITS);
806 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
807 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
811 ixgbe_standby_eeprom(hw);
815 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
816 * devices (and only 0-5mSec on 5V devices)
818 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
819 hw_dbg(hw, "SPI EEPROM Status error\n");
820 status = IXGBE_ERR_EEPROM;
827 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
828 * @hw: pointer to hardware structure
830 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
834 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
836 /* Toggle CS to flush commands */
838 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
839 IXGBE_WRITE_FLUSH(hw);
841 eec &= ~IXGBE_EEC_CS;
842 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
843 IXGBE_WRITE_FLUSH(hw);
848 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
849 * @hw: pointer to hardware structure
850 * @data: data to send to the EEPROM
851 * @count: number of bits to shift out
853 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
860 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
863 * Mask is used to shift "count" bits of "data" out to the EEPROM
864 * one bit at a time. Determine the starting bit based on count
866 mask = 0x01 << (count - 1);
868 for (i = 0; i < count; i++) {
870 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
871 * "1", and then raising and then lowering the clock (the SK
872 * bit controls the clock input to the EEPROM). A "0" is
873 * shifted out to the EEPROM by setting "DI" to "0" and then
874 * raising and then lowering the clock.
879 eec &= ~IXGBE_EEC_DI;
881 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
882 IXGBE_WRITE_FLUSH(hw);
886 ixgbe_raise_eeprom_clk(hw, &eec);
887 ixgbe_lower_eeprom_clk(hw, &eec);
890 * Shift mask to signify next bit of data to shift in to the
896 /* We leave the "DI" bit set to "0" when we leave this routine. */
897 eec &= ~IXGBE_EEC_DI;
898 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
899 IXGBE_WRITE_FLUSH(hw);
903 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
904 * @hw: pointer to hardware structure
906 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
913 * In order to read a register from the EEPROM, we need to shift
914 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
915 * the clock input to the EEPROM (setting the SK bit), and then reading
916 * the value of the "DO" bit. During this "shifting in" process the
917 * "DI" bit should always be clear.
919 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
921 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
923 for (i = 0; i < count; i++) {
925 ixgbe_raise_eeprom_clk(hw, &eec);
927 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
929 eec &= ~(IXGBE_EEC_DI);
930 if (eec & IXGBE_EEC_DO)
933 ixgbe_lower_eeprom_clk(hw, &eec);
940 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
941 * @hw: pointer to hardware structure
942 * @eec: EEC register's current value
944 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
947 * Raise the clock input to the EEPROM
948 * (setting the SK bit), then delay
950 *eec = *eec | IXGBE_EEC_SK;
951 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
952 IXGBE_WRITE_FLUSH(hw);
957 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
958 * @hw: pointer to hardware structure
959 * @eecd: EECD's current value
961 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
964 * Lower the clock input to the EEPROM (clearing the SK bit), then
967 *eec = *eec & ~IXGBE_EEC_SK;
968 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
969 IXGBE_WRITE_FLUSH(hw);
974 * ixgbe_release_eeprom - Release EEPROM, release semaphores
975 * @hw: pointer to hardware structure
977 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
981 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
983 eec |= IXGBE_EEC_CS; /* Pull CS high */
984 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
986 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
987 IXGBE_WRITE_FLUSH(hw);
991 /* Stop requesting EEPROM access */
992 eec &= ~IXGBE_EEC_REQ;
993 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
995 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
999 * ixgbe_calc_eeprom_checksum - Calculates and returns the checksum
1000 * @hw: pointer to hardware structure
1002 static u16 ixgbe_calc_eeprom_checksum(struct ixgbe_hw *hw)
1011 /* Include 0x0-0x3F in the checksum */
1012 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
1013 if (hw->eeprom.ops.read(hw, i, &word) != 0) {
1014 hw_dbg(hw, "EEPROM read failed\n");
1020 /* Include all data from pointers except for the fw pointer */
1021 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
1022 hw->eeprom.ops.read(hw, i, &pointer);
1024 /* Make sure the pointer seems valid */
1025 if (pointer != 0xFFFF && pointer != 0) {
1026 hw->eeprom.ops.read(hw, pointer, &length);
1028 if (length != 0xFFFF && length != 0) {
1029 for (j = pointer+1; j <= pointer+length; j++) {
1030 hw->eeprom.ops.read(hw, j, &word);
1037 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1043 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
1044 * @hw: pointer to hardware structure
1045 * @checksum_val: calculated checksum
1047 * Performs checksum calculation and validates the EEPROM checksum. If the
1048 * caller does not need checksum_val, the value can be NULL.
1050 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
1055 u16 read_checksum = 0;
1058 * Read the first word from the EEPROM. If this times out or fails, do
1059 * not continue or we could be in for a very long wait while every
1062 status = hw->eeprom.ops.read(hw, 0, &checksum);
1065 checksum = ixgbe_calc_eeprom_checksum(hw);
1067 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
1070 * Verify read checksum from EEPROM is the same as
1071 * calculated checksum
1073 if (read_checksum != checksum)
1074 status = IXGBE_ERR_EEPROM_CHECKSUM;
1076 /* If the user cares, return the calculated checksum */
1078 *checksum_val = checksum;
1080 hw_dbg(hw, "EEPROM read failed\n");
1087 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
1088 * @hw: pointer to hardware structure
1090 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
1096 * Read the first word from the EEPROM. If this times out or fails, do
1097 * not continue or we could be in for a very long wait while every
1100 status = hw->eeprom.ops.read(hw, 0, &checksum);
1103 checksum = ixgbe_calc_eeprom_checksum(hw);
1104 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
1107 hw_dbg(hw, "EEPROM read failed\n");
1114 * ixgbe_validate_mac_addr - Validate MAC address
1115 * @mac_addr: pointer to MAC address.
1117 * Tests a MAC address to ensure it is a valid Individual Address
1119 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
1123 /* Make sure it is not a multicast address */
1124 if (IXGBE_IS_MULTICAST(mac_addr))
1125 status = IXGBE_ERR_INVALID_MAC_ADDR;
1126 /* Not a broadcast address */
1127 else if (IXGBE_IS_BROADCAST(mac_addr))
1128 status = IXGBE_ERR_INVALID_MAC_ADDR;
1129 /* Reject the zero address */
1130 else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
1131 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0)
1132 status = IXGBE_ERR_INVALID_MAC_ADDR;
1138 * ixgbe_set_rar_generic - Set Rx address register
1139 * @hw: pointer to hardware structure
1140 * @index: Receive address register to write
1141 * @addr: Address to put into receive address register
1142 * @vmdq: VMDq "set" or "pool" index
1143 * @enable_addr: set flag that address is active
1145 * Puts an ethernet address into a receive address register.
1147 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
1150 u32 rar_low, rar_high;
1151 u32 rar_entries = hw->mac.num_rar_entries;
1153 /* setup VMDq pool selection before this RAR gets enabled */
1154 hw->mac.ops.set_vmdq(hw, index, vmdq);
1156 /* Make sure we are using a valid rar index range */
1157 if (index < rar_entries) {
1159 * HW expects these in little endian so we reverse the byte
1160 * order from network order (big endian) to little endian
1162 rar_low = ((u32)addr[0] |
1163 ((u32)addr[1] << 8) |
1164 ((u32)addr[2] << 16) |
1165 ((u32)addr[3] << 24));
1167 * Some parts put the VMDq setting in the extra RAH bits,
1168 * so save everything except the lower 16 bits that hold part
1169 * of the address and the address valid bit.
1171 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1172 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1173 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
1175 if (enable_addr != 0)
1176 rar_high |= IXGBE_RAH_AV;
1178 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
1179 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1181 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1188 * ixgbe_clear_rar_generic - Remove Rx address register
1189 * @hw: pointer to hardware structure
1190 * @index: Receive address register to write
1192 * Clears an ethernet address from a receive address register.
1194 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
1197 u32 rar_entries = hw->mac.num_rar_entries;
1199 /* Make sure we are using a valid rar index range */
1200 if (index < rar_entries) {
1202 * Some parts put the VMDq setting in the extra RAH bits,
1203 * so save everything except the lower 16 bits that hold part
1204 * of the address and the address valid bit.
1206 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1207 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
1209 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
1210 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1212 hw_dbg(hw, "RAR index %d is out of range.\n", index);
1215 /* clear VMDq pool/queue selection for this RAR */
1216 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
1222 * ixgbe_enable_rar - Enable Rx address register
1223 * @hw: pointer to hardware structure
1224 * @index: index into the RAR table
1226 * Enables the select receive address register.
1228 static void ixgbe_enable_rar(struct ixgbe_hw *hw, u32 index)
1232 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1233 rar_high |= IXGBE_RAH_AV;
1234 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1238 * ixgbe_disable_rar - Disable Rx address register
1239 * @hw: pointer to hardware structure
1240 * @index: index into the RAR table
1242 * Disables the select receive address register.
1244 static void ixgbe_disable_rar(struct ixgbe_hw *hw, u32 index)
1248 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
1249 rar_high &= (~IXGBE_RAH_AV);
1250 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
1254 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
1255 * @hw: pointer to hardware structure
1257 * Places the MAC address in receive address register 0 and clears the rest
1258 * of the receive address registers. Clears the multicast table. Assumes
1259 * the receiver is in reset when the routine is called.
1261 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
1264 u32 rar_entries = hw->mac.num_rar_entries;
1267 * If the current mac address is valid, assume it is a software override
1268 * to the permanent address.
1269 * Otherwise, use the permanent address from the eeprom.
1271 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
1272 IXGBE_ERR_INVALID_MAC_ADDR) {
1273 /* Get the MAC address from the RAR0 for later reference */
1274 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
1276 hw_dbg(hw, " Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
1277 hw->mac.addr[0], hw->mac.addr[1],
1279 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1280 hw->mac.addr[4], hw->mac.addr[5]);
1282 /* Setup the receive address. */
1283 hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
1284 hw_dbg(hw, " New MAC Addr =%.2X %.2X %.2X ",
1285 hw->mac.addr[0], hw->mac.addr[1],
1287 hw_dbg(hw, "%.2X %.2X %.2X\n", hw->mac.addr[3],
1288 hw->mac.addr[4], hw->mac.addr[5]);
1290 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
1292 hw->addr_ctrl.overflow_promisc = 0;
1294 hw->addr_ctrl.rar_used_count = 1;
1296 /* Zero out the other receive addresses. */
1297 hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
1298 for (i = 1; i < rar_entries; i++) {
1299 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1300 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1304 hw->addr_ctrl.mc_addr_in_rar_count = 0;
1305 hw->addr_ctrl.mta_in_use = 0;
1306 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1308 hw_dbg(hw, " Clearing MTA\n");
1309 for (i = 0; i < hw->mac.mcft_size; i++)
1310 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1312 if (hw->mac.ops.init_uta_tables)
1313 hw->mac.ops.init_uta_tables(hw);
1319 * ixgbe_add_uc_addr - Adds a secondary unicast address.
1320 * @hw: pointer to hardware structure
1321 * @addr: new address
1323 * Adds it to unused receive address register or goes into promiscuous mode.
1325 static void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
1327 u32 rar_entries = hw->mac.num_rar_entries;
1330 hw_dbg(hw, " UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
1331 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
1334 * Place this address in the RAR if there is room,
1335 * else put the controller into promiscuous mode
1337 if (hw->addr_ctrl.rar_used_count < rar_entries) {
1338 rar = hw->addr_ctrl.rar_used_count -
1339 hw->addr_ctrl.mc_addr_in_rar_count;
1340 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
1341 hw_dbg(hw, "Added a secondary address to RAR[%d]\n", rar);
1342 hw->addr_ctrl.rar_used_count++;
1344 hw->addr_ctrl.overflow_promisc++;
1347 hw_dbg(hw, "ixgbe_add_uc_addr Complete\n");
1351 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
1352 * @hw: pointer to hardware structure
1353 * @addr_list: the list of new addresses
1354 * @addr_count: number of addresses
1355 * @next: iterator function to walk the address list
1357 * The given list replaces any existing list. Clears the secondary addrs from
1358 * receive address registers. Uses unused receive address registers for the
1359 * first secondary addresses, and falls back to promiscuous mode as needed.
1361 * Drivers using secondary unicast addresses must set user_set_promisc when
1362 * manually putting the device into promiscuous mode.
1364 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw,
1365 struct list_head *uc_list)
1368 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
1371 struct netdev_hw_addr *ha;
1374 * Clear accounting of old secondary address list,
1375 * don't count RAR[0]
1377 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
1378 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
1379 hw->addr_ctrl.overflow_promisc = 0;
1381 /* Zero out the other receive addresses */
1382 hw_dbg(hw, "Clearing RAR[1-%d]\n", uc_addr_in_use);
1383 for (i = 1; i <= uc_addr_in_use; i++) {
1384 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
1385 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
1388 /* Add the new addresses */
1389 list_for_each_entry(ha, uc_list, list) {
1390 hw_dbg(hw, " Adding the secondary addresses:\n");
1391 ixgbe_add_uc_addr(hw, ha->addr, 0);
1394 if (hw->addr_ctrl.overflow_promisc) {
1395 /* enable promisc if not already in overflow or set by user */
1396 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1397 hw_dbg(hw, " Entering address overflow promisc mode\n");
1398 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1399 fctrl |= IXGBE_FCTRL_UPE;
1400 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1403 /* only disable if set by overflow, not by user */
1404 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
1405 hw_dbg(hw, " Leaving address overflow promisc mode\n");
1406 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1407 fctrl &= ~IXGBE_FCTRL_UPE;
1408 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1412 hw_dbg(hw, "ixgbe_update_uc_addr_list_generic Complete\n");
1417 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
1418 * @hw: pointer to hardware structure
1419 * @mc_addr: the multicast address
1421 * Extracts the 12 bits, from a multicast address, to determine which
1422 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
1423 * incoming rx multicast addresses, to determine the bit-vector to check in
1424 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
1425 * by the MO field of the MCSTCTRL. The MO field is set during initialization
1426 * to mc_filter_type.
1428 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
1432 switch (hw->mac.mc_filter_type) {
1433 case 0: /* use bits [47:36] of the address */
1434 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
1436 case 1: /* use bits [46:35] of the address */
1437 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
1439 case 2: /* use bits [45:34] of the address */
1440 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
1442 case 3: /* use bits [43:32] of the address */
1443 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
1445 default: /* Invalid mc_filter_type */
1446 hw_dbg(hw, "MC filter type param set incorrectly\n");
1450 /* vector can only be 12-bits or boundary will be exceeded */
1456 * ixgbe_set_mta - Set bit-vector in multicast table
1457 * @hw: pointer to hardware structure
1458 * @hash_value: Multicast address hash value
1460 * Sets the bit-vector in the multicast table.
1462 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
1469 hw->addr_ctrl.mta_in_use++;
1471 vector = ixgbe_mta_vector(hw, mc_addr);
1472 hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
1475 * The MTA is a register array of 128 32-bit registers. It is treated
1476 * like an array of 4096 bits. We want to set bit
1477 * BitArray[vector_value]. So we figure out what register the bit is
1478 * in, read it, OR in the new bit, then write back the new value. The
1479 * register is determined by the upper 7 bits of the vector value and
1480 * the bit within that register are determined by the lower 5 bits of
1483 vector_reg = (vector >> 5) & 0x7F;
1484 vector_bit = vector & 0x1F;
1485 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg));
1486 mta_reg |= (1 << vector_bit);
1487 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg);
1491 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
1492 * @hw: pointer to hardware structure
1493 * @mc_addr_list: the list of new multicast addresses
1494 * @mc_addr_count: number of addresses
1495 * @next: iterator function to walk the multicast address list
1497 * The given list replaces any existing list. Clears the MC addrs from receive
1498 * address registers and the multicast table. Uses unused receive address
1499 * registers for the first multicast addresses, and hashes the rest into the
1502 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
1503 u32 mc_addr_count, ixgbe_mc_addr_itr next)
1509 * Set the new number of MC addresses that we are being requested to
1512 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
1513 hw->addr_ctrl.mta_in_use = 0;
1516 hw_dbg(hw, " Clearing MTA\n");
1517 for (i = 0; i < hw->mac.mcft_size; i++)
1518 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
1520 /* Add the new addresses */
1521 for (i = 0; i < mc_addr_count; i++) {
1522 hw_dbg(hw, " Adding the multicast addresses:\n");
1523 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
1527 if (hw->addr_ctrl.mta_in_use > 0)
1528 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
1529 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
1531 hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
1536 * ixgbe_enable_mc_generic - Enable multicast address in RAR
1537 * @hw: pointer to hardware structure
1539 * Enables multicast address in RAR and the use of the multicast hash table.
1541 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
1544 u32 rar_entries = hw->mac.num_rar_entries;
1545 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1547 if (a->mc_addr_in_rar_count > 0)
1548 for (i = (rar_entries - a->mc_addr_in_rar_count);
1549 i < rar_entries; i++)
1550 ixgbe_enable_rar(hw, i);
1552 if (a->mta_in_use > 0)
1553 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
1554 hw->mac.mc_filter_type);
1560 * ixgbe_disable_mc_generic - Disable multicast address in RAR
1561 * @hw: pointer to hardware structure
1563 * Disables multicast address in RAR and the use of the multicast hash table.
1565 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
1568 u32 rar_entries = hw->mac.num_rar_entries;
1569 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
1571 if (a->mc_addr_in_rar_count > 0)
1572 for (i = (rar_entries - a->mc_addr_in_rar_count);
1573 i < rar_entries; i++)
1574 ixgbe_disable_rar(hw, i);
1576 if (a->mta_in_use > 0)
1577 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
1583 * ixgbe_fc_enable_generic - Enable flow control
1584 * @hw: pointer to hardware structure
1585 * @packetbuf_num: packet buffer number (0-7)
1587 * Enable flow control according to the current settings.
1589 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num)
1592 u32 mflcn_reg, fccfg_reg;
1597 if (hw->fc.requested_mode == ixgbe_fc_pfc)
1600 #endif /* CONFIG_DCB */
1601 /* Negotiate the fc mode to use */
1602 ret_val = ixgbe_fc_autoneg(hw);
1606 /* Disable any previous flow control settings */
1607 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
1608 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE);
1610 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
1611 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
1614 * The possible values of fc.current_mode are:
1615 * 0: Flow control is completely disabled
1616 * 1: Rx flow control is enabled (we can receive pause frames,
1617 * but not send pause frames).
1618 * 2: Tx flow control is enabled (we can send pause frames but
1619 * we do not support receiving pause frames).
1620 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1621 * 4: Priority Flow Control is enabled.
1624 switch (hw->fc.current_mode) {
1627 * Flow control is disabled by software override or autoneg.
1628 * The code below will actually disable it in the HW.
1631 case ixgbe_fc_rx_pause:
1633 * Rx Flow control is enabled and Tx Flow control is
1634 * disabled by software override. Since there really
1635 * isn't a way to advertise that we are capable of RX
1636 * Pause ONLY, we will advertise that we support both
1637 * symmetric and asymmetric Rx PAUSE. Later, we will
1638 * disable the adapter's ability to send PAUSE frames.
1640 mflcn_reg |= IXGBE_MFLCN_RFCE;
1642 case ixgbe_fc_tx_pause:
1644 * Tx Flow control is enabled, and Rx Flow control is
1645 * disabled by software override.
1647 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1650 /* Flow control (both Rx and Tx) is enabled by SW override. */
1651 mflcn_reg |= IXGBE_MFLCN_RFCE;
1652 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
1658 #endif /* CONFIG_DCB */
1660 hw_dbg(hw, "Flow control param set incorrectly\n");
1661 ret_val = -IXGBE_ERR_CONFIG;
1666 /* Set 802.3x based flow control settings. */
1667 mflcn_reg |= IXGBE_MFLCN_DPF;
1668 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
1669 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
1671 reg = IXGBE_READ_REG(hw, IXGBE_MTQC);
1672 /* Thresholds are different for link flow control when in DCB mode */
1673 if (reg & IXGBE_MTQC_RT_ENA) {
1674 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num));
1676 /* Always disable XON for LFC when in DCB mode */
1677 reg = (rx_pba_size >> 5) & 0xFFE0;
1678 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg);
1680 reg = (rx_pba_size >> 2) & 0xFFE0;
1681 if (hw->fc.current_mode & ixgbe_fc_tx_pause)
1682 reg |= IXGBE_FCRTH_FCEN;
1683 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg);
1686 * Set up and enable Rx high/low water mark thresholds,
1689 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
1690 if (hw->fc.send_xon) {
1692 IXGBE_FCRTL_82599(packetbuf_num),
1697 IXGBE_FCRTL_82599(packetbuf_num),
1701 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num),
1702 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
1706 /* Configure pause time (2 TCs per register) */
1707 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2));
1708 if ((packetbuf_num & 1) == 0)
1709 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
1711 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
1712 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
1714 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
1721 * ixgbe_fc_autoneg - Configure flow control
1722 * @hw: pointer to hardware structure
1724 * Compares our advertised flow control capabilities to those advertised by
1725 * our link partner, and determines the proper flow control mode to use.
1727 s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw)
1730 ixgbe_link_speed speed;
1731 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
1735 * AN should have completed when the cable was plugged in.
1736 * Look for reasons to bail out. Bail out if:
1737 * - FC autoneg is disabled, or if
1738 * - we don't have multispeed fiber, or if
1739 * - we're not running at 1G, or if
1740 * - link is not up, or if
1741 * - link is up but AN did not complete, or if
1742 * - link is up and AN completed but timed out
1744 * Since we're being called from an LSC, link is already know to be up.
1745 * So use link_up_wait_to_complete=false.
1747 hw->mac.ops.check_link(hw, &speed, &link_up, false);
1748 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
1750 if (hw->fc.disable_fc_autoneg ||
1751 !hw->phy.multispeed_fiber ||
1752 (speed != IXGBE_LINK_SPEED_1GB_FULL) ||
1754 ((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
1755 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
1756 hw->fc.fc_was_autonegged = false;
1757 hw->fc.current_mode = hw->fc.requested_mode;
1758 hw_dbg(hw, "Autoneg FC was skipped.\n");
1763 * Read the AN advertisement and LP ability registers and resolve
1764 * local flow control settings accordingly
1766 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1767 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
1768 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1769 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) {
1771 * Now we need to check if the user selected Rx ONLY
1772 * of pause frames. In this case, we had to advertise
1773 * FULL flow control because we could not advertise RX
1774 * ONLY. Hence, we must now check to see if we need to
1775 * turn OFF the TRANSMISSION of PAUSE frames.
1777 if (hw->fc.requested_mode == ixgbe_fc_full) {
1778 hw->fc.current_mode = ixgbe_fc_full;
1779 hw_dbg(hw, "Flow Control = FULL.\n");
1781 hw->fc.current_mode = ixgbe_fc_rx_pause;
1782 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1784 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1785 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1786 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1787 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1788 hw->fc.current_mode = ixgbe_fc_tx_pause;
1789 hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
1790 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1791 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) &&
1792 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) &&
1793 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) {
1794 hw->fc.current_mode = ixgbe_fc_rx_pause;
1795 hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
1797 hw->fc.current_mode = ixgbe_fc_none;
1798 hw_dbg(hw, "Flow Control = NONE.\n");
1801 /* Record that current_mode is the result of a successful autoneg */
1802 hw->fc.fc_was_autonegged = true;
1809 * ixgbe_setup_fc - Set up flow control
1810 * @hw: pointer to hardware structure
1812 * Called at init time to set up flow control.
1814 s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num)
1820 if (hw->fc.requested_mode == ixgbe_fc_pfc) {
1821 hw->fc.current_mode = hw->fc.requested_mode;
1826 /* Validate the packetbuf configuration */
1827 if (packetbuf_num < 0 || packetbuf_num > 7) {
1828 hw_dbg(hw, "Invalid packet buffer number [%d], expected range "
1829 "is 0-7\n", packetbuf_num);
1830 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1835 * Validate the water mark configuration. Zero water marks are invalid
1836 * because it causes the controller to just blast out fc packets.
1838 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
1839 hw_dbg(hw, "Invalid water mark configuration\n");
1840 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1845 * Validate the requested mode. Strict IEEE mode does not allow
1846 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
1848 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
1849 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict "
1851 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
1856 * 10gig parts do not have a word in the EEPROM to determine the
1857 * default flow control setting, so we explicitly set it to full.
1859 if (hw->fc.requested_mode == ixgbe_fc_default)
1860 hw->fc.requested_mode = ixgbe_fc_full;
1863 * Set up the 1G flow control advertisement registers so the HW will be
1864 * able to do fc autoneg once the cable is plugged in. If we end up
1865 * using 10g instead, this is harmless.
1867 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
1870 * The possible values of fc.requested_mode are:
1871 * 0: Flow control is completely disabled
1872 * 1: Rx flow control is enabled (we can receive pause frames,
1873 * but not send pause frames).
1874 * 2: Tx flow control is enabled (we can send pause frames but
1875 * we do not support receiving pause frames).
1876 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1878 * 4: Priority Flow Control is enabled.
1882 switch (hw->fc.requested_mode) {
1884 /* Flow control completely disabled by software override. */
1885 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1887 case ixgbe_fc_rx_pause:
1889 * Rx Flow control is enabled and Tx Flow control is
1890 * disabled by software override. Since there really
1891 * isn't a way to advertise that we are capable of RX
1892 * Pause ONLY, we will advertise that we support both
1893 * symmetric and asymmetric Rx PAUSE. Later, we will
1894 * disable the adapter's ability to send PAUSE frames.
1896 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1898 case ixgbe_fc_tx_pause:
1900 * Tx Flow control is enabled, and Rx Flow control is
1901 * disabled by software override.
1903 reg |= (IXGBE_PCS1GANA_ASM_PAUSE);
1904 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE);
1907 /* Flow control (both Rx and Tx) is enabled by SW override. */
1908 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
1914 #endif /* CONFIG_DCB */
1916 hw_dbg(hw, "Flow control param set incorrectly\n");
1917 ret_val = -IXGBE_ERR_CONFIG;
1922 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
1923 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
1925 /* Enable and restart autoneg to inform the link partner */
1926 reg |= IXGBE_PCS1GLCTL_AN_ENABLE | IXGBE_PCS1GLCTL_AN_RESTART;
1928 /* Disable AN timeout */
1929 if (hw->fc.strict_ieee)
1930 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
1932 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
1933 hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
1940 * ixgbe_disable_pcie_master - Disable PCI-express master access
1941 * @hw: pointer to hardware structure
1943 * Disables PCI-Express master access and verifies there are no pending
1944 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
1945 * bit hasn't caused the master requests to be disabled, else 0
1946 * is returned signifying master requests disabled.
1948 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
1952 u32 number_of_queues;
1953 s32 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
1955 /* Disable the receive unit by stopping each queue */
1956 number_of_queues = hw->mac.max_rx_queues;
1957 for (i = 0; i < number_of_queues; i++) {
1958 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1959 if (reg_val & IXGBE_RXDCTL_ENABLE) {
1960 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1961 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1965 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL);
1966 reg_val |= IXGBE_CTRL_GIO_DIS;
1967 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val);
1969 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
1970 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) {
1982 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
1983 * @hw: pointer to hardware structure
1984 * @mask: Mask to specify which semaphore to acquire
1986 * Acquires the SWFW semaphore thought the GSSR register for the specified
1987 * function (CSR, PHY0, PHY1, EEPROM, Flash)
1989 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
1993 u32 fwmask = mask << 5;
1997 if (ixgbe_get_eeprom_semaphore(hw))
1998 return -IXGBE_ERR_SWFW_SYNC;
2000 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2001 if (!(gssr & (fwmask | swmask)))
2005 * Firmware currently using resource (fwmask) or other software
2006 * thread currently using resource (swmask)
2008 ixgbe_release_eeprom_semaphore(hw);
2014 hw_dbg(hw, "Driver can't access resource, GSSR timeout.\n");
2015 return -IXGBE_ERR_SWFW_SYNC;
2019 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2021 ixgbe_release_eeprom_semaphore(hw);
2026 * ixgbe_release_swfw_sync - Release SWFW semaphore
2027 * @hw: pointer to hardware structure
2028 * @mask: Mask to specify which semaphore to release
2030 * Releases the SWFW semaphore thought the GSSR register for the specified
2031 * function (CSR, PHY0, PHY1, EEPROM, Flash)
2033 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
2038 ixgbe_get_eeprom_semaphore(hw);
2040 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
2042 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
2044 ixgbe_release_eeprom_semaphore(hw);
2048 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
2049 * @hw: pointer to hardware structure
2050 * @regval: register value to write to RXCTRL
2052 * Enables the Rx DMA unit
2054 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
2056 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2062 * ixgbe_blink_led_start_generic - Blink LED based on index.
2063 * @hw: pointer to hardware structure
2064 * @index: led number to blink
2066 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
2068 ixgbe_link_speed speed = 0;
2070 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2071 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2074 * Link must be up to auto-blink the LEDs;
2075 * Force it if link is down.
2077 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2080 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2081 autoc_reg |= IXGBE_AUTOC_FLU;
2082 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2086 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2087 led_reg |= IXGBE_LED_BLINK(index);
2088 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2089 IXGBE_WRITE_FLUSH(hw);
2095 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
2096 * @hw: pointer to hardware structure
2097 * @index: led number to stop blinking
2099 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
2101 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2102 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
2104 autoc_reg &= ~IXGBE_AUTOC_FLU;
2105 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2106 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2108 led_reg &= ~IXGBE_LED_MODE_MASK(index);
2109 led_reg &= ~IXGBE_LED_BLINK(index);
2110 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
2111 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
2112 IXGBE_WRITE_FLUSH(hw);