drivers/net/ixgbe/ixgbe_82598.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34
  35 #define IXGBE_82598_MAX_TX_QUEUES 32
  36 #define IXGBE_82598_MAX_RX_QUEUES 64
  37 #define IXGBE_82598_RAR_ENTRIES   16
  38 #define IXGBE_82598_MC_TBL_SIZE  128
  39 #define IXGBE_82598_VFT_TBL_SIZE 128
  40
  41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
  42                                              ixgbe_link_speed *speed,
  43                                              bool *autoneg);
  44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
  45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
  46                                                ixgbe_link_speed speed,
  47                                                bool autoneg,
  48                                                bool autoneg_wait_to_complete);
  49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
  50                                        u8 *eeprom_data);
  51
  52 /**
  53  *  ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Read PCIe configuration space, and get the MSI-X vector count from
  57  *  the capabilities table.
  58  **/
  59 u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_adapter *adapter = hw->back;
  62         u16 msix_count;
  63         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
  64                              &msix_count);
  65         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
  66
  67         /* MSI-X count is zero-based in HW, so increment to give proper value */
  68         msix_count++;
  69
  70         return msix_count;
  71 }
  72
  73 /**
  74  */
  75 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
  76 {
  77         struct ixgbe_mac_info *mac = &hw->mac;
  78         struct ixgbe_phy_info *phy = &hw->phy;
  79         s32 ret_val = 0;
  80         u16 list_offset, data_offset;
  81
  82         /* Call PHY identify routine to get the phy type */
  83         ixgbe_identify_phy_generic(hw);
  84
  85         /* PHY Init */
  86         switch (phy->type) {
  87         case ixgbe_phy_tn:
  88                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
  89                 phy->ops.get_firmware_version =
  90                              &ixgbe_get_phy_firmware_version_tnx;
  91                 break;
  92         case ixgbe_phy_nl:
  93                 phy->ops.reset = &ixgbe_reset_phy_nl;
  94
  95                 /* Call SFP+ identify routine to get the SFP+ module type */
  96                 ret_val = phy->ops.identify_sfp(hw);
  97                 if (ret_val != 0)
  98                         goto out;
  99                 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
 100                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 101                         goto out;
 102                 }
 103
 104                 /* Check to see if SFP+ module is supported */
 105                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
 106                                                               &list_offset,
 107                                                               &data_offset);
 108                 if (ret_val != 0) {
 109                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 110                         goto out;
 111                 }
 112                 break;
 113         default:
 114                 break;
 115         }
 116
 117         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 118                 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
 119                 mac->ops.setup_link_speed =
 120                                      &ixgbe_setup_copper_link_speed_82598;
 121                 mac->ops.get_link_capabilities =
 122                                      &ixgbe_get_copper_link_capabilities_82598;
 123         }
 124
 125         mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
 126         mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
 127         mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
 128         mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
 129         mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
 130         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
 131
 132 out:
 133         return ret_val;
 134 }
 135
 136 /**
 137  *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
 138  *  @hw: pointer to hardware structure
 139  *  @speed: pointer to link speed
 140  *  @autoneg: boolean auto-negotiation value
 141  *
 142  *  Determines the link capabilities by reading the AUTOC register.
 143  **/
 144 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
 145                                              ixgbe_link_speed *speed,
 146                                              bool *autoneg)
 147 {
 148         s32 status = 0;
 149
 150         /*
 151          * Determine link capabilities based on the stored value of AUTOC,
 152          * which represents EEPROM defaults.
 153          */
 154         switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
 155         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 156                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 157                 *autoneg = false;
 158                 break;
 159
 160         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 161                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 162                 *autoneg = false;
 163                 break;
 164
 165         case IXGBE_AUTOC_LMS_1G_AN:
 166                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 167                 *autoneg = true;
 168                 break;
 169
 170         case IXGBE_AUTOC_LMS_KX4_AN:
 171         case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
 172                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
 173                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 174                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 175                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
 176                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 177                 *autoneg = true;
 178                 break;
 179
 180         default:
 181                 status = IXGBE_ERR_LINK_SETUP;
 182                 break;
 183         }
 184
 185         return status;
 186 }
 187
 188 /**
 189  *  ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
 190  *  @hw: pointer to hardware structure
 191  *  @speed: pointer to link speed
 192  *  @autoneg: boolean auto-negotiation value
 193  *
 194  *  Determines the link capabilities by reading the AUTOC register.
 195  **/
 196 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
 197                                                     ixgbe_link_speed *speed,
 198                                                     bool *autoneg)
 199 {
 200         s32 status = IXGBE_ERR_LINK_SETUP;
 201         u16 speed_ability;
 202
 203         *speed = 0;
 204         *autoneg = true;
 205
 206         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 207                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 208                                       &speed_ability);
 209
 210         if (status == 0) {
 211                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 212                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 213                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 214                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 215         }
 216
 217         return status;
 218 }
 219
 220 /**
 221  *  ixgbe_get_media_type_82598 - Determines media type
 222  *  @hw: pointer to hardware structure
 223  *
 224  *  Returns the media type (fiber, copper, backplane)
 225  **/
 226 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
 227 {
 228         enum ixgbe_media_type media_type;
 229
 230         /* Media type for I82598 is based on device ID */
 231         switch (hw->device_id) {
 232         case IXGBE_DEV_ID_82598:
 233         case IXGBE_DEV_ID_82598_BX:
 234                 media_type = ixgbe_media_type_backplane;
 235                 break;
 236         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
 237         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
 238         case IXGBE_DEV_ID_82598EB_CX4:
 239         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
 240         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
 241         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
 242         case IXGBE_DEV_ID_82598EB_XF_LR:
 243         case IXGBE_DEV_ID_82598EB_SFP_LOM:
 244                 media_type = ixgbe_media_type_fiber;
 245                 break;
 246         case IXGBE_DEV_ID_82598AT:
 247                 media_type = ixgbe_media_type_copper;
 248                 break;
 249         default:
 250                 media_type = ixgbe_media_type_unknown;
 251                 break;
 252         }
 253
 254         return media_type;
 255 }
 256
 257 /**
 258  *  ixgbe_setup_fc_82598 - Configure flow control settings
 259  *  @hw: pointer to hardware structure
 260  *  @packetbuf_num: packet buffer number (0-7)
 261  *
 262  *  Configures the flow control settings based on SW configuration.  This
 263  *  function is used for 802.3x flow control configuration only.
 264  **/
 265 static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 266 {
 267         u32 frctl_reg;
 268         u32 rmcs_reg;
 269
 270         if (packetbuf_num < 0 || packetbuf_num > 7) {
 271                 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
 272                           " 0-7\n", packetbuf_num);
 273         }
 274
 275         frctl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 276         frctl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
 277
 278         rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
 279         rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
 280
 281         /*
 282          * 10 gig parts do not have a word in the EEPROM to determine the
 283          * default flow control setting, so we explicitly set it to full.
 284          */
 285         if (hw->fc.type == ixgbe_fc_default)
 286                 hw->fc.type = ixgbe_fc_full;
 287
 288         /*
 289          * We want to save off the original Flow Control configuration just in
 290          * case we get disconnected and then reconnected into a different hub
 291          * or switch with different Flow Control capabilities.
 292          */
 293         hw->fc.original_type = hw->fc.type;
 294
 295         /*
 296          * The possible values of the "flow_control" parameter are:
 297          * 0: Flow control is completely disabled
 298          * 1: Rx flow control is enabled (we can receive pause frames but not
 299          *    send pause frames).
 300          * 2: Tx flow control is enabled (we can send pause frames but we do not
 301          *    support receiving pause frames)
 302          * 3: Both Rx and Tx flow control (symmetric) are enabled.
 303          * other: Invalid.
 304          */
 305         switch (hw->fc.type) {
 306         case ixgbe_fc_none:
 307                 break;
 308         case ixgbe_fc_rx_pause:
 309                 /*
 310                  * Rx Flow control is enabled,
 311                  * and Tx Flow control is disabled.
 312                  */
 313                 frctl_reg |= IXGBE_FCTRL_RFCE;
 314                 break;
 315         case ixgbe_fc_tx_pause:
 316                 /*
 317                  * Tx Flow control is enabled, and Rx Flow control is disabled,
 318                  * by a software over-ride.
 319                  */
 320                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 321                 break;
 322         case ixgbe_fc_full:
 323                 /*
 324                  * Flow control (both Rx and Tx) is enabled by a software
 325                  * over-ride.
 326                  */
 327                 frctl_reg |= IXGBE_FCTRL_RFCE;
 328                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 329                 break;
 330         default:
 331                 /* We should never get here.  The value should be 0-3. */
 332                 hw_dbg(hw, "Flow control param set incorrectly\n");
 333                 break;
 334         }
 335
 336         /* Enable 802.3x based flow control settings. */
 337         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, frctl_reg);
 338         IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
 339
 340         /*
 341          * Check for invalid software configuration, zeros are completely
 342          * invalid for all parameters used past this point, and if we enable
 343          * flow control with zero water marks, we blast flow control packets.
 344          */
 345         if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
 346                 hw_dbg(hw, "Flow control structure initialized incorrectly\n");
 347                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
 348         }
 349
 350         /*
 351          * We need to set up the Receive Threshold high and low water
 352          * marks as well as (optionally) enabling the transmission of
 353          * XON frames.
 354          */
 355         if (hw->fc.type & ixgbe_fc_tx_pause) {
 356                 if (hw->fc.send_xon) {
 357                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 358                                         (hw->fc.low_water | IXGBE_FCRTL_XONE));
 359                 } else {
 360                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 361                                         hw->fc.low_water);
 362                 }
 363                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
 364                                 (hw->fc.high_water)|IXGBE_FCRTH_FCEN);
 365         }
 366
 367         IXGBE_WRITE_REG(hw, IXGBE_FCTTV(0), hw->fc.pause_time);
 368         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
 369
 370         return 0;
 371 }
 372
 373 /**
 374  *  ixgbe_setup_mac_link_82598 - Configures MAC link settings
 375  *  @hw: pointer to hardware structure
 376  *
 377  *  Configures link settings based on values in the ixgbe_hw struct.
 378  *  Restarts the link.  Performs autonegotiation if needed.
 379  **/
 380 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
 381 {
 382         u32 autoc_reg;
 383         u32 links_reg;
 384         u32 i;
 385         s32 status = 0;
 386
 387         /* Restart link */
 388         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 389         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 390         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 391
 392         /* Only poll for autoneg to complete if specified to do so */
 393         if (hw->phy.autoneg_wait_to_complete) {
 394                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 395                      IXGBE_AUTOC_LMS_KX4_AN ||
 396                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 397                      IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 398                         links_reg = 0; /* Just in case Autoneg time = 0 */
 399                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 400                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 401                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 402                                         break;
 403                                 msleep(100);
 404                         }
 405                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 406                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 407                                 hw_dbg(hw, "Autonegotiation did not complete.\n");
 408                         }
 409                 }
 410         }
 411
 412         /*
 413          * We want to save off the original Flow Control configuration just in
 414          * case we get disconnected and then reconnected into a different hub
 415          * or switch with different Flow Control capabilities.
 416          */
 417         hw->fc.original_type = hw->fc.type;
 418         ixgbe_setup_fc_82598(hw, 0);
 419
 420         /* Add delay to filter out noises during initial link setup */
 421         msleep(50);
 422
 423         return status;
 424 }
 425
 426 /**
 427  *  ixgbe_check_mac_link_82598 - Get link/speed status
 428  *  @hw: pointer to hardware structure
 429  *  @speed: pointer to link speed
 430  *  @link_up: true is link is up, false otherwise
 431  *  @link_up_wait_to_complete: bool used to wait for link up or not
 432  *
 433  *  Reads the links register to determine if link is up and the current speed
 434  **/
 435 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
 436                                       ixgbe_link_speed *speed, bool *link_up,
 437                                       bool link_up_wait_to_complete)
 438 {
 439         u32 links_reg;
 440         u32 i;
 441         u16 link_reg, adapt_comp_reg;
 442
 443         /*
 444          * SERDES PHY requires us to read link status from register 0xC79F.
 445          * Bit 0 set indicates link is up/ready; clear indicates link down.
 446          * 0xC00C is read to check that the XAUI lanes are active.  Bit 0
 447          * clear indicates active; set indicates inactive.
 448          */
 449         if (hw->phy.type == ixgbe_phy_nl) {
 450                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 451                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 452                 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
 453                                      &adapt_comp_reg);
 454                 if (link_up_wait_to_complete) {
 455                         for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 456                                 if ((link_reg & 1) &&
 457                                     ((adapt_comp_reg & 1) == 0)) {
 458                                         *link_up = true;
 459                                         break;
 460                                 } else {
 461                                         *link_up = false;
 462                                 }
 463                                 msleep(100);
 464                                 hw->phy.ops.read_reg(hw, 0xC79F,
 465                                                      IXGBE_TWINAX_DEV,
 466                                                      &link_reg);
 467                                 hw->phy.ops.read_reg(hw, 0xC00C,
 468                                                      IXGBE_TWINAX_DEV,
 469                                                      &adapt_comp_reg);
 470                         }
 471                 } else {
 472                         if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
 473                                 *link_up = true;
 474                         else
 475                                 *link_up = false;
 476                 }
 477
 478                 if (*link_up == false)
 479                         goto out;
 480         }
 481
 482         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 483         if (link_up_wait_to_complete) {
 484                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 485                         if (links_reg & IXGBE_LINKS_UP) {
 486                                 *link_up = true;
 487                                 break;
 488                         } else {
 489                                 *link_up = false;
 490                         }
 491                         msleep(100);
 492                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 493                 }
 494         } else {
 495                 if (links_reg & IXGBE_LINKS_UP)
 496                         *link_up = true;
 497                 else
 498                         *link_up = false;
 499         }
 500
 501         if (links_reg & IXGBE_LINKS_SPEED)
 502                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 503         else
 504                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 505
 506 out:
 507         return 0;
 508 }
 509
 510
 511 /**
 512  *  ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
 513  *  @hw: pointer to hardware structure
 514  *  @speed: new link speed
 515  *  @autoneg: true if auto-negotiation enabled
 516  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 517  *
 518  *  Set the link speed in the AUTOC register and restarts link.
 519  **/
 520 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
 521                                            ixgbe_link_speed speed, bool autoneg,
 522                                            bool autoneg_wait_to_complete)
 523 {
 524         s32              status            = 0;
 525         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 526         u32              curr_autoc        = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 527         u32              autoc             = curr_autoc;
 528         u32              link_mode         = autoc & IXGBE_AUTOC_LMS_MASK;
 529
 530         /* Check to see if speed passed in is supported. */
 531         ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
 532         speed &= link_capabilities;
 533
 534         if (speed == IXGBE_LINK_SPEED_UNKNOWN)
 535                 status = IXGBE_ERR_LINK_SETUP;
 536
 537         /* Set KX4/KX support according to speed requested */
 538         else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
 539                  link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 540                 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
 541                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 542                         autoc |= IXGBE_AUTOC_KX4_SUPP;
 543                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 544                         autoc |= IXGBE_AUTOC_KX_SUPP;
 545                 if (autoc != curr_autoc)
 546                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
 547         }
 548
 549         if (status == 0) {
 550                 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
 551
 552                 /*
 553                  * Setup and restart the link based on the new values in
 554                  * ixgbe_hw This will write the AUTOC register based on the new
 555                  * stored values
 556                  */
 557                 status = ixgbe_setup_mac_link_82598(hw);
 558         }
 559
 560         return status;
 561 }
 562
 563
 564 /**
 565  *  ixgbe_setup_copper_link_82598 - Setup copper link settings
 566  *  @hw: pointer to hardware structure
 567  *
 568  *  Configures link settings based on values in the ixgbe_hw struct.
 569  *  Restarts the link.  Performs autonegotiation if needed.  Restart
 570  *  phy and wait for autonegotiate to finish.  Then synchronize the
 571  *  MAC and PHY.
 572  **/
 573 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
 574 {
 575         s32 status;
 576
 577         /* Restart autonegotiation on PHY */
 578         status = hw->phy.ops.setup_link(hw);
 579
 580         /* Set up MAC */
 581         ixgbe_setup_mac_link_82598(hw);
 582
 583         return status;
 584 }
 585
 586 /**
 587  *  ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
 588  *  @hw: pointer to hardware structure
 589  *  @speed: new link speed
 590  *  @autoneg: true if autonegotiation enabled
 591  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 592  *
 593  *  Sets the link speed in the AUTOC register in the MAC and restarts link.
 594  **/
 595 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
 596                                                ixgbe_link_speed speed,
 597                                                bool autoneg,
 598                                                bool autoneg_wait_to_complete)
 599 {
 600         s32 status;
 601
 602         /* Setup the PHY according to input speed */
 603         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 604                                               autoneg_wait_to_complete);
 605
 606         /* Set up MAC */
 607         ixgbe_setup_mac_link_82598(hw);
 608
 609         return status;
 610 }
 611
 612 /**
 613  *  ixgbe_reset_hw_82598 - Performs hardware reset
 614  *  @hw: pointer to hardware structure
 615  *
 616  *  Resets the hardware by resetting the transmit and receive units, masks and
 617  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
 618  *  reset.
 619  **/
 620 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
 621 {
 622         s32 status = 0;
 623         u32 ctrl;
 624         u32 gheccr;
 625         u32 i;
 626         u32 autoc;
 627         u8  analog_val;
 628
 629         /* Call adapter stop to disable tx/rx and clear interrupts */
 630         hw->mac.ops.stop_adapter(hw);
 631
 632         /*
 633          * Power up the Atlas Tx lanes if they are currently powered down.
 634          * Atlas Tx lanes are powered down for MAC loopback tests, but
 635          * they are not automatically restored on reset.
 636          */
 637         hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
 638         if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
 639                 /* Enable Tx Atlas so packets can be transmitted again */
 640                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 641                                              &analog_val);
 642                 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
 643                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 644                                               analog_val);
 645
 646                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 647                                              &analog_val);
 648                 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
 649                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 650                                               analog_val);
 651
 652                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 653                                              &analog_val);
 654                 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
 655                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 656                                               analog_val);
 657
 658                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 659                                              &analog_val);
 660                 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
 661                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 662                                               analog_val);
 663         }
 664
 665         /* Reset PHY */
 666         if (hw->phy.reset_disable == false)
 667                 hw->phy.ops.reset(hw);
 668
 669         /*
 670          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 671          * access and verify no pending requests before reset
 672          */
 673         if (ixgbe_disable_pcie_master(hw) != 0) {
 674                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 675                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 676         }
 677
 678         /*
 679          * Issue global reset to the MAC.  This needs to be a SW reset.
 680          * If link reset is used, it might reset the MAC when mng is using it
 681          */
 682         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 683         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
 684         IXGBE_WRITE_FLUSH(hw);
 685
 686         /* Poll for reset bit to self-clear indicating reset is complete */
 687         for (i = 0; i < 10; i++) {
 688                 udelay(1);
 689                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 690                 if (!(ctrl & IXGBE_CTRL_RST))
 691                         break;
 692         }
 693         if (ctrl & IXGBE_CTRL_RST) {
 694                 status = IXGBE_ERR_RESET_FAILED;
 695                 hw_dbg(hw, "Reset polling failed to complete.\n");
 696         }
 697
 698         msleep(50);
 699
 700         gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
 701         gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
 702         IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
 703
 704         /*
 705          * Store the original AUTOC value if it has not been
 706          * stored off yet.  Otherwise restore the stored original
 707          * AUTOC value since the reset operation sets back to deaults.
 708          */
 709         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 710         if (hw->mac.orig_link_settings_stored == false) {
 711                 hw->mac.orig_autoc = autoc;
 712                 hw->mac.orig_link_settings_stored = true;
 713         } else if (autoc != hw->mac.orig_autoc) {
 714                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
 715         }
 716
 717         /* Store the permanent mac address */
 718         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 719
 720         return status;
 721 }
 722
 723 /**
 724  *  ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
 725  *  @hw: pointer to hardware struct
 726  *  @rar: receive address register index to associate with a VMDq index
 727  *  @vmdq: VMDq set index
 728  **/
 729 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 730 {
 731         u32 rar_high;
 732
 733         rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 734         rar_high &= ~IXGBE_RAH_VIND_MASK;
 735         rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
 736         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 737         return 0;
 738 }
 739
 740 /**
 741  *  ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
 742  *  @hw: pointer to hardware struct
 743  *  @rar: receive address register index to associate with a VMDq index
 744  *  @vmdq: VMDq clear index (not used in 82598, but elsewhere)
 745  **/
 746 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 747 {
 748         u32 rar_high;
 749         u32 rar_entries = hw->mac.num_rar_entries;
 750
 751         if (rar < rar_entries) {
 752                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 753                 if (rar_high & IXGBE_RAH_VIND_MASK) {
 754                         rar_high &= ~IXGBE_RAH_VIND_MASK;
 755                         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 756                 }
 757         } else {
 758                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 759         }
 760
 761         return 0;
 762 }
 763
 764 /**
 765  *  ixgbe_set_vfta_82598 - Set VLAN filter table
 766  *  @hw: pointer to hardware structure
 767  *  @vlan: VLAN id to write to VLAN filter
 768  *  @vind: VMDq output index that maps queue to VLAN id in VFTA
 769  *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
 770  *
 771  *  Turn on/off specified VLAN in the VLAN filter table.
 772  **/
 773 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
 774                                 bool vlan_on)
 775 {
 776         u32 regindex;
 777         u32 bitindex;
 778         u32 bits;
 779         u32 vftabyte;
 780
 781         if (vlan > 4095)
 782                 return IXGBE_ERR_PARAM;
 783
 784         /* Determine 32-bit word position in array */
 785         regindex = (vlan >> 5) & 0x7F;   /* upper seven bits */
 786
 787         /* Determine the location of the (VMD) queue index */
 788         vftabyte =  ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
 789         bitindex = (vlan & 0x7) << 2;    /* lower 3 bits indicate nibble */
 790
 791         /* Set the nibble for VMD queue index */
 792         bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
 793         bits &= (~(0x0F << bitindex));
 794         bits |= (vind << bitindex);
 795         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
 796
 797         /* Determine the location of the bit for this VLAN id */
 798         bitindex = vlan & 0x1F;   /* lower five bits */
 799
 800         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
 801         if (vlan_on)
 802                 /* Turn on this VLAN id */
 803                 bits |= (1 << bitindex);
 804         else
 805                 /* Turn off this VLAN id */
 806                 bits &= ~(1 << bitindex);
 807         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
 808
 809         return 0;
 810 }
 811
 812 /**
 813  *  ixgbe_clear_vfta_82598 - Clear VLAN filter table
 814  *  @hw: pointer to hardware structure
 815  *
 816  *  Clears the VLAN filer table, and the VMDq index associated with the filter
 817  **/
 818 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
 819 {
 820         u32 offset;
 821         u32 vlanbyte;
 822
 823         for (offset = 0; offset < hw->mac.vft_size; offset++)
 824                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
 825
 826         for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
 827                 for (offset = 0; offset < hw->mac.vft_size; offset++)
 828                         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
 829                                         0);
 830
 831         return 0;
 832 }
 833
 834 /**
 835  *  ixgbe_blink_led_start_82598 - Blink LED based on index.
 836  *  @hw: pointer to hardware structure
 837  *  @index: led number to blink
 838  **/
 839 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
 840 {
 841         ixgbe_link_speed speed = 0;
 842         bool link_up = 0;
 843         u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 844         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 845
 846         /*
 847          * Link must be up to auto-blink the LEDs on the 82598EB MAC;
 848          * force it if link is down.
 849          */
 850         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 851
 852         if (!link_up) {
 853                 autoc_reg |= IXGBE_AUTOC_FLU;
 854                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 855                 msleep(10);
 856         }
 857
 858         led_reg &= ~IXGBE_LED_MODE_MASK(index);
 859         led_reg |= IXGBE_LED_BLINK(index);
 860         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 861         IXGBE_WRITE_FLUSH(hw);
 862
 863         return 0;
 864 }
 865
 866 /**
 867  *  ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
 868  *  @hw: pointer to hardware structure
 869  *  @index: led number to stop blinking
 870  **/
 871 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
 872 {
 873         u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 874         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 875
 876         autoc_reg &= ~IXGBE_AUTOC_FLU;
 877         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 878         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 879
 880         led_reg &= ~IXGBE_LED_MODE_MASK(index);
 881         led_reg &= ~IXGBE_LED_BLINK(index);
 882         led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 883         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 884         IXGBE_WRITE_FLUSH(hw);
 885
 886         return 0;
 887 }
 888
 889 /**
 890  *  ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
 891  *  @hw: pointer to hardware structure
 892  *  @reg: analog register to read
 893  *  @val: read value
 894  *
 895  *  Performs read operation to Atlas analog register specified.
 896  **/
 897 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
 898 {
 899         u32  atlas_ctl;
 900
 901         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
 902                         IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
 903         IXGBE_WRITE_FLUSH(hw);
 904         udelay(10);
 905         atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 906         *val = (u8)atlas_ctl;
 907
 908         return 0;
 909 }
 910
 911 /**
 912  *  ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
 913  *  @hw: pointer to hardware structure
 914  *  @reg: atlas register to write
 915  *  @val: value to write
 916  *
 917  *  Performs write operation to Atlas analog register specified.
 918  **/
 919 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
 920 {
 921         u32  atlas_ctl;
 922
 923         atlas_ctl = (reg << 8) | val;
 924         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
 925         IXGBE_WRITE_FLUSH(hw);
 926         udelay(10);
 927
 928         return 0;
 929 }
 930
 931 /**
 932  *  ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
 933  *  over I2C interface through an intermediate phy.
 934  *  @hw: pointer to hardware structure
 935  *  @byte_offset: EEPROM byte offset to read
 936  *  @eeprom_data: value read
 937  *
 938  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
 939  **/
 940 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
 941                                        u8 *eeprom_data)
 942 {
 943         s32 status = 0;
 944         u16 sfp_addr = 0;
 945         u16 sfp_data = 0;
 946         u16 sfp_stat = 0;
 947         u32 i;
 948
 949         if (hw->phy.type == ixgbe_phy_nl) {
 950                 /*
 951                  * phy SDA/SCL registers are at addresses 0xC30A to
 952                  * 0xC30D.  These registers are used to talk to the SFP+
 953                  * module's EEPROM through the SDA/SCL (I2C) interface.
 954                  */
 955                 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
 956                 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
 957                 hw->phy.ops.write_reg(hw,
 958                                       IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
 959                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 960                                       sfp_addr);
 961
 962                 /* Poll status */
 963                 for (i = 0; i < 100; i++) {
 964                         hw->phy.ops.read_reg(hw,
 965                                              IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
 966                                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 967                                              &sfp_stat);
 968                         sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
 969                         if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
 970                                 break;
 971                         msleep(10);
 972                 }
 973
 974                 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
 975                         hw_dbg(hw, "EEPROM read did not pass.\n");
 976                         status = IXGBE_ERR_SFP_NOT_PRESENT;
 977                         goto out;
 978                 }
 979
 980                 /* Read data */
 981                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
 982                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
 983
 984                 *eeprom_data = (u8)(sfp_data >> 8);
 985         } else {
 986                 status = IXGBE_ERR_PHY;
 987                 goto out;
 988         }
 989
 990 out:
 991         return status;
 992 }
 993
 994 /**
 995  *  ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
 996  *  @hw: pointer to hardware structure
 997  *
 998  *  Determines physical layer capabilities of the current configuration.
 999  **/
1000 static s32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1001 {
1002         s32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1003
1004         switch (hw->device_id) {
1005         case IXGBE_DEV_ID_82598:
1006                 /* Default device ID is mezzanine card KX/KX4 */
1007                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1008                                   IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1009                 break;
1010         case IXGBE_DEV_ID_82598_BX:
1011                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1012         case IXGBE_DEV_ID_82598EB_CX4:
1013         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1014                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1015                 break;
1016         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1017                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1018                 break;
1019         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1020         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1021         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1022                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1023                 break;
1024         case IXGBE_DEV_ID_82598EB_XF_LR:
1025                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1026                 break;
1027         case IXGBE_DEV_ID_82598AT:
1028                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1029                                   IXGBE_PHYSICAL_LAYER_1000BASE_T);
1030                 break;
1031         case IXGBE_DEV_ID_82598EB_SFP_LOM:
1032                 hw->phy.ops.identify_sfp(hw);
1033
1034                 switch (hw->phy.sfp_type) {
1035                 case ixgbe_sfp_type_da_cu:
1036                         physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1037                         break;
1038                 case ixgbe_sfp_type_sr:
1039                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1040                         break;
1041                 case ixgbe_sfp_type_lr:
1042                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1043                         break;
1044                 default:
1045                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1046                         break;
1047                 }
1048                 break;
1049
1050         default:
1051                 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1052                 break;
1053         }
1054
1055         return physical_layer;
1056 }
1057
1058 static struct ixgbe_mac_operations mac_ops_82598 = {
1059         .init_hw                = &ixgbe_init_hw_generic,
1060         .reset_hw               = &ixgbe_reset_hw_82598,
1061         .start_hw               = &ixgbe_start_hw_generic,
1062         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1063         .get_media_type         = &ixgbe_get_media_type_82598,
1064         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1065         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1066         .stop_adapter           = &ixgbe_stop_adapter_generic,
1067         .read_analog_reg8       = &ixgbe_read_analog_reg8_82598,
1068         .write_analog_reg8      = &ixgbe_write_analog_reg8_82598,
1069         .setup_link             = &ixgbe_setup_mac_link_82598,
1070         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82598,
1071         .check_link             = &ixgbe_check_mac_link_82598,
1072         .get_link_capabilities  = &ixgbe_get_link_capabilities_82598,
1073         .led_on                 = &ixgbe_led_on_generic,
1074         .led_off                = &ixgbe_led_off_generic,
1075         .blink_led_start        = &ixgbe_blink_led_start_82598,
1076         .blink_led_stop         = &ixgbe_blink_led_stop_82598,
1077         .set_rar                = &ixgbe_set_rar_generic,
1078         .clear_rar              = &ixgbe_clear_rar_generic,
1079         .set_vmdq               = &ixgbe_set_vmdq_82598,
1080         .clear_vmdq             = &ixgbe_clear_vmdq_82598,
1081         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1082         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1083         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1084         .enable_mc              = &ixgbe_enable_mc_generic,
1085         .disable_mc             = &ixgbe_disable_mc_generic,
1086         .clear_vfta             = &ixgbe_clear_vfta_82598,
1087         .set_vfta               = &ixgbe_set_vfta_82598,
1088         .setup_fc               = &ixgbe_setup_fc_82598,
1089 };
1090
1091 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1092         .init_params            = &ixgbe_init_eeprom_params_generic,
1093         .read                   = &ixgbe_read_eeprom_generic,
1094         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1095         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1096 };
1097
1098 static struct ixgbe_phy_operations phy_ops_82598 = {
1099         .identify               = &ixgbe_identify_phy_generic,
1100         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1101         .reset                  = &ixgbe_reset_phy_generic,
1102         .read_reg               = &ixgbe_read_phy_reg_generic,
1103         .write_reg              = &ixgbe_write_phy_reg_generic,
1104         .setup_link             = &ixgbe_setup_phy_link_generic,
1105         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1106         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_82598,
1107 };
1108
1109 struct ixgbe_info ixgbe_82598_info = {
1110         .mac                    = ixgbe_mac_82598EB,
1111         .get_invariants         = &ixgbe_get_invariants_82598,
1112         .mac_ops                = &mac_ops_82598,
1113         .eeprom_ops             = &eeprom_ops_82598,
1114         .phy_ops                = &phy_ops_82598,
1115 };
1116