drivers/net/ixgbe/ixgbe_82598.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/pci.h>
  29 #include <linux/delay.h>
  30 #include <linux/sched.h>
  31
  32 #include "ixgbe.h"
  33 #include "ixgbe_phy.h"
  34
  35 #define IXGBE_82598_MAX_TX_QUEUES 32
  36 #define IXGBE_82598_MAX_RX_QUEUES 64
  37 #define IXGBE_82598_RAR_ENTRIES   16
  38 #define IXGBE_82598_MC_TBL_SIZE  128
  39 #define IXGBE_82598_VFT_TBL_SIZE 128
  40
  41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
  42                                              ixgbe_link_speed *speed,
  43                                              bool *autoneg);
  44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
  45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
  46                                                ixgbe_link_speed speed,
  47                                                bool autoneg,
  48                                                bool autoneg_wait_to_complete);
  49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
  50                                        u8 *eeprom_data);
  51
  52 /**
  53  *  ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
  54  *  @hw: pointer to hardware structure
  55  *
  56  *  Read PCIe configuration space, and get the MSI-X vector count from
  57  *  the capabilities table.
  58  **/
  59 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_adapter *adapter = hw->back;
  62         u16 msix_count;
  63         pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
  64                              &msix_count);
  65         msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
  66
  67         /* MSI-X count is zero-based in HW, so increment to give proper value */
  68         msix_count++;
  69
  70         return msix_count;
  71 }
  72
  73 /**
  74  */
  75 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
  76 {
  77         struct ixgbe_mac_info *mac = &hw->mac;
  78         struct ixgbe_phy_info *phy = &hw->phy;
  79         s32 ret_val = 0;
  80         u16 list_offset, data_offset;
  81
  82         /* Set the bus information prior to PHY identification */
  83         mac->ops.get_bus_info(hw);
  84
  85         /* Call PHY identify routine to get the phy type */
  86         ixgbe_identify_phy_generic(hw);
  87
  88         /* PHY Init */
  89         switch (phy->type) {
  90         case ixgbe_phy_tn:
  91                 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
  92                 phy->ops.get_firmware_version =
  93                              &ixgbe_get_phy_firmware_version_tnx;
  94                 break;
  95         case ixgbe_phy_nl:
  96                 phy->ops.reset = &ixgbe_reset_phy_nl;
  97
  98                 /* Call SFP+ identify routine to get the SFP+ module type */
  99                 ret_val = phy->ops.identify_sfp(hw);
 100                 if (ret_val != 0)
 101                         goto out;
 102                 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
 103                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 104                         goto out;
 105                 }
 106
 107                 /* Check to see if SFP+ module is supported */
 108                 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
 109                                                               &list_offset,
 110                                                               &data_offset);
 111                 if (ret_val != 0) {
 112                         ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
 113                         goto out;
 114                 }
 115                 break;
 116         default:
 117                 break;
 118         }
 119
 120         if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 121                 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
 122                 mac->ops.setup_link_speed =
 123                                      &ixgbe_setup_copper_link_speed_82598;
 124                 mac->ops.get_link_capabilities =
 125                                      &ixgbe_get_copper_link_capabilities_82598;
 126         }
 127
 128         mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
 129         mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
 130         mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
 131         mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
 132         mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
 133         mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
 134
 135 out:
 136         return ret_val;
 137 }
 138
 139 /**
 140  *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
 141  *  @hw: pointer to hardware structure
 142  *  @speed: pointer to link speed
 143  *  @autoneg: boolean auto-negotiation value
 144  *
 145  *  Determines the link capabilities by reading the AUTOC register.
 146  **/
 147 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
 148                                              ixgbe_link_speed *speed,
 149                                              bool *autoneg)
 150 {
 151         s32 status = 0;
 152
 153         /*
 154          * Determine link capabilities based on the stored value of AUTOC,
 155          * which represents EEPROM defaults.
 156          */
 157         switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
 158         case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 159                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 160                 *autoneg = false;
 161                 break;
 162
 163         case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 164                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 165                 *autoneg = false;
 166                 break;
 167
 168         case IXGBE_AUTOC_LMS_1G_AN:
 169                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 170                 *autoneg = true;
 171                 break;
 172
 173         case IXGBE_AUTOC_LMS_KX4_AN:
 174         case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
 175                 *speed = IXGBE_LINK_SPEED_UNKNOWN;
 176                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 177                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 178                 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
 179                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 180                 *autoneg = true;
 181                 break;
 182
 183         default:
 184                 status = IXGBE_ERR_LINK_SETUP;
 185                 break;
 186         }
 187
 188         return status;
 189 }
 190
 191 /**
 192  *  ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
 193  *  @hw: pointer to hardware structure
 194  *  @speed: pointer to link speed
 195  *  @autoneg: boolean auto-negotiation value
 196  *
 197  *  Determines the link capabilities by reading the AUTOC register.
 198  **/
 199 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
 200                                                     ixgbe_link_speed *speed,
 201                                                     bool *autoneg)
 202 {
 203         s32 status = IXGBE_ERR_LINK_SETUP;
 204         u16 speed_ability;
 205
 206         *speed = 0;
 207         *autoneg = true;
 208
 209         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 210                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 211                                       &speed_ability);
 212
 213         if (status == 0) {
 214                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 215                     *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 216                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 217                     *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 218         }
 219
 220         return status;
 221 }
 222
 223 /**
 224  *  ixgbe_get_media_type_82598 - Determines media type
 225  *  @hw: pointer to hardware structure
 226  *
 227  *  Returns the media type (fiber, copper, backplane)
 228  **/
 229 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
 230 {
 231         enum ixgbe_media_type media_type;
 232
 233         /* Media type for I82598 is based on device ID */
 234         switch (hw->device_id) {
 235         case IXGBE_DEV_ID_82598:
 236         case IXGBE_DEV_ID_82598_BX:
 237                 media_type = ixgbe_media_type_backplane;
 238                 break;
 239         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
 240         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
 241         case IXGBE_DEV_ID_82598EB_CX4:
 242         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
 243         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
 244         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
 245         case IXGBE_DEV_ID_82598EB_XF_LR:
 246         case IXGBE_DEV_ID_82598EB_SFP_LOM:
 247                 media_type = ixgbe_media_type_fiber;
 248                 break;
 249         case IXGBE_DEV_ID_82598AT:
 250                 media_type = ixgbe_media_type_copper;
 251                 break;
 252         default:
 253                 media_type = ixgbe_media_type_unknown;
 254                 break;
 255         }
 256
 257         return media_type;
 258 }
 259
 260 /**
 261  *  ixgbe_fc_enable_82598 - Enable flow control
 262  *  @hw: pointer to hardware structure
 263  *  @packetbuf_num: packet buffer number (0-7)
 264  *
 265  *  Enable flow control according to the current settings.
 266  **/
 267 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 268 {
 269         s32 ret_val = 0;
 270         u32 fctrl_reg;
 271         u32 rmcs_reg;
 272         u32 reg;
 273
 274         fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 275         fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
 276
 277         rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
 278         rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
 279
 280         /*
 281          * The possible values of fc.current_mode are:
 282          * 0: Flow control is completely disabled
 283          * 1: Rx flow control is enabled (we can receive pause frames,
 284          *    but not send pause frames).
 285          * 2:  Tx flow control is enabled (we can send pause frames but
 286          *     we do not support receiving pause frames).
 287          * 3: Both Rx and Tx flow control (symmetric) are enabled.
 288          * other: Invalid.
 289          */
 290         switch (hw->fc.current_mode) {
 291         case ixgbe_fc_none:
 292                 /* Flow control completely disabled by software override. */
 293                 break;
 294         case ixgbe_fc_rx_pause:
 295                 /*
 296                  * Rx Flow control is enabled and Tx Flow control is
 297                  * disabled by software override. Since there really
 298                  * isn't a way to advertise that we are capable of RX
 299                  * Pause ONLY, we will advertise that we support both
 300                  * symmetric and asymmetric Rx PAUSE.  Later, we will
 301                  * disable the adapter's ability to send PAUSE frames.
 302                  */
 303                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 304                 break;
 305         case ixgbe_fc_tx_pause:
 306                 /*
 307                  * Tx Flow control is enabled, and Rx Flow control is
 308                  * disabled by software override.
 309                  */
 310                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 311                 break;
 312         case ixgbe_fc_full:
 313                 /* Flow control (both Rx and Tx) is enabled by SW override. */
 314                 fctrl_reg |= IXGBE_FCTRL_RFCE;
 315                 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
 316                 break;
 317         default:
 318                 hw_dbg(hw, "Flow control param set incorrectly\n");
 319                 ret_val = -IXGBE_ERR_CONFIG;
 320                 goto out;
 321                 break;
 322         }
 323
 324         /* Enable 802.3x based flow control settings. */
 325         fctrl_reg |= IXGBE_FCTRL_DPF;
 326         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
 327         IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
 328
 329         /* Set up and enable Rx high/low water mark thresholds, enable XON. */
 330         if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
 331                 if (hw->fc.send_xon) {
 332                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 333                                         (hw->fc.low_water | IXGBE_FCRTL_XONE));
 334                 } else {
 335                         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
 336                                         hw->fc.low_water);
 337                 }
 338
 339                 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
 340                                 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
 341         }
 342
 343         /* Configure pause time (2 TCs per register) */
 344         reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
 345         if ((packetbuf_num & 1) == 0)
 346                 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
 347         else
 348                 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
 349         IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
 350
 351         IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
 352
 353 out:
 354         return ret_val;
 355 }
 356
 357 /**
 358  *  ixgbe_setup_fc_82598 - Configure flow control settings
 359  *  @hw: pointer to hardware structure
 360  *  @packetbuf_num: packet buffer number (0-7)
 361  *
 362  *  Configures the flow control settings based on SW configuration.  This
 363  *  function is used for 802.3x flow control configuration only.
 364  **/
 365 static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
 366 {
 367         s32 ret_val = 0;
 368         ixgbe_link_speed speed;
 369         bool link_up;
 370
 371         /* Validate the packetbuf configuration */
 372         if (packetbuf_num < 0 || packetbuf_num > 7) {
 373                 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
 374                           " 0-7\n", packetbuf_num);
 375                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 376                 goto out;
 377         }
 378
 379         /*
 380          * Validate the water mark configuration.  Zero water marks are invalid
 381          * because it causes the controller to just blast out fc packets.
 382          */
 383         if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
 384                 hw_dbg(hw, "Invalid water mark configuration\n");
 385                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 386                 goto out;
 387         }
 388
 389         /*
 390          * Validate the requested mode.  Strict IEEE mode does not allow
 391          * ixgbe_fc_rx_pause because it will cause testing anomalies.
 392          */
 393         if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 394                 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 395                 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 396                 goto out;
 397         }
 398
 399         /*
 400          * 10gig parts do not have a word in the EEPROM to determine the
 401          * default flow control setting, so we explicitly set it to full.
 402          */
 403         if (hw->fc.requested_mode == ixgbe_fc_default)
 404                 hw->fc.requested_mode = ixgbe_fc_full;
 405
 406         /*
 407          * Save off the requested flow control mode for use later.  Depending
 408          * on the link partner's capabilities, we may or may not use this mode.
 409          */
 410
 411         hw->fc.current_mode = hw->fc.requested_mode;
 412
 413         /* Decide whether to use autoneg or not. */
 414         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 415         if (!hw->fc.disable_fc_autoneg && hw->phy.multispeed_fiber &&
 416             (speed == IXGBE_LINK_SPEED_1GB_FULL))
 417                 ret_val = ixgbe_fc_autoneg(hw);
 418
 419         if (ret_val)
 420                 goto out;
 421
 422         ret_val = ixgbe_fc_enable_82598(hw, packetbuf_num);
 423
 424 out:
 425         return ret_val;
 426 }
 427
 428 /**
 429  *  ixgbe_setup_mac_link_82598 - Configures MAC link settings
 430  *  @hw: pointer to hardware structure
 431  *
 432  *  Configures link settings based on values in the ixgbe_hw struct.
 433  *  Restarts the link.  Performs autonegotiation if needed.
 434  **/
 435 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
 436 {
 437         u32 autoc_reg;
 438         u32 links_reg;
 439         u32 i;
 440         s32 status = 0;
 441
 442         /* Restart link */
 443         autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 444         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 445         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 446
 447         /* Only poll for autoneg to complete if specified to do so */
 448         if (hw->phy.autoneg_wait_to_complete) {
 449                 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 450                      IXGBE_AUTOC_LMS_KX4_AN ||
 451                     (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 452                      IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 453                         links_reg = 0; /* Just in case Autoneg time = 0 */
 454                         for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 455                                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 456                                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 457                                         break;
 458                                 msleep(100);
 459                         }
 460                         if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 461                                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 462                                 hw_dbg(hw, "Autonegotiation did not complete.\n");
 463                         }
 464                 }
 465         }
 466
 467         /*
 468          * We want to save off the original Flow Control configuration just in
 469          * case we get disconnected and then reconnected into a different hub
 470          * or switch with different Flow Control capabilities.
 471          */
 472         ixgbe_setup_fc_82598(hw, 0);
 473
 474         /* Add delay to filter out noises during initial link setup */
 475         msleep(50);
 476
 477         return status;
 478 }
 479
 480 /**
 481  *  ixgbe_check_mac_link_82598 - Get link/speed status
 482  *  @hw: pointer to hardware structure
 483  *  @speed: pointer to link speed
 484  *  @link_up: true is link is up, false otherwise
 485  *  @link_up_wait_to_complete: bool used to wait for link up or not
 486  *
 487  *  Reads the links register to determine if link is up and the current speed
 488  **/
 489 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
 490                                       ixgbe_link_speed *speed, bool *link_up,
 491                                       bool link_up_wait_to_complete)
 492 {
 493         u32 links_reg;
 494         u32 i;
 495         u16 link_reg, adapt_comp_reg;
 496
 497         /*
 498          * SERDES PHY requires us to read link status from register 0xC79F.
 499          * Bit 0 set indicates link is up/ready; clear indicates link down.
 500          * 0xC00C is read to check that the XAUI lanes are active.  Bit 0
 501          * clear indicates active; set indicates inactive.
 502          */
 503         if (hw->phy.type == ixgbe_phy_nl) {
 504                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 505                 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
 506                 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
 507                                      &adapt_comp_reg);
 508                 if (link_up_wait_to_complete) {
 509                         for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 510                                 if ((link_reg & 1) &&
 511                                     ((adapt_comp_reg & 1) == 0)) {
 512                                         *link_up = true;
 513                                         break;
 514                                 } else {
 515                                         *link_up = false;
 516                                 }
 517                                 msleep(100);
 518                                 hw->phy.ops.read_reg(hw, 0xC79F,
 519                                                      IXGBE_TWINAX_DEV,
 520                                                      &link_reg);
 521                                 hw->phy.ops.read_reg(hw, 0xC00C,
 522                                                      IXGBE_TWINAX_DEV,
 523                                                      &adapt_comp_reg);
 524                         }
 525                 } else {
 526                         if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
 527                                 *link_up = true;
 528                         else
 529                                 *link_up = false;
 530                 }
 531
 532                 if (*link_up == false)
 533                         goto out;
 534         }
 535
 536         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 537         if (link_up_wait_to_complete) {
 538                 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 539                         if (links_reg & IXGBE_LINKS_UP) {
 540                                 *link_up = true;
 541                                 break;
 542                         } else {
 543                                 *link_up = false;
 544                         }
 545                         msleep(100);
 546                         links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 547                 }
 548         } else {
 549                 if (links_reg & IXGBE_LINKS_UP)
 550                         *link_up = true;
 551                 else
 552                         *link_up = false;
 553         }
 554
 555         if (links_reg & IXGBE_LINKS_SPEED)
 556                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
 557         else
 558                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 559
 560 out:
 561         return 0;
 562 }
 563
 564
 565 /**
 566  *  ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
 567  *  @hw: pointer to hardware structure
 568  *  @speed: new link speed
 569  *  @autoneg: true if auto-negotiation enabled
 570  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 571  *
 572  *  Set the link speed in the AUTOC register and restarts link.
 573  **/
 574 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
 575                                            ixgbe_link_speed speed, bool autoneg,
 576                                            bool autoneg_wait_to_complete)
 577 {
 578         s32              status            = 0;
 579         ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 580         u32              curr_autoc        = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 581         u32              autoc             = curr_autoc;
 582         u32              link_mode         = autoc & IXGBE_AUTOC_LMS_MASK;
 583
 584         /* Check to see if speed passed in is supported. */
 585         ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
 586         speed &= link_capabilities;
 587
 588         if (speed == IXGBE_LINK_SPEED_UNKNOWN)
 589                 status = IXGBE_ERR_LINK_SETUP;
 590
 591         /* Set KX4/KX support according to speed requested */
 592         else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
 593                  link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
 594                 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
 595                 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 596                         autoc |= IXGBE_AUTOC_KX4_SUPP;
 597                 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 598                         autoc |= IXGBE_AUTOC_KX_SUPP;
 599                 if (autoc != curr_autoc)
 600                         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
 601         }
 602
 603         if (status == 0) {
 604                 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
 605
 606                 /*
 607                  * Setup and restart the link based on the new values in
 608                  * ixgbe_hw This will write the AUTOC register based on the new
 609                  * stored values
 610                  */
 611                 status = ixgbe_setup_mac_link_82598(hw);
 612         }
 613
 614         return status;
 615 }
 616
 617
 618 /**
 619  *  ixgbe_setup_copper_link_82598 - Setup copper link settings
 620  *  @hw: pointer to hardware structure
 621  *
 622  *  Configures link settings based on values in the ixgbe_hw struct.
 623  *  Restarts the link.  Performs autonegotiation if needed.  Restart
 624  *  phy and wait for autonegotiate to finish.  Then synchronize the
 625  *  MAC and PHY.
 626  **/
 627 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
 628 {
 629         s32 status;
 630
 631         /* Restart autonegotiation on PHY */
 632         status = hw->phy.ops.setup_link(hw);
 633
 634         /* Set up MAC */
 635         ixgbe_setup_mac_link_82598(hw);
 636
 637         return status;
 638 }
 639
 640 /**
 641  *  ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
 642  *  @hw: pointer to hardware structure
 643  *  @speed: new link speed
 644  *  @autoneg: true if autonegotiation enabled
 645  *  @autoneg_wait_to_complete: true if waiting is needed to complete
 646  *
 647  *  Sets the link speed in the AUTOC register in the MAC and restarts link.
 648  **/
 649 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
 650                                                ixgbe_link_speed speed,
 651                                                bool autoneg,
 652                                                bool autoneg_wait_to_complete)
 653 {
 654         s32 status;
 655
 656         /* Setup the PHY according to input speed */
 657         status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
 658                                               autoneg_wait_to_complete);
 659
 660         /* Set up MAC */
 661         ixgbe_setup_mac_link_82598(hw);
 662
 663         return status;
 664 }
 665
 666 /**
 667  *  ixgbe_reset_hw_82598 - Performs hardware reset
 668  *  @hw: pointer to hardware structure
 669  *
 670  *  Resets the hardware by resetting the transmit and receive units, masks and
 671  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
 672  *  reset.
 673  **/
 674 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
 675 {
 676         s32 status = 0;
 677         u32 ctrl;
 678         u32 gheccr;
 679         u32 i;
 680         u32 autoc;
 681         u8  analog_val;
 682
 683         /* Call adapter stop to disable tx/rx and clear interrupts */
 684         hw->mac.ops.stop_adapter(hw);
 685
 686         /*
 687          * Power up the Atlas Tx lanes if they are currently powered down.
 688          * Atlas Tx lanes are powered down for MAC loopback tests, but
 689          * they are not automatically restored on reset.
 690          */
 691         hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
 692         if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
 693                 /* Enable Tx Atlas so packets can be transmitted again */
 694                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 695                                              &analog_val);
 696                 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
 697                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
 698                                               analog_val);
 699
 700                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 701                                              &analog_val);
 702                 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
 703                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
 704                                               analog_val);
 705
 706                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 707                                              &analog_val);
 708                 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
 709                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
 710                                               analog_val);
 711
 712                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 713                                              &analog_val);
 714                 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
 715                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
 716                                               analog_val);
 717         }
 718
 719         /* Reset PHY */
 720         if (hw->phy.reset_disable == false)
 721                 hw->phy.ops.reset(hw);
 722
 723         /*
 724          * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 725          * access and verify no pending requests before reset
 726          */
 727         if (ixgbe_disable_pcie_master(hw) != 0) {
 728                 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 729                 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
 730         }
 731
 732         /*
 733          * Issue global reset to the MAC.  This needs to be a SW reset.
 734          * If link reset is used, it might reset the MAC when mng is using it
 735          */
 736         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 737         IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
 738         IXGBE_WRITE_FLUSH(hw);
 739
 740         /* Poll for reset bit to self-clear indicating reset is complete */
 741         for (i = 0; i < 10; i++) {
 742                 udelay(1);
 743                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 744                 if (!(ctrl & IXGBE_CTRL_RST))
 745                         break;
 746         }
 747         if (ctrl & IXGBE_CTRL_RST) {
 748                 status = IXGBE_ERR_RESET_FAILED;
 749                 hw_dbg(hw, "Reset polling failed to complete.\n");
 750         }
 751
 752         msleep(50);
 753
 754         gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
 755         gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
 756         IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
 757
 758         /*
 759          * Store the original AUTOC value if it has not been
 760          * stored off yet.  Otherwise restore the stored original
 761          * AUTOC value since the reset operation sets back to deaults.
 762          */
 763         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 764         if (hw->mac.orig_link_settings_stored == false) {
 765                 hw->mac.orig_autoc = autoc;
 766                 hw->mac.orig_link_settings_stored = true;
 767         } else if (autoc != hw->mac.orig_autoc) {
 768                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
 769         }
 770
 771         /* Store the permanent mac address */
 772         hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 773
 774         return status;
 775 }
 776
 777 /**
 778  *  ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
 779  *  @hw: pointer to hardware struct
 780  *  @rar: receive address register index to associate with a VMDq index
 781  *  @vmdq: VMDq set index
 782  **/
 783 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 784 {
 785         u32 rar_high;
 786
 787         rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 788         rar_high &= ~IXGBE_RAH_VIND_MASK;
 789         rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
 790         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 791         return 0;
 792 }
 793
 794 /**
 795  *  ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
 796  *  @hw: pointer to hardware struct
 797  *  @rar: receive address register index to associate with a VMDq index
 798  *  @vmdq: VMDq clear index (not used in 82598, but elsewhere)
 799  **/
 800 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 801 {
 802         u32 rar_high;
 803         u32 rar_entries = hw->mac.num_rar_entries;
 804
 805         if (rar < rar_entries) {
 806                 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
 807                 if (rar_high & IXGBE_RAH_VIND_MASK) {
 808                         rar_high &= ~IXGBE_RAH_VIND_MASK;
 809                         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
 810                 }
 811         } else {
 812                 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 813         }
 814
 815         return 0;
 816 }
 817
 818 /**
 819  *  ixgbe_set_vfta_82598 - Set VLAN filter table
 820  *  @hw: pointer to hardware structure
 821  *  @vlan: VLAN id to write to VLAN filter
 822  *  @vind: VMDq output index that maps queue to VLAN id in VFTA
 823  *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
 824  *
 825  *  Turn on/off specified VLAN in the VLAN filter table.
 826  **/
 827 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
 828                                 bool vlan_on)
 829 {
 830         u32 regindex;
 831         u32 bitindex;
 832         u32 bits;
 833         u32 vftabyte;
 834
 835         if (vlan > 4095)
 836                 return IXGBE_ERR_PARAM;
 837
 838         /* Determine 32-bit word position in array */
 839         regindex = (vlan >> 5) & 0x7F;   /* upper seven bits */
 840
 841         /* Determine the location of the (VMD) queue index */
 842         vftabyte =  ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
 843         bitindex = (vlan & 0x7) << 2;    /* lower 3 bits indicate nibble */
 844
 845         /* Set the nibble for VMD queue index */
 846         bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
 847         bits &= (~(0x0F << bitindex));
 848         bits |= (vind << bitindex);
 849         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
 850
 851         /* Determine the location of the bit for this VLAN id */
 852         bitindex = vlan & 0x1F;   /* lower five bits */
 853
 854         bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
 855         if (vlan_on)
 856                 /* Turn on this VLAN id */
 857                 bits |= (1 << bitindex);
 858         else
 859                 /* Turn off this VLAN id */
 860                 bits &= ~(1 << bitindex);
 861         IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
 862
 863         return 0;
 864 }
 865
 866 /**
 867  *  ixgbe_clear_vfta_82598 - Clear VLAN filter table
 868  *  @hw: pointer to hardware structure
 869  *
 870  *  Clears the VLAN filer table, and the VMDq index associated with the filter
 871  **/
 872 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
 873 {
 874         u32 offset;
 875         u32 vlanbyte;
 876
 877         for (offset = 0; offset < hw->mac.vft_size; offset++)
 878                 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
 879
 880         for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
 881                 for (offset = 0; offset < hw->mac.vft_size; offset++)
 882                         IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
 883                                         0);
 884
 885         return 0;
 886 }
 887
 888 /**
 889  *  ixgbe_blink_led_start_82598 - Blink LED based on index.
 890  *  @hw: pointer to hardware structure
 891  *  @index: led number to blink
 892  **/
 893 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
 894 {
 895         ixgbe_link_speed speed = 0;
 896         bool link_up = 0;
 897         u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 898         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 899
 900         /*
 901          * Link must be up to auto-blink the LEDs on the 82598EB MAC;
 902          * force it if link is down.
 903          */
 904         hw->mac.ops.check_link(hw, &speed, &link_up, false);
 905
 906         if (!link_up) {
 907                 autoc_reg |= IXGBE_AUTOC_FLU;
 908                 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 909                 msleep(10);
 910         }
 911
 912         led_reg &= ~IXGBE_LED_MODE_MASK(index);
 913         led_reg |= IXGBE_LED_BLINK(index);
 914         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 915         IXGBE_WRITE_FLUSH(hw);
 916
 917         return 0;
 918 }
 919
 920 /**
 921  *  ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
 922  *  @hw: pointer to hardware structure
 923  *  @index: led number to stop blinking
 924  **/
 925 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
 926 {
 927         u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 928         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 929
 930         autoc_reg &= ~IXGBE_AUTOC_FLU;
 931         autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 932         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 933
 934         led_reg &= ~IXGBE_LED_MODE_MASK(index);
 935         led_reg &= ~IXGBE_LED_BLINK(index);
 936         led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 937         IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 938         IXGBE_WRITE_FLUSH(hw);
 939
 940         return 0;
 941 }
 942
 943 /**
 944  *  ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
 945  *  @hw: pointer to hardware structure
 946  *  @reg: analog register to read
 947  *  @val: read value
 948  *
 949  *  Performs read operation to Atlas analog register specified.
 950  **/
 951 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
 952 {
 953         u32  atlas_ctl;
 954
 955         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
 956                         IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
 957         IXGBE_WRITE_FLUSH(hw);
 958         udelay(10);
 959         atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 960         *val = (u8)atlas_ctl;
 961
 962         return 0;
 963 }
 964
 965 /**
 966  *  ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
 967  *  @hw: pointer to hardware structure
 968  *  @reg: atlas register to write
 969  *  @val: value to write
 970  *
 971  *  Performs write operation to Atlas analog register specified.
 972  **/
 973 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
 974 {
 975         u32  atlas_ctl;
 976
 977         atlas_ctl = (reg << 8) | val;
 978         IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
 979         IXGBE_WRITE_FLUSH(hw);
 980         udelay(10);
 981
 982         return 0;
 983 }
 984
 985 /**
 986  *  ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
 987  *  over I2C interface through an intermediate phy.
 988  *  @hw: pointer to hardware structure
 989  *  @byte_offset: EEPROM byte offset to read
 990  *  @eeprom_data: value read
 991  *
 992  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
 993  **/
 994 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
 995                                        u8 *eeprom_data)
 996 {
 997         s32 status = 0;
 998         u16 sfp_addr = 0;
 999         u16 sfp_data = 0;
1000         u16 sfp_stat = 0;
1001         u32 i;
1002
1003         if (hw->phy.type == ixgbe_phy_nl) {
1004                 /*
1005                  * phy SDA/SCL registers are at addresses 0xC30A to
1006                  * 0xC30D.  These registers are used to talk to the SFP+
1007                  * module's EEPROM through the SDA/SCL (I2C) interface.
1008                  */
1009                 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1010                 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1011                 hw->phy.ops.write_reg(hw,
1012                                       IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1013                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1014                                       sfp_addr);
1015
1016                 /* Poll status */
1017                 for (i = 0; i < 100; i++) {
1018                         hw->phy.ops.read_reg(hw,
1019                                              IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1020                                              IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1021                                              &sfp_stat);
1022                         sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1023                         if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1024                                 break;
1025                         msleep(10);
1026                 }
1027
1028                 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1029                         hw_dbg(hw, "EEPROM read did not pass.\n");
1030                         status = IXGBE_ERR_SFP_NOT_PRESENT;
1031                         goto out;
1032                 }
1033
1034                 /* Read data */
1035                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1036                                      IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1037
1038                 *eeprom_data = (u8)(sfp_data >> 8);
1039         } else {
1040                 status = IXGBE_ERR_PHY;
1041                 goto out;
1042         }
1043
1044 out:
1045         return status;
1046 }
1047
1048 /**
1049  *  ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1050  *  @hw: pointer to hardware structure
1051  *
1052  *  Determines physical layer capabilities of the current configuration.
1053  **/
1054 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1055 {
1056         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1057
1058         switch (hw->device_id) {
1059         case IXGBE_DEV_ID_82598:
1060                 /* Default device ID is mezzanine card KX/KX4 */
1061                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1062                                   IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1063                 break;
1064         case IXGBE_DEV_ID_82598_BX:
1065                 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1066         case IXGBE_DEV_ID_82598EB_CX4:
1067         case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1068                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1069                 break;
1070         case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1071                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1072                 break;
1073         case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1074         case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1075         case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1076                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1077                 break;
1078         case IXGBE_DEV_ID_82598EB_XF_LR:
1079                 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1080                 break;
1081         case IXGBE_DEV_ID_82598AT:
1082                 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1083                                   IXGBE_PHYSICAL_LAYER_1000BASE_T);
1084                 break;
1085         case IXGBE_DEV_ID_82598EB_SFP_LOM:
1086                 hw->phy.ops.identify_sfp(hw);
1087
1088                 switch (hw->phy.sfp_type) {
1089                 case ixgbe_sfp_type_da_cu:
1090                         physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1091                         break;
1092                 case ixgbe_sfp_type_sr:
1093                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1094                         break;
1095                 case ixgbe_sfp_type_lr:
1096                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1097                         break;
1098                 default:
1099                         physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1100                         break;
1101                 }
1102                 break;
1103
1104         default:
1105                 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1106                 break;
1107         }
1108
1109         return physical_layer;
1110 }
1111
1112 static struct ixgbe_mac_operations mac_ops_82598 = {
1113         .init_hw                = &ixgbe_init_hw_generic,
1114         .reset_hw               = &ixgbe_reset_hw_82598,
1115         .start_hw               = &ixgbe_start_hw_generic,
1116         .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
1117         .get_media_type         = &ixgbe_get_media_type_82598,
1118         .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1119         .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
1120         .get_mac_addr           = &ixgbe_get_mac_addr_generic,
1121         .stop_adapter           = &ixgbe_stop_adapter_generic,
1122         .get_bus_info           = &ixgbe_get_bus_info_generic,
1123         .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
1124         .read_analog_reg8       = &ixgbe_read_analog_reg8_82598,
1125         .write_analog_reg8      = &ixgbe_write_analog_reg8_82598,
1126         .setup_link             = &ixgbe_setup_mac_link_82598,
1127         .setup_link_speed       = &ixgbe_setup_mac_link_speed_82598,
1128         .check_link             = &ixgbe_check_mac_link_82598,
1129         .get_link_capabilities  = &ixgbe_get_link_capabilities_82598,
1130         .led_on                 = &ixgbe_led_on_generic,
1131         .led_off                = &ixgbe_led_off_generic,
1132         .blink_led_start        = &ixgbe_blink_led_start_82598,
1133         .blink_led_stop         = &ixgbe_blink_led_stop_82598,
1134         .set_rar                = &ixgbe_set_rar_generic,
1135         .clear_rar              = &ixgbe_clear_rar_generic,
1136         .set_vmdq               = &ixgbe_set_vmdq_82598,
1137         .clear_vmdq             = &ixgbe_clear_vmdq_82598,
1138         .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
1139         .update_uc_addr_list    = &ixgbe_update_uc_addr_list_generic,
1140         .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1141         .enable_mc              = &ixgbe_enable_mc_generic,
1142         .disable_mc             = &ixgbe_disable_mc_generic,
1143         .clear_vfta             = &ixgbe_clear_vfta_82598,
1144         .set_vfta               = &ixgbe_set_vfta_82598,
1145         .setup_fc               = &ixgbe_setup_fc_82598,
1146 };
1147
1148 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1149         .init_params            = &ixgbe_init_eeprom_params_generic,
1150         .read                   = &ixgbe_read_eeprom_generic,
1151         .validate_checksum      = &ixgbe_validate_eeprom_checksum_generic,
1152         .update_checksum        = &ixgbe_update_eeprom_checksum_generic,
1153 };
1154
1155 static struct ixgbe_phy_operations phy_ops_82598 = {
1156         .identify               = &ixgbe_identify_phy_generic,
1157         .identify_sfp           = &ixgbe_identify_sfp_module_generic,
1158         .reset                  = &ixgbe_reset_phy_generic,
1159         .read_reg               = &ixgbe_read_phy_reg_generic,
1160         .write_reg              = &ixgbe_write_phy_reg_generic,
1161         .setup_link             = &ixgbe_setup_phy_link_generic,
1162         .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
1163         .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_82598,
1164 };
1165
1166 struct ixgbe_info ixgbe_82598_info = {
1167         .mac                    = ixgbe_mac_82598EB,
1168         .get_invariants         = &ixgbe_get_invariants_82598,
1169         .mac_ops                = &mac_ops_82598,
1170         .eeprom_ops             = &eeprom_ops_82598,
1171         .phy_ops                = &phy_ops_82598,
1172 };
1173