1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
33 #include "ixgbe_phy.h"
35 #define IXGBE_82598_MAX_TX_QUEUES 32
36 #define IXGBE_82598_MAX_RX_QUEUES 64
37 #define IXGBE_82598_RAR_ENTRIES 16
38 #define IXGBE_82598_MC_TBL_SIZE 128
39 #define IXGBE_82598_VFT_TBL_SIZE 128
41 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
44 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw);
45 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
53 * ixgbe_get_pcie_msix_count_82598 - Gets MSI-X vector count
54 * @hw: pointer to hardware structure
56 * Read PCIe configuration space, and get the MSI-X vector count from
57 * the capabilities table.
59 static u16 ixgbe_get_pcie_msix_count_82598(struct ixgbe_hw *hw)
61 struct ixgbe_adapter *adapter = hw->back;
63 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82598_CAPS,
65 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
67 /* MSI-X count is zero-based in HW, so increment to give proper value */
75 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
77 struct ixgbe_mac_info *mac = &hw->mac;
79 /* Call PHY identify routine to get the phy type */
80 ixgbe_identify_phy_generic(hw);
82 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
83 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
84 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
85 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
86 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
87 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82598(hw);
93 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
94 * @hw: pointer to hardware structure
96 * Initialize any function pointers that were not able to be
97 * set during get_invariants because the PHY/SFP type was
98 * not known. Perform the SFP init if necessary.
101 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
103 struct ixgbe_mac_info *mac = &hw->mac;
104 struct ixgbe_phy_info *phy = &hw->phy;
106 u16 list_offset, data_offset;
108 /* Identify the PHY */
109 phy->ops.identify(hw);
111 /* Overwrite the link function pointers if copper PHY */
112 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
113 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
114 mac->ops.setup_link_speed =
115 &ixgbe_setup_copper_link_speed_82598;
116 mac->ops.get_link_capabilities =
117 &ixgbe_get_copper_link_capabilities_82598;
120 switch (hw->phy.type) {
122 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
123 phy->ops.get_firmware_version =
124 &ixgbe_get_phy_firmware_version_tnx;
127 phy->ops.reset = &ixgbe_reset_phy_nl;
129 /* Call SFP+ identify routine to get the SFP+ module type */
130 ret_val = phy->ops.identify_sfp(hw);
133 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
134 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
138 /* Check to see if SFP+ module is supported */
139 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
143 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
156 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
157 * @hw: pointer to hardware structure
158 * @speed: pointer to link speed
159 * @autoneg: boolean auto-negotiation value
161 * Determines the link capabilities by reading the AUTOC register.
163 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
164 ixgbe_link_speed *speed,
170 * Determine link capabilities based on the stored value of AUTOC,
171 * which represents EEPROM defaults.
173 switch (hw->mac.orig_autoc & IXGBE_AUTOC_LMS_MASK) {
174 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
175 *speed = IXGBE_LINK_SPEED_1GB_FULL;
179 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
180 *speed = IXGBE_LINK_SPEED_10GB_FULL;
184 case IXGBE_AUTOC_LMS_1G_AN:
185 *speed = IXGBE_LINK_SPEED_1GB_FULL;
189 case IXGBE_AUTOC_LMS_KX4_AN:
190 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
191 *speed = IXGBE_LINK_SPEED_UNKNOWN;
192 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX4_SUPP)
193 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
194 if (hw->mac.orig_autoc & IXGBE_AUTOC_KX_SUPP)
195 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
200 status = IXGBE_ERR_LINK_SETUP;
208 * ixgbe_get_copper_link_capabilities_82598 - Determines link capabilities
209 * @hw: pointer to hardware structure
210 * @speed: pointer to link speed
211 * @autoneg: boolean auto-negotiation value
213 * Determines the link capabilities by reading the AUTOC register.
215 static s32 ixgbe_get_copper_link_capabilities_82598(struct ixgbe_hw *hw,
216 ixgbe_link_speed *speed,
219 s32 status = IXGBE_ERR_LINK_SETUP;
225 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
226 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
230 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
231 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
232 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
233 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
240 * ixgbe_get_media_type_82598 - Determines media type
241 * @hw: pointer to hardware structure
243 * Returns the media type (fiber, copper, backplane)
245 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
247 enum ixgbe_media_type media_type;
249 /* Media type for I82598 is based on device ID */
250 switch (hw->device_id) {
251 case IXGBE_DEV_ID_82598:
252 case IXGBE_DEV_ID_82598_BX:
253 media_type = ixgbe_media_type_backplane;
255 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
256 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
257 case IXGBE_DEV_ID_82598EB_CX4:
258 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
259 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
260 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
261 case IXGBE_DEV_ID_82598EB_XF_LR:
262 case IXGBE_DEV_ID_82598EB_SFP_LOM:
263 media_type = ixgbe_media_type_fiber;
265 case IXGBE_DEV_ID_82598AT:
266 media_type = ixgbe_media_type_copper;
269 media_type = ixgbe_media_type_unknown;
277 * ixgbe_fc_enable_82598 - Enable flow control
278 * @hw: pointer to hardware structure
279 * @packetbuf_num: packet buffer number (0-7)
281 * Enable flow control according to the current settings.
283 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
290 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
291 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
293 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
294 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
297 * The possible values of fc.current_mode are:
298 * 0: Flow control is completely disabled
299 * 1: Rx flow control is enabled (we can receive pause frames,
300 * but not send pause frames).
301 * 2: Tx flow control is enabled (we can send pause frames but
302 * we do not support receiving pause frames).
303 * 3: Both Rx and Tx flow control (symmetric) are enabled.
306 switch (hw->fc.current_mode) {
308 /* Flow control completely disabled by software override. */
310 case ixgbe_fc_rx_pause:
312 * Rx Flow control is enabled and Tx Flow control is
313 * disabled by software override. Since there really
314 * isn't a way to advertise that we are capable of RX
315 * Pause ONLY, we will advertise that we support both
316 * symmetric and asymmetric Rx PAUSE. Later, we will
317 * disable the adapter's ability to send PAUSE frames.
319 fctrl_reg |= IXGBE_FCTRL_RFCE;
321 case ixgbe_fc_tx_pause:
323 * Tx Flow control is enabled, and Rx Flow control is
324 * disabled by software override.
326 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
329 /* Flow control (both Rx and Tx) is enabled by SW override. */
330 fctrl_reg |= IXGBE_FCTRL_RFCE;
331 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
334 hw_dbg(hw, "Flow control param set incorrectly\n");
335 ret_val = -IXGBE_ERR_CONFIG;
340 /* Enable 802.3x based flow control settings. */
341 fctrl_reg |= IXGBE_FCTRL_DPF;
342 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
343 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
345 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
346 if (hw->fc.current_mode & ixgbe_fc_tx_pause) {
347 if (hw->fc.send_xon) {
348 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
349 (hw->fc.low_water | IXGBE_FCRTL_XONE));
351 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(packetbuf_num),
355 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(packetbuf_num),
356 (hw->fc.high_water | IXGBE_FCRTH_FCEN));
359 /* Configure pause time (2 TCs per register) */
360 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num));
361 if ((packetbuf_num & 1) == 0)
362 reg = (reg & 0xFFFF0000) | hw->fc.pause_time;
364 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16);
365 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg);
367 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1));
374 * ixgbe_setup_fc_82598 - Configure flow control settings
375 * @hw: pointer to hardware structure
376 * @packetbuf_num: packet buffer number (0-7)
378 * Configures the flow control settings based on SW configuration. This
379 * function is used for 802.3x flow control configuration only.
381 static s32 ixgbe_setup_fc_82598(struct ixgbe_hw *hw, s32 packetbuf_num)
384 ixgbe_link_speed speed;
387 /* Validate the packetbuf configuration */
388 if (packetbuf_num < 0 || packetbuf_num > 7) {
389 hw_dbg(hw, "Invalid packet buffer number [%d], expected range is"
390 " 0-7\n", packetbuf_num);
391 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
396 * Validate the water mark configuration. Zero water marks are invalid
397 * because it causes the controller to just blast out fc packets.
399 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) {
400 if (hw->fc.requested_mode != ixgbe_fc_none) {
401 hw_dbg(hw, "Invalid water mark configuration\n");
402 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
408 * Validate the requested mode. Strict IEEE mode does not allow
409 * ixgbe_fc_rx_pause because it will cause testing anomalies.
411 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
412 hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
413 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
418 * 10gig parts do not have a word in the EEPROM to determine the
419 * default flow control setting, so we explicitly set it to full.
421 if (hw->fc.requested_mode == ixgbe_fc_default)
422 hw->fc.requested_mode = ixgbe_fc_full;
425 * Save off the requested flow control mode for use later. Depending
426 * on the link partner's capabilities, we may or may not use this mode.
429 hw->fc.current_mode = hw->fc.requested_mode;
431 /* Decide whether to use autoneg or not. */
432 hw->mac.ops.check_link(hw, &speed, &link_up, false);
433 if (!hw->fc.disable_fc_autoneg && hw->phy.multispeed_fiber &&
434 (speed == IXGBE_LINK_SPEED_1GB_FULL))
435 ret_val = ixgbe_fc_autoneg(hw);
440 ret_val = ixgbe_fc_enable_82598(hw, packetbuf_num);
447 * ixgbe_setup_mac_link_82598 - Configures MAC link settings
448 * @hw: pointer to hardware structure
450 * Configures link settings based on values in the ixgbe_hw struct.
451 * Restarts the link. Performs autonegotiation if needed.
453 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw)
461 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
462 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
463 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
465 /* Only poll for autoneg to complete if specified to do so */
466 if (hw->phy.autoneg_wait_to_complete) {
467 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
468 IXGBE_AUTOC_LMS_KX4_AN ||
469 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
470 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
471 links_reg = 0; /* Just in case Autoneg time = 0 */
472 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
473 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
474 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
478 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
479 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
480 hw_dbg(hw, "Autonegotiation did not complete.\n");
486 * We want to save off the original Flow Control configuration just in
487 * case we get disconnected and then reconnected into a different hub
488 * or switch with different Flow Control capabilities.
490 ixgbe_setup_fc_82598(hw, 0);
492 /* Add delay to filter out noises during initial link setup */
499 * ixgbe_check_mac_link_82598 - Get link/speed status
500 * @hw: pointer to hardware structure
501 * @speed: pointer to link speed
502 * @link_up: true is link is up, false otherwise
503 * @link_up_wait_to_complete: bool used to wait for link up or not
505 * Reads the links register to determine if link is up and the current speed
507 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
508 ixgbe_link_speed *speed, bool *link_up,
509 bool link_up_wait_to_complete)
513 u16 link_reg, adapt_comp_reg;
516 * SERDES PHY requires us to read link status from register 0xC79F.
517 * Bit 0 set indicates link is up/ready; clear indicates link down.
518 * 0xC00C is read to check that the XAUI lanes are active. Bit 0
519 * clear indicates active; set indicates inactive.
521 if (hw->phy.type == ixgbe_phy_nl) {
522 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
523 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
524 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
526 if (link_up_wait_to_complete) {
527 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
528 if ((link_reg & 1) &&
529 ((adapt_comp_reg & 1) == 0)) {
536 hw->phy.ops.read_reg(hw, 0xC79F,
539 hw->phy.ops.read_reg(hw, 0xC00C,
544 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
550 if (*link_up == false)
554 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
555 if (link_up_wait_to_complete) {
556 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
557 if (links_reg & IXGBE_LINKS_UP) {
564 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
567 if (links_reg & IXGBE_LINKS_UP)
573 if (links_reg & IXGBE_LINKS_SPEED)
574 *speed = IXGBE_LINK_SPEED_10GB_FULL;
576 *speed = IXGBE_LINK_SPEED_1GB_FULL;
584 * ixgbe_setup_mac_link_speed_82598 - Set MAC link speed
585 * @hw: pointer to hardware structure
586 * @speed: new link speed
587 * @autoneg: true if auto-negotiation enabled
588 * @autoneg_wait_to_complete: true if waiting is needed to complete
590 * Set the link speed in the AUTOC register and restarts link.
592 static s32 ixgbe_setup_mac_link_speed_82598(struct ixgbe_hw *hw,
593 ixgbe_link_speed speed, bool autoneg,
594 bool autoneg_wait_to_complete)
597 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
598 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
599 u32 autoc = curr_autoc;
600 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
602 /* Check to see if speed passed in is supported. */
603 ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
604 speed &= link_capabilities;
606 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
607 status = IXGBE_ERR_LINK_SETUP;
609 /* Set KX4/KX support according to speed requested */
610 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
611 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
612 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
613 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
614 autoc |= IXGBE_AUTOC_KX4_SUPP;
615 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
616 autoc |= IXGBE_AUTOC_KX_SUPP;
617 if (autoc != curr_autoc)
618 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
622 hw->phy.autoneg_wait_to_complete = autoneg_wait_to_complete;
625 * Setup and restart the link based on the new values in
626 * ixgbe_hw This will write the AUTOC register based on the new
629 status = ixgbe_setup_mac_link_82598(hw);
637 * ixgbe_setup_copper_link_82598 - Setup copper link settings
638 * @hw: pointer to hardware structure
640 * Configures link settings based on values in the ixgbe_hw struct.
641 * Restarts the link. Performs autonegotiation if needed. Restart
642 * phy and wait for autonegotiate to finish. Then synchronize the
645 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw)
649 /* Restart autonegotiation on PHY */
650 status = hw->phy.ops.setup_link(hw);
653 ixgbe_setup_mac_link_82598(hw);
659 * ixgbe_setup_copper_link_speed_82598 - Set the PHY autoneg advertised field
660 * @hw: pointer to hardware structure
661 * @speed: new link speed
662 * @autoneg: true if autonegotiation enabled
663 * @autoneg_wait_to_complete: true if waiting is needed to complete
665 * Sets the link speed in the AUTOC register in the MAC and restarts link.
667 static s32 ixgbe_setup_copper_link_speed_82598(struct ixgbe_hw *hw,
668 ixgbe_link_speed speed,
670 bool autoneg_wait_to_complete)
674 /* Setup the PHY according to input speed */
675 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
676 autoneg_wait_to_complete);
679 ixgbe_setup_mac_link_82598(hw);
685 * ixgbe_reset_hw_82598 - Performs hardware reset
686 * @hw: pointer to hardware structure
688 * Resets the hardware by resetting the transmit and receive units, masks and
689 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
692 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
701 /* Call adapter stop to disable tx/rx and clear interrupts */
702 hw->mac.ops.stop_adapter(hw);
705 * Power up the Atlas Tx lanes if they are currently powered down.
706 * Atlas Tx lanes are powered down for MAC loopback tests, but
707 * they are not automatically restored on reset.
709 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
710 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
711 /* Enable Tx Atlas so packets can be transmitted again */
712 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
714 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
715 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
718 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
720 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
721 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
724 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
726 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
727 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
730 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
732 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
733 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
738 if (hw->phy.reset_disable == false) {
739 /* PHY ops must be identified and initialized prior to reset */
741 /* Init PHY and function pointers, perform SFP setup */
742 status = hw->phy.ops.init(hw);
743 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
746 hw->phy.ops.reset(hw);
750 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
751 * access and verify no pending requests before reset
753 status = ixgbe_disable_pcie_master(hw);
755 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
756 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
760 * Issue global reset to the MAC. This needs to be a SW reset.
761 * If link reset is used, it might reset the MAC when mng is using it
763 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
764 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
765 IXGBE_WRITE_FLUSH(hw);
767 /* Poll for reset bit to self-clear indicating reset is complete */
768 for (i = 0; i < 10; i++) {
770 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
771 if (!(ctrl & IXGBE_CTRL_RST))
774 if (ctrl & IXGBE_CTRL_RST) {
775 status = IXGBE_ERR_RESET_FAILED;
776 hw_dbg(hw, "Reset polling failed to complete.\n");
781 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
782 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
783 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
786 * Store the original AUTOC value if it has not been
787 * stored off yet. Otherwise restore the stored original
788 * AUTOC value since the reset operation sets back to deaults.
790 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
791 if (hw->mac.orig_link_settings_stored == false) {
792 hw->mac.orig_autoc = autoc;
793 hw->mac.orig_link_settings_stored = true;
794 } else if (autoc != hw->mac.orig_autoc) {
795 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
798 /* Store the permanent mac address */
799 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
806 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
807 * @hw: pointer to hardware struct
808 * @rar: receive address register index to associate with a VMDq index
809 * @vmdq: VMDq set index
811 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
815 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
816 rar_high &= ~IXGBE_RAH_VIND_MASK;
817 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
818 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
823 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
824 * @hw: pointer to hardware struct
825 * @rar: receive address register index to associate with a VMDq index
826 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
828 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
831 u32 rar_entries = hw->mac.num_rar_entries;
833 if (rar < rar_entries) {
834 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
835 if (rar_high & IXGBE_RAH_VIND_MASK) {
836 rar_high &= ~IXGBE_RAH_VIND_MASK;
837 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
840 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
847 * ixgbe_set_vfta_82598 - Set VLAN filter table
848 * @hw: pointer to hardware structure
849 * @vlan: VLAN id to write to VLAN filter
850 * @vind: VMDq output index that maps queue to VLAN id in VFTA
851 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
853 * Turn on/off specified VLAN in the VLAN filter table.
855 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
864 return IXGBE_ERR_PARAM;
866 /* Determine 32-bit word position in array */
867 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
869 /* Determine the location of the (VMD) queue index */
870 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
871 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
873 /* Set the nibble for VMD queue index */
874 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
875 bits &= (~(0x0F << bitindex));
876 bits |= (vind << bitindex);
877 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
879 /* Determine the location of the bit for this VLAN id */
880 bitindex = vlan & 0x1F; /* lower five bits */
882 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
884 /* Turn on this VLAN id */
885 bits |= (1 << bitindex);
887 /* Turn off this VLAN id */
888 bits &= ~(1 << bitindex);
889 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
895 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
896 * @hw: pointer to hardware structure
898 * Clears the VLAN filer table, and the VMDq index associated with the filter
900 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
905 for (offset = 0; offset < hw->mac.vft_size; offset++)
906 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
908 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
909 for (offset = 0; offset < hw->mac.vft_size; offset++)
910 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
917 * ixgbe_blink_led_start_82598 - Blink LED based on index.
918 * @hw: pointer to hardware structure
919 * @index: led number to blink
921 static s32 ixgbe_blink_led_start_82598(struct ixgbe_hw *hw, u32 index)
923 ixgbe_link_speed speed = 0;
925 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
926 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
929 * Link must be up to auto-blink the LEDs on the 82598EB MAC;
930 * force it if link is down.
932 hw->mac.ops.check_link(hw, &speed, &link_up, false);
935 autoc_reg |= IXGBE_AUTOC_FLU;
936 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
940 led_reg &= ~IXGBE_LED_MODE_MASK(index);
941 led_reg |= IXGBE_LED_BLINK(index);
942 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
943 IXGBE_WRITE_FLUSH(hw);
949 * ixgbe_blink_led_stop_82598 - Stop blinking LED based on index.
950 * @hw: pointer to hardware structure
951 * @index: led number to stop blinking
953 static s32 ixgbe_blink_led_stop_82598(struct ixgbe_hw *hw, u32 index)
955 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
956 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
958 autoc_reg &= ~IXGBE_AUTOC_FLU;
959 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
960 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
962 led_reg &= ~IXGBE_LED_MODE_MASK(index);
963 led_reg &= ~IXGBE_LED_BLINK(index);
964 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
965 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
966 IXGBE_WRITE_FLUSH(hw);
972 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
973 * @hw: pointer to hardware structure
974 * @reg: analog register to read
977 * Performs read operation to Atlas analog register specified.
979 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
983 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
984 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
985 IXGBE_WRITE_FLUSH(hw);
987 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
988 *val = (u8)atlas_ctl;
994 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
995 * @hw: pointer to hardware structure
996 * @reg: atlas register to write
997 * @val: value to write
999 * Performs write operation to Atlas analog register specified.
1001 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1005 atlas_ctl = (reg << 8) | val;
1006 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1007 IXGBE_WRITE_FLUSH(hw);
1014 * ixgbe_read_i2c_eeprom_82598 - Read 8 bit EEPROM word of an SFP+ module
1015 * over I2C interface through an intermediate phy.
1016 * @hw: pointer to hardware structure
1017 * @byte_offset: EEPROM byte offset to read
1018 * @eeprom_data: value read
1020 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1022 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1031 if (hw->phy.type == ixgbe_phy_nl) {
1033 * phy SDA/SCL registers are at addresses 0xC30A to
1034 * 0xC30D. These registers are used to talk to the SFP+
1035 * module's EEPROM through the SDA/SCL (I2C) interface.
1037 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1038 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1039 hw->phy.ops.write_reg(hw,
1040 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1041 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1045 for (i = 0; i < 100; i++) {
1046 hw->phy.ops.read_reg(hw,
1047 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1048 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1050 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1051 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1056 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1057 hw_dbg(hw, "EEPROM read did not pass.\n");
1058 status = IXGBE_ERR_SFP_NOT_PRESENT;
1063 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1064 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1066 *eeprom_data = (u8)(sfp_data >> 8);
1068 status = IXGBE_ERR_PHY;
1077 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1078 * @hw: pointer to hardware structure
1080 * Determines physical layer capabilities of the current configuration.
1082 static u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1084 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1086 switch (hw->device_id) {
1087 case IXGBE_DEV_ID_82598:
1088 /* Default device ID is mezzanine card KX/KX4 */
1089 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_KX4 |
1090 IXGBE_PHYSICAL_LAYER_1000BASE_KX);
1092 case IXGBE_DEV_ID_82598_BX:
1093 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1094 case IXGBE_DEV_ID_82598EB_CX4:
1095 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
1096 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1098 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1099 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1101 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1102 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1103 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1104 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1106 case IXGBE_DEV_ID_82598EB_XF_LR:
1107 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1109 case IXGBE_DEV_ID_82598AT:
1110 physical_layer = (IXGBE_PHYSICAL_LAYER_10GBASE_T |
1111 IXGBE_PHYSICAL_LAYER_1000BASE_T);
1113 case IXGBE_DEV_ID_82598EB_SFP_LOM:
1114 hw->phy.ops.identify_sfp(hw);
1116 switch (hw->phy.sfp_type) {
1117 case ixgbe_sfp_type_da_cu:
1118 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1120 case ixgbe_sfp_type_sr:
1121 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1123 case ixgbe_sfp_type_lr:
1124 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1127 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1133 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1137 return physical_layer;
1140 static struct ixgbe_mac_operations mac_ops_82598 = {
1141 .init_hw = &ixgbe_init_hw_generic,
1142 .reset_hw = &ixgbe_reset_hw_82598,
1143 .start_hw = &ixgbe_start_hw_generic,
1144 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1145 .get_media_type = &ixgbe_get_media_type_82598,
1146 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82598,
1147 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
1148 .get_mac_addr = &ixgbe_get_mac_addr_generic,
1149 .stop_adapter = &ixgbe_stop_adapter_generic,
1150 .get_bus_info = &ixgbe_get_bus_info_generic,
1151 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
1152 .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1153 .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1154 .setup_link = &ixgbe_setup_mac_link_82598,
1155 .setup_link_speed = &ixgbe_setup_mac_link_speed_82598,
1156 .check_link = &ixgbe_check_mac_link_82598,
1157 .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1158 .led_on = &ixgbe_led_on_generic,
1159 .led_off = &ixgbe_led_off_generic,
1160 .blink_led_start = &ixgbe_blink_led_start_82598,
1161 .blink_led_stop = &ixgbe_blink_led_stop_82598,
1162 .set_rar = &ixgbe_set_rar_generic,
1163 .clear_rar = &ixgbe_clear_rar_generic,
1164 .set_vmdq = &ixgbe_set_vmdq_82598,
1165 .clear_vmdq = &ixgbe_clear_vmdq_82598,
1166 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1167 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
1168 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1169 .enable_mc = &ixgbe_enable_mc_generic,
1170 .disable_mc = &ixgbe_disable_mc_generic,
1171 .clear_vfta = &ixgbe_clear_vfta_82598,
1172 .set_vfta = &ixgbe_set_vfta_82598,
1173 .setup_fc = &ixgbe_setup_fc_82598,
1176 static struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1177 .init_params = &ixgbe_init_eeprom_params_generic,
1178 .read = &ixgbe_read_eeprom_generic,
1179 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1180 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1183 static struct ixgbe_phy_operations phy_ops_82598 = {
1184 .identify = &ixgbe_identify_phy_generic,
1185 .identify_sfp = &ixgbe_identify_sfp_module_generic,
1186 .init = &ixgbe_init_phy_ops_82598,
1187 .reset = &ixgbe_reset_phy_generic,
1188 .read_reg = &ixgbe_read_phy_reg_generic,
1189 .write_reg = &ixgbe_write_phy_reg_generic,
1190 .setup_link = &ixgbe_setup_phy_link_generic,
1191 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1192 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
1195 struct ixgbe_info ixgbe_82598_info = {
1196 .mac = ixgbe_mac_82598EB,
1197 .get_invariants = &ixgbe_get_invariants_82598,
1198 .mac_ops = &mac_ops_82598,
1199 .eeprom_ops = &eeprom_ops_82598,
1200 .phy_ops = &phy_ops_82598,