1 /*********************************************************************
5 * Description: Driver for the VIA VT8231/VT8233 IrDA chipsets
6 * Author: VIA Technologies, inc
9 Copyright (c) 1998-2003 VIA Technologies, Inc.
11 This program is free software; you can redistribute it and/or modify it under
12 the terms of the GNU General Public License as published by the Free Software
13 Foundation; either version 2, or (at your option) any later version.
15 This program is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
18 See the GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License along with
21 this program; if not, see <http://www.gnu.org/licenses/>.
24 * jul/08/2002 : Rx buffer length should use Rx ring ptr.
25 * Oct/28/2002 : Add SB id for 3147 and 3177.
26 * jul/09/2002 : only implement two kind of dongle currently.
27 * Oct/02/2002 : work on VT8231 and VT8233 .
28 * Aug/06/2003 : change driver format to pci driver .
29 ********************************************************************/
32 #include <linux/time.h>
33 #include <linux/spinlock.h>
35 #include <linux/types.h>
38 #define MAX_TX_WINDOW 7
39 #define MAX_RX_WINDOW 7
41 struct st_fifo_entry {
47 struct st_fifo_entry entries[MAX_RX_WINDOW + 2];
55 void *start; /* Start of frame in DMA mem */
56 int len; /* Length of frame in DMA mem */
60 struct frame_cb queue[MAX_TX_WINDOW + 2]; /* Info about frames in queue */
61 int ptr; /* Currently being sent */
62 int len; /* Length of queue */
63 int free; /* Next free slot */
64 void *tail; /* Next free start in DMA mem */
68 struct eventflag // for keeping track of Interrupt Events
71 unsigned char TxFIFOUnderRun;
72 unsigned char EOMessage;
73 unsigned char TxFIFOReady;
74 unsigned char EarlyEOM;
78 unsigned char RxFIFOOverRun;
79 unsigned char EOPacket;
80 unsigned char RxAvail;
81 unsigned char TooLargePacket;
84 unsigned char Unknown;
86 unsigned char TimeOut;
87 unsigned char RxDMATC;
88 unsigned char TxDMATC;
91 /* Private data for each instance */
93 struct st_fifo st_fifo; /* Info about received frames */
94 struct tx_fifo tx_fifo; /* Info about frames to be transmitted */
96 struct net_device *netdev; /* Yes! we are some kind of netdevice */
98 struct irlap_cb *irlap; /* The link layer we are binded to */
99 struct qos_info qos; /* QoS capabilities for this device */
101 chipio_t io; /* IrDA controller information */
102 iobuff_t tx_buff; /* Transmit buffer */
103 iobuff_t rx_buff; /* Receive buffer */
104 dma_addr_t tx_buff_dma;
105 dma_addr_t rx_buff_dma;
107 __u8 ier; /* Interrupt enable register */
109 struct timeval stamp;
112 spinlock_t lock; /* For serializing operations */
114 __u32 flags; /* Interface flags */
116 int index; /* Instance index */
118 struct eventflag EventFlag;
119 unsigned int chip_id; /* to remember chip id */
120 unsigned int RetryCount;
121 unsigned int RxDataReady;
122 unsigned int RxLastCount;
126 //---------I=Infrared, H=Host, M=Misc, T=Tx, R=Rx, ST=Status,
127 // CF=Config, CT=Control, L=Low, H=High, C=Count
128 #define I_CF_L_0 0x10
129 #define I_CF_H_0 0x11
130 #define I_SIR_BOF 0x12
131 #define I_SIR_EOF 0x13
132 #define I_ST_CT_0 0x15
133 #define I_ST_L_1 0x16
134 #define I_ST_H_1 0x17
135 #define I_CF_L_1 0x18
136 #define I_CF_H_1 0x19
137 #define I_CF_L_2 0x1a
138 #define I_CF_H_2 0x1b
161 //-------------------------------
162 #define StartAddr 0x10 // the first register address
163 #define EndAddr 0x3f // the last register address
164 #define GetBit(val,bit) val = (unsigned char) ((val>>bit) & 0x1)
166 #define SetBit(val,bit) val= (unsigned char ) (val | (0x1 << bit))
168 #define ResetBit(val,bit) val= (unsigned char ) (val & ~(0x1 << bit))
173 #define DMA_TX_MODE 0x08
174 #define DMA_RX_MODE 0x04
178 #define MASK1 DMA1+0x0a
179 #define MASK2 DMA2+0x14
183 #define Rd_Valid 0x08
186 static void DisableDmaChannel(unsigned int channel)
188 switch (channel) { // 8 Bit DMA channels DMAC1
190 outb(4, MASK1); //mask channel 0
193 outb(5, MASK1); //Mask channel 1
196 outb(6, MASK1); //Mask channel 2
199 outb(7, MASK1); //Mask channel 3
202 outb(5, MASK2); //Mask channel 5
205 outb(6, MASK2); //Mask channel 6
208 outb(7, MASK2); //Mask channel 7
215 static unsigned char ReadLPCReg(int iRegNum)
228 static void WriteLPCReg(int iRegNum, unsigned char iVal)
238 static __u8 ReadReg(unsigned int BaseAddr, int iRegNum)
240 return (__u8) inb(BaseAddr + iRegNum);
243 static void WriteReg(unsigned int BaseAddr, int iRegNum, unsigned char iVal)
245 outb(iVal, BaseAddr + iRegNum);
248 static int WriteRegBit(unsigned int BaseAddr, unsigned char RegNum,
249 unsigned char BitPos, unsigned char value)
256 if ((RegNum < StartAddr) || (RegNum > EndAddr))
258 Rtemp = ReadReg(BaseAddr, RegNum);
260 Wtemp = ResetBit(Rtemp, BitPos);
263 Wtemp = SetBit(Rtemp, BitPos);
267 WriteReg(BaseAddr, RegNum, Wtemp);
271 static __u8 CheckRegBit(unsigned int BaseAddr, unsigned char RegNum,
272 unsigned char BitPos)
278 if ((RegNum < StartAddr) || (RegNum > EndAddr)) {
279 // printf("what is the register %x!\n",RegNum);
281 temp = ReadReg(BaseAddr, RegNum);
282 return GetBit(temp, BitPos);
285 static void SetMaxRxPacketSize(__u16 iobase, __u16 size)
288 if ((size & 0xe000) == 0) {
290 high = (size & 0x1f00) >> 8;
291 WriteReg(iobase, I_CF_L_2, low);
292 WriteReg(iobase, I_CF_H_2, high);
300 static void SetFIFO(__u16 iobase, __u16 value)
304 WriteRegBit(iobase, 0x11, 0, 0);
305 WriteRegBit(iobase, 0x11, 7, 1);
308 WriteRegBit(iobase, 0x11, 0, 0);
309 WriteRegBit(iobase, 0x11, 7, 0);
312 WriteRegBit(iobase, 0x11, 0, 1);
313 WriteRegBit(iobase, 0x11, 7, 0);
316 WriteRegBit(iobase, 0x11, 0, 0);
317 WriteRegBit(iobase, 0x11, 7, 0);
322 #define CRC16(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,7,val) //0 for 32 CRC
324 #define SetVFIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,5,val)
325 #define SetFIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,6,val)
326 #define SetMIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,5,val)
327 #define SetSIR(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,4,val)
329 #define SIRFilter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,3,val)
330 #define Filter(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,2,val)
331 #define InvertTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,1,val)
332 #define InvertRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_L_0,0,val)
333 //****************************I_CF_H_0
334 #define EnableTX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,4,val)
335 #define EnableRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,3,val)
336 #define EnableDMA(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,2,val)
337 #define SIRRecvAny(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,1,val)
338 #define DiableTrans(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_H_0,0,val)
339 //***************************I_SIR_BOF,I_SIR_EOF
340 #define SetSIRBOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_BOF,val)
341 #define SetSIREOF(BaseAddr,val) WriteReg(BaseAddr,I_SIR_EOF,val)
342 #define GetSIRBOF(BaseAddr) ReadReg(BaseAddr,I_SIR_BOF)
343 #define GetSIREOF(BaseAddr) ReadReg(BaseAddr,I_SIR_EOF)
344 //*******************I_ST_CT_0
345 #define EnPhys(BaseAddr,val) WriteRegBit(BaseAddr,I_ST_CT_0,7,val)
346 #define IsModeError(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,6) //RO
347 #define IsVFIROn(BaseAddr) CheckRegBit(BaseAddr,0x14,0) //RO for VT1211 only
348 #define IsFIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,5) //RO
349 #define IsMIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,4) //RO
350 #define IsSIROn(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,3) //RO
351 #define IsEnableTX(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,2) //RO
352 #define IsEnableRX(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,1) //RO
353 #define Is16CRC(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,0) //RO
354 //***************************I_CF_3
355 #define DisableAdjacentPulseWidth(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,5,val) //1 disable
356 #define DisablePulseWidthAdjust(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,4,val) //1 disable
357 #define UseOneRX(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,1,val) //0 use two RX
358 #define SlowIRRXLowActive(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,0,val) //0 show RX high=1 in SIR
359 //***************************H_CT
360 #define EnAllInt(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,7,val)
361 #define TXStart(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,6,val)
362 #define RXStart(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,5,val)
363 #define ClearRXInt(BaseAddr,val) WriteRegBit(BaseAddr,H_CT,4,val) // 1 clear
364 //*****************H_ST
365 #define IsRXInt(BaseAddr) CheckRegBit(BaseAddr,H_ST,4)
366 #define GetIntIndentify(BaseAddr) ((ReadReg(BaseAddr,H_ST)&0xf1) >>1)
367 #define IsHostBusy(BaseAddr) CheckRegBit(BaseAddr,H_ST,0)
368 #define GetHostStatus(BaseAddr) ReadReg(BaseAddr,H_ST) //RO
369 //**************************M_CT
370 #define EnTXDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,7,val)
371 #define EnRXDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,6,val)
372 #define SwapDMA(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,5,val)
373 #define EnInternalLoop(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,4,val)
374 #define EnExternalLoop(BaseAddr,val) WriteRegBit(BaseAddr,M_CT,3,val)
375 //**************************TX_CT_1
376 #define EnTXFIFOHalfLevelInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,4,val) //half empty int (1 half)
377 #define EnTXFIFOUnderrunEOMInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,5,val)
378 #define EnTXFIFOReadyInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,6,val) //int when reach it threshold (setting by bit 4)
379 //**************************TX_CT_2
380 #define ForceUnderrun(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,7,val) // force an underrun int
381 #define EnTXCRC(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,6,val) //1 for FIR,MIR...0 (not SIR)
382 #define ForceBADCRC(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,5,val) //force an bad CRC
383 #define SendSIP(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,4,val) //send indication pulse for prevent SIR disturb
384 #define ClearEnTX(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_2,3,val) // opposite to EnTX
385 //*****************TX_ST
386 #define GetTXStatus(BaseAddr) ReadReg(BaseAddr,TX_ST) //RO
387 //**************************RX_CT
388 #define EnRXSpecInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,0,val)
389 #define EnRXFIFOReadyInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,1,val) //enable int when reach it threshold (setting by bit 7)
390 #define EnRXFIFOHalfLevelInt(BaseAddr,val) WriteRegBit(BaseAddr,RX_CT,7,val) //enable int when (1) half full...or (0) just not full
391 //*****************RX_ST
392 #define GetRXStatus(BaseAddr) ReadReg(BaseAddr,RX_ST) //RO
393 //***********************P_ADDR
394 #define SetPacketAddr(BaseAddr,addr) WriteReg(BaseAddr,P_ADDR,addr)
395 //***********************I_CF_4
396 #define EnGPIOtoRX2(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,7,val)
397 #define EnTimerInt(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,1,val)
398 #define ClearTimerInt(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_4,0,val)
399 //***********************I_T_C_L
400 #define WriteGIO(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_L,7,val)
401 #define ReadGIO(BaseAddr) CheckRegBit(BaseAddr,I_T_C_L,7)
402 #define ReadRX(BaseAddr) CheckRegBit(BaseAddr,I_T_C_L,3) //RO
403 #define WriteTX(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_L,0,val)
404 //***********************I_T_C_H
405 #define EnRX2(BaseAddr,val) WriteRegBit(BaseAddr,I_T_C_H,7,val)
406 #define ReadRX2(BaseAddr) CheckRegBit(BaseAddr,I_T_C_H,7)
407 //**********************Version
408 #define GetFIRVersion(BaseAddr) ReadReg(BaseAddr,VERSION)
411 static void SetTimer(__u16 iobase, __u8 count)
413 EnTimerInt(iobase, OFF);
414 WriteReg(iobase, TIMER, count);
415 EnTimerInt(iobase, ON);
419 static void SetSendByte(__u16 iobase, __u32 count)
423 if ((count & 0xf000) == 0) {
424 low = count & 0x00ff;
425 high = (count & 0x0f00) >> 8;
426 WriteReg(iobase, TX_C_L, low);
427 WriteReg(iobase, TX_C_H, high);
431 static void ResetChip(__u16 iobase, __u8 type)
435 value = (type + 2) << 4;
436 WriteReg(iobase, RESET, type);
439 static int CkRxRecv(__u16 iobase, struct via_ircc_cb *self)
442 __u16 wTmp = 0, wTmp1 = 0, wTmp_new = 0;
444 low = ReadReg(iobase, RX_C_L);
445 high = ReadReg(iobase, RX_C_H);
447 wTmp = (wTmp1 << 8) | low;
449 low = ReadReg(iobase, RX_C_L);
450 high = ReadReg(iobase, RX_C_H);
452 wTmp_new = (wTmp1 << 8) | low;
453 if (wTmp_new != wTmp)
460 static __u16 RxCurCount(__u16 iobase, struct via_ircc_cb * self)
463 __u16 wTmp = 0, wTmp1 = 0;
465 low = ReadReg(iobase, RX_P_L);
466 high = ReadReg(iobase, RX_P_H);
468 wTmp = (wTmp1 << 8) | low;
472 /* This Routine can only use in recevie_complete
473 * for it will update last count.
476 static __u16 GetRecvByte(__u16 iobase, struct via_ircc_cb * self)
479 __u16 wTmp, wTmp1, ret;
481 low = ReadReg(iobase, RX_P_L);
482 high = ReadReg(iobase, RX_P_H);
484 wTmp = (wTmp1 << 8) | low;
487 if (wTmp >= self->RxLastCount)
488 ret = wTmp - self->RxLastCount;
490 ret = (0x8000 - self->RxLastCount) + wTmp;
491 self->RxLastCount = wTmp;
493 /* RX_P is more actually the RX_C
494 low=ReadReg(iobase,RX_C_L);
495 high=ReadReg(iobase,RX_C_H);
506 static void Sdelay(__u16 scale)
511 for (j = 0; j < scale; j++) {
512 for (i = 0; i < 0x20; i++) {
519 static void Tdelay(__u16 scale)
524 for (j = 0; j < scale; j++) {
525 for (i = 0; i < 0x50; i++) {
533 static void ActClk(__u16 iobase, __u8 value)
536 bTmp = ReadReg(iobase, 0x34);
538 WriteReg(iobase, 0x34, bTmp | Clk_bit);
540 WriteReg(iobase, 0x34, bTmp & ~Clk_bit);
543 static void ClkTx(__u16 iobase, __u8 Clk, __u8 Tx)
547 bTmp = ReadReg(iobase, 0x34);
554 WriteReg(iobase, 0x34, bTmp);
562 WriteReg(iobase, 0x34, bTmp);
565 static void Wr_Byte(__u16 iobase, __u8 data)
577 for (i = 0; i < 8; i++) { //LDN
579 if ((bData >> i) & 0x01) {
580 ClkTx(iobase, 0, 1); //bit data = 1;
582 ClkTx(iobase, 0, 0); //bit data = 1;
586 ActClk(iobase, 1); //clk hi
591 static __u8 Rd_Indx(__u16 iobase, __u8 addr, __u8 index)
593 __u8 data = 0, bTmp, data_bit;
596 bTmp = addr | (index << 1) | 0;
601 Wr_Byte(iobase, bTmp);
605 for (i = 0; i < 10; i++) {
612 bTmp = ReadReg(iobase, 0x34);
613 if (!(bTmp & Rd_Valid))
616 if (!(bTmp & Rd_Valid)) {
617 for (i = 0; i < 8; i++) {
621 bTmp = ReadReg(iobase, 0x34);
630 for (i = 0; i < 2; i++) {
636 bTmp = ReadReg(iobase, 0x34);
638 for (i = 0; i < 1; i++) {
646 for (i = 0; i < 3; i++) {
655 static void Wr_Indx(__u16 iobase, __u8 addr, __u8 index, __u8 data)
664 bTmp = addr | (index << 1) | 1;
665 Wr_Byte(iobase, bTmp);
666 Wr_Byte(iobase, data);
667 for (i = 0; i < 2; i++) {
676 static void ResetDongle(__u16 iobase)
681 for (i = 0; i < 30; i++) {
690 static void SetSITmode(__u16 iobase)
695 bTmp = ReadLPCReg(0x28);
696 WriteLPCReg(0x28, bTmp | 0x10); //select ITMOFF
697 bTmp = ReadReg(iobase, 0x35);
698 WriteReg(iobase, 0x35, bTmp | 0x40); // Driver ITMOFF
699 WriteReg(iobase, 0x28, bTmp | 0x80); // enable All interrupt
702 static void SI_SetMode(__u16 iobase, int mode)
707 WriteLPCReg(0x28, 0x70); // S/W Reset
711 Wr_Indx(iobase, 0x40, 0x0, 0x17); //RX ,APEN enable,Normal power
712 Wr_Indx(iobase, 0x40, 0x1, mode); //Set Mode
713 Wr_Indx(iobase, 0x40, 0x2, 0xff); //Set power to FIR VFIR > 1m
714 bTmp = Rd_Indx(iobase, 0x40, 1);
717 static void InitCard(__u16 iobase)
719 ResetChip(iobase, 5);
720 WriteReg(iobase, I_ST_CT_0, 0x00); // open CHIP on
721 SetSIRBOF(iobase, 0xc0); // hardware default value
722 SetSIREOF(iobase, 0xc1);
725 static void CommonInit(__u16 iobase)
727 // EnTXCRC(iobase,0);
728 SwapDMA(iobase, OFF);
729 SetMaxRxPacketSize(iobase, 0x0fff); //set to max:4095
730 EnRXFIFOReadyInt(iobase, OFF);
731 EnRXFIFOHalfLevelInt(iobase, OFF);
732 EnTXFIFOHalfLevelInt(iobase, OFF);
733 EnTXFIFOUnderrunEOMInt(iobase, ON);
734 // EnTXFIFOReadyInt(iobase,ON);
735 InvertTX(iobase, OFF);
736 InvertRX(iobase, OFF);
737 // WriteLPCReg(0xF0,0); //(if VT1211 then do this)
738 if (IsSIROn(iobase)) {
739 SIRFilter(iobase, ON);
740 SIRRecvAny(iobase, ON);
742 SIRFilter(iobase, OFF);
743 SIRRecvAny(iobase, OFF);
745 EnRXSpecInt(iobase, ON);
746 WriteReg(iobase, I_ST_CT_0, 0x80);
747 EnableDMA(iobase, ON);
750 static void SetBaudRate(__u16 iobase, __u32 rate)
752 __u8 value = 11, temp;
754 if (IsSIROn(iobase)) {
756 case (__u32) (2400L):
759 case (__u32) (9600L):
762 case (__u32) (19200L):
765 case (__u32) (38400L):
768 case (__u32) (57600L):
771 case (__u32) (115200L):
777 } else if (IsMIROn(iobase)) {
778 value = 0; // will automatically be fixed in 1.152M
779 } else if (IsFIROn(iobase)) {
780 value = 0; // will automatically be fixed in 4M
782 temp = (ReadReg(iobase, I_CF_H_1) & 0x03);
784 WriteReg(iobase, I_CF_H_1, temp);
787 static void SetPulseWidth(__u16 iobase, __u8 width)
789 __u8 temp, temp1, temp2;
791 temp = (ReadReg(iobase, I_CF_L_1) & 0x1f);
792 temp1 = (ReadReg(iobase, I_CF_H_1) & 0xfc);
793 temp2 = (width & 0x07) << 5;
795 temp2 = (width & 0x18) >> 3;
797 WriteReg(iobase, I_CF_L_1, temp);
798 WriteReg(iobase, I_CF_H_1, temp1);
801 static void SetSendPreambleCount(__u16 iobase, __u8 count)
805 temp = ReadReg(iobase, I_CF_L_1) & 0xe0;
807 WriteReg(iobase, I_CF_L_1, temp);
811 static void SetVFIR(__u16 BaseAddr, __u8 val)
815 tmp = ReadReg(BaseAddr, I_CF_L_0);
816 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
817 WriteRegBit(BaseAddr, I_CF_H_0, 5, val);
820 static void SetFIR(__u16 BaseAddr, __u8 val)
824 WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
825 tmp = ReadReg(BaseAddr, I_CF_L_0);
826 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
827 WriteRegBit(BaseAddr, I_CF_L_0, 6, val);
830 static void SetMIR(__u16 BaseAddr, __u8 val)
834 WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
835 tmp = ReadReg(BaseAddr, I_CF_L_0);
836 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
837 WriteRegBit(BaseAddr, I_CF_L_0, 5, val);
840 static void SetSIR(__u16 BaseAddr, __u8 val)
844 WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);
845 tmp = ReadReg(BaseAddr, I_CF_L_0);
846 WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);
847 WriteRegBit(BaseAddr, I_CF_L_0, 4, val);
850 #endif /* via_IRCC_H */