drivers/net/ipa/reg/gsi_reg-v4.9.c

   1 // SPDX-License-Identifier: GPL-2.0
   2
   3 /* Copyright (C) 2023 Linaro Ltd. */
   4
   5 #include <linux/types.h>
   6
   7 #include "../gsi.h"
   8 #include "../reg.h"
   9 #include "../gsi_reg.h"
  10
  11 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
  12     0x0000c020 + 0x1000 * GSI_EE_AP);
  13
  14 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
  15     0x0000c024 + 0x1000 * GSI_EE_AP);
  16
  17 static const u32 reg_ch_c_cntxt_0_fmask[] = {
  18         [CHTYPE_PROTOCOL]                               = GENMASK(2, 0),
  19         [CHTYPE_DIR]                                    = BIT(3),
  20         [CH_EE]                                         = GENMASK(7, 4),
  21         [CHID]                                          = GENMASK(12, 8),
  22         [CHTYPE_PROTOCOL_MSB]                           = BIT(13),
  23         [ERINDEX]                                       = GENMASK(18, 14),
  24                                                 /* Bit 19 reserved */
  25         [CHSTATE]                                       = GENMASK(23, 20),
  26         [ELEMENT_SIZE]                                  = GENMASK(31, 24),
  27 };
  28
  29 REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
  30                   0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
  31
  32 static const u32 reg_ch_c_cntxt_1_fmask[] = {
  33         [CH_R_LENGTH]                                   = GENMASK(19, 0),
  34                                                 /* Bits 20-31 reserved */
  35 };
  36
  37 REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
  38                   0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
  39
  40 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
  41
  42 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
  43
  44 static const u32 reg_ch_c_qos_fmask[] = {
  45         [WRR_WEIGHT]                                    = GENMASK(3, 0),
  46                                                 /* Bits 4-7 reserved */
  47         [MAX_PREFETCH]                                  = BIT(8),
  48         [USE_DB_ENG]                                    = BIT(9),
  49         [PREFETCH_MODE]                                 = GENMASK(13, 10),
  50                                                 /* Bits 14-15 reserved */
  51         [EMPTY_LVL_THRSHOLD]                            = GENMASK(23, 16),
  52         [DB_IN_BYTES]                                   = BIT(24),
  53                                                 /* Bits 25-31 reserved */
  54 };
  55
  56 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
  57
  58 static const u32 reg_error_log_fmask[] = {
  59         [ERR_ARG3]                                      = GENMASK(3, 0),
  60         [ERR_ARG2]                                      = GENMASK(7, 4),
  61         [ERR_ARG1]                                      = GENMASK(11, 8),
  62         [ERR_CODE]                                      = GENMASK(15, 12),
  63                                                 /* Bits 16-18 reserved */
  64         [ERR_VIRT_IDX]                                  = GENMASK(23, 19),
  65         [ERR_TYPE]                                      = GENMASK(27, 24),
  66         [ERR_EE]                                        = GENMASK(31, 28),
  67 };
  68
  69 REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
  70            0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
  71
  72 REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
  73            0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
  74
  75 REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
  76            0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
  77
  78 REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
  79            0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
  80
  81 static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
  82         [EV_CHTYPE]                                     = GENMASK(3, 0),
  83         [EV_EE]                                         = GENMASK(7, 4),
  84         [EV_EVCHID]                                     = GENMASK(15, 8),
  85         [EV_INTYPE]                                     = BIT(16),
  86                                                 /* Bits 17-19 reserved */
  87         [EV_CHSTATE]                                    = GENMASK(23, 20),
  88         [EV_ELEMENT_SIZE]                               = GENMASK(31, 24),
  89 };
  90
  91 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
  92                   0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
  93
  94 static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
  95         [R_LENGTH]                                      = GENMASK(15, 0),
  96 };
  97
  98 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
  99                   0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
 100
 101 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
 102            0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
 103
 104 REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
 105            0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
 106
 107 REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
 108            0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
 109
 110 static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
 111         [EV_MODT]                                       = GENMASK(15, 0),
 112         [EV_MODC]                                       = GENMASK(23, 16),
 113         [EV_MOD_CNT]                                    = GENMASK(31, 24),
 114 };
 115
 116 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
 117                   0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
 118
 119 REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
 120            0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
 121
 122 REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
 123            0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
 124
 125 REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
 126            0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
 127
 128 REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
 129            0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
 130
 131 REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
 132            0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
 133
 134 REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
 135            0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
 136
 137 REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
 138            0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
 139
 140 REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
 141            0x00011000 + 0x4000 * GSI_EE_AP, 0x08);
 142
 143 REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
 144            0x00011100 + 0x4000 * GSI_EE_AP, 0x08);
 145
 146 static const u32 reg_gsi_status_fmask[] = {
 147         [ENABLED]                                       = BIT(0),
 148                                                 /* Bits 1-31 reserved */
 149 };
 150
 151 REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP);
 152
 153 static const u32 reg_ch_cmd_fmask[] = {
 154         [CH_CHID]                                       = GENMASK(7, 0),
 155                                                 /* Bits 8-23 reserved */
 156         [CH_OPCODE]                                     = GENMASK(31, 24),
 157 };
 158
 159 REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP);
 160
 161 static const u32 reg_ev_ch_cmd_fmask[] = {
 162         [EV_CHID]                                       = GENMASK(7, 0),
 163                                                 /* Bits 8-23 reserved */
 164         [EV_OPCODE]                                     = GENMASK(31, 24),
 165 };
 166
 167 REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP);
 168
 169 static const u32 reg_generic_cmd_fmask[] = {
 170         [GENERIC_OPCODE]                                = GENMASK(4, 0),
 171         [GENERIC_CHID]                                  = GENMASK(9, 5),
 172         [GENERIC_EE]                                    = GENMASK(13, 10),
 173                                                 /* Bits 14-31 reserved */
 174 };
 175
 176 REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP);
 177
 178 static const u32 reg_hw_param_2_fmask[] = {
 179         [IRAM_SIZE]                                     = GENMASK(2, 0),
 180         [NUM_CH_PER_EE]                                 = GENMASK(7, 3),
 181         [NUM_EV_PER_EE]                                 = GENMASK(12, 8),
 182         [GSI_CH_PEND_TRANSLATE]                         = BIT(13),
 183         [GSI_CH_FULL_LOGIC]                             = BIT(14),
 184         [GSI_USE_SDMA]                                  = BIT(15),
 185         [GSI_SDMA_N_INT]                                = GENMASK(18, 16),
 186         [GSI_SDMA_MAX_BURST]                            = GENMASK(26, 19),
 187         [GSI_SDMA_N_IOVEC]                              = GENMASK(29, 27),
 188         [GSI_USE_RD_WR_ENG]                             = BIT(30),
 189         [GSI_USE_INTER_EE]                              = BIT(31),
 190 };
 191
 192 REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP);
 193
 194 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
 195
 196 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
 197
 198 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
 199
 200 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
 201
 202 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
 203     0x00012098 + 0x4000 * GSI_EE_AP);
 204
 205 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
 206     0x0001209c + 0x4000 * GSI_EE_AP);
 207
 208 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
 209     0x000120a0 + 0x4000 * GSI_EE_AP);
 210
 211 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
 212     0x000120a4 + 0x4000 * GSI_EE_AP);
 213
 214 REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
 215
 216 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
 217     0x000120b8 + 0x4000 * GSI_EE_AP);
 218
 219 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
 220     0x000120c0 + 0x4000 * GSI_EE_AP);
 221
 222 REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
 223
 224 REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
 225
 226 REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
 227
 228 REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
 229
 230 REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
 231
 232 REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
 233
 234 static const u32 reg_cntxt_intset_fmask[] = {
 235         [INTYPE]                                        = BIT(0)
 236                                                 /* Bits 1-31 reserved */
 237 };
 238
 239 REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP);
 240
 241 REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP);
 242
 243 REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
 244
 245 static const u32 reg_cntxt_scratch_0_fmask[] = {
 246         [INTER_EE_RESULT]                               = GENMASK(2, 0),
 247                                                 /* Bits 3-4 reserved */
 248         [GENERIC_EE_RESULT]                             = GENMASK(7, 5),
 249                                                 /* Bits 8-31 reserved */
 250 };
 251
 252 REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP);
 253
 254 static const struct reg *reg_array[] = {
 255         [INTER_EE_SRC_CH_IRQ_MSK]       = &reg_inter_ee_src_ch_irq_msk,
 256         [INTER_EE_SRC_EV_CH_IRQ_MSK]    = &reg_inter_ee_src_ev_ch_irq_msk,
 257         [CH_C_CNTXT_0]                  = &reg_ch_c_cntxt_0,
 258         [CH_C_CNTXT_1]                  = &reg_ch_c_cntxt_1,
 259         [CH_C_CNTXT_2]                  = &reg_ch_c_cntxt_2,
 260         [CH_C_CNTXT_3]                  = &reg_ch_c_cntxt_3,
 261         [CH_C_QOS]                      = &reg_ch_c_qos,
 262         [CH_C_SCRATCH_0]                = &reg_ch_c_scratch_0,
 263         [CH_C_SCRATCH_1]                = &reg_ch_c_scratch_1,
 264         [CH_C_SCRATCH_2]                = &reg_ch_c_scratch_2,
 265         [CH_C_SCRATCH_3]                = &reg_ch_c_scratch_3,
 266         [EV_CH_E_CNTXT_0]               = &reg_ev_ch_e_cntxt_0,
 267         [EV_CH_E_CNTXT_1]               = &reg_ev_ch_e_cntxt_1,
 268         [EV_CH_E_CNTXT_2]               = &reg_ev_ch_e_cntxt_2,
 269         [EV_CH_E_CNTXT_3]               = &reg_ev_ch_e_cntxt_3,
 270         [EV_CH_E_CNTXT_4]               = &reg_ev_ch_e_cntxt_4,
 271         [EV_CH_E_CNTXT_8]               = &reg_ev_ch_e_cntxt_8,
 272         [EV_CH_E_CNTXT_9]               = &reg_ev_ch_e_cntxt_9,
 273         [EV_CH_E_CNTXT_10]              = &reg_ev_ch_e_cntxt_10,
 274         [EV_CH_E_CNTXT_11]              = &reg_ev_ch_e_cntxt_11,
 275         [EV_CH_E_CNTXT_12]              = &reg_ev_ch_e_cntxt_12,
 276         [EV_CH_E_CNTXT_13]              = &reg_ev_ch_e_cntxt_13,
 277         [EV_CH_E_SCRATCH_0]             = &reg_ev_ch_e_scratch_0,
 278         [EV_CH_E_SCRATCH_1]             = &reg_ev_ch_e_scratch_1,
 279         [CH_C_DOORBELL_0]               = &reg_ch_c_doorbell_0,
 280         [EV_CH_E_DOORBELL_0]            = &reg_ev_ch_e_doorbell_0,
 281         [GSI_STATUS]                    = &reg_gsi_status,
 282         [CH_CMD]                        = &reg_ch_cmd,
 283         [EV_CH_CMD]                     = &reg_ev_ch_cmd,
 284         [GENERIC_CMD]                   = &reg_generic_cmd,
 285         [HW_PARAM_2]                    = &reg_hw_param_2,
 286         [CNTXT_TYPE_IRQ]                = &reg_cntxt_type_irq,
 287         [CNTXT_TYPE_IRQ_MSK]            = &reg_cntxt_type_irq_msk,
 288         [CNTXT_SRC_CH_IRQ]              = &reg_cntxt_src_ch_irq,
 289         [CNTXT_SRC_EV_CH_IRQ]           = &reg_cntxt_src_ev_ch_irq,
 290         [CNTXT_SRC_CH_IRQ_MSK]          = &reg_cntxt_src_ch_irq_msk,
 291         [CNTXT_SRC_EV_CH_IRQ_MSK]       = &reg_cntxt_src_ev_ch_irq_msk,
 292         [CNTXT_SRC_CH_IRQ_CLR]          = &reg_cntxt_src_ch_irq_clr,
 293         [CNTXT_SRC_EV_CH_IRQ_CLR]       = &reg_cntxt_src_ev_ch_irq_clr,
 294         [CNTXT_SRC_IEOB_IRQ]            = &reg_cntxt_src_ieob_irq,
 295         [CNTXT_SRC_IEOB_IRQ_MSK]        = &reg_cntxt_src_ieob_irq_msk,
 296         [CNTXT_SRC_IEOB_IRQ_CLR]        = &reg_cntxt_src_ieob_irq_clr,
 297         [CNTXT_GLOB_IRQ_STTS]           = &reg_cntxt_glob_irq_stts,
 298         [CNTXT_GLOB_IRQ_EN]             = &reg_cntxt_glob_irq_en,
 299         [CNTXT_GLOB_IRQ_CLR]            = &reg_cntxt_glob_irq_clr,
 300         [CNTXT_GSI_IRQ_STTS]            = &reg_cntxt_gsi_irq_stts,
 301         [CNTXT_GSI_IRQ_EN]              = &reg_cntxt_gsi_irq_en,
 302         [CNTXT_GSI_IRQ_CLR]             = &reg_cntxt_gsi_irq_clr,
 303         [CNTXT_INTSET]                  = &reg_cntxt_intset,
 304         [ERROR_LOG]                     = &reg_error_log,
 305         [ERROR_LOG_CLR]                 = &reg_error_log_clr,
 306         [CNTXT_SCRATCH_0]               = &reg_cntxt_scratch_0,
 307 };
 308
 309 const struct regs gsi_regs_v4_9 = {
 310         .reg_count      = ARRAY_SIZE(reg_array),
 311         .reg            = reg_array,
 312 };