1 // SPDX-License-Identifier: GPL-2.0
3 /* Copyright (C) 2023 Linaro Ltd. */
5 #include <linux/types.h>
9 #include "../gsi_reg.h"
11 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
12 0x0000c020 + 0x1000 * GSI_EE_AP);
14 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
15 0x0000c024 + 0x1000 * GSI_EE_AP);
17 static const u32 reg_ch_c_cntxt_0_fmask[] = {
18 [CHTYPE_PROTOCOL] = GENMASK(2, 0),
19 [CHTYPE_DIR] = BIT(3),
20 [CH_EE] = GENMASK(7, 4),
21 [CHID] = GENMASK(12, 8),
22 [CHTYPE_PROTOCOL_MSB] = BIT(13),
23 [ERINDEX] = GENMASK(18, 14),
25 [CHSTATE] = GENMASK(23, 20),
26 [ELEMENT_SIZE] = GENMASK(31, 24),
29 REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
30 0x0000f000 + 0x4000 * GSI_EE_AP, 0x80);
32 static const u32 reg_ch_c_cntxt_1_fmask[] = {
33 [CH_R_LENGTH] = GENMASK(19, 0),
34 /* Bits 20-31 reserved */
37 REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
38 0x0000f004 + 0x4000 * GSI_EE_AP, 0x80);
40 REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0000f008 + 0x4000 * GSI_EE_AP, 0x80);
42 REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0000f00c + 0x4000 * GSI_EE_AP, 0x80);
44 static const u32 reg_ch_c_qos_fmask[] = {
45 [WRR_WEIGHT] = GENMASK(3, 0),
46 /* Bits 4-7 reserved */
47 [MAX_PREFETCH] = BIT(8),
48 [USE_DB_ENG] = BIT(9),
49 [PREFETCH_MODE] = GENMASK(13, 10),
50 /* Bits 14-15 reserved */
51 [EMPTY_LVL_THRSHOLD] = GENMASK(23, 16),
52 [DB_IN_BYTES] = BIT(24),
53 /* Bits 25-31 reserved */
56 REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0000f05c + 0x4000 * GSI_EE_AP, 0x80);
58 static const u32 reg_error_log_fmask[] = {
59 [ERR_ARG3] = GENMASK(3, 0),
60 [ERR_ARG2] = GENMASK(7, 4),
61 [ERR_ARG1] = GENMASK(11, 8),
62 [ERR_CODE] = GENMASK(15, 12),
63 /* Bits 16-18 reserved */
64 [ERR_VIRT_IDX] = GENMASK(23, 19),
65 [ERR_TYPE] = GENMASK(27, 24),
66 [ERR_EE] = GENMASK(31, 28),
69 REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
70 0x0000f060 + 0x4000 * GSI_EE_AP, 0x80);
72 REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
73 0x0000f064 + 0x4000 * GSI_EE_AP, 0x80);
75 REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
76 0x0000f068 + 0x4000 * GSI_EE_AP, 0x80);
78 REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
79 0x0000f06c + 0x4000 * GSI_EE_AP, 0x80);
81 static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
82 [EV_CHTYPE] = GENMASK(3, 0),
83 [EV_EE] = GENMASK(7, 4),
84 [EV_EVCHID] = GENMASK(15, 8),
85 [EV_INTYPE] = BIT(16),
86 /* Bits 17-19 reserved */
87 [EV_CHSTATE] = GENMASK(23, 20),
88 [EV_ELEMENT_SIZE] = GENMASK(31, 24),
91 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
92 0x00010000 + 0x4000 * GSI_EE_AP, 0x80);
94 REG_STRIDE(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
95 0x00010004 + 0x4000 * GSI_EE_AP, 0x80);
97 REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
98 0x00010008 + 0x4000 * GSI_EE_AP, 0x80);
100 REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
101 0x0001000c + 0x4000 * GSI_EE_AP, 0x80);
103 REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
104 0x00010010 + 0x4000 * GSI_EE_AP, 0x80);
106 static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
107 [EV_MODT] = GENMASK(15, 0),
108 [EV_MODC] = GENMASK(23, 16),
109 [EV_MOD_CNT] = GENMASK(31, 24),
112 REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
113 0x00010020 + 0x4000 * GSI_EE_AP, 0x80);
115 REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
116 0x00010024 + 0x4000 * GSI_EE_AP, 0x80);
118 REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
119 0x00010028 + 0x4000 * GSI_EE_AP, 0x80);
121 REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
122 0x0001002c + 0x4000 * GSI_EE_AP, 0x80);
124 REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
125 0x00010030 + 0x4000 * GSI_EE_AP, 0x80);
127 REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
128 0x00010034 + 0x4000 * GSI_EE_AP, 0x80);
130 REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
131 0x00010048 + 0x4000 * GSI_EE_AP, 0x80);
133 REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
134 0x0001004c + 0x4000 * GSI_EE_AP, 0x80);
136 REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
137 0x00011000 + 0x4000 * GSI_EE_AP, 0x08);
139 REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
140 0x00011100 + 0x4000 * GSI_EE_AP, 0x08);
142 static const u32 reg_gsi_status_fmask[] = {
144 /* Bits 1-31 reserved */
147 REG_FIELDS(GSI_STATUS, gsi_status, 0x00012000 + 0x4000 * GSI_EE_AP);
149 static const u32 reg_ch_cmd_fmask[] = {
150 [CH_CHID] = GENMASK(7, 0),
151 /* Bits 8-23 reserved */
152 [CH_OPCODE] = GENMASK(31, 24),
155 REG_FIELDS(CH_CMD, ch_cmd, 0x00012008 + 0x4000 * GSI_EE_AP);
157 static const u32 reg_ev_ch_cmd_fmask[] = {
158 [EV_CHID] = GENMASK(7, 0),
159 /* Bits 8-23 reserved */
160 [EV_OPCODE] = GENMASK(31, 24),
163 REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00012010 + 0x4000 * GSI_EE_AP);
165 static const u32 reg_generic_cmd_fmask[] = {
166 [GENERIC_OPCODE] = GENMASK(4, 0),
167 [GENERIC_CHID] = GENMASK(9, 5),
168 [GENERIC_EE] = GENMASK(13, 10),
169 /* Bits 14-23 reserved */
170 [GENERIC_PARAMS] = GENMASK(31, 24),
173 REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00012018 + 0x4000 * GSI_EE_AP);
175 static const u32 reg_hw_param_2_fmask[] = {
176 [IRAM_SIZE] = GENMASK(2, 0),
177 [NUM_CH_PER_EE] = GENMASK(7, 3),
178 [NUM_EV_PER_EE] = GENMASK(12, 8),
179 [GSI_CH_PEND_TRANSLATE] = BIT(13),
180 [GSI_CH_FULL_LOGIC] = BIT(14),
181 [GSI_USE_SDMA] = BIT(15),
182 [GSI_SDMA_N_INT] = GENMASK(18, 16),
183 [GSI_SDMA_MAX_BURST] = GENMASK(26, 19),
184 [GSI_SDMA_N_IOVEC] = GENMASK(29, 27),
185 [GSI_USE_RD_WR_ENG] = BIT(30),
186 [GSI_USE_INTER_EE] = BIT(31),
189 REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00012040 + 0x4000 * GSI_EE_AP);
191 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
193 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
195 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
197 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
199 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
200 0x00012098 + 0x4000 * GSI_EE_AP);
202 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
203 0x0001209c + 0x4000 * GSI_EE_AP);
205 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
206 0x000120a0 + 0x4000 * GSI_EE_AP);
208 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
209 0x000120a4 + 0x4000 * GSI_EE_AP);
211 REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000120b0 + 0x4000 * GSI_EE_AP);
213 REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
214 0x000120b8 + 0x4000 * GSI_EE_AP);
216 REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
217 0x000120c0 + 0x4000 * GSI_EE_AP);
219 REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00012100 + 0x4000 * GSI_EE_AP);
221 REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00012108 + 0x4000 * GSI_EE_AP);
223 REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00012110 + 0x4000 * GSI_EE_AP);
225 REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x00012118 + 0x4000 * GSI_EE_AP);
227 REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00012120 + 0x4000 * GSI_EE_AP);
229 REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00012128 + 0x4000 * GSI_EE_AP);
231 static const u32 reg_cntxt_intset_fmask[] = {
233 /* Bits 1-31 reserved */
236 REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00012180 + 0x4000 * GSI_EE_AP);
238 REG_FIELDS(ERROR_LOG, error_log, 0x00012200 + 0x4000 * GSI_EE_AP);
240 REG(ERROR_LOG_CLR, error_log_clr, 0x00012210 + 0x4000 * GSI_EE_AP);
242 static const u32 reg_cntxt_scratch_0_fmask[] = {
243 [INTER_EE_RESULT] = GENMASK(2, 0),
244 /* Bits 3-4 reserved */
245 [GENERIC_EE_RESULT] = GENMASK(7, 5),
246 /* Bits 8-31 reserved */
249 REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00012400 + 0x4000 * GSI_EE_AP);
251 static const struct reg *reg_array[] = {
252 [INTER_EE_SRC_CH_IRQ_MSK] = ®_inter_ee_src_ch_irq_msk,
253 [INTER_EE_SRC_EV_CH_IRQ_MSK] = ®_inter_ee_src_ev_ch_irq_msk,
254 [CH_C_CNTXT_0] = ®_ch_c_cntxt_0,
255 [CH_C_CNTXT_1] = ®_ch_c_cntxt_1,
256 [CH_C_CNTXT_2] = ®_ch_c_cntxt_2,
257 [CH_C_CNTXT_3] = ®_ch_c_cntxt_3,
258 [CH_C_QOS] = ®_ch_c_qos,
259 [CH_C_SCRATCH_0] = ®_ch_c_scratch_0,
260 [CH_C_SCRATCH_1] = ®_ch_c_scratch_1,
261 [CH_C_SCRATCH_2] = ®_ch_c_scratch_2,
262 [CH_C_SCRATCH_3] = ®_ch_c_scratch_3,
263 [EV_CH_E_CNTXT_0] = ®_ev_ch_e_cntxt_0,
264 [EV_CH_E_CNTXT_1] = ®_ev_ch_e_cntxt_1,
265 [EV_CH_E_CNTXT_2] = ®_ev_ch_e_cntxt_2,
266 [EV_CH_E_CNTXT_3] = ®_ev_ch_e_cntxt_3,
267 [EV_CH_E_CNTXT_4] = ®_ev_ch_e_cntxt_4,
268 [EV_CH_E_CNTXT_8] = ®_ev_ch_e_cntxt_8,
269 [EV_CH_E_CNTXT_9] = ®_ev_ch_e_cntxt_9,
270 [EV_CH_E_CNTXT_10] = ®_ev_ch_e_cntxt_10,
271 [EV_CH_E_CNTXT_11] = ®_ev_ch_e_cntxt_11,
272 [EV_CH_E_CNTXT_12] = ®_ev_ch_e_cntxt_12,
273 [EV_CH_E_CNTXT_13] = ®_ev_ch_e_cntxt_13,
274 [EV_CH_E_SCRATCH_0] = ®_ev_ch_e_scratch_0,
275 [EV_CH_E_SCRATCH_1] = ®_ev_ch_e_scratch_1,
276 [CH_C_DOORBELL_0] = ®_ch_c_doorbell_0,
277 [EV_CH_E_DOORBELL_0] = ®_ev_ch_e_doorbell_0,
278 [GSI_STATUS] = ®_gsi_status,
279 [CH_CMD] = ®_ch_cmd,
280 [EV_CH_CMD] = ®_ev_ch_cmd,
281 [GENERIC_CMD] = ®_generic_cmd,
282 [HW_PARAM_2] = ®_hw_param_2,
283 [CNTXT_TYPE_IRQ] = ®_cntxt_type_irq,
284 [CNTXT_TYPE_IRQ_MSK] = ®_cntxt_type_irq_msk,
285 [CNTXT_SRC_CH_IRQ] = ®_cntxt_src_ch_irq,
286 [CNTXT_SRC_EV_CH_IRQ] = ®_cntxt_src_ev_ch_irq,
287 [CNTXT_SRC_CH_IRQ_MSK] = ®_cntxt_src_ch_irq_msk,
288 [CNTXT_SRC_EV_CH_IRQ_MSK] = ®_cntxt_src_ev_ch_irq_msk,
289 [CNTXT_SRC_CH_IRQ_CLR] = ®_cntxt_src_ch_irq_clr,
290 [CNTXT_SRC_EV_CH_IRQ_CLR] = ®_cntxt_src_ev_ch_irq_clr,
291 [CNTXT_SRC_IEOB_IRQ] = ®_cntxt_src_ieob_irq,
292 [CNTXT_SRC_IEOB_IRQ_MSK] = ®_cntxt_src_ieob_irq_msk,
293 [CNTXT_SRC_IEOB_IRQ_CLR] = ®_cntxt_src_ieob_irq_clr,
294 [CNTXT_GLOB_IRQ_STTS] = ®_cntxt_glob_irq_stts,
295 [CNTXT_GLOB_IRQ_EN] = ®_cntxt_glob_irq_en,
296 [CNTXT_GLOB_IRQ_CLR] = ®_cntxt_glob_irq_clr,
297 [CNTXT_GSI_IRQ_STTS] = ®_cntxt_gsi_irq_stts,
298 [CNTXT_GSI_IRQ_EN] = ®_cntxt_gsi_irq_en,
299 [CNTXT_GSI_IRQ_CLR] = ®_cntxt_gsi_irq_clr,
300 [CNTXT_INTSET] = ®_cntxt_intset,
301 [ERROR_LOG] = ®_error_log,
302 [ERROR_LOG_CLR] = ®_error_log_clr,
303 [CNTXT_SCRATCH_0] = ®_cntxt_scratch_0,
306 const struct regs gsi_regs_v4_11 = {
307 .reg_count = ARRAY_SIZE(reg_array),