drivers/net/igb/igb_ethtool.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for igb */
  29
  30 #include <linux/vmalloc.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/pci.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/if_ether.h>
  36 #include <linux/ethtool.h>
  37
  38 #include "igb.h"
  39
  40 enum {NETDEV_STATS, IGB_STATS};
  41
  42 struct igb_stats {
  43         char stat_string[ETH_GSTRING_LEN];
  44         int type;
  45         int sizeof_stat;
  46         int stat_offset;
  47 };
  48
  49 #define IGB_STAT(m)             IGB_STATS, \
  50                                 FIELD_SIZEOF(struct igb_adapter, m), \
  51                                 offsetof(struct igb_adapter, m)
  52 #define IGB_NETDEV_STAT(m)      NETDEV_STATS, \
  53                                 FIELD_SIZEOF(struct net_device, m), \
  54                                 offsetof(struct net_device, m)
  55
  56 static const struct igb_stats igb_gstrings_stats[] = {
  57         { "rx_packets", IGB_STAT(stats.gprc) },
  58         { "tx_packets", IGB_STAT(stats.gptc) },
  59         { "rx_bytes", IGB_STAT(stats.gorc) },
  60         { "tx_bytes", IGB_STAT(stats.gotc) },
  61         { "rx_broadcast", IGB_STAT(stats.bprc) },
  62         { "tx_broadcast", IGB_STAT(stats.bptc) },
  63         { "rx_multicast", IGB_STAT(stats.mprc) },
  64         { "tx_multicast", IGB_STAT(stats.mptc) },
  65         { "rx_errors", IGB_NETDEV_STAT(stats.rx_errors) },
  66         { "tx_errors", IGB_NETDEV_STAT(stats.tx_errors) },
  67         { "tx_dropped", IGB_NETDEV_STAT(stats.tx_dropped) },
  68         { "multicast", IGB_STAT(stats.mprc) },
  69         { "collisions", IGB_STAT(stats.colc) },
  70         { "rx_length_errors", IGB_NETDEV_STAT(stats.rx_length_errors) },
  71         { "rx_over_errors", IGB_NETDEV_STAT(stats.rx_over_errors) },
  72         { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
  73         { "rx_frame_errors", IGB_NETDEV_STAT(stats.rx_frame_errors) },
  74         { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
  75         { "rx_queue_drop_packet_count", IGB_NETDEV_STAT(stats.rx_fifo_errors) },
  76         { "rx_missed_errors", IGB_STAT(stats.mpc) },
  77         { "tx_aborted_errors", IGB_STAT(stats.ecol) },
  78         { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
  79         { "tx_fifo_errors", IGB_NETDEV_STAT(stats.tx_fifo_errors) },
  80         { "tx_heartbeat_errors", IGB_NETDEV_STAT(stats.tx_heartbeat_errors) },
  81         { "tx_window_errors", IGB_STAT(stats.latecol) },
  82         { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
  83         { "tx_deferred_ok", IGB_STAT(stats.dc) },
  84         { "tx_single_coll_ok", IGB_STAT(stats.scc) },
  85         { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
  86         { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
  87         { "tx_restart_queue", IGB_STAT(restart_queue) },
  88         { "rx_long_length_errors", IGB_STAT(stats.roc) },
  89         { "rx_short_length_errors", IGB_STAT(stats.ruc) },
  90         { "rx_align_errors", IGB_STAT(stats.algnerrc) },
  91         { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
  92         { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
  93         { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
  94         { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
  95         { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
  96         { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
  97         { "rx_long_byte_count", IGB_STAT(stats.gorc) },
  98         { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
  99         { "tx_dma_out_of_sync", IGB_STAT(stats.doosync) },
 100         { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
 101         { "tx_smbus", IGB_STAT(stats.mgptc) },
 102         { "rx_smbus", IGB_STAT(stats.mgprc) },
 103         { "dropped_smbus", IGB_STAT(stats.mgpdc) },
 104 };
 105
 106 #define IGB_QUEUE_STATS_LEN \
 107         (((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues)* \
 108           (sizeof(struct igb_rx_queue_stats) / sizeof(u64))) + \
 109          ((((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues) * \
 110           (sizeof(struct igb_tx_queue_stats) / sizeof(u64))))
 111 #define IGB_GLOBAL_STATS_LEN    \
 112         sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
 113 #define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
 114 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
 115         "Register test  (offline)", "Eeprom test    (offline)",
 116         "Interrupt test (offline)", "Loopback test  (offline)",
 117         "Link test   (on/offline)"
 118 };
 119 #define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
 120
 121 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 122 {
 123         struct igb_adapter *adapter = netdev_priv(netdev);
 124         struct e1000_hw *hw = &adapter->hw;
 125
 126         if (hw->phy.media_type == e1000_media_type_copper) {
 127
 128                 ecmd->supported = (SUPPORTED_10baseT_Half |
 129                                    SUPPORTED_10baseT_Full |
 130                                    SUPPORTED_100baseT_Half |
 131                                    SUPPORTED_100baseT_Full |
 132                                    SUPPORTED_1000baseT_Full|
 133                                    SUPPORTED_Autoneg |
 134                                    SUPPORTED_TP);
 135                 ecmd->advertising = ADVERTISED_TP;
 136
 137                 if (hw->mac.autoneg == 1) {
 138                         ecmd->advertising |= ADVERTISED_Autoneg;
 139                         /* the e1000 autoneg seems to match ethtool nicely */
 140                         ecmd->advertising |= hw->phy.autoneg_advertised;
 141                 }
 142
 143                 ecmd->port = PORT_TP;
 144                 ecmd->phy_address = hw->phy.addr;
 145         } else {
 146                 ecmd->supported   = (SUPPORTED_1000baseT_Full |
 147                                      SUPPORTED_FIBRE |
 148                                      SUPPORTED_Autoneg);
 149
 150                 ecmd->advertising = (ADVERTISED_1000baseT_Full |
 151                                      ADVERTISED_FIBRE |
 152                                      ADVERTISED_Autoneg);
 153
 154                 ecmd->port = PORT_FIBRE;
 155         }
 156
 157         ecmd->transceiver = XCVR_INTERNAL;
 158
 159         if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
 160
 161                 adapter->hw.mac.ops.get_speed_and_duplex(hw,
 162                                         &adapter->link_speed,
 163                                         &adapter->link_duplex);
 164                 ecmd->speed = adapter->link_speed;
 165
 166                 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
 167                  *          and HALF_DUPLEX != DUPLEX_HALF */
 168
 169                 if (adapter->link_duplex == FULL_DUPLEX)
 170                         ecmd->duplex = DUPLEX_FULL;
 171                 else
 172                         ecmd->duplex = DUPLEX_HALF;
 173         } else {
 174                 ecmd->speed = -1;
 175                 ecmd->duplex = -1;
 176         }
 177
 178         ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
 179         return 0;
 180 }
 181
 182 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 183 {
 184         struct igb_adapter *adapter = netdev_priv(netdev);
 185         struct e1000_hw *hw = &adapter->hw;
 186
 187         /* When SoL/IDER sessions are active, autoneg/speed/duplex
 188          * cannot be changed */
 189         if (igb_check_reset_block(hw)) {
 190                 dev_err(&adapter->pdev->dev, "Cannot change link "
 191                         "characteristics when SoL/IDER is active.\n");
 192                 return -EINVAL;
 193         }
 194
 195         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 196                 msleep(1);
 197
 198         if (ecmd->autoneg == AUTONEG_ENABLE) {
 199                 hw->mac.autoneg = 1;
 200                 hw->phy.autoneg_advertised = ecmd->advertising |
 201                                              ADVERTISED_TP |
 202                                              ADVERTISED_Autoneg;
 203                 ecmd->advertising = hw->phy.autoneg_advertised;
 204                 if (adapter->fc_autoneg)
 205                         hw->fc.requested_mode = e1000_fc_default;
 206         } else {
 207                 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
 208                         clear_bit(__IGB_RESETTING, &adapter->state);
 209                         return -EINVAL;
 210                 }
 211         }
 212
 213         /* reset the link */
 214         if (netif_running(adapter->netdev)) {
 215                 igb_down(adapter);
 216                 igb_up(adapter);
 217         } else
 218                 igb_reset(adapter);
 219
 220         clear_bit(__IGB_RESETTING, &adapter->state);
 221         return 0;
 222 }
 223
 224 static void igb_get_pauseparam(struct net_device *netdev,
 225                                struct ethtool_pauseparam *pause)
 226 {
 227         struct igb_adapter *adapter = netdev_priv(netdev);
 228         struct e1000_hw *hw = &adapter->hw;
 229
 230         pause->autoneg =
 231                 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
 232
 233         if (hw->fc.current_mode == e1000_fc_rx_pause)
 234                 pause->rx_pause = 1;
 235         else if (hw->fc.current_mode == e1000_fc_tx_pause)
 236                 pause->tx_pause = 1;
 237         else if (hw->fc.current_mode == e1000_fc_full) {
 238                 pause->rx_pause = 1;
 239                 pause->tx_pause = 1;
 240         }
 241 }
 242
 243 static int igb_set_pauseparam(struct net_device *netdev,
 244                               struct ethtool_pauseparam *pause)
 245 {
 246         struct igb_adapter *adapter = netdev_priv(netdev);
 247         struct e1000_hw *hw = &adapter->hw;
 248         int retval = 0;
 249
 250         adapter->fc_autoneg = pause->autoneg;
 251
 252         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 253                 msleep(1);
 254
 255         if (adapter->fc_autoneg == AUTONEG_ENABLE) {
 256                 hw->fc.requested_mode = e1000_fc_default;
 257                 if (netif_running(adapter->netdev)) {
 258                         igb_down(adapter);
 259                         igb_up(adapter);
 260                 } else
 261                         igb_reset(adapter);
 262         } else {
 263                 if (pause->rx_pause && pause->tx_pause)
 264                         hw->fc.requested_mode = e1000_fc_full;
 265                 else if (pause->rx_pause && !pause->tx_pause)
 266                         hw->fc.requested_mode = e1000_fc_rx_pause;
 267                 else if (!pause->rx_pause && pause->tx_pause)
 268                         hw->fc.requested_mode = e1000_fc_tx_pause;
 269                 else if (!pause->rx_pause && !pause->tx_pause)
 270                         hw->fc.requested_mode = e1000_fc_none;
 271
 272                 hw->fc.current_mode = hw->fc.requested_mode;
 273
 274                 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
 275                           igb_force_mac_fc(hw) : igb_setup_link(hw));
 276         }
 277
 278         clear_bit(__IGB_RESETTING, &adapter->state);
 279         return retval;
 280 }
 281
 282 static u32 igb_get_rx_csum(struct net_device *netdev)
 283 {
 284         struct igb_adapter *adapter = netdev_priv(netdev);
 285         return !(adapter->flags & IGB_FLAG_RX_CSUM_DISABLED);
 286 }
 287
 288 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
 289 {
 290         struct igb_adapter *adapter = netdev_priv(netdev);
 291
 292         if (data)
 293                 adapter->flags &= ~IGB_FLAG_RX_CSUM_DISABLED;
 294         else
 295                 adapter->flags |= IGB_FLAG_RX_CSUM_DISABLED;
 296
 297         return 0;
 298 }
 299
 300 static u32 igb_get_tx_csum(struct net_device *netdev)
 301 {
 302         return (netdev->features & NETIF_F_IP_CSUM) != 0;
 303 }
 304
 305 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
 306 {
 307         struct igb_adapter *adapter = netdev_priv(netdev);
 308
 309         if (data) {
 310                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 311                 if (adapter->hw.mac.type == e1000_82576)
 312                         netdev->features |= NETIF_F_SCTP_CSUM;
 313         } else {
 314                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
 315                                       NETIF_F_SCTP_CSUM);
 316         }
 317
 318         return 0;
 319 }
 320
 321 static int igb_set_tso(struct net_device *netdev, u32 data)
 322 {
 323         struct igb_adapter *adapter = netdev_priv(netdev);
 324
 325         if (data) {
 326                 netdev->features |= NETIF_F_TSO;
 327                 netdev->features |= NETIF_F_TSO6;
 328         } else {
 329                 netdev->features &= ~NETIF_F_TSO;
 330                 netdev->features &= ~NETIF_F_TSO6;
 331         }
 332
 333         dev_info(&adapter->pdev->dev, "TSO is %s\n",
 334                  data ? "Enabled" : "Disabled");
 335         return 0;
 336 }
 337
 338 static u32 igb_get_msglevel(struct net_device *netdev)
 339 {
 340         struct igb_adapter *adapter = netdev_priv(netdev);
 341         return adapter->msg_enable;
 342 }
 343
 344 static void igb_set_msglevel(struct net_device *netdev, u32 data)
 345 {
 346         struct igb_adapter *adapter = netdev_priv(netdev);
 347         adapter->msg_enable = data;
 348 }
 349
 350 static int igb_get_regs_len(struct net_device *netdev)
 351 {
 352 #define IGB_REGS_LEN 551
 353         return IGB_REGS_LEN * sizeof(u32);
 354 }
 355
 356 static void igb_get_regs(struct net_device *netdev,
 357                          struct ethtool_regs *regs, void *p)
 358 {
 359         struct igb_adapter *adapter = netdev_priv(netdev);
 360         struct e1000_hw *hw = &adapter->hw;
 361         u32 *regs_buff = p;
 362         u8 i;
 363
 364         memset(p, 0, IGB_REGS_LEN * sizeof(u32));
 365
 366         regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
 367
 368         /* General Registers */
 369         regs_buff[0] = rd32(E1000_CTRL);
 370         regs_buff[1] = rd32(E1000_STATUS);
 371         regs_buff[2] = rd32(E1000_CTRL_EXT);
 372         regs_buff[3] = rd32(E1000_MDIC);
 373         regs_buff[4] = rd32(E1000_SCTL);
 374         regs_buff[5] = rd32(E1000_CONNSW);
 375         regs_buff[6] = rd32(E1000_VET);
 376         regs_buff[7] = rd32(E1000_LEDCTL);
 377         regs_buff[8] = rd32(E1000_PBA);
 378         regs_buff[9] = rd32(E1000_PBS);
 379         regs_buff[10] = rd32(E1000_FRTIMER);
 380         regs_buff[11] = rd32(E1000_TCPTIMER);
 381
 382         /* NVM Register */
 383         regs_buff[12] = rd32(E1000_EECD);
 384
 385         /* Interrupt */
 386         /* Reading EICS for EICR because they read the
 387          * same but EICS does not clear on read */
 388         regs_buff[13] = rd32(E1000_EICS);
 389         regs_buff[14] = rd32(E1000_EICS);
 390         regs_buff[15] = rd32(E1000_EIMS);
 391         regs_buff[16] = rd32(E1000_EIMC);
 392         regs_buff[17] = rd32(E1000_EIAC);
 393         regs_buff[18] = rd32(E1000_EIAM);
 394         /* Reading ICS for ICR because they read the
 395          * same but ICS does not clear on read */
 396         regs_buff[19] = rd32(E1000_ICS);
 397         regs_buff[20] = rd32(E1000_ICS);
 398         regs_buff[21] = rd32(E1000_IMS);
 399         regs_buff[22] = rd32(E1000_IMC);
 400         regs_buff[23] = rd32(E1000_IAC);
 401         regs_buff[24] = rd32(E1000_IAM);
 402         regs_buff[25] = rd32(E1000_IMIRVP);
 403
 404         /* Flow Control */
 405         regs_buff[26] = rd32(E1000_FCAL);
 406         regs_buff[27] = rd32(E1000_FCAH);
 407         regs_buff[28] = rd32(E1000_FCTTV);
 408         regs_buff[29] = rd32(E1000_FCRTL);
 409         regs_buff[30] = rd32(E1000_FCRTH);
 410         regs_buff[31] = rd32(E1000_FCRTV);
 411
 412         /* Receive */
 413         regs_buff[32] = rd32(E1000_RCTL);
 414         regs_buff[33] = rd32(E1000_RXCSUM);
 415         regs_buff[34] = rd32(E1000_RLPML);
 416         regs_buff[35] = rd32(E1000_RFCTL);
 417         regs_buff[36] = rd32(E1000_MRQC);
 418         regs_buff[37] = rd32(E1000_VT_CTL);
 419
 420         /* Transmit */
 421         regs_buff[38] = rd32(E1000_TCTL);
 422         regs_buff[39] = rd32(E1000_TCTL_EXT);
 423         regs_buff[40] = rd32(E1000_TIPG);
 424         regs_buff[41] = rd32(E1000_DTXCTL);
 425
 426         /* Wake Up */
 427         regs_buff[42] = rd32(E1000_WUC);
 428         regs_buff[43] = rd32(E1000_WUFC);
 429         regs_buff[44] = rd32(E1000_WUS);
 430         regs_buff[45] = rd32(E1000_IPAV);
 431         regs_buff[46] = rd32(E1000_WUPL);
 432
 433         /* MAC */
 434         regs_buff[47] = rd32(E1000_PCS_CFG0);
 435         regs_buff[48] = rd32(E1000_PCS_LCTL);
 436         regs_buff[49] = rd32(E1000_PCS_LSTAT);
 437         regs_buff[50] = rd32(E1000_PCS_ANADV);
 438         regs_buff[51] = rd32(E1000_PCS_LPAB);
 439         regs_buff[52] = rd32(E1000_PCS_NPTX);
 440         regs_buff[53] = rd32(E1000_PCS_LPABNP);
 441
 442         /* Statistics */
 443         regs_buff[54] = adapter->stats.crcerrs;
 444         regs_buff[55] = adapter->stats.algnerrc;
 445         regs_buff[56] = adapter->stats.symerrs;
 446         regs_buff[57] = adapter->stats.rxerrc;
 447         regs_buff[58] = adapter->stats.mpc;
 448         regs_buff[59] = adapter->stats.scc;
 449         regs_buff[60] = adapter->stats.ecol;
 450         regs_buff[61] = adapter->stats.mcc;
 451         regs_buff[62] = adapter->stats.latecol;
 452         regs_buff[63] = adapter->stats.colc;
 453         regs_buff[64] = adapter->stats.dc;
 454         regs_buff[65] = adapter->stats.tncrs;
 455         regs_buff[66] = adapter->stats.sec;
 456         regs_buff[67] = adapter->stats.htdpmc;
 457         regs_buff[68] = adapter->stats.rlec;
 458         regs_buff[69] = adapter->stats.xonrxc;
 459         regs_buff[70] = adapter->stats.xontxc;
 460         regs_buff[71] = adapter->stats.xoffrxc;
 461         regs_buff[72] = adapter->stats.xofftxc;
 462         regs_buff[73] = adapter->stats.fcruc;
 463         regs_buff[74] = adapter->stats.prc64;
 464         regs_buff[75] = adapter->stats.prc127;
 465         regs_buff[76] = adapter->stats.prc255;
 466         regs_buff[77] = adapter->stats.prc511;
 467         regs_buff[78] = adapter->stats.prc1023;
 468         regs_buff[79] = adapter->stats.prc1522;
 469         regs_buff[80] = adapter->stats.gprc;
 470         regs_buff[81] = adapter->stats.bprc;
 471         regs_buff[82] = adapter->stats.mprc;
 472         regs_buff[83] = adapter->stats.gptc;
 473         regs_buff[84] = adapter->stats.gorc;
 474         regs_buff[86] = adapter->stats.gotc;
 475         regs_buff[88] = adapter->stats.rnbc;
 476         regs_buff[89] = adapter->stats.ruc;
 477         regs_buff[90] = adapter->stats.rfc;
 478         regs_buff[91] = adapter->stats.roc;
 479         regs_buff[92] = adapter->stats.rjc;
 480         regs_buff[93] = adapter->stats.mgprc;
 481         regs_buff[94] = adapter->stats.mgpdc;
 482         regs_buff[95] = adapter->stats.mgptc;
 483         regs_buff[96] = adapter->stats.tor;
 484         regs_buff[98] = adapter->stats.tot;
 485         regs_buff[100] = adapter->stats.tpr;
 486         regs_buff[101] = adapter->stats.tpt;
 487         regs_buff[102] = adapter->stats.ptc64;
 488         regs_buff[103] = adapter->stats.ptc127;
 489         regs_buff[104] = adapter->stats.ptc255;
 490         regs_buff[105] = adapter->stats.ptc511;
 491         regs_buff[106] = adapter->stats.ptc1023;
 492         regs_buff[107] = adapter->stats.ptc1522;
 493         regs_buff[108] = adapter->stats.mptc;
 494         regs_buff[109] = adapter->stats.bptc;
 495         regs_buff[110] = adapter->stats.tsctc;
 496         regs_buff[111] = adapter->stats.iac;
 497         regs_buff[112] = adapter->stats.rpthc;
 498         regs_buff[113] = adapter->stats.hgptc;
 499         regs_buff[114] = adapter->stats.hgorc;
 500         regs_buff[116] = adapter->stats.hgotc;
 501         regs_buff[118] = adapter->stats.lenerrs;
 502         regs_buff[119] = adapter->stats.scvpc;
 503         regs_buff[120] = adapter->stats.hrmpc;
 504
 505         /* These should probably be added to e1000_regs.h instead */
 506         #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
 507         #define E1000_IP4AT_REG(_i)   (0x05840 + ((_i) * 8))
 508         #define E1000_IP6AT_REG(_i)   (0x05880 + ((_i) * 4))
 509         #define E1000_WUPM_REG(_i)    (0x05A00 + ((_i) * 4))
 510         #define E1000_FFMT_REG(_i)    (0x09000 + ((_i) * 8))
 511         #define E1000_FFVT_REG(_i)    (0x09800 + ((_i) * 8))
 512         #define E1000_FFLT_REG(_i)    (0x05F00 + ((_i) * 8))
 513
 514         for (i = 0; i < 4; i++)
 515                 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
 516         for (i = 0; i < 4; i++)
 517                 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
 518         for (i = 0; i < 4; i++)
 519                 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
 520         for (i = 0; i < 4; i++)
 521                 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
 522         for (i = 0; i < 4; i++)
 523                 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
 524         for (i = 0; i < 4; i++)
 525                 regs_buff[141 + i] = rd32(E1000_RDH(i));
 526         for (i = 0; i < 4; i++)
 527                 regs_buff[145 + i] = rd32(E1000_RDT(i));
 528         for (i = 0; i < 4; i++)
 529                 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
 530
 531         for (i = 0; i < 10; i++)
 532                 regs_buff[153 + i] = rd32(E1000_EITR(i));
 533         for (i = 0; i < 8; i++)
 534                 regs_buff[163 + i] = rd32(E1000_IMIR(i));
 535         for (i = 0; i < 8; i++)
 536                 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
 537         for (i = 0; i < 16; i++)
 538                 regs_buff[179 + i] = rd32(E1000_RAL(i));
 539         for (i = 0; i < 16; i++)
 540                 regs_buff[195 + i] = rd32(E1000_RAH(i));
 541
 542         for (i = 0; i < 4; i++)
 543                 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
 544         for (i = 0; i < 4; i++)
 545                 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
 546         for (i = 0; i < 4; i++)
 547                 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
 548         for (i = 0; i < 4; i++)
 549                 regs_buff[223 + i] = rd32(E1000_TDH(i));
 550         for (i = 0; i < 4; i++)
 551                 regs_buff[227 + i] = rd32(E1000_TDT(i));
 552         for (i = 0; i < 4; i++)
 553                 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
 554         for (i = 0; i < 4; i++)
 555                 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
 556         for (i = 0; i < 4; i++)
 557                 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
 558         for (i = 0; i < 4; i++)
 559                 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
 560
 561         for (i = 0; i < 4; i++)
 562                 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
 563         for (i = 0; i < 4; i++)
 564                 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
 565         for (i = 0; i < 32; i++)
 566                 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
 567         for (i = 0; i < 128; i++)
 568                 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
 569         for (i = 0; i < 128; i++)
 570                 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
 571         for (i = 0; i < 4; i++)
 572                 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
 573
 574         regs_buff[547] = rd32(E1000_TDFH);
 575         regs_buff[548] = rd32(E1000_TDFT);
 576         regs_buff[549] = rd32(E1000_TDFHS);
 577         regs_buff[550] = rd32(E1000_TDFPC);
 578
 579 }
 580
 581 static int igb_get_eeprom_len(struct net_device *netdev)
 582 {
 583         struct igb_adapter *adapter = netdev_priv(netdev);
 584         return adapter->hw.nvm.word_size * 2;
 585 }
 586
 587 static int igb_get_eeprom(struct net_device *netdev,
 588                           struct ethtool_eeprom *eeprom, u8 *bytes)
 589 {
 590         struct igb_adapter *adapter = netdev_priv(netdev);
 591         struct e1000_hw *hw = &adapter->hw;
 592         u16 *eeprom_buff;
 593         int first_word, last_word;
 594         int ret_val = 0;
 595         u16 i;
 596
 597         if (eeprom->len == 0)
 598                 return -EINVAL;
 599
 600         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 601
 602         first_word = eeprom->offset >> 1;
 603         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 604
 605         eeprom_buff = kmalloc(sizeof(u16) *
 606                         (last_word - first_word + 1), GFP_KERNEL);
 607         if (!eeprom_buff)
 608                 return -ENOMEM;
 609
 610         if (hw->nvm.type == e1000_nvm_eeprom_spi)
 611                 ret_val = hw->nvm.ops.read(hw, first_word,
 612                                             last_word - first_word + 1,
 613                                             eeprom_buff);
 614         else {
 615                 for (i = 0; i < last_word - first_word + 1; i++) {
 616                         ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
 617                                                     &eeprom_buff[i]);
 618                         if (ret_val)
 619                                 break;
 620                 }
 621         }
 622
 623         /* Device's eeprom is always little-endian, word addressable */
 624         for (i = 0; i < last_word - first_word + 1; i++)
 625                 le16_to_cpus(&eeprom_buff[i]);
 626
 627         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
 628                         eeprom->len);
 629         kfree(eeprom_buff);
 630
 631         return ret_val;
 632 }
 633
 634 static int igb_set_eeprom(struct net_device *netdev,
 635                           struct ethtool_eeprom *eeprom, u8 *bytes)
 636 {
 637         struct igb_adapter *adapter = netdev_priv(netdev);
 638         struct e1000_hw *hw = &adapter->hw;
 639         u16 *eeprom_buff;
 640         void *ptr;
 641         int max_len, first_word, last_word, ret_val = 0;
 642         u16 i;
 643
 644         if (eeprom->len == 0)
 645                 return -EOPNOTSUPP;
 646
 647         if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
 648                 return -EFAULT;
 649
 650         max_len = hw->nvm.word_size * 2;
 651
 652         first_word = eeprom->offset >> 1;
 653         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 654         eeprom_buff = kmalloc(max_len, GFP_KERNEL);
 655         if (!eeprom_buff)
 656                 return -ENOMEM;
 657
 658         ptr = (void *)eeprom_buff;
 659
 660         if (eeprom->offset & 1) {
 661                 /* need read/modify/write of first changed EEPROM word */
 662                 /* only the second byte of the word is being modified */
 663                 ret_val = hw->nvm.ops.read(hw, first_word, 1,
 664                                             &eeprom_buff[0]);
 665                 ptr++;
 666         }
 667         if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
 668                 /* need read/modify/write of last changed EEPROM word */
 669                 /* only the first byte of the word is being modified */
 670                 ret_val = hw->nvm.ops.read(hw, last_word, 1,
 671                                    &eeprom_buff[last_word - first_word]);
 672         }
 673
 674         /* Device's eeprom is always little-endian, word addressable */
 675         for (i = 0; i < last_word - first_word + 1; i++)
 676                 le16_to_cpus(&eeprom_buff[i]);
 677
 678         memcpy(ptr, bytes, eeprom->len);
 679
 680         for (i = 0; i < last_word - first_word + 1; i++)
 681                 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
 682
 683         ret_val = hw->nvm.ops.write(hw, first_word,
 684                                      last_word - first_word + 1, eeprom_buff);
 685
 686         /* Update the checksum over the first part of the EEPROM if needed
 687          * and flush shadow RAM for 82573 controllers */
 688         if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
 689                 igb_update_nvm_checksum(hw);
 690
 691         kfree(eeprom_buff);
 692         return ret_val;
 693 }
 694
 695 static void igb_get_drvinfo(struct net_device *netdev,
 696                             struct ethtool_drvinfo *drvinfo)
 697 {
 698         struct igb_adapter *adapter = netdev_priv(netdev);
 699         char firmware_version[32];
 700         u16 eeprom_data;
 701
 702         strncpy(drvinfo->driver,  igb_driver_name, 32);
 703         strncpy(drvinfo->version, igb_driver_version, 32);
 704
 705         /* EEPROM image version # is reported as firmware version # for
 706          * 82575 controllers */
 707         adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
 708         sprintf(firmware_version, "%d.%d-%d",
 709                 (eeprom_data & 0xF000) >> 12,
 710                 (eeprom_data & 0x0FF0) >> 4,
 711                 eeprom_data & 0x000F);
 712
 713         strncpy(drvinfo->fw_version, firmware_version, 32);
 714         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
 715         drvinfo->n_stats = IGB_STATS_LEN;
 716         drvinfo->testinfo_len = IGB_TEST_LEN;
 717         drvinfo->regdump_len = igb_get_regs_len(netdev);
 718         drvinfo->eedump_len = igb_get_eeprom_len(netdev);
 719 }
 720
 721 static void igb_get_ringparam(struct net_device *netdev,
 722                               struct ethtool_ringparam *ring)
 723 {
 724         struct igb_adapter *adapter = netdev_priv(netdev);
 725
 726         ring->rx_max_pending = IGB_MAX_RXD;
 727         ring->tx_max_pending = IGB_MAX_TXD;
 728         ring->rx_mini_max_pending = 0;
 729         ring->rx_jumbo_max_pending = 0;
 730         ring->rx_pending = adapter->rx_ring_count;
 731         ring->tx_pending = adapter->tx_ring_count;
 732         ring->rx_mini_pending = 0;
 733         ring->rx_jumbo_pending = 0;
 734 }
 735
 736 static int igb_set_ringparam(struct net_device *netdev,
 737                              struct ethtool_ringparam *ring)
 738 {
 739         struct igb_adapter *adapter = netdev_priv(netdev);
 740         struct igb_ring *temp_ring;
 741         int i, err = 0;
 742         u32 new_rx_count, new_tx_count;
 743
 744         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 745                 return -EINVAL;
 746
 747         new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
 748         new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
 749         new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
 750
 751         new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
 752         new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
 753         new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
 754
 755         if ((new_tx_count == adapter->tx_ring_count) &&
 756             (new_rx_count == adapter->rx_ring_count)) {
 757                 /* nothing to do */
 758                 return 0;
 759         }
 760
 761         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 762                 msleep(1);
 763
 764         if (!netif_running(adapter->netdev)) {
 765                 for (i = 0; i < adapter->num_tx_queues; i++)
 766                         adapter->tx_ring[i].count = new_tx_count;
 767                 for (i = 0; i < adapter->num_rx_queues; i++)
 768                         adapter->rx_ring[i].count = new_rx_count;
 769                 adapter->tx_ring_count = new_tx_count;
 770                 adapter->rx_ring_count = new_rx_count;
 771                 goto clear_reset;
 772         }
 773
 774         if (adapter->num_tx_queues > adapter->num_rx_queues)
 775                 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
 776         else
 777                 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
 778
 779         if (!temp_ring) {
 780                 err = -ENOMEM;
 781                 goto clear_reset;
 782         }
 783
 784         igb_down(adapter);
 785
 786         /*
 787          * We can't just free everything and then setup again,
 788          * because the ISRs in MSI-X mode get passed pointers
 789          * to the tx and rx ring structs.
 790          */
 791         if (new_tx_count != adapter->tx_ring_count) {
 792                 memcpy(temp_ring, adapter->tx_ring,
 793                        adapter->num_tx_queues * sizeof(struct igb_ring));
 794
 795                 for (i = 0; i < adapter->num_tx_queues; i++) {
 796                         temp_ring[i].count = new_tx_count;
 797                         err = igb_setup_tx_resources(&temp_ring[i]);
 798                         if (err) {
 799                                 while (i) {
 800                                         i--;
 801                                         igb_free_tx_resources(&temp_ring[i]);
 802                                 }
 803                                 goto err_setup;
 804                         }
 805                 }
 806
 807                 for (i = 0; i < adapter->num_tx_queues; i++)
 808                         igb_free_tx_resources(&adapter->tx_ring[i]);
 809
 810                 memcpy(adapter->tx_ring, temp_ring,
 811                        adapter->num_tx_queues * sizeof(struct igb_ring));
 812
 813                 adapter->tx_ring_count = new_tx_count;
 814         }
 815
 816         if (new_rx_count != adapter->rx_ring->count) {
 817                 memcpy(temp_ring, adapter->rx_ring,
 818                        adapter->num_rx_queues * sizeof(struct igb_ring));
 819
 820                 for (i = 0; i < adapter->num_rx_queues; i++) {
 821                         temp_ring[i].count = new_rx_count;
 822                         err = igb_setup_rx_resources(&temp_ring[i]);
 823                         if (err) {
 824                                 while (i) {
 825                                         i--;
 826                                         igb_free_rx_resources(&temp_ring[i]);
 827                                 }
 828                                 goto err_setup;
 829                         }
 830
 831                 }
 832
 833                 for (i = 0; i < adapter->num_rx_queues; i++)
 834                         igb_free_rx_resources(&adapter->rx_ring[i]);
 835
 836                 memcpy(adapter->rx_ring, temp_ring,
 837                        adapter->num_rx_queues * sizeof(struct igb_ring));
 838
 839                 adapter->rx_ring_count = new_rx_count;
 840         }
 841 err_setup:
 842         igb_up(adapter);
 843         vfree(temp_ring);
 844 clear_reset:
 845         clear_bit(__IGB_RESETTING, &adapter->state);
 846         return err;
 847 }
 848
 849 /* ethtool register test data */
 850 struct igb_reg_test {
 851         u16 reg;
 852         u16 reg_offset;
 853         u16 array_len;
 854         u16 test_type;
 855         u32 mask;
 856         u32 write;
 857 };
 858
 859 /* In the hardware, registers are laid out either singly, in arrays
 860  * spaced 0x100 bytes apart, or in contiguous tables.  We assume
 861  * most tests take place on arrays or single registers (handled
 862  * as a single-element array) and special-case the tables.
 863  * Table tests are always pattern tests.
 864  *
 865  * We also make provision for some required setup steps by specifying
 866  * registers to be written without any read-back testing.
 867  */
 868
 869 #define PATTERN_TEST    1
 870 #define SET_READ_TEST   2
 871 #define WRITE_NO_TEST   3
 872 #define TABLE32_TEST    4
 873 #define TABLE64_TEST_LO 5
 874 #define TABLE64_TEST_HI 6
 875
 876 /* 82576 reg test */
 877 static struct igb_reg_test reg_test_82576[] = {
 878         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 879         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 880         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 881         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 882         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 883         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 884         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 885         { E1000_RDBAL(4),  0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 886         { E1000_RDBAH(4),  0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 887         { E1000_RDLEN(4),  0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 888         /* Enable all RX queues before testing. */
 889         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 890         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 891         /* RDH is read-only for 82576, only test RDT. */
 892         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 893         { E1000_RDT(4),    0x40, 12,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 894         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
 895         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, 0 },
 896         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 897         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 898         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 899         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 900         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 901         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 902         { E1000_TDBAL(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 903         { E1000_TDBAH(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 904         { E1000_TDLEN(4),  0x40, 12,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 905         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 906         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 907         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 908         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 909         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 910         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
 911         { E1000_RA2,       0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 912         { E1000_RA2,       0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
 913         { E1000_MTA,       0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 914         { 0, 0, 0, 0 }
 915 };
 916
 917 /* 82575 register test */
 918 static struct igb_reg_test reg_test_82575[] = {
 919         { E1000_FCAL,      0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 920         { E1000_FCAH,      0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 921         { E1000_FCT,       0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 922         { E1000_VET,       0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 923         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 924         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 925         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 926         /* Enable all four RX queues before testing. */
 927         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 928         /* RDH is read-only for 82575, only test RDT. */
 929         { E1000_RDT(0),    0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 930         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
 931         { E1000_FCRTH,     0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 932         { E1000_FCTTV,     0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 933         { E1000_TIPG,      0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 934         { E1000_TDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 935         { E1000_TDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 936         { E1000_TDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 937         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 938         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
 939         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
 940         { E1000_TCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 941         { E1000_TXCW,      0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
 942         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 943         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
 944         { E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 945         { 0, 0, 0, 0 }
 946 };
 947
 948 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
 949                              int reg, u32 mask, u32 write)
 950 {
 951         struct e1000_hw *hw = &adapter->hw;
 952         u32 pat, val;
 953         u32 _test[] =
 954                 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
 955         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
 956                 wr32(reg, (_test[pat] & write));
 957                 val = rd32(reg);
 958                 if (val != (_test[pat] & write & mask)) {
 959                         dev_err(&adapter->pdev->dev, "pattern test reg %04X "
 960                                 "failed: got 0x%08X expected 0x%08X\n",
 961                                 reg, val, (_test[pat] & write & mask));
 962                         *data = reg;
 963                         return 1;
 964                 }
 965         }
 966         return 0;
 967 }
 968
 969 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
 970                               int reg, u32 mask, u32 write)
 971 {
 972         struct e1000_hw *hw = &adapter->hw;
 973         u32 val;
 974         wr32(reg, write & mask);
 975         val = rd32(reg);
 976         if ((write & mask) != (val & mask)) {
 977                 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
 978                         " got 0x%08X expected 0x%08X\n", reg,
 979                         (val & mask), (write & mask));
 980                 *data = reg;
 981                 return 1;
 982         }
 983         return 0;
 984 }
 985
 986 #define REG_PATTERN_TEST(reg, mask, write) \
 987         do { \
 988                 if (reg_pattern_test(adapter, data, reg, mask, write)) \
 989                         return 1; \
 990         } while (0)
 991
 992 #define REG_SET_AND_CHECK(reg, mask, write) \
 993         do { \
 994                 if (reg_set_and_check(adapter, data, reg, mask, write)) \
 995                         return 1; \
 996         } while (0)
 997
 998 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
 999 {
1000         struct e1000_hw *hw = &adapter->hw;
1001         struct igb_reg_test *test;
1002         u32 value, before, after;
1003         u32 i, toggle;
1004
1005         toggle = 0x7FFFF3FF;
1006
1007         switch (adapter->hw.mac.type) {
1008         case e1000_82576:
1009                 test = reg_test_82576;
1010                 break;
1011         default:
1012                 test = reg_test_82575;
1013                 break;
1014         }
1015
1016         /* Because the status register is such a special case,
1017          * we handle it separately from the rest of the register
1018          * tests.  Some bits are read-only, some toggle, and some
1019          * are writable on newer MACs.
1020          */
1021         before = rd32(E1000_STATUS);
1022         value = (rd32(E1000_STATUS) & toggle);
1023         wr32(E1000_STATUS, toggle);
1024         after = rd32(E1000_STATUS) & toggle;
1025         if (value != after) {
1026                 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1027                         "got: 0x%08X expected: 0x%08X\n", after, value);
1028                 *data = 1;
1029                 return 1;
1030         }
1031         /* restore previous status */
1032         wr32(E1000_STATUS, before);
1033
1034         /* Perform the remainder of the register test, looping through
1035          * the test table until we either fail or reach the null entry.
1036          */
1037         while (test->reg) {
1038                 for (i = 0; i < test->array_len; i++) {
1039                         switch (test->test_type) {
1040                         case PATTERN_TEST:
1041                                 REG_PATTERN_TEST(test->reg +
1042                                                 (i * test->reg_offset),
1043                                                 test->mask,
1044                                                 test->write);
1045                                 break;
1046                         case SET_READ_TEST:
1047                                 REG_SET_AND_CHECK(test->reg +
1048                                                 (i * test->reg_offset),
1049                                                 test->mask,
1050                                                 test->write);
1051                                 break;
1052                         case WRITE_NO_TEST:
1053                                 writel(test->write,
1054                                     (adapter->hw.hw_addr + test->reg)
1055                                         + (i * test->reg_offset));
1056                                 break;
1057                         case TABLE32_TEST:
1058                                 REG_PATTERN_TEST(test->reg + (i * 4),
1059                                                 test->mask,
1060                                                 test->write);
1061                                 break;
1062                         case TABLE64_TEST_LO:
1063                                 REG_PATTERN_TEST(test->reg + (i * 8),
1064                                                 test->mask,
1065                                                 test->write);
1066                                 break;
1067                         case TABLE64_TEST_HI:
1068                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1069                                                 test->mask,
1070                                                 test->write);
1071                                 break;
1072                         }
1073                 }
1074                 test++;
1075         }
1076
1077         *data = 0;
1078         return 0;
1079 }
1080
1081 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1082 {
1083         u16 temp;
1084         u16 checksum = 0;
1085         u16 i;
1086
1087         *data = 0;
1088         /* Read and add up the contents of the EEPROM */
1089         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1090                 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp))
1091                     < 0) {
1092                         *data = 1;
1093                         break;
1094                 }
1095                 checksum += temp;
1096         }
1097
1098         /* If Checksum is not Correct return error else test passed */
1099         if ((checksum != (u16) NVM_SUM) && !(*data))
1100                 *data = 2;
1101
1102         return *data;
1103 }
1104
1105 static irqreturn_t igb_test_intr(int irq, void *data)
1106 {
1107         struct net_device *netdev = (struct net_device *) data;
1108         struct igb_adapter *adapter = netdev_priv(netdev);
1109         struct e1000_hw *hw = &adapter->hw;
1110
1111         adapter->test_icr |= rd32(E1000_ICR);
1112
1113         return IRQ_HANDLED;
1114 }
1115
1116 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1117 {
1118         struct e1000_hw *hw = &adapter->hw;
1119         struct net_device *netdev = adapter->netdev;
1120         u32 mask, ics_mask, i = 0, shared_int = true;
1121         u32 irq = adapter->pdev->irq;
1122
1123         *data = 0;
1124
1125         /* Hook up test interrupt handler just for this test */
1126         if (adapter->msix_entries)
1127                 /* NOTE: we don't test MSI-X interrupts here, yet */
1128                 return 0;
1129
1130         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1131                 shared_int = false;
1132                 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1133                         *data = 1;
1134                         return -1;
1135                 }
1136         } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1137                                 netdev->name, netdev)) {
1138                 shared_int = false;
1139         } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1140                  netdev->name, netdev)) {
1141                 *data = 1;
1142                 return -1;
1143         }
1144         dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1145                 (shared_int ? "shared" : "unshared"));
1146         /* Disable all the interrupts */
1147         wr32(E1000_IMC, 0xFFFFFFFF);
1148         msleep(10);
1149
1150         /* Define all writable bits for ICS */
1151         switch(hw->mac.type) {
1152         case e1000_82575:
1153                 ics_mask = 0x37F47EDD;
1154                 break;
1155         case e1000_82576:
1156                 ics_mask = 0x77D4FBFD;
1157                 break;
1158         default:
1159                 ics_mask = 0x7FFFFFFF;
1160                 break;
1161         }
1162
1163         /* Test each interrupt */
1164         for (; i < 31; i++) {
1165                 /* Interrupt to test */
1166                 mask = 1 << i;
1167
1168                 if (!(mask & ics_mask))
1169                         continue;
1170
1171                 if (!shared_int) {
1172                         /* Disable the interrupt to be reported in
1173                          * the cause register and then force the same
1174                          * interrupt and see if one gets posted.  If
1175                          * an interrupt was posted to the bus, the
1176                          * test failed.
1177                          */
1178                         adapter->test_icr = 0;
1179
1180                         /* Flush any pending interrupts */
1181                         wr32(E1000_ICR, ~0);
1182
1183                         wr32(E1000_IMC, mask);
1184                         wr32(E1000_ICS, mask);
1185                         msleep(10);
1186
1187                         if (adapter->test_icr & mask) {
1188                                 *data = 3;
1189                                 break;
1190                         }
1191                 }
1192
1193                 /* Enable the interrupt to be reported in
1194                  * the cause register and then force the same
1195                  * interrupt and see if one gets posted.  If
1196                  * an interrupt was not posted to the bus, the
1197                  * test failed.
1198                  */
1199                 adapter->test_icr = 0;
1200
1201                 /* Flush any pending interrupts */
1202                 wr32(E1000_ICR, ~0);
1203
1204                 wr32(E1000_IMS, mask);
1205                 wr32(E1000_ICS, mask);
1206                 msleep(10);
1207
1208                 if (!(adapter->test_icr & mask)) {
1209                         *data = 4;
1210                         break;
1211                 }
1212
1213                 if (!shared_int) {
1214                         /* Disable the other interrupts to be reported in
1215                          * the cause register and then force the other
1216                          * interrupts and see if any get posted.  If
1217                          * an interrupt was posted to the bus, the
1218                          * test failed.
1219                          */
1220                         adapter->test_icr = 0;
1221
1222                         /* Flush any pending interrupts */
1223                         wr32(E1000_ICR, ~0);
1224
1225                         wr32(E1000_IMC, ~mask);
1226                         wr32(E1000_ICS, ~mask);
1227                         msleep(10);
1228
1229                         if (adapter->test_icr & mask) {
1230                                 *data = 5;
1231                                 break;
1232                         }
1233                 }
1234         }
1235
1236         /* Disable all the interrupts */
1237         wr32(E1000_IMC, ~0);
1238         msleep(10);
1239
1240         /* Unhook test interrupt handler */
1241         free_irq(irq, netdev);
1242
1243         return *data;
1244 }
1245
1246 static void igb_free_desc_rings(struct igb_adapter *adapter)
1247 {
1248         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1249         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1250         struct pci_dev *pdev = adapter->pdev;
1251         int i;
1252
1253         if (tx_ring->desc && tx_ring->buffer_info) {
1254                 for (i = 0; i < tx_ring->count; i++) {
1255                         struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1256                         if (buf->dma)
1257                                 pci_unmap_single(pdev, buf->dma, buf->length,
1258                                                  PCI_DMA_TODEVICE);
1259                         if (buf->skb)
1260                                 dev_kfree_skb(buf->skb);
1261                 }
1262         }
1263
1264         if (rx_ring->desc && rx_ring->buffer_info) {
1265                 for (i = 0; i < rx_ring->count; i++) {
1266                         struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1267                         if (buf->dma)
1268                                 pci_unmap_single(pdev, buf->dma,
1269                                                  IGB_RXBUFFER_2048,
1270                                                  PCI_DMA_FROMDEVICE);
1271                         if (buf->skb)
1272                                 dev_kfree_skb(buf->skb);
1273                 }
1274         }
1275
1276         if (tx_ring->desc) {
1277                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1278                                     tx_ring->dma);
1279                 tx_ring->desc = NULL;
1280         }
1281         if (rx_ring->desc) {
1282                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1283                                     rx_ring->dma);
1284                 rx_ring->desc = NULL;
1285         }
1286
1287         kfree(tx_ring->buffer_info);
1288         tx_ring->buffer_info = NULL;
1289         kfree(rx_ring->buffer_info);
1290         rx_ring->buffer_info = NULL;
1291
1292         return;
1293 }
1294
1295 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1296 {
1297         struct e1000_hw *hw = &adapter->hw;
1298         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1299         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1300         struct pci_dev *pdev = adapter->pdev;
1301         struct igb_buffer *buffer_info;
1302         u32 rctl;
1303         int i, ret_val;
1304
1305         /* Setup Tx descriptor ring and Tx buffers */
1306
1307         if (!tx_ring->count)
1308                 tx_ring->count = IGB_DEFAULT_TXD;
1309
1310         tx_ring->buffer_info = kcalloc(tx_ring->count,
1311                                        sizeof(struct igb_buffer),
1312                                        GFP_KERNEL);
1313         if (!tx_ring->buffer_info) {
1314                 ret_val = 1;
1315                 goto err_nomem;
1316         }
1317
1318         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1319         tx_ring->size = ALIGN(tx_ring->size, 4096);
1320         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1321                                              &tx_ring->dma);
1322         if (!tx_ring->desc) {
1323                 ret_val = 2;
1324                 goto err_nomem;
1325         }
1326         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1327
1328         wr32(E1000_TDBAL(0),
1329                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1330         wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1331         wr32(E1000_TDLEN(0),
1332                         tx_ring->count * sizeof(union e1000_adv_tx_desc));
1333         wr32(E1000_TDH(0), 0);
1334         wr32(E1000_TDT(0), 0);
1335         wr32(E1000_TCTL,
1336                         E1000_TCTL_PSP | E1000_TCTL_EN |
1337                         E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1338                         E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1339
1340         for (i = 0; i < tx_ring->count; i++) {
1341                 union e1000_adv_tx_desc *tx_desc;
1342                 struct sk_buff *skb;
1343                 unsigned int size = 1024;
1344
1345                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
1346                 skb = alloc_skb(size, GFP_KERNEL);
1347                 if (!skb) {
1348                         ret_val = 3;
1349                         goto err_nomem;
1350                 }
1351                 skb_put(skb, size);
1352                 buffer_info = &tx_ring->buffer_info[i];
1353                 buffer_info->skb = skb;
1354                 buffer_info->length = skb->len;
1355                 buffer_info->dma = pci_map_single(pdev, skb->data, skb->len,
1356                                                   PCI_DMA_TODEVICE);
1357                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
1358                 tx_desc->read.olinfo_status = cpu_to_le32(skb->len) <<
1359                                               E1000_ADVTXD_PAYLEN_SHIFT;
1360                 tx_desc->read.cmd_type_len = cpu_to_le32(skb->len);
1361                 tx_desc->read.cmd_type_len |= cpu_to_le32(E1000_TXD_CMD_EOP |
1362                                                           E1000_TXD_CMD_IFCS |
1363                                                           E1000_TXD_CMD_RS |
1364                                                           E1000_ADVTXD_DTYP_DATA |
1365                                                           E1000_ADVTXD_DCMD_DEXT);
1366         }
1367
1368         /* Setup Rx descriptor ring and Rx buffers */
1369
1370         if (!rx_ring->count)
1371                 rx_ring->count = IGB_DEFAULT_RXD;
1372
1373         rx_ring->buffer_info = kcalloc(rx_ring->count,
1374                                        sizeof(struct igb_buffer),
1375                                        GFP_KERNEL);
1376         if (!rx_ring->buffer_info) {
1377                 ret_val = 4;
1378                 goto err_nomem;
1379         }
1380
1381         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
1382         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1383                                              &rx_ring->dma);
1384         if (!rx_ring->desc) {
1385                 ret_val = 5;
1386                 goto err_nomem;
1387         }
1388         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1389
1390         rctl = rd32(E1000_RCTL);
1391         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1392         wr32(E1000_RDBAL(0),
1393                         ((u64) rx_ring->dma & 0xFFFFFFFF));
1394         wr32(E1000_RDBAH(0),
1395                         ((u64) rx_ring->dma >> 32));
1396         wr32(E1000_RDLEN(0), rx_ring->size);
1397         wr32(E1000_RDH(0), 0);
1398         wr32(E1000_RDT(0), 0);
1399         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1400         rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1401                 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1402         wr32(E1000_RCTL, rctl);
1403         wr32(E1000_SRRCTL(0), E1000_SRRCTL_DESCTYPE_ADV_ONEBUF);
1404
1405         for (i = 0; i < rx_ring->count; i++) {
1406                 union e1000_adv_rx_desc *rx_desc;
1407                 struct sk_buff *skb;
1408
1409                 buffer_info = &rx_ring->buffer_info[i];
1410                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
1411                 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1412                                 GFP_KERNEL);
1413                 if (!skb) {
1414                         ret_val = 6;
1415                         goto err_nomem;
1416                 }
1417                 skb_reserve(skb, NET_IP_ALIGN);
1418                 buffer_info->skb = skb;
1419                 buffer_info->dma = pci_map_single(pdev, skb->data,
1420                                                   IGB_RXBUFFER_2048,
1421                                                   PCI_DMA_FROMDEVICE);
1422                 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
1423                 memset(skb->data, 0x00, skb->len);
1424         }
1425
1426         return 0;
1427
1428 err_nomem:
1429         igb_free_desc_rings(adapter);
1430         return ret_val;
1431 }
1432
1433 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1434 {
1435         struct e1000_hw *hw = &adapter->hw;
1436
1437         /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1438         igb_write_phy_reg(hw, 29, 0x001F);
1439         igb_write_phy_reg(hw, 30, 0x8FFC);
1440         igb_write_phy_reg(hw, 29, 0x001A);
1441         igb_write_phy_reg(hw, 30, 0x8FF0);
1442 }
1443
1444 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1445 {
1446         struct e1000_hw *hw = &adapter->hw;
1447         u32 ctrl_reg = 0;
1448
1449         hw->mac.autoneg = false;
1450
1451         if (hw->phy.type == e1000_phy_m88) {
1452                 /* Auto-MDI/MDIX Off */
1453                 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1454                 /* reset to update Auto-MDI/MDIX */
1455                 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1456                 /* autoneg off */
1457                 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1458         }
1459
1460         ctrl_reg = rd32(E1000_CTRL);
1461
1462         /* force 1000, set loopback */
1463         igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1464
1465         /* Now set up the MAC to the same speed/duplex as the PHY. */
1466         ctrl_reg = rd32(E1000_CTRL);
1467         ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1468         ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1469                      E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1470                      E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1471                      E1000_CTRL_FD |     /* Force Duplex to FULL */
1472                      E1000_CTRL_SLU);    /* Set link up enable bit */
1473
1474         if (hw->phy.type == e1000_phy_m88)
1475                 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1476
1477         wr32(E1000_CTRL, ctrl_reg);
1478
1479         /* Disable the receiver on the PHY so when a cable is plugged in, the
1480          * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1481          */
1482         if (hw->phy.type == e1000_phy_m88)
1483                 igb_phy_disable_receiver(adapter);
1484
1485         udelay(500);
1486
1487         return 0;
1488 }
1489
1490 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1491 {
1492         return igb_integrated_phy_loopback(adapter);
1493 }
1494
1495 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1496 {
1497         struct e1000_hw *hw = &adapter->hw;
1498         u32 reg;
1499
1500         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1501                 reg = rd32(E1000_RCTL);
1502                 reg |= E1000_RCTL_LBM_TCVR;
1503                 wr32(E1000_RCTL, reg);
1504
1505                 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1506
1507                 reg = rd32(E1000_CTRL);
1508                 reg &= ~(E1000_CTRL_RFCE |
1509                          E1000_CTRL_TFCE |
1510                          E1000_CTRL_LRST);
1511                 reg |= E1000_CTRL_SLU |
1512                        E1000_CTRL_FD;
1513                 wr32(E1000_CTRL, reg);
1514
1515                 /* Unset switch control to serdes energy detect */
1516                 reg = rd32(E1000_CONNSW);
1517                 reg &= ~E1000_CONNSW_ENRGSRC;
1518                 wr32(E1000_CONNSW, reg);
1519
1520                 /* Set PCS register for forced speed */
1521                 reg = rd32(E1000_PCS_LCTL);
1522                 reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
1523                 reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1524                        E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1525                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1526                        E1000_PCS_LCTL_FSD |           /* Force Speed */
1527                        E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1528                 wr32(E1000_PCS_LCTL, reg);
1529
1530                 return 0;
1531         } else if (hw->phy.media_type == e1000_media_type_copper) {
1532                 return igb_set_phy_loopback(adapter);
1533         }
1534
1535         return 7;
1536 }
1537
1538 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1539 {
1540         struct e1000_hw *hw = &adapter->hw;
1541         u32 rctl;
1542         u16 phy_reg;
1543
1544         rctl = rd32(E1000_RCTL);
1545         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1546         wr32(E1000_RCTL, rctl);
1547
1548         hw->mac.autoneg = true;
1549         igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1550         if (phy_reg & MII_CR_LOOPBACK) {
1551                 phy_reg &= ~MII_CR_LOOPBACK;
1552                 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1553                 igb_phy_sw_reset(hw);
1554         }
1555 }
1556
1557 static void igb_create_lbtest_frame(struct sk_buff *skb,
1558                                     unsigned int frame_size)
1559 {
1560         memset(skb->data, 0xFF, frame_size);
1561         frame_size &= ~1;
1562         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1563         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1564         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1565 }
1566
1567 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1568 {
1569         frame_size &= ~1;
1570         if (*(skb->data + 3) == 0xFF)
1571                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1572                    (*(skb->data + frame_size / 2 + 12) == 0xAF))
1573                         return 0;
1574         return 13;
1575 }
1576
1577 static int igb_run_loopback_test(struct igb_adapter *adapter)
1578 {
1579         struct e1000_hw *hw = &adapter->hw;
1580         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1581         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1582         struct pci_dev *pdev = adapter->pdev;
1583         int i, j, k, l, lc, good_cnt;
1584         int ret_val = 0;
1585         unsigned long time;
1586
1587         wr32(E1000_RDT(0), rx_ring->count - 1);
1588
1589         /* Calculate the loop count based on the largest descriptor ring
1590          * The idea is to wrap the largest ring a number of times using 64
1591          * send/receive pairs during each loop
1592          */
1593
1594         if (rx_ring->count <= tx_ring->count)
1595                 lc = ((tx_ring->count / 64) * 2) + 1;
1596         else
1597                 lc = ((rx_ring->count / 64) * 2) + 1;
1598
1599         k = l = 0;
1600         for (j = 0; j <= lc; j++) { /* loop count loop */
1601                 for (i = 0; i < 64; i++) { /* send the packets */
1602                         igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1603                                                 1024);
1604                         pci_dma_sync_single_for_device(pdev,
1605                                 tx_ring->buffer_info[k].dma,
1606                                 tx_ring->buffer_info[k].length,
1607                                 PCI_DMA_TODEVICE);
1608                         k++;
1609                         if (k == tx_ring->count)
1610                                 k = 0;
1611                 }
1612                 wr32(E1000_TDT(0), k);
1613                 msleep(200);
1614                 time = jiffies; /* set the start time for the receive */
1615                 good_cnt = 0;
1616                 do { /* receive the sent packets */
1617                         pci_dma_sync_single_for_cpu(pdev,
1618                                         rx_ring->buffer_info[l].dma,
1619                                         IGB_RXBUFFER_2048,
1620                                         PCI_DMA_FROMDEVICE);
1621
1622                         ret_val = igb_check_lbtest_frame(
1623                                              rx_ring->buffer_info[l].skb, 1024);
1624                         if (!ret_val)
1625                                 good_cnt++;
1626                         l++;
1627                         if (l == rx_ring->count)
1628                                 l = 0;
1629                         /* time + 20 msecs (200 msecs on 2.4) is more than
1630                          * enough time to complete the receives, if it's
1631                          * exceeded, break and error off
1632                          */
1633                 } while (good_cnt < 64 && jiffies < (time + 20));
1634                 if (good_cnt != 64) {
1635                         ret_val = 13; /* ret_val is the same as mis-compare */
1636                         break;
1637                 }
1638                 if (jiffies >= (time + 20)) {
1639                         ret_val = 14; /* error code for time out error */
1640                         break;
1641                 }
1642         } /* end loop count loop */
1643         return ret_val;
1644 }
1645
1646 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1647 {
1648         /* PHY loopback cannot be performed if SoL/IDER
1649          * sessions are active */
1650         if (igb_check_reset_block(&adapter->hw)) {
1651                 dev_err(&adapter->pdev->dev,
1652                         "Cannot do PHY loopback test "
1653                         "when SoL/IDER is active.\n");
1654                 *data = 0;
1655                 goto out;
1656         }
1657         *data = igb_setup_desc_rings(adapter);
1658         if (*data)
1659                 goto out;
1660         *data = igb_setup_loopback_test(adapter);
1661         if (*data)
1662                 goto err_loopback;
1663         *data = igb_run_loopback_test(adapter);
1664         igb_loopback_cleanup(adapter);
1665
1666 err_loopback:
1667         igb_free_desc_rings(adapter);
1668 out:
1669         return *data;
1670 }
1671
1672 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1673 {
1674         struct e1000_hw *hw = &adapter->hw;
1675         *data = 0;
1676         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1677                 int i = 0;
1678                 hw->mac.serdes_has_link = false;
1679
1680                 /* On some blade server designs, link establishment
1681                  * could take as long as 2-3 minutes */
1682                 do {
1683                         hw->mac.ops.check_for_link(&adapter->hw);
1684                         if (hw->mac.serdes_has_link)
1685                                 return *data;
1686                         msleep(20);
1687                 } while (i++ < 3750);
1688
1689                 *data = 1;
1690         } else {
1691                 hw->mac.ops.check_for_link(&adapter->hw);
1692                 if (hw->mac.autoneg)
1693                         msleep(4000);
1694
1695                 if (!(rd32(E1000_STATUS) &
1696                       E1000_STATUS_LU))
1697                         *data = 1;
1698         }
1699         return *data;
1700 }
1701
1702 static void igb_diag_test(struct net_device *netdev,
1703                           struct ethtool_test *eth_test, u64 *data)
1704 {
1705         struct igb_adapter *adapter = netdev_priv(netdev);
1706         u16 autoneg_advertised;
1707         u8 forced_speed_duplex, autoneg;
1708         bool if_running = netif_running(netdev);
1709
1710         set_bit(__IGB_TESTING, &adapter->state);
1711         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1712                 /* Offline tests */
1713
1714                 /* save speed, duplex, autoneg settings */
1715                 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1716                 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1717                 autoneg = adapter->hw.mac.autoneg;
1718
1719                 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1720
1721                 /* Link test performed before hardware reset so autoneg doesn't
1722                  * interfere with test result */
1723                 if (igb_link_test(adapter, &data[4]))
1724                         eth_test->flags |= ETH_TEST_FL_FAILED;
1725
1726                 if (if_running)
1727                         /* indicate we're in test mode */
1728                         dev_close(netdev);
1729                 else
1730                         igb_reset(adapter);
1731
1732                 if (igb_reg_test(adapter, &data[0]))
1733                         eth_test->flags |= ETH_TEST_FL_FAILED;
1734
1735                 igb_reset(adapter);
1736                 if (igb_eeprom_test(adapter, &data[1]))
1737                         eth_test->flags |= ETH_TEST_FL_FAILED;
1738
1739                 igb_reset(adapter);
1740                 if (igb_intr_test(adapter, &data[2]))
1741                         eth_test->flags |= ETH_TEST_FL_FAILED;
1742
1743                 igb_reset(adapter);
1744                 if (igb_loopback_test(adapter, &data[3]))
1745                         eth_test->flags |= ETH_TEST_FL_FAILED;
1746
1747                 /* restore speed, duplex, autoneg settings */
1748                 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1749                 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1750                 adapter->hw.mac.autoneg = autoneg;
1751
1752                 /* force this routine to wait until autoneg complete/timeout */
1753                 adapter->hw.phy.autoneg_wait_to_complete = true;
1754                 igb_reset(adapter);
1755                 adapter->hw.phy.autoneg_wait_to_complete = false;
1756
1757                 clear_bit(__IGB_TESTING, &adapter->state);
1758                 if (if_running)
1759                         dev_open(netdev);
1760         } else {
1761                 dev_info(&adapter->pdev->dev, "online testing starting\n");
1762                 /* Online tests */
1763                 if (igb_link_test(adapter, &data[4]))
1764                         eth_test->flags |= ETH_TEST_FL_FAILED;
1765
1766                 /* Online tests aren't run; pass by default */
1767                 data[0] = 0;
1768                 data[1] = 0;
1769                 data[2] = 0;
1770                 data[3] = 0;
1771
1772                 clear_bit(__IGB_TESTING, &adapter->state);
1773         }
1774         msleep_interruptible(4 * 1000);
1775 }
1776
1777 static int igb_wol_exclusion(struct igb_adapter *adapter,
1778                              struct ethtool_wolinfo *wol)
1779 {
1780         struct e1000_hw *hw = &adapter->hw;
1781         int retval = 1; /* fail by default */
1782
1783         switch (hw->device_id) {
1784         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1785                 /* WoL not supported */
1786                 wol->supported = 0;
1787                 break;
1788         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1789         case E1000_DEV_ID_82576_FIBER:
1790         case E1000_DEV_ID_82576_SERDES:
1791                 /* Wake events not supported on port B */
1792                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1793                         wol->supported = 0;
1794                         break;
1795                 }
1796                 /* return success for non excluded adapter ports */
1797                 retval = 0;
1798                 break;
1799         case E1000_DEV_ID_82576_QUAD_COPPER:
1800                 /* quad port adapters only support WoL on port A */
1801                 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1802                         wol->supported = 0;
1803                         break;
1804                 }
1805                 /* return success for non excluded adapter ports */
1806                 retval = 0;
1807                 break;
1808         default:
1809                 /* dual port cards only support WoL on port A from now on
1810                  * unless it was enabled in the eeprom for port B
1811                  * so exclude FUNC_1 ports from having WoL enabled */
1812                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1813                     !adapter->eeprom_wol) {
1814                         wol->supported = 0;
1815                         break;
1816                 }
1817
1818                 retval = 0;
1819         }
1820
1821         return retval;
1822 }
1823
1824 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1825 {
1826         struct igb_adapter *adapter = netdev_priv(netdev);
1827
1828         wol->supported = WAKE_UCAST | WAKE_MCAST |
1829                          WAKE_BCAST | WAKE_MAGIC;
1830         wol->wolopts = 0;
1831
1832         /* this function will set ->supported = 0 and return 1 if wol is not
1833          * supported by this hardware */
1834         if (igb_wol_exclusion(adapter, wol) ||
1835             !device_can_wakeup(&adapter->pdev->dev))
1836                 return;
1837
1838         /* apply any specific unsupported masks here */
1839         switch (adapter->hw.device_id) {
1840         default:
1841                 break;
1842         }
1843
1844         if (adapter->wol & E1000_WUFC_EX)
1845                 wol->wolopts |= WAKE_UCAST;
1846         if (adapter->wol & E1000_WUFC_MC)
1847                 wol->wolopts |= WAKE_MCAST;
1848         if (adapter->wol & E1000_WUFC_BC)
1849                 wol->wolopts |= WAKE_BCAST;
1850         if (adapter->wol & E1000_WUFC_MAG)
1851                 wol->wolopts |= WAKE_MAGIC;
1852
1853         return;
1854 }
1855
1856 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1857 {
1858         struct igb_adapter *adapter = netdev_priv(netdev);
1859
1860         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1861                 return -EOPNOTSUPP;
1862
1863         if (igb_wol_exclusion(adapter, wol) ||
1864             !device_can_wakeup(&adapter->pdev->dev))
1865                 return wol->wolopts ? -EOPNOTSUPP : 0;
1866
1867         /* these settings will always override what we currently have */
1868         adapter->wol = 0;
1869
1870         if (wol->wolopts & WAKE_UCAST)
1871                 adapter->wol |= E1000_WUFC_EX;
1872         if (wol->wolopts & WAKE_MCAST)
1873                 adapter->wol |= E1000_WUFC_MC;
1874         if (wol->wolopts & WAKE_BCAST)
1875                 adapter->wol |= E1000_WUFC_BC;
1876         if (wol->wolopts & WAKE_MAGIC)
1877                 adapter->wol |= E1000_WUFC_MAG;
1878
1879         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1880
1881         return 0;
1882 }
1883
1884 /* bit defines for adapter->led_status */
1885 #define IGB_LED_ON              0
1886
1887 static int igb_phys_id(struct net_device *netdev, u32 data)
1888 {
1889         struct igb_adapter *adapter = netdev_priv(netdev);
1890         struct e1000_hw *hw = &adapter->hw;
1891
1892         if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1893                 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1894
1895         igb_blink_led(hw);
1896         msleep_interruptible(data * 1000);
1897
1898         igb_led_off(hw);
1899         clear_bit(IGB_LED_ON, &adapter->led_status);
1900         igb_cleanup_led(hw);
1901
1902         return 0;
1903 }
1904
1905 static int igb_set_coalesce(struct net_device *netdev,
1906                             struct ethtool_coalesce *ec)
1907 {
1908         struct igb_adapter *adapter = netdev_priv(netdev);
1909         int i;
1910
1911         if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1912             ((ec->rx_coalesce_usecs > 3) &&
1913              (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1914             (ec->rx_coalesce_usecs == 2))
1915                 return -EINVAL;
1916
1917         /* convert to rate of irq's per second */
1918         if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
1919                 adapter->itr_setting = ec->rx_coalesce_usecs;
1920                 adapter->itr = IGB_START_ITR;
1921         } else {
1922                 adapter->itr_setting = ec->rx_coalesce_usecs << 2;
1923                 adapter->itr = adapter->itr_setting;
1924         }
1925
1926         for (i = 0; i < adapter->num_q_vectors; i++) {
1927                 struct igb_q_vector *q_vector = adapter->q_vector[i];
1928                 q_vector->itr_val = adapter->itr;
1929                 q_vector->set_itr = 1;
1930         }
1931
1932         return 0;
1933 }
1934
1935 static int igb_get_coalesce(struct net_device *netdev,
1936                             struct ethtool_coalesce *ec)
1937 {
1938         struct igb_adapter *adapter = netdev_priv(netdev);
1939
1940         if (adapter->itr_setting <= 3)
1941                 ec->rx_coalesce_usecs = adapter->itr_setting;
1942         else
1943                 ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
1944
1945         return 0;
1946 }
1947
1948
1949 static int igb_nway_reset(struct net_device *netdev)
1950 {
1951         struct igb_adapter *adapter = netdev_priv(netdev);
1952         if (netif_running(netdev))
1953                 igb_reinit_locked(adapter);
1954         return 0;
1955 }
1956
1957 static int igb_get_sset_count(struct net_device *netdev, int sset)
1958 {
1959         switch (sset) {
1960         case ETH_SS_STATS:
1961                 return IGB_STATS_LEN;
1962         case ETH_SS_TEST:
1963                 return IGB_TEST_LEN;
1964         default:
1965                 return -ENOTSUPP;
1966         }
1967 }
1968
1969 static void igb_get_ethtool_stats(struct net_device *netdev,
1970                                   struct ethtool_stats *stats, u64 *data)
1971 {
1972         struct igb_adapter *adapter = netdev_priv(netdev);
1973         u64 *queue_stat;
1974         int stat_count_tx = sizeof(struct igb_tx_queue_stats) / sizeof(u64);
1975         int stat_count_rx = sizeof(struct igb_rx_queue_stats) / sizeof(u64);
1976         int j;
1977         int i;
1978         char *p = NULL;
1979
1980         igb_update_stats(adapter);
1981         for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1982                 switch (igb_gstrings_stats[i].type) {
1983                 case NETDEV_STATS:
1984                         p = (char *) netdev +
1985                                         igb_gstrings_stats[i].stat_offset;
1986                         break;
1987                 case IGB_STATS:
1988                         p = (char *) adapter +
1989                                         igb_gstrings_stats[i].stat_offset;
1990                         break;
1991                 }
1992
1993                 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1994                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1995         }
1996         for (j = 0; j < adapter->num_tx_queues; j++) {
1997                 int k;
1998                 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
1999                 for (k = 0; k < stat_count_tx; k++)
2000                         data[i + k] = queue_stat[k];
2001                 i += k;
2002         }
2003         for (j = 0; j < adapter->num_rx_queues; j++) {
2004                 int k;
2005                 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
2006                 for (k = 0; k < stat_count_rx; k++)
2007                         data[i + k] = queue_stat[k];
2008                 i += k;
2009         }
2010 }
2011
2012 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2013 {
2014         struct igb_adapter *adapter = netdev_priv(netdev);
2015         u8 *p = data;
2016         int i;
2017
2018         switch (stringset) {
2019         case ETH_SS_TEST:
2020                 memcpy(data, *igb_gstrings_test,
2021                         IGB_TEST_LEN*ETH_GSTRING_LEN);
2022                 break;
2023         case ETH_SS_STATS:
2024                 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2025                         memcpy(p, igb_gstrings_stats[i].stat_string,
2026                                ETH_GSTRING_LEN);
2027                         p += ETH_GSTRING_LEN;
2028                 }
2029                 for (i = 0; i < adapter->num_tx_queues; i++) {
2030                         sprintf(p, "tx_queue_%u_packets", i);
2031                         p += ETH_GSTRING_LEN;
2032                         sprintf(p, "tx_queue_%u_bytes", i);
2033                         p += ETH_GSTRING_LEN;
2034                 }
2035                 for (i = 0; i < adapter->num_rx_queues; i++) {
2036                         sprintf(p, "rx_queue_%u_packets", i);
2037                         p += ETH_GSTRING_LEN;
2038                         sprintf(p, "rx_queue_%u_bytes", i);
2039                         p += ETH_GSTRING_LEN;
2040                         sprintf(p, "rx_queue_%u_drops", i);
2041                         p += ETH_GSTRING_LEN;
2042                 }
2043 /*              BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2044                 break;
2045         }
2046 }
2047
2048 static const struct ethtool_ops igb_ethtool_ops = {
2049         .get_settings           = igb_get_settings,
2050         .set_settings           = igb_set_settings,
2051         .get_drvinfo            = igb_get_drvinfo,
2052         .get_regs_len           = igb_get_regs_len,
2053         .get_regs               = igb_get_regs,
2054         .get_wol                = igb_get_wol,
2055         .set_wol                = igb_set_wol,
2056         .get_msglevel           = igb_get_msglevel,
2057         .set_msglevel           = igb_set_msglevel,
2058         .nway_reset             = igb_nway_reset,
2059         .get_link               = ethtool_op_get_link,
2060         .get_eeprom_len         = igb_get_eeprom_len,
2061         .get_eeprom             = igb_get_eeprom,
2062         .set_eeprom             = igb_set_eeprom,
2063         .get_ringparam          = igb_get_ringparam,
2064         .set_ringparam          = igb_set_ringparam,
2065         .get_pauseparam         = igb_get_pauseparam,
2066         .set_pauseparam         = igb_set_pauseparam,
2067         .get_rx_csum            = igb_get_rx_csum,
2068         .set_rx_csum            = igb_set_rx_csum,
2069         .get_tx_csum            = igb_get_tx_csum,
2070         .set_tx_csum            = igb_set_tx_csum,
2071         .get_sg                 = ethtool_op_get_sg,
2072         .set_sg                 = ethtool_op_set_sg,
2073         .get_tso                = ethtool_op_get_tso,
2074         .set_tso                = igb_set_tso,
2075         .self_test              = igb_diag_test,
2076         .get_strings            = igb_get_strings,
2077         .phys_id                = igb_phys_id,
2078         .get_sset_count         = igb_get_sset_count,
2079         .get_ethtool_stats      = igb_get_ethtool_stats,
2080         .get_coalesce           = igb_get_coalesce,
2081         .set_coalesce           = igb_set_coalesce,
2082 };
2083
2084 void igb_set_ethtool_ops(struct net_device *netdev)
2085 {
2086         SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2087 }