drivers/net/igb/igb_ethtool.c

   1 /*******************************************************************************
   2
   3   Intel(R) Gigabit Ethernet Linux driver
   4   Copyright(c) 2007-2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for igb */
  29
  30 #include <linux/vmalloc.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/pci.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/if_ether.h>
  36 #include <linux/ethtool.h>
  37
  38 #include "igb.h"
  39
  40 enum {NETDEV_STATS, IGB_STATS};
  41
  42 struct igb_stats {
  43         char stat_string[ETH_GSTRING_LEN];
  44         int type;
  45         int sizeof_stat;
  46         int stat_offset;
  47 };
  48
  49 #define IGB_STAT(m)             IGB_STATS, \
  50                                 FIELD_SIZEOF(struct igb_adapter, m), \
  51                                 offsetof(struct igb_adapter, m)
  52 #define IGB_NETDEV_STAT(m)      NETDEV_STATS, \
  53                                 FIELD_SIZEOF(struct net_device, m), \
  54                                 offsetof(struct net_device, m)
  55
  56 static const struct igb_stats igb_gstrings_stats[] = {
  57         { "rx_packets", IGB_STAT(stats.gprc) },
  58         { "tx_packets", IGB_STAT(stats.gptc) },
  59         { "rx_bytes", IGB_STAT(stats.gorc) },
  60         { "tx_bytes", IGB_STAT(stats.gotc) },
  61         { "rx_broadcast", IGB_STAT(stats.bprc) },
  62         { "tx_broadcast", IGB_STAT(stats.bptc) },
  63         { "rx_multicast", IGB_STAT(stats.mprc) },
  64         { "tx_multicast", IGB_STAT(stats.mptc) },
  65         { "rx_errors", IGB_NETDEV_STAT(stats.rx_errors) },
  66         { "tx_errors", IGB_NETDEV_STAT(stats.tx_errors) },
  67         { "tx_dropped", IGB_NETDEV_STAT(stats.tx_dropped) },
  68         { "multicast", IGB_STAT(stats.mprc) },
  69         { "collisions", IGB_STAT(stats.colc) },
  70         { "rx_length_errors", IGB_NETDEV_STAT(stats.rx_length_errors) },
  71         { "rx_over_errors", IGB_NETDEV_STAT(stats.rx_over_errors) },
  72         { "rx_crc_errors", IGB_STAT(stats.crcerrs) },
  73         { "rx_frame_errors", IGB_NETDEV_STAT(stats.rx_frame_errors) },
  74         { "rx_no_buffer_count", IGB_STAT(stats.rnbc) },
  75         { "rx_queue_drop_packet_count", IGB_NETDEV_STAT(stats.rx_fifo_errors) },
  76         { "rx_missed_errors", IGB_STAT(stats.mpc) },
  77         { "tx_aborted_errors", IGB_STAT(stats.ecol) },
  78         { "tx_carrier_errors", IGB_STAT(stats.tncrs) },
  79         { "tx_fifo_errors", IGB_NETDEV_STAT(stats.tx_fifo_errors) },
  80         { "tx_heartbeat_errors", IGB_NETDEV_STAT(stats.tx_heartbeat_errors) },
  81         { "tx_window_errors", IGB_STAT(stats.latecol) },
  82         { "tx_abort_late_coll", IGB_STAT(stats.latecol) },
  83         { "tx_deferred_ok", IGB_STAT(stats.dc) },
  84         { "tx_single_coll_ok", IGB_STAT(stats.scc) },
  85         { "tx_multi_coll_ok", IGB_STAT(stats.mcc) },
  86         { "tx_timeout_count", IGB_STAT(tx_timeout_count) },
  87         { "tx_restart_queue", IGB_STAT(restart_queue) },
  88         { "rx_long_length_errors", IGB_STAT(stats.roc) },
  89         { "rx_short_length_errors", IGB_STAT(stats.ruc) },
  90         { "rx_align_errors", IGB_STAT(stats.algnerrc) },
  91         { "tx_tcp_seg_good", IGB_STAT(stats.tsctc) },
  92         { "tx_tcp_seg_failed", IGB_STAT(stats.tsctfc) },
  93         { "rx_flow_control_xon", IGB_STAT(stats.xonrxc) },
  94         { "rx_flow_control_xoff", IGB_STAT(stats.xoffrxc) },
  95         { "tx_flow_control_xon", IGB_STAT(stats.xontxc) },
  96         { "tx_flow_control_xoff", IGB_STAT(stats.xofftxc) },
  97         { "rx_long_byte_count", IGB_STAT(stats.gorc) },
  98         { "rx_csum_offload_good", IGB_STAT(hw_csum_good) },
  99         { "rx_csum_offload_errors", IGB_STAT(hw_csum_err) },
 100         { "tx_dma_out_of_sync", IGB_STAT(stats.doosync) },
 101         { "alloc_rx_buff_failed", IGB_STAT(alloc_rx_buff_failed) },
 102         { "tx_smbus", IGB_STAT(stats.mgptc) },
 103         { "rx_smbus", IGB_STAT(stats.mgprc) },
 104         { "dropped_smbus", IGB_STAT(stats.mgpdc) },
 105 };
 106
 107 #define IGB_QUEUE_STATS_LEN \
 108         (((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues)* \
 109           (sizeof(struct igb_rx_queue_stats) / sizeof(u64))) + \
 110          ((((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues) * \
 111           (sizeof(struct igb_tx_queue_stats) / sizeof(u64))))
 112 #define IGB_GLOBAL_STATS_LEN    \
 113         sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)
 114 #define IGB_STATS_LEN (IGB_GLOBAL_STATS_LEN + IGB_QUEUE_STATS_LEN)
 115 static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
 116         "Register test  (offline)", "Eeprom test    (offline)",
 117         "Interrupt test (offline)", "Loopback test  (offline)",
 118         "Link test   (on/offline)"
 119 };
 120 #define IGB_TEST_LEN sizeof(igb_gstrings_test) / ETH_GSTRING_LEN
 121
 122 static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 123 {
 124         struct igb_adapter *adapter = netdev_priv(netdev);
 125         struct e1000_hw *hw = &adapter->hw;
 126
 127         if (hw->phy.media_type == e1000_media_type_copper) {
 128
 129                 ecmd->supported = (SUPPORTED_10baseT_Half |
 130                                    SUPPORTED_10baseT_Full |
 131                                    SUPPORTED_100baseT_Half |
 132                                    SUPPORTED_100baseT_Full |
 133                                    SUPPORTED_1000baseT_Full|
 134                                    SUPPORTED_Autoneg |
 135                                    SUPPORTED_TP);
 136                 ecmd->advertising = ADVERTISED_TP;
 137
 138                 if (hw->mac.autoneg == 1) {
 139                         ecmd->advertising |= ADVERTISED_Autoneg;
 140                         /* the e1000 autoneg seems to match ethtool nicely */
 141                         ecmd->advertising |= hw->phy.autoneg_advertised;
 142                 }
 143
 144                 ecmd->port = PORT_TP;
 145                 ecmd->phy_address = hw->phy.addr;
 146         } else {
 147                 ecmd->supported   = (SUPPORTED_1000baseT_Full |
 148                                      SUPPORTED_FIBRE |
 149                                      SUPPORTED_Autoneg);
 150
 151                 ecmd->advertising = (ADVERTISED_1000baseT_Full |
 152                                      ADVERTISED_FIBRE |
 153                                      ADVERTISED_Autoneg);
 154
 155                 ecmd->port = PORT_FIBRE;
 156         }
 157
 158         ecmd->transceiver = XCVR_INTERNAL;
 159
 160         if (rd32(E1000_STATUS) & E1000_STATUS_LU) {
 161
 162                 adapter->hw.mac.ops.get_speed_and_duplex(hw,
 163                                         &adapter->link_speed,
 164                                         &adapter->link_duplex);
 165                 ecmd->speed = adapter->link_speed;
 166
 167                 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
 168                  *          and HALF_DUPLEX != DUPLEX_HALF */
 169
 170                 if (adapter->link_duplex == FULL_DUPLEX)
 171                         ecmd->duplex = DUPLEX_FULL;
 172                 else
 173                         ecmd->duplex = DUPLEX_HALF;
 174         } else {
 175                 ecmd->speed = -1;
 176                 ecmd->duplex = -1;
 177         }
 178
 179         ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
 180         return 0;
 181 }
 182
 183 static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
 184 {
 185         struct igb_adapter *adapter = netdev_priv(netdev);
 186         struct e1000_hw *hw = &adapter->hw;
 187
 188         /* When SoL/IDER sessions are active, autoneg/speed/duplex
 189          * cannot be changed */
 190         if (igb_check_reset_block(hw)) {
 191                 dev_err(&adapter->pdev->dev, "Cannot change link "
 192                         "characteristics when SoL/IDER is active.\n");
 193                 return -EINVAL;
 194         }
 195
 196         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 197                 msleep(1);
 198
 199         if (ecmd->autoneg == AUTONEG_ENABLE) {
 200                 hw->mac.autoneg = 1;
 201                 hw->phy.autoneg_advertised = ecmd->advertising |
 202                                              ADVERTISED_TP |
 203                                              ADVERTISED_Autoneg;
 204                 ecmd->advertising = hw->phy.autoneg_advertised;
 205                 if (adapter->fc_autoneg)
 206                         hw->fc.requested_mode = e1000_fc_default;
 207         } else {
 208                 if (igb_set_spd_dplx(adapter, ecmd->speed + ecmd->duplex)) {
 209                         clear_bit(__IGB_RESETTING, &adapter->state);
 210                         return -EINVAL;
 211                 }
 212         }
 213
 214         /* reset the link */
 215         if (netif_running(adapter->netdev)) {
 216                 igb_down(adapter);
 217                 igb_up(adapter);
 218         } else
 219                 igb_reset(adapter);
 220
 221         clear_bit(__IGB_RESETTING, &adapter->state);
 222         return 0;
 223 }
 224
 225 static void igb_get_pauseparam(struct net_device *netdev,
 226                                struct ethtool_pauseparam *pause)
 227 {
 228         struct igb_adapter *adapter = netdev_priv(netdev);
 229         struct e1000_hw *hw = &adapter->hw;
 230
 231         pause->autoneg =
 232                 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
 233
 234         if (hw->fc.current_mode == e1000_fc_rx_pause)
 235                 pause->rx_pause = 1;
 236         else if (hw->fc.current_mode == e1000_fc_tx_pause)
 237                 pause->tx_pause = 1;
 238         else if (hw->fc.current_mode == e1000_fc_full) {
 239                 pause->rx_pause = 1;
 240                 pause->tx_pause = 1;
 241         }
 242 }
 243
 244 static int igb_set_pauseparam(struct net_device *netdev,
 245                               struct ethtool_pauseparam *pause)
 246 {
 247         struct igb_adapter *adapter = netdev_priv(netdev);
 248         struct e1000_hw *hw = &adapter->hw;
 249         int retval = 0;
 250
 251         adapter->fc_autoneg = pause->autoneg;
 252
 253         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 254                 msleep(1);
 255
 256         if (adapter->fc_autoneg == AUTONEG_ENABLE) {
 257                 hw->fc.requested_mode = e1000_fc_default;
 258                 if (netif_running(adapter->netdev)) {
 259                         igb_down(adapter);
 260                         igb_up(adapter);
 261                 } else
 262                         igb_reset(adapter);
 263         } else {
 264                 if (pause->rx_pause && pause->tx_pause)
 265                         hw->fc.requested_mode = e1000_fc_full;
 266                 else if (pause->rx_pause && !pause->tx_pause)
 267                         hw->fc.requested_mode = e1000_fc_rx_pause;
 268                 else if (!pause->rx_pause && pause->tx_pause)
 269                         hw->fc.requested_mode = e1000_fc_tx_pause;
 270                 else if (!pause->rx_pause && !pause->tx_pause)
 271                         hw->fc.requested_mode = e1000_fc_none;
 272
 273                 hw->fc.current_mode = hw->fc.requested_mode;
 274
 275                 retval = ((hw->phy.media_type == e1000_media_type_copper) ?
 276                           igb_force_mac_fc(hw) : igb_setup_link(hw));
 277         }
 278
 279         clear_bit(__IGB_RESETTING, &adapter->state);
 280         return retval;
 281 }
 282
 283 static u32 igb_get_rx_csum(struct net_device *netdev)
 284 {
 285         struct igb_adapter *adapter = netdev_priv(netdev);
 286         return !(adapter->flags & IGB_FLAG_RX_CSUM_DISABLED);
 287 }
 288
 289 static int igb_set_rx_csum(struct net_device *netdev, u32 data)
 290 {
 291         struct igb_adapter *adapter = netdev_priv(netdev);
 292
 293         if (data)
 294                 adapter->flags &= ~IGB_FLAG_RX_CSUM_DISABLED;
 295         else
 296                 adapter->flags |= IGB_FLAG_RX_CSUM_DISABLED;
 297
 298         return 0;
 299 }
 300
 301 static u32 igb_get_tx_csum(struct net_device *netdev)
 302 {
 303         return (netdev->features & NETIF_F_IP_CSUM) != 0;
 304 }
 305
 306 static int igb_set_tx_csum(struct net_device *netdev, u32 data)
 307 {
 308         struct igb_adapter *adapter = netdev_priv(netdev);
 309
 310         if (data) {
 311                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 312                 if (adapter->hw.mac.type == e1000_82576)
 313                         netdev->features |= NETIF_F_SCTP_CSUM;
 314         } else {
 315                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
 316                                       NETIF_F_SCTP_CSUM);
 317         }
 318
 319         return 0;
 320 }
 321
 322 static int igb_set_tso(struct net_device *netdev, u32 data)
 323 {
 324         struct igb_adapter *adapter = netdev_priv(netdev);
 325
 326         if (data) {
 327                 netdev->features |= NETIF_F_TSO;
 328                 netdev->features |= NETIF_F_TSO6;
 329         } else {
 330                 netdev->features &= ~NETIF_F_TSO;
 331                 netdev->features &= ~NETIF_F_TSO6;
 332         }
 333
 334         dev_info(&adapter->pdev->dev, "TSO is %s\n",
 335                  data ? "Enabled" : "Disabled");
 336         return 0;
 337 }
 338
 339 static u32 igb_get_msglevel(struct net_device *netdev)
 340 {
 341         struct igb_adapter *adapter = netdev_priv(netdev);
 342         return adapter->msg_enable;
 343 }
 344
 345 static void igb_set_msglevel(struct net_device *netdev, u32 data)
 346 {
 347         struct igb_adapter *adapter = netdev_priv(netdev);
 348         adapter->msg_enable = data;
 349 }
 350
 351 static int igb_get_regs_len(struct net_device *netdev)
 352 {
 353 #define IGB_REGS_LEN 551
 354         return IGB_REGS_LEN * sizeof(u32);
 355 }
 356
 357 static void igb_get_regs(struct net_device *netdev,
 358                          struct ethtool_regs *regs, void *p)
 359 {
 360         struct igb_adapter *adapter = netdev_priv(netdev);
 361         struct e1000_hw *hw = &adapter->hw;
 362         u32 *regs_buff = p;
 363         u8 i;
 364
 365         memset(p, 0, IGB_REGS_LEN * sizeof(u32));
 366
 367         regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
 368
 369         /* General Registers */
 370         regs_buff[0] = rd32(E1000_CTRL);
 371         regs_buff[1] = rd32(E1000_STATUS);
 372         regs_buff[2] = rd32(E1000_CTRL_EXT);
 373         regs_buff[3] = rd32(E1000_MDIC);
 374         regs_buff[4] = rd32(E1000_SCTL);
 375         regs_buff[5] = rd32(E1000_CONNSW);
 376         regs_buff[6] = rd32(E1000_VET);
 377         regs_buff[7] = rd32(E1000_LEDCTL);
 378         regs_buff[8] = rd32(E1000_PBA);
 379         regs_buff[9] = rd32(E1000_PBS);
 380         regs_buff[10] = rd32(E1000_FRTIMER);
 381         regs_buff[11] = rd32(E1000_TCPTIMER);
 382
 383         /* NVM Register */
 384         regs_buff[12] = rd32(E1000_EECD);
 385
 386         /* Interrupt */
 387         /* Reading EICS for EICR because they read the
 388          * same but EICS does not clear on read */
 389         regs_buff[13] = rd32(E1000_EICS);
 390         regs_buff[14] = rd32(E1000_EICS);
 391         regs_buff[15] = rd32(E1000_EIMS);
 392         regs_buff[16] = rd32(E1000_EIMC);
 393         regs_buff[17] = rd32(E1000_EIAC);
 394         regs_buff[18] = rd32(E1000_EIAM);
 395         /* Reading ICS for ICR because they read the
 396          * same but ICS does not clear on read */
 397         regs_buff[19] = rd32(E1000_ICS);
 398         regs_buff[20] = rd32(E1000_ICS);
 399         regs_buff[21] = rd32(E1000_IMS);
 400         regs_buff[22] = rd32(E1000_IMC);
 401         regs_buff[23] = rd32(E1000_IAC);
 402         regs_buff[24] = rd32(E1000_IAM);
 403         regs_buff[25] = rd32(E1000_IMIRVP);
 404
 405         /* Flow Control */
 406         regs_buff[26] = rd32(E1000_FCAL);
 407         regs_buff[27] = rd32(E1000_FCAH);
 408         regs_buff[28] = rd32(E1000_FCTTV);
 409         regs_buff[29] = rd32(E1000_FCRTL);
 410         regs_buff[30] = rd32(E1000_FCRTH);
 411         regs_buff[31] = rd32(E1000_FCRTV);
 412
 413         /* Receive */
 414         regs_buff[32] = rd32(E1000_RCTL);
 415         regs_buff[33] = rd32(E1000_RXCSUM);
 416         regs_buff[34] = rd32(E1000_RLPML);
 417         regs_buff[35] = rd32(E1000_RFCTL);
 418         regs_buff[36] = rd32(E1000_MRQC);
 419         regs_buff[37] = rd32(E1000_VT_CTL);
 420
 421         /* Transmit */
 422         regs_buff[38] = rd32(E1000_TCTL);
 423         regs_buff[39] = rd32(E1000_TCTL_EXT);
 424         regs_buff[40] = rd32(E1000_TIPG);
 425         regs_buff[41] = rd32(E1000_DTXCTL);
 426
 427         /* Wake Up */
 428         regs_buff[42] = rd32(E1000_WUC);
 429         regs_buff[43] = rd32(E1000_WUFC);
 430         regs_buff[44] = rd32(E1000_WUS);
 431         regs_buff[45] = rd32(E1000_IPAV);
 432         regs_buff[46] = rd32(E1000_WUPL);
 433
 434         /* MAC */
 435         regs_buff[47] = rd32(E1000_PCS_CFG0);
 436         regs_buff[48] = rd32(E1000_PCS_LCTL);
 437         regs_buff[49] = rd32(E1000_PCS_LSTAT);
 438         regs_buff[50] = rd32(E1000_PCS_ANADV);
 439         regs_buff[51] = rd32(E1000_PCS_LPAB);
 440         regs_buff[52] = rd32(E1000_PCS_NPTX);
 441         regs_buff[53] = rd32(E1000_PCS_LPABNP);
 442
 443         /* Statistics */
 444         regs_buff[54] = adapter->stats.crcerrs;
 445         regs_buff[55] = adapter->stats.algnerrc;
 446         regs_buff[56] = adapter->stats.symerrs;
 447         regs_buff[57] = adapter->stats.rxerrc;
 448         regs_buff[58] = adapter->stats.mpc;
 449         regs_buff[59] = adapter->stats.scc;
 450         regs_buff[60] = adapter->stats.ecol;
 451         regs_buff[61] = adapter->stats.mcc;
 452         regs_buff[62] = adapter->stats.latecol;
 453         regs_buff[63] = adapter->stats.colc;
 454         regs_buff[64] = adapter->stats.dc;
 455         regs_buff[65] = adapter->stats.tncrs;
 456         regs_buff[66] = adapter->stats.sec;
 457         regs_buff[67] = adapter->stats.htdpmc;
 458         regs_buff[68] = adapter->stats.rlec;
 459         regs_buff[69] = adapter->stats.xonrxc;
 460         regs_buff[70] = adapter->stats.xontxc;
 461         regs_buff[71] = adapter->stats.xoffrxc;
 462         regs_buff[72] = adapter->stats.xofftxc;
 463         regs_buff[73] = adapter->stats.fcruc;
 464         regs_buff[74] = adapter->stats.prc64;
 465         regs_buff[75] = adapter->stats.prc127;
 466         regs_buff[76] = adapter->stats.prc255;
 467         regs_buff[77] = adapter->stats.prc511;
 468         regs_buff[78] = adapter->stats.prc1023;
 469         regs_buff[79] = adapter->stats.prc1522;
 470         regs_buff[80] = adapter->stats.gprc;
 471         regs_buff[81] = adapter->stats.bprc;
 472         regs_buff[82] = adapter->stats.mprc;
 473         regs_buff[83] = adapter->stats.gptc;
 474         regs_buff[84] = adapter->stats.gorc;
 475         regs_buff[86] = adapter->stats.gotc;
 476         regs_buff[88] = adapter->stats.rnbc;
 477         regs_buff[89] = adapter->stats.ruc;
 478         regs_buff[90] = adapter->stats.rfc;
 479         regs_buff[91] = adapter->stats.roc;
 480         regs_buff[92] = adapter->stats.rjc;
 481         regs_buff[93] = adapter->stats.mgprc;
 482         regs_buff[94] = adapter->stats.mgpdc;
 483         regs_buff[95] = adapter->stats.mgptc;
 484         regs_buff[96] = adapter->stats.tor;
 485         regs_buff[98] = adapter->stats.tot;
 486         regs_buff[100] = adapter->stats.tpr;
 487         regs_buff[101] = adapter->stats.tpt;
 488         regs_buff[102] = adapter->stats.ptc64;
 489         regs_buff[103] = adapter->stats.ptc127;
 490         regs_buff[104] = adapter->stats.ptc255;
 491         regs_buff[105] = adapter->stats.ptc511;
 492         regs_buff[106] = adapter->stats.ptc1023;
 493         regs_buff[107] = adapter->stats.ptc1522;
 494         regs_buff[108] = adapter->stats.mptc;
 495         regs_buff[109] = adapter->stats.bptc;
 496         regs_buff[110] = adapter->stats.tsctc;
 497         regs_buff[111] = adapter->stats.iac;
 498         regs_buff[112] = adapter->stats.rpthc;
 499         regs_buff[113] = adapter->stats.hgptc;
 500         regs_buff[114] = adapter->stats.hgorc;
 501         regs_buff[116] = adapter->stats.hgotc;
 502         regs_buff[118] = adapter->stats.lenerrs;
 503         regs_buff[119] = adapter->stats.scvpc;
 504         regs_buff[120] = adapter->stats.hrmpc;
 505
 506         /* These should probably be added to e1000_regs.h instead */
 507         #define E1000_PSRTYPE_REG(_i) (0x05480 + ((_i) * 4))
 508         #define E1000_IP4AT_REG(_i)   (0x05840 + ((_i) * 8))
 509         #define E1000_IP6AT_REG(_i)   (0x05880 + ((_i) * 4))
 510         #define E1000_WUPM_REG(_i)    (0x05A00 + ((_i) * 4))
 511         #define E1000_FFMT_REG(_i)    (0x09000 + ((_i) * 8))
 512         #define E1000_FFVT_REG(_i)    (0x09800 + ((_i) * 8))
 513         #define E1000_FFLT_REG(_i)    (0x05F00 + ((_i) * 8))
 514
 515         for (i = 0; i < 4; i++)
 516                 regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
 517         for (i = 0; i < 4; i++)
 518                 regs_buff[125 + i] = rd32(E1000_PSRTYPE_REG(i));
 519         for (i = 0; i < 4; i++)
 520                 regs_buff[129 + i] = rd32(E1000_RDBAL(i));
 521         for (i = 0; i < 4; i++)
 522                 regs_buff[133 + i] = rd32(E1000_RDBAH(i));
 523         for (i = 0; i < 4; i++)
 524                 regs_buff[137 + i] = rd32(E1000_RDLEN(i));
 525         for (i = 0; i < 4; i++)
 526                 regs_buff[141 + i] = rd32(E1000_RDH(i));
 527         for (i = 0; i < 4; i++)
 528                 regs_buff[145 + i] = rd32(E1000_RDT(i));
 529         for (i = 0; i < 4; i++)
 530                 regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
 531
 532         for (i = 0; i < 10; i++)
 533                 regs_buff[153 + i] = rd32(E1000_EITR(i));
 534         for (i = 0; i < 8; i++)
 535                 regs_buff[163 + i] = rd32(E1000_IMIR(i));
 536         for (i = 0; i < 8; i++)
 537                 regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
 538         for (i = 0; i < 16; i++)
 539                 regs_buff[179 + i] = rd32(E1000_RAL(i));
 540         for (i = 0; i < 16; i++)
 541                 regs_buff[195 + i] = rd32(E1000_RAH(i));
 542
 543         for (i = 0; i < 4; i++)
 544                 regs_buff[211 + i] = rd32(E1000_TDBAL(i));
 545         for (i = 0; i < 4; i++)
 546                 regs_buff[215 + i] = rd32(E1000_TDBAH(i));
 547         for (i = 0; i < 4; i++)
 548                 regs_buff[219 + i] = rd32(E1000_TDLEN(i));
 549         for (i = 0; i < 4; i++)
 550                 regs_buff[223 + i] = rd32(E1000_TDH(i));
 551         for (i = 0; i < 4; i++)
 552                 regs_buff[227 + i] = rd32(E1000_TDT(i));
 553         for (i = 0; i < 4; i++)
 554                 regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
 555         for (i = 0; i < 4; i++)
 556                 regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
 557         for (i = 0; i < 4; i++)
 558                 regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
 559         for (i = 0; i < 4; i++)
 560                 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
 561
 562         for (i = 0; i < 4; i++)
 563                 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
 564         for (i = 0; i < 4; i++)
 565                 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
 566         for (i = 0; i < 32; i++)
 567                 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
 568         for (i = 0; i < 128; i++)
 569                 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
 570         for (i = 0; i < 128; i++)
 571                 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
 572         for (i = 0; i < 4; i++)
 573                 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
 574
 575         regs_buff[547] = rd32(E1000_TDFH);
 576         regs_buff[548] = rd32(E1000_TDFT);
 577         regs_buff[549] = rd32(E1000_TDFHS);
 578         regs_buff[550] = rd32(E1000_TDFPC);
 579
 580 }
 581
 582 static int igb_get_eeprom_len(struct net_device *netdev)
 583 {
 584         struct igb_adapter *adapter = netdev_priv(netdev);
 585         return adapter->hw.nvm.word_size * 2;
 586 }
 587
 588 static int igb_get_eeprom(struct net_device *netdev,
 589                           struct ethtool_eeprom *eeprom, u8 *bytes)
 590 {
 591         struct igb_adapter *adapter = netdev_priv(netdev);
 592         struct e1000_hw *hw = &adapter->hw;
 593         u16 *eeprom_buff;
 594         int first_word, last_word;
 595         int ret_val = 0;
 596         u16 i;
 597
 598         if (eeprom->len == 0)
 599                 return -EINVAL;
 600
 601         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 602
 603         first_word = eeprom->offset >> 1;
 604         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 605
 606         eeprom_buff = kmalloc(sizeof(u16) *
 607                         (last_word - first_word + 1), GFP_KERNEL);
 608         if (!eeprom_buff)
 609                 return -ENOMEM;
 610
 611         if (hw->nvm.type == e1000_nvm_eeprom_spi)
 612                 ret_val = hw->nvm.ops.read(hw, first_word,
 613                                             last_word - first_word + 1,
 614                                             eeprom_buff);
 615         else {
 616                 for (i = 0; i < last_word - first_word + 1; i++) {
 617                         ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
 618                                                     &eeprom_buff[i]);
 619                         if (ret_val)
 620                                 break;
 621                 }
 622         }
 623
 624         /* Device's eeprom is always little-endian, word addressable */
 625         for (i = 0; i < last_word - first_word + 1; i++)
 626                 le16_to_cpus(&eeprom_buff[i]);
 627
 628         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
 629                         eeprom->len);
 630         kfree(eeprom_buff);
 631
 632         return ret_val;
 633 }
 634
 635 static int igb_set_eeprom(struct net_device *netdev,
 636                           struct ethtool_eeprom *eeprom, u8 *bytes)
 637 {
 638         struct igb_adapter *adapter = netdev_priv(netdev);
 639         struct e1000_hw *hw = &adapter->hw;
 640         u16 *eeprom_buff;
 641         void *ptr;
 642         int max_len, first_word, last_word, ret_val = 0;
 643         u16 i;
 644
 645         if (eeprom->len == 0)
 646                 return -EOPNOTSUPP;
 647
 648         if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
 649                 return -EFAULT;
 650
 651         max_len = hw->nvm.word_size * 2;
 652
 653         first_word = eeprom->offset >> 1;
 654         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 655         eeprom_buff = kmalloc(max_len, GFP_KERNEL);
 656         if (!eeprom_buff)
 657                 return -ENOMEM;
 658
 659         ptr = (void *)eeprom_buff;
 660
 661         if (eeprom->offset & 1) {
 662                 /* need read/modify/write of first changed EEPROM word */
 663                 /* only the second byte of the word is being modified */
 664                 ret_val = hw->nvm.ops.read(hw, first_word, 1,
 665                                             &eeprom_buff[0]);
 666                 ptr++;
 667         }
 668         if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
 669                 /* need read/modify/write of last changed EEPROM word */
 670                 /* only the first byte of the word is being modified */
 671                 ret_val = hw->nvm.ops.read(hw, last_word, 1,
 672                                    &eeprom_buff[last_word - first_word]);
 673         }
 674
 675         /* Device's eeprom is always little-endian, word addressable */
 676         for (i = 0; i < last_word - first_word + 1; i++)
 677                 le16_to_cpus(&eeprom_buff[i]);
 678
 679         memcpy(ptr, bytes, eeprom->len);
 680
 681         for (i = 0; i < last_word - first_word + 1; i++)
 682                 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
 683
 684         ret_val = hw->nvm.ops.write(hw, first_word,
 685                                      last_word - first_word + 1, eeprom_buff);
 686
 687         /* Update the checksum over the first part of the EEPROM if needed
 688          * and flush shadow RAM for 82573 controllers */
 689         if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
 690                 igb_update_nvm_checksum(hw);
 691
 692         kfree(eeprom_buff);
 693         return ret_val;
 694 }
 695
 696 static void igb_get_drvinfo(struct net_device *netdev,
 697                             struct ethtool_drvinfo *drvinfo)
 698 {
 699         struct igb_adapter *adapter = netdev_priv(netdev);
 700         char firmware_version[32];
 701         u16 eeprom_data;
 702
 703         strncpy(drvinfo->driver,  igb_driver_name, 32);
 704         strncpy(drvinfo->version, igb_driver_version, 32);
 705
 706         /* EEPROM image version # is reported as firmware version # for
 707          * 82575 controllers */
 708         adapter->hw.nvm.ops.read(&adapter->hw, 5, 1, &eeprom_data);
 709         sprintf(firmware_version, "%d.%d-%d",
 710                 (eeprom_data & 0xF000) >> 12,
 711                 (eeprom_data & 0x0FF0) >> 4,
 712                 eeprom_data & 0x000F);
 713
 714         strncpy(drvinfo->fw_version, firmware_version, 32);
 715         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
 716         drvinfo->n_stats = IGB_STATS_LEN;
 717         drvinfo->testinfo_len = IGB_TEST_LEN;
 718         drvinfo->regdump_len = igb_get_regs_len(netdev);
 719         drvinfo->eedump_len = igb_get_eeprom_len(netdev);
 720 }
 721
 722 static void igb_get_ringparam(struct net_device *netdev,
 723                               struct ethtool_ringparam *ring)
 724 {
 725         struct igb_adapter *adapter = netdev_priv(netdev);
 726
 727         ring->rx_max_pending = IGB_MAX_RXD;
 728         ring->tx_max_pending = IGB_MAX_TXD;
 729         ring->rx_mini_max_pending = 0;
 730         ring->rx_jumbo_max_pending = 0;
 731         ring->rx_pending = adapter->rx_ring_count;
 732         ring->tx_pending = adapter->tx_ring_count;
 733         ring->rx_mini_pending = 0;
 734         ring->rx_jumbo_pending = 0;
 735 }
 736
 737 static int igb_set_ringparam(struct net_device *netdev,
 738                              struct ethtool_ringparam *ring)
 739 {
 740         struct igb_adapter *adapter = netdev_priv(netdev);
 741         struct igb_ring *temp_ring;
 742         int i, err = 0;
 743         u32 new_rx_count, new_tx_count;
 744
 745         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 746                 return -EINVAL;
 747
 748         new_rx_count = max(ring->rx_pending, (u32)IGB_MIN_RXD);
 749         new_rx_count = min(new_rx_count, (u32)IGB_MAX_RXD);
 750         new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
 751
 752         new_tx_count = max(ring->tx_pending, (u32)IGB_MIN_TXD);
 753         new_tx_count = min(new_tx_count, (u32)IGB_MAX_TXD);
 754         new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
 755
 756         if ((new_tx_count == adapter->tx_ring_count) &&
 757             (new_rx_count == adapter->rx_ring_count)) {
 758                 /* nothing to do */
 759                 return 0;
 760         }
 761
 762         while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
 763                 msleep(1);
 764
 765         if (!netif_running(adapter->netdev)) {
 766                 for (i = 0; i < adapter->num_tx_queues; i++)
 767                         adapter->tx_ring[i].count = new_tx_count;
 768                 for (i = 0; i < adapter->num_rx_queues; i++)
 769                         adapter->rx_ring[i].count = new_rx_count;
 770                 adapter->tx_ring_count = new_tx_count;
 771                 adapter->rx_ring_count = new_rx_count;
 772                 goto clear_reset;
 773         }
 774
 775         if (adapter->num_tx_queues > adapter->num_rx_queues)
 776                 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
 777         else
 778                 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
 779
 780         if (!temp_ring) {
 781                 err = -ENOMEM;
 782                 goto clear_reset;
 783         }
 784
 785         igb_down(adapter);
 786
 787         /*
 788          * We can't just free everything and then setup again,
 789          * because the ISRs in MSI-X mode get passed pointers
 790          * to the tx and rx ring structs.
 791          */
 792         if (new_tx_count != adapter->tx_ring_count) {
 793                 memcpy(temp_ring, adapter->tx_ring,
 794                        adapter->num_tx_queues * sizeof(struct igb_ring));
 795
 796                 for (i = 0; i < adapter->num_tx_queues; i++) {
 797                         temp_ring[i].count = new_tx_count;
 798                         err = igb_setup_tx_resources(adapter, &temp_ring[i]);
 799                         if (err) {
 800                                 while (i) {
 801                                         i--;
 802                                         igb_free_tx_resources(&temp_ring[i]);
 803                                 }
 804                                 goto err_setup;
 805                         }
 806                 }
 807
 808                 for (i = 0; i < adapter->num_tx_queues; i++)
 809                         igb_free_tx_resources(&adapter->tx_ring[i]);
 810
 811                 memcpy(adapter->tx_ring, temp_ring,
 812                        adapter->num_tx_queues * sizeof(struct igb_ring));
 813
 814                 adapter->tx_ring_count = new_tx_count;
 815         }
 816
 817         if (new_rx_count != adapter->rx_ring->count) {
 818                 memcpy(temp_ring, adapter->rx_ring,
 819                        adapter->num_rx_queues * sizeof(struct igb_ring));
 820
 821                 for (i = 0; i < adapter->num_rx_queues; i++) {
 822                         temp_ring[i].count = new_rx_count;
 823                         err = igb_setup_rx_resources(adapter, &temp_ring[i]);
 824                         if (err) {
 825                                 while (i) {
 826                                         i--;
 827                                         igb_free_rx_resources(&temp_ring[i]);
 828                                 }
 829                                 goto err_setup;
 830                         }
 831
 832                 }
 833
 834                 for (i = 0; i < adapter->num_rx_queues; i++)
 835                         igb_free_rx_resources(&adapter->rx_ring[i]);
 836
 837                 memcpy(adapter->rx_ring, temp_ring,
 838                        adapter->num_rx_queues * sizeof(struct igb_ring));
 839
 840                 adapter->rx_ring_count = new_rx_count;
 841         }
 842 err_setup:
 843         igb_up(adapter);
 844         vfree(temp_ring);
 845 clear_reset:
 846         clear_bit(__IGB_RESETTING, &adapter->state);
 847         return err;
 848 }
 849
 850 /* ethtool register test data */
 851 struct igb_reg_test {
 852         u16 reg;
 853         u16 reg_offset;
 854         u16 array_len;
 855         u16 test_type;
 856         u32 mask;
 857         u32 write;
 858 };
 859
 860 /* In the hardware, registers are laid out either singly, in arrays
 861  * spaced 0x100 bytes apart, or in contiguous tables.  We assume
 862  * most tests take place on arrays or single registers (handled
 863  * as a single-element array) and special-case the tables.
 864  * Table tests are always pattern tests.
 865  *
 866  * We also make provision for some required setup steps by specifying
 867  * registers to be written without any read-back testing.
 868  */
 869
 870 #define PATTERN_TEST    1
 871 #define SET_READ_TEST   2
 872 #define WRITE_NO_TEST   3
 873 #define TABLE32_TEST    4
 874 #define TABLE64_TEST_LO 5
 875 #define TABLE64_TEST_HI 6
 876
 877 /* 82576 reg test */
 878 static struct igb_reg_test reg_test_82576[] = {
 879         { E1000_FCAL,      0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 880         { E1000_FCAH,      0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 881         { E1000_FCT,       0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 882         { E1000_VET,       0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 883         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 884         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 885         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 886         { E1000_RDBAL(4),  0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 887         { E1000_RDBAH(4),  0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 888         { E1000_RDLEN(4),  0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 889         /* Enable all RX queues before testing. */
 890         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 891         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 892         /* RDH is read-only for 82576, only test RDT. */
 893         { E1000_RDT(0),    0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 894         { E1000_RDT(4),    0x40, 12,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 895         { E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
 896         { E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, 0 },
 897         { E1000_FCRTH,     0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 898         { E1000_FCTTV,     0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 899         { E1000_TIPG,      0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 900         { E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 901         { E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 902         { E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 903         { E1000_TDBAL(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 904         { E1000_TDBAH(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 905         { E1000_TDLEN(4),  0x40, 12,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
 906         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 907         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
 908         { E1000_RCTL,      0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
 909         { E1000_TCTL,      0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 910         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 911         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
 912         { E1000_RA2,       0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 913         { E1000_RA2,       0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
 914         { E1000_MTA,       0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 915         { 0, 0, 0, 0 }
 916 };
 917
 918 /* 82575 register test */
 919 static struct igb_reg_test reg_test_82575[] = {
 920         { E1000_FCAL,      0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 921         { E1000_FCAH,      0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 922         { E1000_FCT,       0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
 923         { E1000_VET,       0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 924         { E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 925         { E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 926         { E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 927         /* Enable all four RX queues before testing. */
 928         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
 929         /* RDH is read-only for 82575, only test RDT. */
 930         { E1000_RDT(0),    0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 931         { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
 932         { E1000_FCRTH,     0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
 933         { E1000_FCTTV,     0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
 934         { E1000_TIPG,      0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
 935         { E1000_TDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
 936         { E1000_TDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 937         { E1000_TDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
 938         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 939         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
 940         { E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
 941         { E1000_TCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
 942         { E1000_TXCW,      0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
 943         { E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
 944         { E1000_RA,        0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
 945         { E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
 946         { 0, 0, 0, 0 }
 947 };
 948
 949 static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
 950                              int reg, u32 mask, u32 write)
 951 {
 952         struct e1000_hw *hw = &adapter->hw;
 953         u32 pat, val;
 954         u32 _test[] =
 955                 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
 956         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
 957                 wr32(reg, (_test[pat] & write));
 958                 val = rd32(reg);
 959                 if (val != (_test[pat] & write & mask)) {
 960                         dev_err(&adapter->pdev->dev, "pattern test reg %04X "
 961                                 "failed: got 0x%08X expected 0x%08X\n",
 962                                 reg, val, (_test[pat] & write & mask));
 963                         *data = reg;
 964                         return 1;
 965                 }
 966         }
 967         return 0;
 968 }
 969
 970 static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
 971                               int reg, u32 mask, u32 write)
 972 {
 973         struct e1000_hw *hw = &adapter->hw;
 974         u32 val;
 975         wr32(reg, write & mask);
 976         val = rd32(reg);
 977         if ((write & mask) != (val & mask)) {
 978                 dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
 979                         " got 0x%08X expected 0x%08X\n", reg,
 980                         (val & mask), (write & mask));
 981                 *data = reg;
 982                 return 1;
 983         }
 984         return 0;
 985 }
 986
 987 #define REG_PATTERN_TEST(reg, mask, write) \
 988         do { \
 989                 if (reg_pattern_test(adapter, data, reg, mask, write)) \
 990                         return 1; \
 991         } while (0)
 992
 993 #define REG_SET_AND_CHECK(reg, mask, write) \
 994         do { \
 995                 if (reg_set_and_check(adapter, data, reg, mask, write)) \
 996                         return 1; \
 997         } while (0)
 998
 999 static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1000 {
1001         struct e1000_hw *hw = &adapter->hw;
1002         struct igb_reg_test *test;
1003         u32 value, before, after;
1004         u32 i, toggle;
1005
1006         toggle = 0x7FFFF3FF;
1007
1008         switch (adapter->hw.mac.type) {
1009         case e1000_82576:
1010                 test = reg_test_82576;
1011                 break;
1012         default:
1013                 test = reg_test_82575;
1014                 break;
1015         }
1016
1017         /* Because the status register is such a special case,
1018          * we handle it separately from the rest of the register
1019          * tests.  Some bits are read-only, some toggle, and some
1020          * are writable on newer MACs.
1021          */
1022         before = rd32(E1000_STATUS);
1023         value = (rd32(E1000_STATUS) & toggle);
1024         wr32(E1000_STATUS, toggle);
1025         after = rd32(E1000_STATUS) & toggle;
1026         if (value != after) {
1027                 dev_err(&adapter->pdev->dev, "failed STATUS register test "
1028                         "got: 0x%08X expected: 0x%08X\n", after, value);
1029                 *data = 1;
1030                 return 1;
1031         }
1032         /* restore previous status */
1033         wr32(E1000_STATUS, before);
1034
1035         /* Perform the remainder of the register test, looping through
1036          * the test table until we either fail or reach the null entry.
1037          */
1038         while (test->reg) {
1039                 for (i = 0; i < test->array_len; i++) {
1040                         switch (test->test_type) {
1041                         case PATTERN_TEST:
1042                                 REG_PATTERN_TEST(test->reg +
1043                                                 (i * test->reg_offset),
1044                                                 test->mask,
1045                                                 test->write);
1046                                 break;
1047                         case SET_READ_TEST:
1048                                 REG_SET_AND_CHECK(test->reg +
1049                                                 (i * test->reg_offset),
1050                                                 test->mask,
1051                                                 test->write);
1052                                 break;
1053                         case WRITE_NO_TEST:
1054                                 writel(test->write,
1055                                     (adapter->hw.hw_addr + test->reg)
1056                                         + (i * test->reg_offset));
1057                                 break;
1058                         case TABLE32_TEST:
1059                                 REG_PATTERN_TEST(test->reg + (i * 4),
1060                                                 test->mask,
1061                                                 test->write);
1062                                 break;
1063                         case TABLE64_TEST_LO:
1064                                 REG_PATTERN_TEST(test->reg + (i * 8),
1065                                                 test->mask,
1066                                                 test->write);
1067                                 break;
1068                         case TABLE64_TEST_HI:
1069                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1070                                                 test->mask,
1071                                                 test->write);
1072                                 break;
1073                         }
1074                 }
1075                 test++;
1076         }
1077
1078         *data = 0;
1079         return 0;
1080 }
1081
1082 static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1083 {
1084         u16 temp;
1085         u16 checksum = 0;
1086         u16 i;
1087
1088         *data = 0;
1089         /* Read and add up the contents of the EEPROM */
1090         for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1091                 if ((adapter->hw.nvm.ops.read(&adapter->hw, i, 1, &temp))
1092                     < 0) {
1093                         *data = 1;
1094                         break;
1095                 }
1096                 checksum += temp;
1097         }
1098
1099         /* If Checksum is not Correct return error else test passed */
1100         if ((checksum != (u16) NVM_SUM) && !(*data))
1101                 *data = 2;
1102
1103         return *data;
1104 }
1105
1106 static irqreturn_t igb_test_intr(int irq, void *data)
1107 {
1108         struct net_device *netdev = (struct net_device *) data;
1109         struct igb_adapter *adapter = netdev_priv(netdev);
1110         struct e1000_hw *hw = &adapter->hw;
1111
1112         adapter->test_icr |= rd32(E1000_ICR);
1113
1114         return IRQ_HANDLED;
1115 }
1116
1117 static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1118 {
1119         struct e1000_hw *hw = &adapter->hw;
1120         struct net_device *netdev = adapter->netdev;
1121         u32 mask, ics_mask, i = 0, shared_int = true;
1122         u32 irq = adapter->pdev->irq;
1123
1124         *data = 0;
1125
1126         /* Hook up test interrupt handler just for this test */
1127         if (adapter->msix_entries)
1128                 /* NOTE: we don't test MSI-X interrupts here, yet */
1129                 return 0;
1130
1131         if (adapter->flags & IGB_FLAG_HAS_MSI) {
1132                 shared_int = false;
1133                 if (request_irq(irq, &igb_test_intr, 0, netdev->name, netdev)) {
1134                         *data = 1;
1135                         return -1;
1136                 }
1137         } else if (!request_irq(irq, &igb_test_intr, IRQF_PROBE_SHARED,
1138                                 netdev->name, netdev)) {
1139                 shared_int = false;
1140         } else if (request_irq(irq, &igb_test_intr, IRQF_SHARED,
1141                  netdev->name, netdev)) {
1142                 *data = 1;
1143                 return -1;
1144         }
1145         dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1146                 (shared_int ? "shared" : "unshared"));
1147         /* Disable all the interrupts */
1148         wr32(E1000_IMC, 0xFFFFFFFF);
1149         msleep(10);
1150
1151         /* Define all writable bits for ICS */
1152         switch(hw->mac.type) {
1153         case e1000_82575:
1154                 ics_mask = 0x37F47EDD;
1155                 break;
1156         case e1000_82576:
1157                 ics_mask = 0x77D4FBFD;
1158                 break;
1159         default:
1160                 ics_mask = 0x7FFFFFFF;
1161                 break;
1162         }
1163
1164         /* Test each interrupt */
1165         for (; i < 31; i++) {
1166                 /* Interrupt to test */
1167                 mask = 1 << i;
1168
1169                 if (!(mask & ics_mask))
1170                         continue;
1171
1172                 if (!shared_int) {
1173                         /* Disable the interrupt to be reported in
1174                          * the cause register and then force the same
1175                          * interrupt and see if one gets posted.  If
1176                          * an interrupt was posted to the bus, the
1177                          * test failed.
1178                          */
1179                         adapter->test_icr = 0;
1180
1181                         /* Flush any pending interrupts */
1182                         wr32(E1000_ICR, ~0);
1183
1184                         wr32(E1000_IMC, mask);
1185                         wr32(E1000_ICS, mask);
1186                         msleep(10);
1187
1188                         if (adapter->test_icr & mask) {
1189                                 *data = 3;
1190                                 break;
1191                         }
1192                 }
1193
1194                 /* Enable the interrupt to be reported in
1195                  * the cause register and then force the same
1196                  * interrupt and see if one gets posted.  If
1197                  * an interrupt was not posted to the bus, the
1198                  * test failed.
1199                  */
1200                 adapter->test_icr = 0;
1201
1202                 /* Flush any pending interrupts */
1203                 wr32(E1000_ICR, ~0);
1204
1205                 wr32(E1000_IMS, mask);
1206                 wr32(E1000_ICS, mask);
1207                 msleep(10);
1208
1209                 if (!(adapter->test_icr & mask)) {
1210                         *data = 4;
1211                         break;
1212                 }
1213
1214                 if (!shared_int) {
1215                         /* Disable the other interrupts to be reported in
1216                          * the cause register and then force the other
1217                          * interrupts and see if any get posted.  If
1218                          * an interrupt was posted to the bus, the
1219                          * test failed.
1220                          */
1221                         adapter->test_icr = 0;
1222
1223                         /* Flush any pending interrupts */
1224                         wr32(E1000_ICR, ~0);
1225
1226                         wr32(E1000_IMC, ~mask);
1227                         wr32(E1000_ICS, ~mask);
1228                         msleep(10);
1229
1230                         if (adapter->test_icr & mask) {
1231                                 *data = 5;
1232                                 break;
1233                         }
1234                 }
1235         }
1236
1237         /* Disable all the interrupts */
1238         wr32(E1000_IMC, ~0);
1239         msleep(10);
1240
1241         /* Unhook test interrupt handler */
1242         free_irq(irq, netdev);
1243
1244         return *data;
1245 }
1246
1247 static void igb_free_desc_rings(struct igb_adapter *adapter)
1248 {
1249         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1250         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1251         struct pci_dev *pdev = adapter->pdev;
1252         int i;
1253
1254         if (tx_ring->desc && tx_ring->buffer_info) {
1255                 for (i = 0; i < tx_ring->count; i++) {
1256                         struct igb_buffer *buf = &(tx_ring->buffer_info[i]);
1257                         if (buf->dma)
1258                                 pci_unmap_single(pdev, buf->dma, buf->length,
1259                                                  PCI_DMA_TODEVICE);
1260                         if (buf->skb)
1261                                 dev_kfree_skb(buf->skb);
1262                 }
1263         }
1264
1265         if (rx_ring->desc && rx_ring->buffer_info) {
1266                 for (i = 0; i < rx_ring->count; i++) {
1267                         struct igb_buffer *buf = &(rx_ring->buffer_info[i]);
1268                         if (buf->dma)
1269                                 pci_unmap_single(pdev, buf->dma,
1270                                                  IGB_RXBUFFER_2048,
1271                                                  PCI_DMA_FROMDEVICE);
1272                         if (buf->skb)
1273                                 dev_kfree_skb(buf->skb);
1274                 }
1275         }
1276
1277         if (tx_ring->desc) {
1278                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1279                                     tx_ring->dma);
1280                 tx_ring->desc = NULL;
1281         }
1282         if (rx_ring->desc) {
1283                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1284                                     rx_ring->dma);
1285                 rx_ring->desc = NULL;
1286         }
1287
1288         kfree(tx_ring->buffer_info);
1289         tx_ring->buffer_info = NULL;
1290         kfree(rx_ring->buffer_info);
1291         rx_ring->buffer_info = NULL;
1292
1293         return;
1294 }
1295
1296 static int igb_setup_desc_rings(struct igb_adapter *adapter)
1297 {
1298         struct e1000_hw *hw = &adapter->hw;
1299         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1300         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1301         struct pci_dev *pdev = adapter->pdev;
1302         struct igb_buffer *buffer_info;
1303         u32 rctl;
1304         int i, ret_val;
1305
1306         /* Setup Tx descriptor ring and Tx buffers */
1307
1308         if (!tx_ring->count)
1309                 tx_ring->count = IGB_DEFAULT_TXD;
1310
1311         tx_ring->buffer_info = kcalloc(tx_ring->count,
1312                                        sizeof(struct igb_buffer),
1313                                        GFP_KERNEL);
1314         if (!tx_ring->buffer_info) {
1315                 ret_val = 1;
1316                 goto err_nomem;
1317         }
1318
1319         tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
1320         tx_ring->size = ALIGN(tx_ring->size, 4096);
1321         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1322                                              &tx_ring->dma);
1323         if (!tx_ring->desc) {
1324                 ret_val = 2;
1325                 goto err_nomem;
1326         }
1327         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1328
1329         wr32(E1000_TDBAL(0),
1330                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1331         wr32(E1000_TDBAH(0), ((u64) tx_ring->dma >> 32));
1332         wr32(E1000_TDLEN(0),
1333                         tx_ring->count * sizeof(union e1000_adv_tx_desc));
1334         wr32(E1000_TDH(0), 0);
1335         wr32(E1000_TDT(0), 0);
1336         wr32(E1000_TCTL,
1337                         E1000_TCTL_PSP | E1000_TCTL_EN |
1338                         E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT |
1339                         E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT);
1340
1341         for (i = 0; i < tx_ring->count; i++) {
1342                 union e1000_adv_tx_desc *tx_desc;
1343                 struct sk_buff *skb;
1344                 unsigned int size = 1024;
1345
1346                 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
1347                 skb = alloc_skb(size, GFP_KERNEL);
1348                 if (!skb) {
1349                         ret_val = 3;
1350                         goto err_nomem;
1351                 }
1352                 skb_put(skb, size);
1353                 buffer_info = &tx_ring->buffer_info[i];
1354                 buffer_info->skb = skb;
1355                 buffer_info->length = skb->len;
1356                 buffer_info->dma = pci_map_single(pdev, skb->data, skb->len,
1357                                                   PCI_DMA_TODEVICE);
1358                 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
1359                 tx_desc->read.olinfo_status = cpu_to_le32(skb->len) <<
1360                                               E1000_ADVTXD_PAYLEN_SHIFT;
1361                 tx_desc->read.cmd_type_len = cpu_to_le32(skb->len);
1362                 tx_desc->read.cmd_type_len |= cpu_to_le32(E1000_TXD_CMD_EOP |
1363                                                           E1000_TXD_CMD_IFCS |
1364                                                           E1000_TXD_CMD_RS |
1365                                                           E1000_ADVTXD_DTYP_DATA |
1366                                                           E1000_ADVTXD_DCMD_DEXT);
1367         }
1368
1369         /* Setup Rx descriptor ring and Rx buffers */
1370
1371         if (!rx_ring->count)
1372                 rx_ring->count = IGB_DEFAULT_RXD;
1373
1374         rx_ring->buffer_info = kcalloc(rx_ring->count,
1375                                        sizeof(struct igb_buffer),
1376                                        GFP_KERNEL);
1377         if (!rx_ring->buffer_info) {
1378                 ret_val = 4;
1379                 goto err_nomem;
1380         }
1381
1382         rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc);
1383         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1384                                              &rx_ring->dma);
1385         if (!rx_ring->desc) {
1386                 ret_val = 5;
1387                 goto err_nomem;
1388         }
1389         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1390
1391         rctl = rd32(E1000_RCTL);
1392         wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1393         wr32(E1000_RDBAL(0),
1394                         ((u64) rx_ring->dma & 0xFFFFFFFF));
1395         wr32(E1000_RDBAH(0),
1396                         ((u64) rx_ring->dma >> 32));
1397         wr32(E1000_RDLEN(0), rx_ring->size);
1398         wr32(E1000_RDH(0), 0);
1399         wr32(E1000_RDT(0), 0);
1400         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1401         rctl = E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
1402                 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1403         wr32(E1000_RCTL, rctl);
1404         wr32(E1000_SRRCTL(0), E1000_SRRCTL_DESCTYPE_ADV_ONEBUF);
1405
1406         for (i = 0; i < rx_ring->count; i++) {
1407                 union e1000_adv_rx_desc *rx_desc;
1408                 struct sk_buff *skb;
1409
1410                 buffer_info = &rx_ring->buffer_info[i];
1411                 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
1412                 skb = alloc_skb(IGB_RXBUFFER_2048 + NET_IP_ALIGN,
1413                                 GFP_KERNEL);
1414                 if (!skb) {
1415                         ret_val = 6;
1416                         goto err_nomem;
1417                 }
1418                 skb_reserve(skb, NET_IP_ALIGN);
1419                 buffer_info->skb = skb;
1420                 buffer_info->dma = pci_map_single(pdev, skb->data,
1421                                                   IGB_RXBUFFER_2048,
1422                                                   PCI_DMA_FROMDEVICE);
1423                 rx_desc->read.pkt_addr = cpu_to_le64(buffer_info->dma);
1424                 memset(skb->data, 0x00, skb->len);
1425         }
1426
1427         return 0;
1428
1429 err_nomem:
1430         igb_free_desc_rings(adapter);
1431         return ret_val;
1432 }
1433
1434 static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1435 {
1436         struct e1000_hw *hw = &adapter->hw;
1437
1438         /* Write out to PHY registers 29 and 30 to disable the Receiver. */
1439         igb_write_phy_reg(hw, 29, 0x001F);
1440         igb_write_phy_reg(hw, 30, 0x8FFC);
1441         igb_write_phy_reg(hw, 29, 0x001A);
1442         igb_write_phy_reg(hw, 30, 0x8FF0);
1443 }
1444
1445 static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1446 {
1447         struct e1000_hw *hw = &adapter->hw;
1448         u32 ctrl_reg = 0;
1449
1450         hw->mac.autoneg = false;
1451
1452         if (hw->phy.type == e1000_phy_m88) {
1453                 /* Auto-MDI/MDIX Off */
1454                 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1455                 /* reset to update Auto-MDI/MDIX */
1456                 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1457                 /* autoneg off */
1458                 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1459         }
1460
1461         ctrl_reg = rd32(E1000_CTRL);
1462
1463         /* force 1000, set loopback */
1464         igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1465
1466         /* Now set up the MAC to the same speed/duplex as the PHY. */
1467         ctrl_reg = rd32(E1000_CTRL);
1468         ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1469         ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1470                      E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1471                      E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1472                      E1000_CTRL_FD |     /* Force Duplex to FULL */
1473                      E1000_CTRL_SLU);    /* Set link up enable bit */
1474
1475         if (hw->phy.type == e1000_phy_m88)
1476                 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1477
1478         wr32(E1000_CTRL, ctrl_reg);
1479
1480         /* Disable the receiver on the PHY so when a cable is plugged in, the
1481          * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1482          */
1483         if (hw->phy.type == e1000_phy_m88)
1484                 igb_phy_disable_receiver(adapter);
1485
1486         udelay(500);
1487
1488         return 0;
1489 }
1490
1491 static int igb_set_phy_loopback(struct igb_adapter *adapter)
1492 {
1493         return igb_integrated_phy_loopback(adapter);
1494 }
1495
1496 static int igb_setup_loopback_test(struct igb_adapter *adapter)
1497 {
1498         struct e1000_hw *hw = &adapter->hw;
1499         u32 reg;
1500
1501         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1502                 reg = rd32(E1000_RCTL);
1503                 reg |= E1000_RCTL_LBM_TCVR;
1504                 wr32(E1000_RCTL, reg);
1505
1506                 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1507
1508                 reg = rd32(E1000_CTRL);
1509                 reg &= ~(E1000_CTRL_RFCE |
1510                          E1000_CTRL_TFCE |
1511                          E1000_CTRL_LRST);
1512                 reg |= E1000_CTRL_SLU |
1513                        E1000_CTRL_FD;
1514                 wr32(E1000_CTRL, reg);
1515
1516                 /* Unset switch control to serdes energy detect */
1517                 reg = rd32(E1000_CONNSW);
1518                 reg &= ~E1000_CONNSW_ENRGSRC;
1519                 wr32(E1000_CONNSW, reg);
1520
1521                 /* Set PCS register for forced speed */
1522                 reg = rd32(E1000_PCS_LCTL);
1523                 reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
1524                 reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1525                        E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1526                        E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1527                        E1000_PCS_LCTL_FSD |           /* Force Speed */
1528                        E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1529                 wr32(E1000_PCS_LCTL, reg);
1530
1531                 return 0;
1532         } else if (hw->phy.media_type == e1000_media_type_copper) {
1533                 return igb_set_phy_loopback(adapter);
1534         }
1535
1536         return 7;
1537 }
1538
1539 static void igb_loopback_cleanup(struct igb_adapter *adapter)
1540 {
1541         struct e1000_hw *hw = &adapter->hw;
1542         u32 rctl;
1543         u16 phy_reg;
1544
1545         rctl = rd32(E1000_RCTL);
1546         rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1547         wr32(E1000_RCTL, rctl);
1548
1549         hw->mac.autoneg = true;
1550         igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1551         if (phy_reg & MII_CR_LOOPBACK) {
1552                 phy_reg &= ~MII_CR_LOOPBACK;
1553                 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1554                 igb_phy_sw_reset(hw);
1555         }
1556 }
1557
1558 static void igb_create_lbtest_frame(struct sk_buff *skb,
1559                                     unsigned int frame_size)
1560 {
1561         memset(skb->data, 0xFF, frame_size);
1562         frame_size &= ~1;
1563         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1564         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1565         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1566 }
1567
1568 static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1569 {
1570         frame_size &= ~1;
1571         if (*(skb->data + 3) == 0xFF)
1572                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1573                    (*(skb->data + frame_size / 2 + 12) == 0xAF))
1574                         return 0;
1575         return 13;
1576 }
1577
1578 static int igb_run_loopback_test(struct igb_adapter *adapter)
1579 {
1580         struct e1000_hw *hw = &adapter->hw;
1581         struct igb_ring *tx_ring = &adapter->test_tx_ring;
1582         struct igb_ring *rx_ring = &adapter->test_rx_ring;
1583         struct pci_dev *pdev = adapter->pdev;
1584         int i, j, k, l, lc, good_cnt;
1585         int ret_val = 0;
1586         unsigned long time;
1587
1588         wr32(E1000_RDT(0), rx_ring->count - 1);
1589
1590         /* Calculate the loop count based on the largest descriptor ring
1591          * The idea is to wrap the largest ring a number of times using 64
1592          * send/receive pairs during each loop
1593          */
1594
1595         if (rx_ring->count <= tx_ring->count)
1596                 lc = ((tx_ring->count / 64) * 2) + 1;
1597         else
1598                 lc = ((rx_ring->count / 64) * 2) + 1;
1599
1600         k = l = 0;
1601         for (j = 0; j <= lc; j++) { /* loop count loop */
1602                 for (i = 0; i < 64; i++) { /* send the packets */
1603                         igb_create_lbtest_frame(tx_ring->buffer_info[k].skb,
1604                                                 1024);
1605                         pci_dma_sync_single_for_device(pdev,
1606                                 tx_ring->buffer_info[k].dma,
1607                                 tx_ring->buffer_info[k].length,
1608                                 PCI_DMA_TODEVICE);
1609                         k++;
1610                         if (k == tx_ring->count)
1611                                 k = 0;
1612                 }
1613                 wr32(E1000_TDT(0), k);
1614                 msleep(200);
1615                 time = jiffies; /* set the start time for the receive */
1616                 good_cnt = 0;
1617                 do { /* receive the sent packets */
1618                         pci_dma_sync_single_for_cpu(pdev,
1619                                         rx_ring->buffer_info[l].dma,
1620                                         IGB_RXBUFFER_2048,
1621                                         PCI_DMA_FROMDEVICE);
1622
1623                         ret_val = igb_check_lbtest_frame(
1624                                              rx_ring->buffer_info[l].skb, 1024);
1625                         if (!ret_val)
1626                                 good_cnt++;
1627                         l++;
1628                         if (l == rx_ring->count)
1629                                 l = 0;
1630                         /* time + 20 msecs (200 msecs on 2.4) is more than
1631                          * enough time to complete the receives, if it's
1632                          * exceeded, break and error off
1633                          */
1634                 } while (good_cnt < 64 && jiffies < (time + 20));
1635                 if (good_cnt != 64) {
1636                         ret_val = 13; /* ret_val is the same as mis-compare */
1637                         break;
1638                 }
1639                 if (jiffies >= (time + 20)) {
1640                         ret_val = 14; /* error code for time out error */
1641                         break;
1642                 }
1643         } /* end loop count loop */
1644         return ret_val;
1645 }
1646
1647 static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1648 {
1649         /* PHY loopback cannot be performed if SoL/IDER
1650          * sessions are active */
1651         if (igb_check_reset_block(&adapter->hw)) {
1652                 dev_err(&adapter->pdev->dev,
1653                         "Cannot do PHY loopback test "
1654                         "when SoL/IDER is active.\n");
1655                 *data = 0;
1656                 goto out;
1657         }
1658         *data = igb_setup_desc_rings(adapter);
1659         if (*data)
1660                 goto out;
1661         *data = igb_setup_loopback_test(adapter);
1662         if (*data)
1663                 goto err_loopback;
1664         *data = igb_run_loopback_test(adapter);
1665         igb_loopback_cleanup(adapter);
1666
1667 err_loopback:
1668         igb_free_desc_rings(adapter);
1669 out:
1670         return *data;
1671 }
1672
1673 static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1674 {
1675         struct e1000_hw *hw = &adapter->hw;
1676         *data = 0;
1677         if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1678                 int i = 0;
1679                 hw->mac.serdes_has_link = false;
1680
1681                 /* On some blade server designs, link establishment
1682                  * could take as long as 2-3 minutes */
1683                 do {
1684                         hw->mac.ops.check_for_link(&adapter->hw);
1685                         if (hw->mac.serdes_has_link)
1686                                 return *data;
1687                         msleep(20);
1688                 } while (i++ < 3750);
1689
1690                 *data = 1;
1691         } else {
1692                 hw->mac.ops.check_for_link(&adapter->hw);
1693                 if (hw->mac.autoneg)
1694                         msleep(4000);
1695
1696                 if (!(rd32(E1000_STATUS) &
1697                       E1000_STATUS_LU))
1698                         *data = 1;
1699         }
1700         return *data;
1701 }
1702
1703 static void igb_diag_test(struct net_device *netdev,
1704                           struct ethtool_test *eth_test, u64 *data)
1705 {
1706         struct igb_adapter *adapter = netdev_priv(netdev);
1707         u16 autoneg_advertised;
1708         u8 forced_speed_duplex, autoneg;
1709         bool if_running = netif_running(netdev);
1710
1711         set_bit(__IGB_TESTING, &adapter->state);
1712         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1713                 /* Offline tests */
1714
1715                 /* save speed, duplex, autoneg settings */
1716                 autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1717                 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1718                 autoneg = adapter->hw.mac.autoneg;
1719
1720                 dev_info(&adapter->pdev->dev, "offline testing starting\n");
1721
1722                 /* Link test performed before hardware reset so autoneg doesn't
1723                  * interfere with test result */
1724                 if (igb_link_test(adapter, &data[4]))
1725                         eth_test->flags |= ETH_TEST_FL_FAILED;
1726
1727                 if (if_running)
1728                         /* indicate we're in test mode */
1729                         dev_close(netdev);
1730                 else
1731                         igb_reset(adapter);
1732
1733                 if (igb_reg_test(adapter, &data[0]))
1734                         eth_test->flags |= ETH_TEST_FL_FAILED;
1735
1736                 igb_reset(adapter);
1737                 if (igb_eeprom_test(adapter, &data[1]))
1738                         eth_test->flags |= ETH_TEST_FL_FAILED;
1739
1740                 igb_reset(adapter);
1741                 if (igb_intr_test(adapter, &data[2]))
1742                         eth_test->flags |= ETH_TEST_FL_FAILED;
1743
1744                 igb_reset(adapter);
1745                 if (igb_loopback_test(adapter, &data[3]))
1746                         eth_test->flags |= ETH_TEST_FL_FAILED;
1747
1748                 /* restore speed, duplex, autoneg settings */
1749                 adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1750                 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1751                 adapter->hw.mac.autoneg = autoneg;
1752
1753                 /* force this routine to wait until autoneg complete/timeout */
1754                 adapter->hw.phy.autoneg_wait_to_complete = true;
1755                 igb_reset(adapter);
1756                 adapter->hw.phy.autoneg_wait_to_complete = false;
1757
1758                 clear_bit(__IGB_TESTING, &adapter->state);
1759                 if (if_running)
1760                         dev_open(netdev);
1761         } else {
1762                 dev_info(&adapter->pdev->dev, "online testing starting\n");
1763                 /* Online tests */
1764                 if (igb_link_test(adapter, &data[4]))
1765                         eth_test->flags |= ETH_TEST_FL_FAILED;
1766
1767                 /* Online tests aren't run; pass by default */
1768                 data[0] = 0;
1769                 data[1] = 0;
1770                 data[2] = 0;
1771                 data[3] = 0;
1772
1773                 clear_bit(__IGB_TESTING, &adapter->state);
1774         }
1775         msleep_interruptible(4 * 1000);
1776 }
1777
1778 static int igb_wol_exclusion(struct igb_adapter *adapter,
1779                              struct ethtool_wolinfo *wol)
1780 {
1781         struct e1000_hw *hw = &adapter->hw;
1782         int retval = 1; /* fail by default */
1783
1784         switch (hw->device_id) {
1785         case E1000_DEV_ID_82575GB_QUAD_COPPER:
1786                 /* WoL not supported */
1787                 wol->supported = 0;
1788                 break;
1789         case E1000_DEV_ID_82575EB_FIBER_SERDES:
1790         case E1000_DEV_ID_82576_FIBER:
1791         case E1000_DEV_ID_82576_SERDES:
1792                 /* Wake events not supported on port B */
1793                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1794                         wol->supported = 0;
1795                         break;
1796                 }
1797                 /* return success for non excluded adapter ports */
1798                 retval = 0;
1799                 break;
1800         case E1000_DEV_ID_82576_QUAD_COPPER:
1801                 /* quad port adapters only support WoL on port A */
1802                 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1803                         wol->supported = 0;
1804                         break;
1805                 }
1806                 /* return success for non excluded adapter ports */
1807                 retval = 0;
1808                 break;
1809         default:
1810                 /* dual port cards only support WoL on port A from now on
1811                  * unless it was enabled in the eeprom for port B
1812                  * so exclude FUNC_1 ports from having WoL enabled */
1813                 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1 &&
1814                     !adapter->eeprom_wol) {
1815                         wol->supported = 0;
1816                         break;
1817                 }
1818
1819                 retval = 0;
1820         }
1821
1822         return retval;
1823 }
1824
1825 static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1826 {
1827         struct igb_adapter *adapter = netdev_priv(netdev);
1828
1829         wol->supported = WAKE_UCAST | WAKE_MCAST |
1830                          WAKE_BCAST | WAKE_MAGIC;
1831         wol->wolopts = 0;
1832
1833         /* this function will set ->supported = 0 and return 1 if wol is not
1834          * supported by this hardware */
1835         if (igb_wol_exclusion(adapter, wol) ||
1836             !device_can_wakeup(&adapter->pdev->dev))
1837                 return;
1838
1839         /* apply any specific unsupported masks here */
1840         switch (adapter->hw.device_id) {
1841         default:
1842                 break;
1843         }
1844
1845         if (adapter->wol & E1000_WUFC_EX)
1846                 wol->wolopts |= WAKE_UCAST;
1847         if (adapter->wol & E1000_WUFC_MC)
1848                 wol->wolopts |= WAKE_MCAST;
1849         if (adapter->wol & E1000_WUFC_BC)
1850                 wol->wolopts |= WAKE_BCAST;
1851         if (adapter->wol & E1000_WUFC_MAG)
1852                 wol->wolopts |= WAKE_MAGIC;
1853
1854         return;
1855 }
1856
1857 static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1858 {
1859         struct igb_adapter *adapter = netdev_priv(netdev);
1860
1861         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1862                 return -EOPNOTSUPP;
1863
1864         if (igb_wol_exclusion(adapter, wol) ||
1865             !device_can_wakeup(&adapter->pdev->dev))
1866                 return wol->wolopts ? -EOPNOTSUPP : 0;
1867
1868         /* these settings will always override what we currently have */
1869         adapter->wol = 0;
1870
1871         if (wol->wolopts & WAKE_UCAST)
1872                 adapter->wol |= E1000_WUFC_EX;
1873         if (wol->wolopts & WAKE_MCAST)
1874                 adapter->wol |= E1000_WUFC_MC;
1875         if (wol->wolopts & WAKE_BCAST)
1876                 adapter->wol |= E1000_WUFC_BC;
1877         if (wol->wolopts & WAKE_MAGIC)
1878                 adapter->wol |= E1000_WUFC_MAG;
1879
1880         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1881
1882         return 0;
1883 }
1884
1885 /* bit defines for adapter->led_status */
1886 #define IGB_LED_ON              0
1887
1888 static int igb_phys_id(struct net_device *netdev, u32 data)
1889 {
1890         struct igb_adapter *adapter = netdev_priv(netdev);
1891         struct e1000_hw *hw = &adapter->hw;
1892
1893         if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
1894                 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
1895
1896         igb_blink_led(hw);
1897         msleep_interruptible(data * 1000);
1898
1899         igb_led_off(hw);
1900         clear_bit(IGB_LED_ON, &adapter->led_status);
1901         igb_cleanup_led(hw);
1902
1903         return 0;
1904 }
1905
1906 static int igb_set_coalesce(struct net_device *netdev,
1907                             struct ethtool_coalesce *ec)
1908 {
1909         struct igb_adapter *adapter = netdev_priv(netdev);
1910         int i;
1911
1912         if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
1913             ((ec->rx_coalesce_usecs > 3) &&
1914              (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
1915             (ec->rx_coalesce_usecs == 2))
1916                 return -EINVAL;
1917
1918         /* convert to rate of irq's per second */
1919         if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) {
1920                 adapter->itr_setting = ec->rx_coalesce_usecs;
1921                 adapter->itr = IGB_START_ITR;
1922         } else {
1923                 adapter->itr_setting = ec->rx_coalesce_usecs << 2;
1924                 adapter->itr = adapter->itr_setting;
1925         }
1926
1927         for (i = 0; i < adapter->num_q_vectors; i++) {
1928                 struct igb_q_vector *q_vector = adapter->q_vector[i];
1929                 q_vector->itr_val = adapter->itr;
1930                 q_vector->set_itr = 1;
1931         }
1932
1933         return 0;
1934 }
1935
1936 static int igb_get_coalesce(struct net_device *netdev,
1937                             struct ethtool_coalesce *ec)
1938 {
1939         struct igb_adapter *adapter = netdev_priv(netdev);
1940
1941         if (adapter->itr_setting <= 3)
1942                 ec->rx_coalesce_usecs = adapter->itr_setting;
1943         else
1944                 ec->rx_coalesce_usecs = adapter->itr_setting >> 2;
1945
1946         return 0;
1947 }
1948
1949
1950 static int igb_nway_reset(struct net_device *netdev)
1951 {
1952         struct igb_adapter *adapter = netdev_priv(netdev);
1953         if (netif_running(netdev))
1954                 igb_reinit_locked(adapter);
1955         return 0;
1956 }
1957
1958 static int igb_get_sset_count(struct net_device *netdev, int sset)
1959 {
1960         switch (sset) {
1961         case ETH_SS_STATS:
1962                 return IGB_STATS_LEN;
1963         case ETH_SS_TEST:
1964                 return IGB_TEST_LEN;
1965         default:
1966                 return -ENOTSUPP;
1967         }
1968 }
1969
1970 static void igb_get_ethtool_stats(struct net_device *netdev,
1971                                   struct ethtool_stats *stats, u64 *data)
1972 {
1973         struct igb_adapter *adapter = netdev_priv(netdev);
1974         u64 *queue_stat;
1975         int stat_count_tx = sizeof(struct igb_tx_queue_stats) / sizeof(u64);
1976         int stat_count_rx = sizeof(struct igb_rx_queue_stats) / sizeof(u64);
1977         int j;
1978         int i;
1979         char *p = NULL;
1980
1981         igb_update_stats(adapter);
1982         for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
1983                 switch (igb_gstrings_stats[i].type) {
1984                 case NETDEV_STATS:
1985                         p = (char *) netdev +
1986                                         igb_gstrings_stats[i].stat_offset;
1987                         break;
1988                 case IGB_STATS:
1989                         p = (char *) adapter +
1990                                         igb_gstrings_stats[i].stat_offset;
1991                         break;
1992                 }
1993
1994                 data[i] = (igb_gstrings_stats[i].sizeof_stat ==
1995                         sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
1996         }
1997         for (j = 0; j < adapter->num_tx_queues; j++) {
1998                 int k;
1999                 queue_stat = (u64 *)&adapter->tx_ring[j].tx_stats;
2000                 for (k = 0; k < stat_count_tx; k++)
2001                         data[i + k] = queue_stat[k];
2002                 i += k;
2003         }
2004         for (j = 0; j < adapter->num_rx_queues; j++) {
2005                 int k;
2006                 queue_stat = (u64 *)&adapter->rx_ring[j].rx_stats;
2007                 for (k = 0; k < stat_count_rx; k++)
2008                         data[i + k] = queue_stat[k];
2009                 i += k;
2010         }
2011 }
2012
2013 static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2014 {
2015         struct igb_adapter *adapter = netdev_priv(netdev);
2016         u8 *p = data;
2017         int i;
2018
2019         switch (stringset) {
2020         case ETH_SS_TEST:
2021                 memcpy(data, *igb_gstrings_test,
2022                         IGB_TEST_LEN*ETH_GSTRING_LEN);
2023                 break;
2024         case ETH_SS_STATS:
2025                 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2026                         memcpy(p, igb_gstrings_stats[i].stat_string,
2027                                ETH_GSTRING_LEN);
2028                         p += ETH_GSTRING_LEN;
2029                 }
2030                 for (i = 0; i < adapter->num_tx_queues; i++) {
2031                         sprintf(p, "tx_queue_%u_packets", i);
2032                         p += ETH_GSTRING_LEN;
2033                         sprintf(p, "tx_queue_%u_bytes", i);
2034                         p += ETH_GSTRING_LEN;
2035                 }
2036                 for (i = 0; i < adapter->num_rx_queues; i++) {
2037                         sprintf(p, "rx_queue_%u_packets", i);
2038                         p += ETH_GSTRING_LEN;
2039                         sprintf(p, "rx_queue_%u_bytes", i);
2040                         p += ETH_GSTRING_LEN;
2041                         sprintf(p, "rx_queue_%u_drops", i);
2042                         p += ETH_GSTRING_LEN;
2043                 }
2044 /*              BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2045                 break;
2046         }
2047 }
2048
2049 static const struct ethtool_ops igb_ethtool_ops = {
2050         .get_settings           = igb_get_settings,
2051         .set_settings           = igb_set_settings,
2052         .get_drvinfo            = igb_get_drvinfo,
2053         .get_regs_len           = igb_get_regs_len,
2054         .get_regs               = igb_get_regs,
2055         .get_wol                = igb_get_wol,
2056         .set_wol                = igb_set_wol,
2057         .get_msglevel           = igb_get_msglevel,
2058         .set_msglevel           = igb_set_msglevel,
2059         .nway_reset             = igb_nway_reset,
2060         .get_link               = ethtool_op_get_link,
2061         .get_eeprom_len         = igb_get_eeprom_len,
2062         .get_eeprom             = igb_get_eeprom,
2063         .set_eeprom             = igb_set_eeprom,
2064         .get_ringparam          = igb_get_ringparam,
2065         .set_ringparam          = igb_set_ringparam,
2066         .get_pauseparam         = igb_get_pauseparam,
2067         .set_pauseparam         = igb_set_pauseparam,
2068         .get_rx_csum            = igb_get_rx_csum,
2069         .set_rx_csum            = igb_set_rx_csum,
2070         .get_tx_csum            = igb_get_tx_csum,
2071         .set_tx_csum            = igb_set_tx_csum,
2072         .get_sg                 = ethtool_op_get_sg,
2073         .set_sg                 = ethtool_op_set_sg,
2074         .get_tso                = ethtool_op_get_tso,
2075         .set_tso                = igb_set_tso,
2076         .self_test              = igb_diag_test,
2077         .get_strings            = igb_get_strings,
2078         .phys_id                = igb_phys_id,
2079         .get_sset_count         = igb_get_sset_count,
2080         .get_ethtool_stats      = igb_get_ethtool_stats,
2081         .get_coalesce           = igb_get_coalesce,
2082         .set_coalesce           = igb_set_coalesce,
2083 };
2084
2085 void igb_set_ethtool_ops(struct net_device *netdev)
2086 {
2087         SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2088 }