2 * drivers/net/gianfar.h
4 * Gianfar Ethernet Driver
5 * Driver for FEC on MPC8540 and TSEC on MPC8540/MPC8560
6 * Based on 8260_io/fcc_enet.c
9 * Maintainer: Kumar Gala
10 * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
12 * Copyright 2002-2009 Freescale Semiconductor, Inc.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License as published by the
16 * Free Software Foundation; either version 2 of the License, or (at your
17 * option) any later version.
20 * -Add support for module parameters
21 * -Add patch for ethtool phys id
26 #include <linux/kernel.h>
27 #include <linux/sched.h>
28 #include <linux/string.h>
29 #include <linux/errno.h>
30 #include <linux/slab.h>
31 #include <linux/interrupt.h>
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/spinlock.h>
39 #include <linux/mii.h>
40 #include <linux/phy.h>
44 #include <asm/uaccess.h>
45 #include <linux/module.h>
46 #include <linux/crc32.h>
47 #include <linux/workqueue.h>
48 #include <linux/ethtool.h>
50 /* The maximum number of packets to be handled in one call of gfar_poll */
51 #define GFAR_DEV_WEIGHT 64
54 #define GMAC_FCB_LEN 8
56 /* Default padding amount */
57 #define DEFAULT_PADDING 2
59 /* Number of bytes to align the rx bufs to */
60 #define RXBUF_ALIGNMENT 64
62 /* The number of bytes which composes a unit for the purpose of
63 * allocating data buffers. ie-for any given MTU, the data buffer
64 * will be the next highest multiple of 512 bytes. */
65 #define INCREMENTAL_BUFFER_SIZE 512
68 #define MAC_ADDR_LEN 6
70 #define PHY_INIT_TIMEOUT 100000
71 #define GFAR_PHY_CHANGE_TIME 2
73 #define DEVICE_NAME "%s: Gianfar Ethernet Controller Version 1.2, "
74 #define DRV_NAME "gfar-enet"
75 extern const char gfar_driver_name[];
76 extern const char gfar_driver_version[];
78 /* MAXIMUM NUMBER OF QUEUES SUPPORTED */
82 /* MAXIMUM NUMBER OF GROUPS SUPPORTED */
85 /* These need to be powers of 2 for this driver */
86 #define DEFAULT_TX_RING_SIZE 256
87 #define DEFAULT_RX_RING_SIZE 256
89 #define GFAR_RX_MAX_RING_SIZE 256
90 #define GFAR_TX_MAX_RING_SIZE 256
92 #define GFAR_MAX_FIFO_THRESHOLD 511
93 #define GFAR_MAX_FIFO_STARVE 511
94 #define GFAR_MAX_FIFO_STARVE_OFF 511
96 #define DEFAULT_RX_BUFFER_SIZE 1536
97 #define TX_RING_MOD_MASK(size) (size-1)
98 #define RX_RING_MOD_MASK(size) (size-1)
99 #define JUMBO_BUFFER_SIZE 9728
100 #define JUMBO_FRAME_SIZE 9600
102 #define DEFAULT_FIFO_TX_THR 0x100
103 #define DEFAULT_FIFO_TX_STARVE 0x40
104 #define DEFAULT_FIFO_TX_STARVE_OFF 0x80
105 #define DEFAULT_BD_STASH 1
106 #define DEFAULT_STASH_LENGTH 96
107 #define DEFAULT_STASH_INDEX 0
109 /* The number of Exact Match registers */
110 #define GFAR_EM_NUM 15
112 /* Latency of interface clock in nanoseconds */
113 /* Interface clock latency , in this case, means the
114 * time described by a value of 1 in the interrupt
115 * coalescing registers' time fields. Since those fields
116 * refer to the time it takes for 64 clocks to pass, the
117 * latencies are as such:
118 * GBIT = 125MHz => 8ns/clock => 8*64 ns / tick
119 * 100 = 25 MHz => 40ns/clock => 40*64 ns / tick
120 * 10 = 2.5 MHz => 400ns/clock => 400*64 ns / tick
122 #define GFAR_GBIT_TIME 512
123 #define GFAR_100_TIME 2560
124 #define GFAR_10_TIME 25600
126 #define DEFAULT_TX_COALESCE 1
127 #define DEFAULT_TXCOUNT 16
128 #define DEFAULT_TXTIME 21
130 #define DEFAULT_RXTIME 21
132 #define DEFAULT_RX_COALESCE 0
133 #define DEFAULT_RXCOUNT 0
135 #define GFAR_SUPPORTED (SUPPORTED_10baseT_Half \
136 | SUPPORTED_10baseT_Full \
137 | SUPPORTED_100baseT_Half \
138 | SUPPORTED_100baseT_Full \
139 | SUPPORTED_Autoneg \
142 /* TBI register addresses */
143 #define MII_TBICON 0x11
145 /* TBICON register bit fields */
146 #define TBICON_CLK_SELECT 0x0020
148 /* MAC register bits */
149 #define MACCFG1_SOFT_RESET 0x80000000
150 #define MACCFG1_RESET_RX_MC 0x00080000
151 #define MACCFG1_RESET_TX_MC 0x00040000
152 #define MACCFG1_RESET_RX_FUN 0x00020000
153 #define MACCFG1_RESET_TX_FUN 0x00010000
154 #define MACCFG1_LOOPBACK 0x00000100
155 #define MACCFG1_RX_FLOW 0x00000020
156 #define MACCFG1_TX_FLOW 0x00000010
157 #define MACCFG1_SYNCD_RX_EN 0x00000008
158 #define MACCFG1_RX_EN 0x00000004
159 #define MACCFG1_SYNCD_TX_EN 0x00000002
160 #define MACCFG1_TX_EN 0x00000001
162 #define MACCFG2_INIT_SETTINGS 0x00007205
163 #define MACCFG2_FULL_DUPLEX 0x00000001
164 #define MACCFG2_IF 0x00000300
165 #define MACCFG2_MII 0x00000100
166 #define MACCFG2_GMII 0x00000200
167 #define MACCFG2_HUGEFRAME 0x00000020
168 #define MACCFG2_LENGTHCHECK 0x00000010
169 #define MACCFG2_MPEN 0x00000008
171 #define ECNTRL_INIT_SETTINGS 0x00001000
172 #define ECNTRL_TBI_MODE 0x00000020
173 #define ECNTRL_REDUCED_MODE 0x00000010
174 #define ECNTRL_R100 0x00000008
175 #define ECNTRL_REDUCED_MII_MODE 0x00000004
176 #define ECNTRL_SGMII_MODE 0x00000002
178 #define MRBLR_INIT_SETTINGS DEFAULT_RX_BUFFER_SIZE
180 #define MINFLR_INIT_SETTINGS 0x00000040
183 #define TQUEUE_EN0 0x00008000
184 #define TQUEUE_EN1 0x00004000
185 #define TQUEUE_EN2 0x00002000
186 #define TQUEUE_EN3 0x00001000
187 #define TQUEUE_EN4 0x00000800
188 #define TQUEUE_EN5 0x00000400
189 #define TQUEUE_EN6 0x00000200
190 #define TQUEUE_EN7 0x00000100
191 #define TQUEUE_EN_ALL 0x0000FF00
193 #define TR03WT_WT0_MASK 0xFF000000
194 #define TR03WT_WT1_MASK 0x00FF0000
195 #define TR03WT_WT2_MASK 0x0000FF00
196 #define TR03WT_WT3_MASK 0x000000FF
198 #define TR47WT_WT4_MASK 0xFF000000
199 #define TR47WT_WT5_MASK 0x00FF0000
200 #define TR47WT_WT6_MASK 0x0000FF00
201 #define TR47WT_WT7_MASK 0x000000FF
204 #define RQUEUE_EX0 0x00800000
205 #define RQUEUE_EX1 0x00400000
206 #define RQUEUE_EX2 0x00200000
207 #define RQUEUE_EX3 0x00100000
208 #define RQUEUE_EX4 0x00080000
209 #define RQUEUE_EX5 0x00040000
210 #define RQUEUE_EX6 0x00020000
211 #define RQUEUE_EX7 0x00010000
212 #define RQUEUE_EX_ALL 0x00FF0000
214 #define RQUEUE_EN0 0x00000080
215 #define RQUEUE_EN1 0x00000040
216 #define RQUEUE_EN2 0x00000020
217 #define RQUEUE_EN3 0x00000010
218 #define RQUEUE_EN4 0x00000008
219 #define RQUEUE_EN5 0x00000004
220 #define RQUEUE_EN6 0x00000002
221 #define RQUEUE_EN7 0x00000001
222 #define RQUEUE_EN_ALL 0x000000FF
224 /* Init to do tx snooping for buffers and descriptors */
225 #define DMACTRL_INIT_SETTINGS 0x000000c3
226 #define DMACTRL_GRS 0x00000010
227 #define DMACTRL_GTS 0x00000008
229 #define TSTAT_CLEAR_THALT_ALL 0xFF000000
230 #define TSTAT_CLEAR_THALT 0x80000000
231 #define TSTAT_CLEAR_THALT0 0x80000000
232 #define TSTAT_CLEAR_THALT1 0x40000000
233 #define TSTAT_CLEAR_THALT2 0x20000000
234 #define TSTAT_CLEAR_THALT3 0x10000000
235 #define TSTAT_CLEAR_THALT4 0x08000000
236 #define TSTAT_CLEAR_THALT5 0x04000000
237 #define TSTAT_CLEAR_THALT6 0x02000000
238 #define TSTAT_CLEAR_THALT7 0x01000000
240 /* Interrupt coalescing macros */
241 #define IC_ICEN 0x80000000
242 #define IC_ICFT_MASK 0x1fe00000
243 #define IC_ICFT_SHIFT 21
244 #define mk_ic_icft(x) \
245 (((unsigned int)x << IC_ICFT_SHIFT)&IC_ICFT_MASK)
246 #define IC_ICTT_MASK 0x0000ffff
247 #define mk_ic_ictt(x) (x&IC_ICTT_MASK)
249 #define mk_ic_value(count, time) (IC_ICEN | \
250 mk_ic_icft(count) | \
252 #define get_icft_value(ic) (((unsigned long)ic & IC_ICFT_MASK) >> \
254 #define get_ictt_value(ic) ((unsigned long)ic & IC_ICTT_MASK)
256 #define DEFAULT_TXIC mk_ic_value(DEFAULT_TXCOUNT, DEFAULT_TXTIME)
257 #define DEFAULT_RXIC mk_ic_value(DEFAULT_RXCOUNT, DEFAULT_RXTIME)
259 #define skip_bd(bdp, stride, base, ring_size) ({ \
260 typeof(bdp) new_bd = (bdp) + (stride); \
261 (new_bd >= (base) + (ring_size)) ? (new_bd - (ring_size)) : new_bd; })
263 #define next_bd(bdp, base, ring_size) skip_bd(bdp, 1, base, ring_size)
265 #define RCTRL_PAL_MASK 0x001f0000
266 #define RCTRL_VLEX 0x00002000
267 #define RCTRL_FILREN 0x00001000
268 #define RCTRL_GHTX 0x00000400
269 #define RCTRL_IPCSEN 0x00000200
270 #define RCTRL_TUCSEN 0x00000100
271 #define RCTRL_PRSDEP_MASK 0x000000c0
272 #define RCTRL_PRSDEP_INIT 0x000000c0
273 #define RCTRL_PROM 0x00000008
274 #define RCTRL_EMEN 0x00000002
275 #define RCTRL_REQ_PARSER (RCTRL_VLEX | RCTRL_IPCSEN | \
277 #define RCTRL_CHECKSUMMING (RCTRL_IPCSEN | RCTRL_TUCSEN | \
279 #define RCTRL_EXTHASH (RCTRL_GHTX)
280 #define RCTRL_VLAN (RCTRL_PRSDEP_INIT)
281 #define RCTRL_PADDING(x) ((x << 16) & RCTRL_PAL_MASK)
284 #define RSTAT_CLEAR_RHALT 0x00800000
286 #define TCTRL_IPCSEN 0x00004000
287 #define TCTRL_TUCSEN 0x00002000
288 #define TCTRL_VLINS 0x00001000
289 #define TCTRL_THDF 0x00000800
290 #define TCTRL_RFCPAUSE 0x00000010
291 #define TCTRL_TFCPAUSE 0x00000008
292 #define TCTRL_TXSCHED_MASK 0x00000006
293 #define TCTRL_TXSCHED_INIT 0x00000000
294 #define TCTRL_TXSCHED_PRIO 0x00000002
295 #define TCTRL_TXSCHED_WRRS 0x00000004
296 #define TCTRL_INIT_CSUM (TCTRL_TUCSEN | TCTRL_IPCSEN)
298 #define IEVENT_INIT_CLEAR 0xffffffff
299 #define IEVENT_BABR 0x80000000
300 #define IEVENT_RXC 0x40000000
301 #define IEVENT_BSY 0x20000000
302 #define IEVENT_EBERR 0x10000000
303 #define IEVENT_MSRO 0x04000000
304 #define IEVENT_GTSC 0x02000000
305 #define IEVENT_BABT 0x01000000
306 #define IEVENT_TXC 0x00800000
307 #define IEVENT_TXE 0x00400000
308 #define IEVENT_TXB 0x00200000
309 #define IEVENT_TXF 0x00100000
310 #define IEVENT_LC 0x00040000
311 #define IEVENT_CRL 0x00020000
312 #define IEVENT_XFUN 0x00010000
313 #define IEVENT_RXB0 0x00008000
314 #define IEVENT_MAG 0x00000800
315 #define IEVENT_GRSC 0x00000100
316 #define IEVENT_RXF0 0x00000080
317 #define IEVENT_FIR 0x00000008
318 #define IEVENT_FIQ 0x00000004
319 #define IEVENT_DPE 0x00000002
320 #define IEVENT_PERR 0x00000001
321 #define IEVENT_RX_MASK (IEVENT_RXB0 | IEVENT_RXF0 | IEVENT_BSY)
322 #define IEVENT_TX_MASK (IEVENT_TXB | IEVENT_TXF)
323 #define IEVENT_RTX_MASK (IEVENT_RX_MASK | IEVENT_TX_MASK)
324 #define IEVENT_ERR_MASK \
325 (IEVENT_RXC | IEVENT_BSY | IEVENT_EBERR | IEVENT_MSRO | \
326 IEVENT_BABT | IEVENT_TXC | IEVENT_TXE | IEVENT_LC \
327 | IEVENT_CRL | IEVENT_XFUN | IEVENT_DPE | IEVENT_PERR \
328 | IEVENT_MAG | IEVENT_BABR)
330 #define IMASK_INIT_CLEAR 0x00000000
331 #define IMASK_BABR 0x80000000
332 #define IMASK_RXC 0x40000000
333 #define IMASK_BSY 0x20000000
334 #define IMASK_EBERR 0x10000000
335 #define IMASK_MSRO 0x04000000
336 #define IMASK_GRSC 0x02000000
337 #define IMASK_BABT 0x01000000
338 #define IMASK_TXC 0x00800000
339 #define IMASK_TXEEN 0x00400000
340 #define IMASK_TXBEN 0x00200000
341 #define IMASK_TXFEN 0x00100000
342 #define IMASK_LC 0x00040000
343 #define IMASK_CRL 0x00020000
344 #define IMASK_XFUN 0x00010000
345 #define IMASK_RXB0 0x00008000
346 #define IMASK_MAG 0x00000800
347 #define IMASK_GTSC 0x00000100
348 #define IMASK_RXFEN0 0x00000080
349 #define IMASK_FIR 0x00000008
350 #define IMASK_FIQ 0x00000004
351 #define IMASK_DPE 0x00000002
352 #define IMASK_PERR 0x00000001
353 #define IMASK_DEFAULT (IMASK_TXEEN | IMASK_TXFEN | IMASK_TXBEN | \
354 IMASK_RXFEN0 | IMASK_BSY | IMASK_EBERR | IMASK_BABR | \
355 IMASK_XFUN | IMASK_RXC | IMASK_BABT | IMASK_DPE \
357 #define IMASK_RTX_DISABLED ((~(IMASK_RXFEN0 | IMASK_TXFEN | IMASK_BSY)) \
360 /* Fifo management */
361 #define FIFO_TX_THR_MASK 0x01ff
362 #define FIFO_TX_STARVE_MASK 0x01ff
363 #define FIFO_TX_STARVE_OFF_MASK 0x01ff
365 /* Attribute fields */
367 /* This enables rx snooping for buffers and descriptors */
368 #define ATTR_BDSTASH 0x00000800
370 #define ATTR_BUFSTASH 0x00004000
372 #define ATTR_SNOOPING 0x000000c0
373 #define ATTR_INIT_SETTINGS ATTR_SNOOPING
375 #define ATTRELI_INIT_SETTINGS 0x0
376 #define ATTRELI_EL_MASK 0x3fff0000
377 #define ATTRELI_EL(x) (x << 16)
378 #define ATTRELI_EI_MASK 0x00003fff
379 #define ATTRELI_EI(x) (x)
381 #define BD_LFLAG(flags) ((flags) << 16)
382 #define BD_LENGTH_MASK 0x0000ffff
384 /* TxBD status field bits */
385 #define TXBD_READY 0x8000
386 #define TXBD_PADCRC 0x4000
387 #define TXBD_WRAP 0x2000
388 #define TXBD_INTERRUPT 0x1000
389 #define TXBD_LAST 0x0800
390 #define TXBD_CRC 0x0400
391 #define TXBD_DEF 0x0200
392 #define TXBD_HUGEFRAME 0x0080
393 #define TXBD_LATECOLLISION 0x0080
394 #define TXBD_RETRYLIMIT 0x0040
395 #define TXBD_RETRYCOUNTMASK 0x003c
396 #define TXBD_UNDERRUN 0x0002
397 #define TXBD_TOE 0x0002
399 /* Tx FCB param bits */
400 #define TXFCB_VLN 0x80
401 #define TXFCB_IP 0x40
402 #define TXFCB_IP6 0x20
403 #define TXFCB_TUP 0x10
404 #define TXFCB_UDP 0x08
405 #define TXFCB_CIP 0x04
406 #define TXFCB_CTU 0x02
407 #define TXFCB_NPH 0x01
408 #define TXFCB_DEFAULT (TXFCB_IP|TXFCB_TUP|TXFCB_CTU|TXFCB_NPH)
410 /* RxBD status field bits */
411 #define RXBD_EMPTY 0x8000
412 #define RXBD_RO1 0x4000
413 #define RXBD_WRAP 0x2000
414 #define RXBD_INTERRUPT 0x1000
415 #define RXBD_LAST 0x0800
416 #define RXBD_FIRST 0x0400
417 #define RXBD_MISS 0x0100
418 #define RXBD_BROADCAST 0x0080
419 #define RXBD_MULTICAST 0x0040
420 #define RXBD_LARGE 0x0020
421 #define RXBD_NONOCTET 0x0010
422 #define RXBD_SHORT 0x0008
423 #define RXBD_CRCERR 0x0004
424 #define RXBD_OVERRUN 0x0002
425 #define RXBD_TRUNCATED 0x0001
426 #define RXBD_STATS 0x01ff
427 #define RXBD_ERR (RXBD_LARGE | RXBD_SHORT | RXBD_NONOCTET \
428 | RXBD_CRCERR | RXBD_OVERRUN \
431 /* Rx FCB status field bits */
432 #define RXFCB_VLN 0x8000
433 #define RXFCB_IP 0x4000
434 #define RXFCB_IP6 0x2000
435 #define RXFCB_TUP 0x1000
436 #define RXFCB_CIP 0x0800
437 #define RXFCB_CTU 0x0400
438 #define RXFCB_EIP 0x0200
439 #define RXFCB_ETU 0x0100
440 #define RXFCB_CSUM_MASK 0x0f00
441 #define RXFCB_PERR_MASK 0x000c
442 #define RXFCB_PERR_BADL3 0x0008
444 #define GFAR_INT_NAME_MAX IFNAMSIZ + 4
450 u16 status; /* Status Fields */
451 u16 length; /* Buffer length */
455 u32 bufPtr; /* Buffer Pointer */
461 u8 l4os; /* Level 4 Header Offset */
462 u8 l3os; /* Level 3 Header Offset */
463 u16 phcs; /* Pseudo-header Checksum */
464 u16 vlctl; /* VLAN control word */
471 u16 status; /* Status Fields */
472 u16 length; /* Buffer Length */
476 u32 bufPtr; /* Buffer Pointer */
481 u8 rq; /* Receive Queue index */
482 u8 pro; /* Layer 4 Protocol */
484 u16 vlctl; /* VLAN control word */
489 u32 tr64; /* 0x.680 - Transmit and Receive 64-byte Frame Counter */
490 u32 tr127; /* 0x.684 - Transmit and Receive 65-127 byte Frame Counter */
491 u32 tr255; /* 0x.688 - Transmit and Receive 128-255 byte Frame Counter */
492 u32 tr511; /* 0x.68c - Transmit and Receive 256-511 byte Frame Counter */
493 u32 tr1k; /* 0x.690 - Transmit and Receive 512-1023 byte Frame Counter */
494 u32 trmax; /* 0x.694 - Transmit and Receive 1024-1518 byte Frame Counter */
495 u32 trmgv; /* 0x.698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */
496 u32 rbyt; /* 0x.69c - Receive Byte Counter */
497 u32 rpkt; /* 0x.6a0 - Receive Packet Counter */
498 u32 rfcs; /* 0x.6a4 - Receive FCS Error Counter */
499 u32 rmca; /* 0x.6a8 - Receive Multicast Packet Counter */
500 u32 rbca; /* 0x.6ac - Receive Broadcast Packet Counter */
501 u32 rxcf; /* 0x.6b0 - Receive Control Frame Packet Counter */
502 u32 rxpf; /* 0x.6b4 - Receive Pause Frame Packet Counter */
503 u32 rxuo; /* 0x.6b8 - Receive Unknown OP Code Counter */
504 u32 raln; /* 0x.6bc - Receive Alignment Error Counter */
505 u32 rflr; /* 0x.6c0 - Receive Frame Length Error Counter */
506 u32 rcde; /* 0x.6c4 - Receive Code Error Counter */
507 u32 rcse; /* 0x.6c8 - Receive Carrier Sense Error Counter */
508 u32 rund; /* 0x.6cc - Receive Undersize Packet Counter */
509 u32 rovr; /* 0x.6d0 - Receive Oversize Packet Counter */
510 u32 rfrg; /* 0x.6d4 - Receive Fragments Counter */
511 u32 rjbr; /* 0x.6d8 - Receive Jabber Counter */
512 u32 rdrp; /* 0x.6dc - Receive Drop Counter */
513 u32 tbyt; /* 0x.6e0 - Transmit Byte Counter Counter */
514 u32 tpkt; /* 0x.6e4 - Transmit Packet Counter */
515 u32 tmca; /* 0x.6e8 - Transmit Multicast Packet Counter */
516 u32 tbca; /* 0x.6ec - Transmit Broadcast Packet Counter */
517 u32 txpf; /* 0x.6f0 - Transmit Pause Control Frame Counter */
518 u32 tdfr; /* 0x.6f4 - Transmit Deferral Packet Counter */
519 u32 tedf; /* 0x.6f8 - Transmit Excessive Deferral Packet Counter */
520 u32 tscl; /* 0x.6fc - Transmit Single Collision Packet Counter */
521 u32 tmcl; /* 0x.700 - Transmit Multiple Collision Packet Counter */
522 u32 tlcl; /* 0x.704 - Transmit Late Collision Packet Counter */
523 u32 txcl; /* 0x.708 - Transmit Excessive Collision Packet Counter */
524 u32 tncl; /* 0x.70c - Transmit Total Collision Counter */
526 u32 tdrp; /* 0x.714 - Transmit Drop Frame Counter */
527 u32 tjbr; /* 0x.718 - Transmit Jabber Frame Counter */
528 u32 tfcs; /* 0x.71c - Transmit FCS Error Counter */
529 u32 txcf; /* 0x.720 - Transmit Control Frame Counter */
530 u32 tovr; /* 0x.724 - Transmit Oversize Frame Counter */
531 u32 tund; /* 0x.728 - Transmit Undersize Frame Counter */
532 u32 tfrg; /* 0x.72c - Transmit Fragments Frame Counter */
533 u32 car1; /* 0x.730 - Carry Register One */
534 u32 car2; /* 0x.734 - Carry Register Two */
535 u32 cam1; /* 0x.738 - Carry Mask Register One */
536 u32 cam2; /* 0x.73c - Carry Mask Register Two */
539 struct gfar_extra_stats {
556 #define GFAR_RMON_LEN ((sizeof(struct rmon_mib) - 16)/sizeof(u32))
557 #define GFAR_EXTRA_STATS_LEN (sizeof(struct gfar_extra_stats)/sizeof(u64))
559 /* Number of stats in the stats structure (ignore car and cam regs)*/
560 #define GFAR_STATS_LEN (GFAR_RMON_LEN + GFAR_EXTRA_STATS_LEN)
562 #define GFAR_INFOSTR_LEN 32
565 u64 extra[GFAR_EXTRA_STATS_LEN];
566 u64 rmon[GFAR_RMON_LEN];
571 u32 tsec_id; /* 0x.000 - Controller ID register */
572 u32 tsec_id2; /* 0x.004 - Controller ID2 register */
574 u32 ievent; /* 0x.010 - Interrupt Event Register */
575 u32 imask; /* 0x.014 - Interrupt Mask Register */
576 u32 edis; /* 0x.018 - Error Disabled Register */
577 u32 emapg; /* 0x.01c - Group Error mapping register */
578 u32 ecntrl; /* 0x.020 - Ethernet Control Register */
579 u32 minflr; /* 0x.024 - Minimum Frame Length Register */
580 u32 ptv; /* 0x.028 - Pause Time Value Register */
581 u32 dmactrl; /* 0x.02c - DMA Control Register */
582 u32 tbipa; /* 0x.030 - TBI PHY Address Register */
584 u32 fifo_rx_pause; /* 0x.050 - FIFO receive pause start threshold
586 u32 fifo_rx_pause_shutoff; /* x.054 - FIFO receive starve shutoff
588 u32 fifo_rx_alarm; /* 0x.058 - FIFO receive alarm start threshold
590 u32 fifo_rx_alarm_shutoff; /*0x.05c - FIFO receive alarm starve
593 u32 fifo_tx_thr; /* 0x.08c - FIFO transmit threshold register */
595 u32 fifo_tx_starve; /* 0x.098 - FIFO transmit starve register */
596 u32 fifo_tx_starve_shutoff; /* 0x.09c - FIFO transmit starve shutoff register */
598 u32 tctrl; /* 0x.100 - Transmit Control Register */
599 u32 tstat; /* 0x.104 - Transmit Status Register */
600 u32 dfvlan; /* 0x.108 - Default VLAN Control word */
601 u32 tbdlen; /* 0x.10c - Transmit Buffer Descriptor Data Length Register */
602 u32 txic; /* 0x.110 - Transmit Interrupt Coalescing Configuration Register */
603 u32 tqueue; /* 0x.114 - Transmit queue control register */
605 u32 tr03wt; /* 0x.140 - TxBD Rings 0-3 round-robin weightings */
606 u32 tr47wt; /* 0x.144 - TxBD Rings 4-7 round-robin weightings */
608 u32 tbdbph; /* 0x.17c - Tx data buffer pointer high */
610 u32 tbptr0; /* 0x.184 - TxBD Pointer for ring 0 */
612 u32 tbptr1; /* 0x.18c - TxBD Pointer for ring 1 */
614 u32 tbptr2; /* 0x.194 - TxBD Pointer for ring 2 */
616 u32 tbptr3; /* 0x.19c - TxBD Pointer for ring 3 */
618 u32 tbptr4; /* 0x.1a4 - TxBD Pointer for ring 4 */
620 u32 tbptr5; /* 0x.1ac - TxBD Pointer for ring 5 */
622 u32 tbptr6; /* 0x.1b4 - TxBD Pointer for ring 6 */
624 u32 tbptr7; /* 0x.1bc - TxBD Pointer for ring 7 */
626 u32 tbaseh; /* 0x.200 - TxBD base address high */
627 u32 tbase0; /* 0x.204 - TxBD Base Address of ring 0 */
629 u32 tbase1; /* 0x.20c - TxBD Base Address of ring 1 */
631 u32 tbase2; /* 0x.214 - TxBD Base Address of ring 2 */
633 u32 tbase3; /* 0x.21c - TxBD Base Address of ring 3 */
635 u32 tbase4; /* 0x.224 - TxBD Base Address of ring 4 */
637 u32 tbase5; /* 0x.22c - TxBD Base Address of ring 5 */
639 u32 tbase6; /* 0x.234 - TxBD Base Address of ring 6 */
641 u32 tbase7; /* 0x.23c - TxBD Base Address of ring 7 */
643 u32 rctrl; /* 0x.300 - Receive Control Register */
644 u32 rstat; /* 0x.304 - Receive Status Register */
646 u32 rxic; /* 0x.310 - Receive Interrupt Coalescing Configuration Register */
647 u32 rqueue; /* 0x.314 - Receive queue control register */
648 u32 rir0; /* 0x.318 - Ring mapping register 0 */
649 u32 rir1; /* 0x.31c - Ring mapping register 1 */
650 u32 rir2; /* 0x.320 - Ring mapping register 2 */
651 u32 rir3; /* 0x.324 - Ring mapping register 3 */
653 u32 rbifx; /* 0x.330 - Receive bit field extract control register */
654 u32 rqfar; /* 0x.334 - Receive queue filing table address register */
655 u32 rqfcr; /* 0x.338 - Receive queue filing table control register */
656 u32 rqfpr; /* 0x.33c - Receive queue filing table property register */
657 u32 mrblr; /* 0x.340 - Maximum Receive Buffer Length Register */
659 u32 rbdbph; /* 0x.37c - Rx data buffer pointer high */
661 u32 rbptr0; /* 0x.384 - RxBD pointer for ring 0 */
663 u32 rbptr1; /* 0x.38c - RxBD pointer for ring 1 */
665 u32 rbptr2; /* 0x.394 - RxBD pointer for ring 2 */
667 u32 rbptr3; /* 0x.39c - RxBD pointer for ring 3 */
669 u32 rbptr4; /* 0x.3a4 - RxBD pointer for ring 4 */
671 u32 rbptr5; /* 0x.3ac - RxBD pointer for ring 5 */
673 u32 rbptr6; /* 0x.3b4 - RxBD pointer for ring 6 */
675 u32 rbptr7; /* 0x.3bc - RxBD pointer for ring 7 */
677 u32 rbaseh; /* 0x.400 - RxBD base address high */
678 u32 rbase0; /* 0x.404 - RxBD base address of ring 0 */
680 u32 rbase1; /* 0x.40c - RxBD base address of ring 1 */
682 u32 rbase2; /* 0x.414 - RxBD base address of ring 2 */
684 u32 rbase3; /* 0x.41c - RxBD base address of ring 3 */
686 u32 rbase4; /* 0x.424 - RxBD base address of ring 4 */
688 u32 rbase5; /* 0x.42c - RxBD base address of ring 5 */
690 u32 rbase6; /* 0x.434 - RxBD base address of ring 6 */
692 u32 rbase7; /* 0x.43c - RxBD base address of ring 7 */
694 u32 maccfg1; /* 0x.500 - MAC Configuration 1 Register */
695 u32 maccfg2; /* 0x.504 - MAC Configuration 2 Register */
696 u32 ipgifg; /* 0x.508 - Inter Packet Gap/Inter Frame Gap Register */
697 u32 hafdup; /* 0x.50c - Half Duplex Register */
698 u32 maxfrm; /* 0x.510 - Maximum Frame Length Register */
700 u8 gfar_mii_regs[24]; /* See gianfar_phy.h */
701 u32 ifctrl; /* 0x.538 - Interface control register */
702 u32 ifstat; /* 0x.53c - Interface Status Register */
703 u32 macstnaddr1; /* 0x.540 - Station Address Part 1 Register */
704 u32 macstnaddr2; /* 0x.544 - Station Address Part 2 Register */
705 u32 mac01addr1; /* 0x.548 - MAC exact match address 1, part 1 */
706 u32 mac01addr2; /* 0x.54c - MAC exact match address 1, part 2 */
707 u32 mac02addr1; /* 0x.550 - MAC exact match address 2, part 1 */
708 u32 mac02addr2; /* 0x.554 - MAC exact match address 2, part 2 */
709 u32 mac03addr1; /* 0x.558 - MAC exact match address 3, part 1 */
710 u32 mac03addr2; /* 0x.55c - MAC exact match address 3, part 2 */
711 u32 mac04addr1; /* 0x.560 - MAC exact match address 4, part 1 */
712 u32 mac04addr2; /* 0x.564 - MAC exact match address 4, part 2 */
713 u32 mac05addr1; /* 0x.568 - MAC exact match address 5, part 1 */
714 u32 mac05addr2; /* 0x.56c - MAC exact match address 5, part 2 */
715 u32 mac06addr1; /* 0x.570 - MAC exact match address 6, part 1 */
716 u32 mac06addr2; /* 0x.574 - MAC exact match address 6, part 2 */
717 u32 mac07addr1; /* 0x.578 - MAC exact match address 7, part 1 */
718 u32 mac07addr2; /* 0x.57c - MAC exact match address 7, part 2 */
719 u32 mac08addr1; /* 0x.580 - MAC exact match address 8, part 1 */
720 u32 mac08addr2; /* 0x.584 - MAC exact match address 8, part 2 */
721 u32 mac09addr1; /* 0x.588 - MAC exact match address 9, part 1 */
722 u32 mac09addr2; /* 0x.58c - MAC exact match address 9, part 2 */
723 u32 mac10addr1; /* 0x.590 - MAC exact match address 10, part 1*/
724 u32 mac10addr2; /* 0x.594 - MAC exact match address 10, part 2*/
725 u32 mac11addr1; /* 0x.598 - MAC exact match address 11, part 1*/
726 u32 mac11addr2; /* 0x.59c - MAC exact match address 11, part 2*/
727 u32 mac12addr1; /* 0x.5a0 - MAC exact match address 12, part 1*/
728 u32 mac12addr2; /* 0x.5a4 - MAC exact match address 12, part 2*/
729 u32 mac13addr1; /* 0x.5a8 - MAC exact match address 13, part 1*/
730 u32 mac13addr2; /* 0x.5ac - MAC exact match address 13, part 2*/
731 u32 mac14addr1; /* 0x.5b0 - MAC exact match address 14, part 1*/
732 u32 mac14addr2; /* 0x.5b4 - MAC exact match address 14, part 2*/
733 u32 mac15addr1; /* 0x.5b8 - MAC exact match address 15, part 1*/
734 u32 mac15addr2; /* 0x.5bc - MAC exact match address 15, part 2*/
736 struct rmon_mib rmon; /* 0x.680-0x.73c */
737 u32 rrej; /* 0x.740 - Receive filer rejected packet counter */
739 u32 igaddr0; /* 0x.800 - Indivdual/Group address register 0*/
740 u32 igaddr1; /* 0x.804 - Indivdual/Group address register 1*/
741 u32 igaddr2; /* 0x.808 - Indivdual/Group address register 2*/
742 u32 igaddr3; /* 0x.80c - Indivdual/Group address register 3*/
743 u32 igaddr4; /* 0x.810 - Indivdual/Group address register 4*/
744 u32 igaddr5; /* 0x.814 - Indivdual/Group address register 5*/
745 u32 igaddr6; /* 0x.818 - Indivdual/Group address register 6*/
746 u32 igaddr7; /* 0x.81c - Indivdual/Group address register 7*/
748 u32 gaddr0; /* 0x.880 - Group address register 0 */
749 u32 gaddr1; /* 0x.884 - Group address register 1 */
750 u32 gaddr2; /* 0x.888 - Group address register 2 */
751 u32 gaddr3; /* 0x.88c - Group address register 3 */
752 u32 gaddr4; /* 0x.890 - Group address register 4 */
753 u32 gaddr5; /* 0x.894 - Group address register 5 */
754 u32 gaddr6; /* 0x.898 - Group address register 6 */
755 u32 gaddr7; /* 0x.89c - Group address register 7 */
757 u32 fifocfg; /* 0x.a00 - FIFO interface config register */
760 u32 attr; /* 0x.bf8 - Attributes Register */
761 u32 attreli; /* 0x.bfc - Attributes Extract Length and Extract Index Register */
763 u32 isrg0; /* 0x.eb0 - Interrupt steering group 0 register */
764 u32 isrg1; /* 0x.eb4 - Interrupt steering group 1 register */
765 u32 isrg2; /* 0x.eb8 - Interrupt steering group 2 register */
766 u32 isrg3; /* 0x.ebc - Interrupt steering group 3 register */
768 u32 rxic0; /* 0x.ed0 - Ring 0 Rx interrupt coalescing */
769 u32 rxic1; /* 0x.ed4 - Ring 1 Rx interrupt coalescing */
770 u32 rxic2; /* 0x.ed8 - Ring 2 Rx interrupt coalescing */
771 u32 rxic3; /* 0x.edc - Ring 3 Rx interrupt coalescing */
772 u32 rxic4; /* 0x.ee0 - Ring 4 Rx interrupt coalescing */
773 u32 rxic5; /* 0x.ee4 - Ring 5 Rx interrupt coalescing */
774 u32 rxic6; /* 0x.ee8 - Ring 6 Rx interrupt coalescing */
775 u32 rxic7; /* 0x.eec - Ring 7 Rx interrupt coalescing */
777 u32 txic0; /* 0x.f10 - Ring 0 Tx interrupt coalescing */
778 u32 txic1; /* 0x.f14 - Ring 1 Tx interrupt coalescing */
779 u32 txic2; /* 0x.f18 - Ring 2 Tx interrupt coalescing */
780 u32 txic3; /* 0x.f1c - Ring 3 Tx interrupt coalescing */
781 u32 txic4; /* 0x.f20 - Ring 4 Tx interrupt coalescing */
782 u32 txic5; /* 0x.f24 - Ring 5 Tx interrupt coalescing */
783 u32 txic6; /* 0x.f28 - Ring 6 Tx interrupt coalescing */
784 u32 txic7; /* 0x.f2c - Ring 7 Tx interrupt coalescing */
788 /* Flags related to gianfar device features */
789 #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
790 #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
791 #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
792 #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
793 #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
794 #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
795 #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
796 #define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
797 #define FSL_GIANFAR_DEV_HAS_MAGIC_PACKET 0x00000100
798 #define FSL_GIANFAR_DEV_HAS_BD_STASHING 0x00000200
799 #define FSL_GIANFAR_DEV_HAS_BUF_STASHING 0x00000400
802 #define DEFAULT_MAPPING 0xAA
804 #define DEFAULT_MAPPING 0xFF
807 #define ISRG_SHIFT_TX 0x10
808 #define ISRG_SHIFT_RX 0x18
810 /* The same driver can operate in two modes */
811 /* SQ_SG_MODE: Single Queue Single Group Mode
812 * (Backward compatible mode)
813 * MQ_MG_MODE: Multi Queue Multi Group mode
821 * struct gfar_priv_tx_q - per tx queue structure
822 * @txlock: per queue tx spin lock
823 * @tx_skbuff:skb pointers
824 * @skb_curtx: to be used skb pointer
825 * @skb_dirtytx:the last used skb pointer
826 * @qindex: index of this queue
827 * @dev: back pointer to the dev structure
828 * @grp: back pointer to the group to which this queue belongs
829 * @tx_bd_base: First tx buffer descriptor
830 * @cur_tx: Next free ring entry
831 * @dirty_tx: First buffer in line to be transmitted
832 * @tx_ring_size: Tx ring size
833 * @num_txbdfree: number of free TxBds
834 * @txcoalescing: enable/disable tx coalescing
835 * @txic: transmit interrupt coalescing value
836 * @txcount: coalescing value if based on tx frame count
837 * @txtime: coalescing value if based on time
839 struct gfar_priv_tx_q {
840 spinlock_t txlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
841 struct sk_buff ** tx_skbuff;
842 /* Buffer descriptor pointers */
843 dma_addr_t tx_bd_dma_base;
844 struct txbd8 *tx_bd_base;
845 struct txbd8 *cur_tx;
846 struct txbd8 *dirty_tx;
847 struct net_device *dev;
848 struct gfar_priv_grp *grp;
852 unsigned int tx_ring_size;
853 unsigned int num_txbdfree;
854 /* Configuration info for the coalescing features */
855 unsigned char txcoalescing;
857 unsigned short txcount;
858 unsigned short txtime;
862 * struct gfar_priv_rx_q - per rx queue structure
863 * @rxlock: per queue rx spin lock
864 * @rx_skbuff: skb pointers
865 * @skb_currx: currently use skb pointer
866 * @rx_bd_base: First rx buffer descriptor
867 * @cur_rx: Next free rx ring entry
868 * @qindex: index of this queue
869 * @dev: back pointer to the dev structure
870 * @rx_ring_size: Rx ring size
871 * @rxcoalescing: enable/disable rx-coalescing
872 * @rxic: receive interrupt coalescing vlaue
875 struct gfar_priv_rx_q {
876 spinlock_t rxlock __attribute__ ((aligned (SMP_CACHE_BYTES)));
877 struct sk_buff ** rx_skbuff;
878 dma_addr_t rx_bd_dma_base;
879 struct rxbd8 *rx_bd_base;
880 struct rxbd8 *cur_rx;
881 struct net_device *dev;
882 struct gfar_priv_grp *grp;
885 unsigned int rx_ring_size;
886 /* RX Coalescing values */
887 unsigned char rxcoalescing;
892 * struct gfar_priv_grp - per group structure
893 * @napi: the napi poll function
894 * @priv: back pointer to the priv structure
895 * @regs: the ioremapped register space for this group
896 * @grp_id: group id for this group
897 * @interruptTransmit: The TX interrupt number for this group
898 * @interruptReceive: The RX interrupt number for this group
899 * @interruptError: The ERROR interrupt number for this group
900 * @int_name_tx: tx interrupt name for this group
901 * @int_name_rx: rx interrupt name for this group
902 * @int_name_er: er interrupt name for this group
905 struct gfar_priv_grp {
906 spinlock_t grplock __attribute__ ((aligned (SMP_CACHE_BYTES)));
907 struct napi_struct napi;
908 struct gfar_private *priv;
909 struct gfar __iomem *regs;
911 unsigned int rx_bit_map;
912 unsigned int tx_bit_map;
913 unsigned int num_tx_queues;
914 unsigned int num_rx_queues;
919 unsigned int interruptTransmit;
920 unsigned int interruptReceive;
921 unsigned int interruptError;
923 char int_name_tx[GFAR_INT_NAME_MAX];
924 char int_name_rx[GFAR_INT_NAME_MAX];
925 char int_name_er[GFAR_INT_NAME_MAX];
928 /* Struct stolen almost completely (and shamelessly) from the FCC enet source
929 * (Ok, that's not so true anymore, but there is a family resemblence)
930 * The GFAR buffer descriptors track the ring buffers. The rx_bd_base
931 * and tx_bd_base always point to the currently available buffer.
932 * The dirty_tx tracks the current buffer that is being sent by the
933 * controller. The cur_tx and dirty_tx are equal under both completely
934 * empty and completely full conditions. The empty/ready indicator in
935 * the buffer descriptor determines the actual condition.
937 struct gfar_private {
939 /* Indicates how many tx, rx queues are enabled */
940 unsigned int num_tx_queues;
941 unsigned int num_rx_queues;
942 unsigned int num_grps;
945 /* The total tx and rx ring size for the enabled queues */
946 unsigned int total_tx_ring_size;
947 unsigned int total_rx_ring_size;
949 struct device_node *node;
950 struct net_device *ndev;
951 struct of_device *ofdev;
953 struct gfar_priv_grp gfargrp[MAXGROUPS];
954 struct gfar_priv_tx_q *tx_queue[MAX_TX_QS];
955 struct gfar_priv_rx_q *rx_queue[MAX_RX_QS];
957 /* RX per device parameters */
958 unsigned int rx_buffer_size;
959 unsigned int rx_stash_size;
960 unsigned int rx_stash_index;
962 struct sk_buff_head rx_recycle;
964 struct vlan_group *vlgrp;
967 /* Hash registers and their width */
968 u32 __iomem *hash_regs[16];
971 /* global parameters */
972 unsigned int fifo_threshold;
973 unsigned int fifo_starve;
974 unsigned int fifo_starve_off;
976 /* Bitfield update lock */
979 phy_interface_t interface;
980 struct device_node *phy_node;
981 struct device_node *tbi_node;
983 unsigned char rx_csum_enable:1,
987 wol_en:1; /* Wake-on-LAN enabled */
988 unsigned short padding;
991 struct phy_device *phydev;
992 struct mii_bus *mii_bus;
999 struct work_struct reset_task;
1001 /* Network Statistics */
1002 struct gfar_extra_stats extra_stats;
1005 static inline u32 gfar_read(volatile unsigned __iomem *addr)
1008 val = in_be32(addr);
1012 static inline void gfar_write(volatile unsigned __iomem *addr, u32 val)
1014 out_be32(addr, val);
1017 extern void lock_rx_qs(struct gfar_private *priv);
1018 extern void lock_tx_qs(struct gfar_private *priv);
1019 extern void unlock_rx_qs(struct gfar_private *priv);
1020 extern void unlock_tx_qs(struct gfar_private *priv);
1021 extern irqreturn_t gfar_receive(int irq, void *dev_id);
1022 extern int startup_gfar(struct net_device *dev);
1023 extern void stop_gfar(struct net_device *dev);
1024 extern void gfar_halt(struct net_device *dev);
1025 extern void gfar_phy_test(struct mii_bus *bus, struct phy_device *phydev,
1026 int enable, u32 regnum, u32 read);
1027 extern void gfar_configure_coalescing(struct gfar_private *priv,
1028 unsigned int tx_mask, unsigned int rx_mask);
1029 void gfar_init_sysfs(struct net_device *dev);
1031 extern const struct ethtool_ops gfar_ethtool_ops;
1033 #endif /* __GIANFAR_H */