2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through platform_device. Structures which
29 * define the configuration needed by the board are defined in a
30 * board structure in arch/ppc/platforms (though I do not
31 * discount the possibility that other architectures could one
34 * The Gianfar Ethernet Controller uses a ring of buffer
35 * descriptors. The beginning is indicated by a register
36 * pointing to the physical address of the start of the ring.
37 * The end is determined by a "wrap" bit being set in the
38 * last descriptor of the ring.
40 * When a packet is received, the RXF bit in the
41 * IEVENT register is set, triggering an interrupt when the
42 * corresponding bit in the IMASK register is also set (if
43 * interrupt coalescing is active, then the interrupt may not
44 * happen immediately, but will wait until either a set number
45 * of frames or amount of time have passed). In NAPI, the
46 * interrupt handler will signal there is work to be done, and
47 * exit. This method will start at the last known empty
48 * descriptor, and process every subsequent descriptor until there
49 * are none left with data (NAPI will stop after a set number of
50 * packets to give time to other tasks, but will eventually
51 * process all the packets). The data arrives inside a
52 * pre-allocated skb, and so after the skb is passed up to the
53 * stack, a new skb must be allocated, and the address field in
54 * the buffer descriptor must be updated to indicate this new
57 * When the kernel requests that a packet be transmitted, the
58 * driver starts where it left off last time, and points the
59 * descriptor at the buffer which was passed in. The driver
60 * then informs the DMA engine that there are packets ready to
61 * be transmitted. Once the controller is finished transmitting
62 * the packet, an interrupt may be triggered (under the same
63 * conditions as for reception, but depending on the TXF bit).
64 * The driver then cleans up the buffer.
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
81 #include <linux/platform_device.h>
83 #include <linux/tcp.h>
84 #include <linux/udp.h>
89 #include <asm/uaccess.h>
90 #include <linux/module.h>
91 #include <linux/dma-mapping.h>
92 #include <linux/crc32.h>
93 #include <linux/mii.h>
94 #include <linux/phy.h>
97 #include "gianfar_mii.h"
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
103 const char gfar_driver_name[] = "Gianfar Ethernet";
104 const char gfar_driver_version[] = "1.3";
106 static int gfar_enet_open(struct net_device *dev);
107 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev);
108 static void gfar_reset_task(struct work_struct *work);
109 static void gfar_timeout(struct net_device *dev);
110 static int gfar_close(struct net_device *dev);
111 struct sk_buff *gfar_new_skb(struct net_device *dev);
112 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
113 struct sk_buff *skb);
114 static int gfar_set_mac_address(struct net_device *dev);
115 static int gfar_change_mtu(struct net_device *dev, int new_mtu);
116 static irqreturn_t gfar_error(int irq, void *dev_id);
117 static irqreturn_t gfar_transmit(int irq, void *dev_id);
118 static irqreturn_t gfar_interrupt(int irq, void *dev_id);
119 static void adjust_link(struct net_device *dev);
120 static void init_registers(struct net_device *dev);
121 static int init_phy(struct net_device *dev);
122 static int gfar_probe(struct platform_device *pdev);
123 static int gfar_remove(struct platform_device *pdev);
124 static void free_skb_resources(struct gfar_private *priv);
125 static void gfar_set_multi(struct net_device *dev);
126 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr);
127 static void gfar_configure_serdes(struct net_device *dev);
128 static int gfar_poll(struct napi_struct *napi, int budget);
129 #ifdef CONFIG_NET_POLL_CONTROLLER
130 static void gfar_netpoll(struct net_device *dev);
132 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit);
133 static int gfar_clean_tx_ring(struct net_device *dev);
134 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb, int length);
135 static void gfar_vlan_rx_register(struct net_device *netdev,
136 struct vlan_group *grp);
137 void gfar_halt(struct net_device *dev);
138 static void gfar_halt_nodisable(struct net_device *dev);
139 void gfar_start(struct net_device *dev);
140 static void gfar_clear_exact_match(struct net_device *dev);
141 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr);
143 extern const struct ethtool_ops gfar_ethtool_ops;
145 MODULE_AUTHOR("Freescale Semiconductor, Inc");
146 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
147 MODULE_LICENSE("GPL");
149 /* Returns 1 if incoming frames use an FCB */
150 static inline int gfar_uses_fcb(struct gfar_private *priv)
152 return (priv->vlan_enable || priv->rx_csum_enable);
155 /* Set up the ethernet device structure, private data,
156 * and anything else we need before we start */
157 static int gfar_probe(struct platform_device *pdev)
160 struct net_device *dev = NULL;
161 struct gfar_private *priv = NULL;
162 struct gianfar_platform_data *einfo;
166 einfo = (struct gianfar_platform_data *) pdev->dev.platform_data;
169 printk(KERN_ERR "gfar %d: Missing additional data!\n",
175 /* Create an ethernet device instance */
176 dev = alloc_etherdev(sizeof (*priv));
181 priv = netdev_priv(dev);
184 /* Set the info in the priv to the current info */
187 /* fill out IRQ fields */
188 if (einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
189 irq = platform_get_irq_byname(pdev, "tx");
192 priv->interruptTransmit = irq;
194 irq = platform_get_irq_byname(pdev, "rx");
197 priv->interruptReceive = irq;
199 irq = platform_get_irq_byname(pdev, "error");
202 priv->interruptError = irq;
204 irq = platform_get_irq(pdev, 0);
207 priv->interruptTransmit = irq;
210 /* get a pointer to the register memory */
211 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
212 priv->regs = ioremap(r->start, sizeof (struct gfar));
214 if (NULL == priv->regs) {
219 spin_lock_init(&priv->txlock);
220 spin_lock_init(&priv->rxlock);
221 spin_lock_init(&priv->bflock);
222 INIT_WORK(&priv->reset_task, gfar_reset_task);
224 platform_set_drvdata(pdev, dev);
226 /* Stop the DMA engine now, in case it was running before */
227 /* (The firmware could have used it, and left it running). */
228 /* To do this, we write Graceful Receive Stop and Graceful */
229 /* Transmit Stop, and then wait until the corresponding bits */
230 /* in IEVENT indicate the stops have completed. */
231 tempval = gfar_read(&priv->regs->dmactrl);
232 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
233 gfar_write(&priv->regs->dmactrl, tempval);
235 tempval = gfar_read(&priv->regs->dmactrl);
236 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
237 gfar_write(&priv->regs->dmactrl, tempval);
239 while (!(gfar_read(&priv->regs->ievent) & (IEVENT_GRSC | IEVENT_GTSC)))
242 /* Reset MAC layer */
243 gfar_write(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
245 tempval = (MACCFG1_TX_FLOW | MACCFG1_RX_FLOW);
246 gfar_write(&priv->regs->maccfg1, tempval);
248 /* Initialize MACCFG2. */
249 gfar_write(&priv->regs->maccfg2, MACCFG2_INIT_SETTINGS);
251 /* Initialize ECNTRL */
252 gfar_write(&priv->regs->ecntrl, ECNTRL_INIT_SETTINGS);
254 /* Copy the station address into the dev structure, */
255 memcpy(dev->dev_addr, einfo->mac_addr, MAC_ADDR_LEN);
257 /* Set the dev->base_addr to the gfar reg region */
258 dev->base_addr = (unsigned long) (priv->regs);
260 SET_NETDEV_DEV(dev, &pdev->dev);
262 /* Fill in the dev structure */
263 dev->open = gfar_enet_open;
264 dev->hard_start_xmit = gfar_start_xmit;
265 dev->tx_timeout = gfar_timeout;
266 dev->watchdog_timeo = TX_TIMEOUT;
267 netif_napi_add(dev, &priv->napi, gfar_poll, GFAR_DEV_WEIGHT);
268 #ifdef CONFIG_NET_POLL_CONTROLLER
269 dev->poll_controller = gfar_netpoll;
271 dev->stop = gfar_close;
272 dev->change_mtu = gfar_change_mtu;
274 dev->set_multicast_list = gfar_set_multi;
276 dev->ethtool_ops = &gfar_ethtool_ops;
278 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_CSUM) {
279 priv->rx_csum_enable = 1;
280 dev->features |= NETIF_F_IP_CSUM;
282 priv->rx_csum_enable = 0;
286 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_VLAN) {
287 dev->vlan_rx_register = gfar_vlan_rx_register;
289 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
291 priv->vlan_enable = 1;
294 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_EXTENDED_HASH) {
295 priv->extended_hash = 1;
296 priv->hash_width = 9;
298 priv->hash_regs[0] = &priv->regs->igaddr0;
299 priv->hash_regs[1] = &priv->regs->igaddr1;
300 priv->hash_regs[2] = &priv->regs->igaddr2;
301 priv->hash_regs[3] = &priv->regs->igaddr3;
302 priv->hash_regs[4] = &priv->regs->igaddr4;
303 priv->hash_regs[5] = &priv->regs->igaddr5;
304 priv->hash_regs[6] = &priv->regs->igaddr6;
305 priv->hash_regs[7] = &priv->regs->igaddr7;
306 priv->hash_regs[8] = &priv->regs->gaddr0;
307 priv->hash_regs[9] = &priv->regs->gaddr1;
308 priv->hash_regs[10] = &priv->regs->gaddr2;
309 priv->hash_regs[11] = &priv->regs->gaddr3;
310 priv->hash_regs[12] = &priv->regs->gaddr4;
311 priv->hash_regs[13] = &priv->regs->gaddr5;
312 priv->hash_regs[14] = &priv->regs->gaddr6;
313 priv->hash_regs[15] = &priv->regs->gaddr7;
316 priv->extended_hash = 0;
317 priv->hash_width = 8;
319 priv->hash_regs[0] = &priv->regs->gaddr0;
320 priv->hash_regs[1] = &priv->regs->gaddr1;
321 priv->hash_regs[2] = &priv->regs->gaddr2;
322 priv->hash_regs[3] = &priv->regs->gaddr3;
323 priv->hash_regs[4] = &priv->regs->gaddr4;
324 priv->hash_regs[5] = &priv->regs->gaddr5;
325 priv->hash_regs[6] = &priv->regs->gaddr6;
326 priv->hash_regs[7] = &priv->regs->gaddr7;
329 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_PADDING)
330 priv->padding = DEFAULT_PADDING;
334 if (dev->features & NETIF_F_IP_CSUM)
335 dev->hard_header_len += GMAC_FCB_LEN;
337 priv->rx_buffer_size = DEFAULT_RX_BUFFER_SIZE;
338 priv->tx_ring_size = DEFAULT_TX_RING_SIZE;
339 priv->rx_ring_size = DEFAULT_RX_RING_SIZE;
341 priv->txcoalescing = DEFAULT_TX_COALESCE;
342 priv->txcount = DEFAULT_TXCOUNT;
343 priv->txtime = DEFAULT_TXTIME;
344 priv->rxcoalescing = DEFAULT_RX_COALESCE;
345 priv->rxcount = DEFAULT_RXCOUNT;
346 priv->rxtime = DEFAULT_RXTIME;
348 /* Enable most messages by default */
349 priv->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
351 /* Carrier starts down, phylib will bring it up */
352 netif_carrier_off(dev);
354 err = register_netdev(dev);
357 printk(KERN_ERR "%s: Cannot register net device, aborting.\n",
362 /* Create all the sysfs files */
363 gfar_init_sysfs(dev);
365 /* Print out the device info */
366 printk(KERN_INFO DEVICE_NAME "%pM\n", dev->name, dev->dev_addr);
368 /* Even more device info helps when determining which kernel */
369 /* provided which set of benchmarks. */
370 printk(KERN_INFO "%s: Running with NAPI enabled\n", dev->name);
371 printk(KERN_INFO "%s: %d/%d RX/TX BD ring size\n",
372 dev->name, priv->rx_ring_size, priv->tx_ring_size);
383 static int gfar_remove(struct platform_device *pdev)
385 struct net_device *dev = platform_get_drvdata(pdev);
386 struct gfar_private *priv = netdev_priv(dev);
388 platform_set_drvdata(pdev, NULL);
397 static int gfar_suspend(struct platform_device *pdev, pm_message_t state)
399 struct net_device *dev = platform_get_drvdata(pdev);
400 struct gfar_private *priv = netdev_priv(dev);
404 int magic_packet = priv->wol_en &&
405 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
407 netif_device_detach(dev);
409 if (netif_running(dev)) {
410 spin_lock_irqsave(&priv->txlock, flags);
411 spin_lock(&priv->rxlock);
413 gfar_halt_nodisable(dev);
415 /* Disable Tx, and Rx if wake-on-LAN is disabled. */
416 tempval = gfar_read(&priv->regs->maccfg1);
418 tempval &= ~MACCFG1_TX_EN;
421 tempval &= ~MACCFG1_RX_EN;
423 gfar_write(&priv->regs->maccfg1, tempval);
425 spin_unlock(&priv->rxlock);
426 spin_unlock_irqrestore(&priv->txlock, flags);
428 napi_disable(&priv->napi);
431 /* Enable interrupt on Magic Packet */
432 gfar_write(&priv->regs->imask, IMASK_MAG);
434 /* Enable Magic Packet mode */
435 tempval = gfar_read(&priv->regs->maccfg2);
436 tempval |= MACCFG2_MPEN;
437 gfar_write(&priv->regs->maccfg2, tempval);
439 phy_stop(priv->phydev);
446 static int gfar_resume(struct platform_device *pdev)
448 struct net_device *dev = platform_get_drvdata(pdev);
449 struct gfar_private *priv = netdev_priv(dev);
452 int magic_packet = priv->wol_en &&
453 (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET);
455 if (!netif_running(dev)) {
456 netif_device_attach(dev);
460 if (!magic_packet && priv->phydev)
461 phy_start(priv->phydev);
463 /* Disable Magic Packet mode, in case something
467 spin_lock_irqsave(&priv->txlock, flags);
468 spin_lock(&priv->rxlock);
470 tempval = gfar_read(&priv->regs->maccfg2);
471 tempval &= ~MACCFG2_MPEN;
472 gfar_write(&priv->regs->maccfg2, tempval);
476 spin_unlock(&priv->rxlock);
477 spin_unlock_irqrestore(&priv->txlock, flags);
479 netif_device_attach(dev);
481 napi_enable(&priv->napi);
486 #define gfar_suspend NULL
487 #define gfar_resume NULL
490 /* Reads the controller's registers to determine what interface
491 * connects it to the PHY.
493 static phy_interface_t gfar_get_interface(struct net_device *dev)
495 struct gfar_private *priv = netdev_priv(dev);
496 u32 ecntrl = gfar_read(&priv->regs->ecntrl);
498 if (ecntrl & ECNTRL_SGMII_MODE)
499 return PHY_INTERFACE_MODE_SGMII;
501 if (ecntrl & ECNTRL_TBI_MODE) {
502 if (ecntrl & ECNTRL_REDUCED_MODE)
503 return PHY_INTERFACE_MODE_RTBI;
505 return PHY_INTERFACE_MODE_TBI;
508 if (ecntrl & ECNTRL_REDUCED_MODE) {
509 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
510 return PHY_INTERFACE_MODE_RMII;
512 phy_interface_t interface = priv->einfo->interface;
515 * This isn't autodetected right now, so it must
516 * be set by the device tree or platform code.
518 if (interface == PHY_INTERFACE_MODE_RGMII_ID)
519 return PHY_INTERFACE_MODE_RGMII_ID;
521 return PHY_INTERFACE_MODE_RGMII;
525 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT)
526 return PHY_INTERFACE_MODE_GMII;
528 return PHY_INTERFACE_MODE_MII;
532 /* Initializes driver's PHY state, and attaches to the PHY.
533 * Returns 0 on success.
535 static int init_phy(struct net_device *dev)
537 struct gfar_private *priv = netdev_priv(dev);
538 uint gigabit_support =
539 priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_GIGABIT ?
540 SUPPORTED_1000baseT_Full : 0;
541 struct phy_device *phydev;
542 char phy_id[BUS_ID_SIZE];
543 phy_interface_t interface;
547 priv->oldduplex = -1;
549 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, priv->einfo->bus_id, priv->einfo->phy_id);
551 interface = gfar_get_interface(dev);
553 phydev = phy_connect(dev, phy_id, &adjust_link, 0, interface);
555 if (interface == PHY_INTERFACE_MODE_SGMII)
556 gfar_configure_serdes(dev);
558 if (IS_ERR(phydev)) {
559 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
560 return PTR_ERR(phydev);
563 /* Remove any features not supported by the controller */
564 phydev->supported &= (GFAR_SUPPORTED | gigabit_support);
565 phydev->advertising = phydev->supported;
567 priv->phydev = phydev;
573 * Initialize TBI PHY interface for communicating with the
574 * SERDES lynx PHY on the chip. We communicate with this PHY
575 * through the MDIO bus on each controller, treating it as a
576 * "normal" PHY at the address found in the TBIPA register. We assume
577 * that the TBIPA register is valid. Either the MDIO bus code will set
578 * it to a value that doesn't conflict with other PHYs on the bus, or the
579 * value doesn't matter, as there are no other PHYs on the bus.
581 static void gfar_configure_serdes(struct net_device *dev)
583 struct gfar_private *priv = netdev_priv(dev);
584 struct gfar_mii __iomem *regs =
585 (void __iomem *)&priv->regs->gfar_mii_regs;
586 int tbipa = gfar_read(&priv->regs->tbipa);
588 /* Single clk mode, mii mode off(for serdes communication) */
589 gfar_local_mdio_write(regs, tbipa, MII_TBICON, TBICON_CLK_SELECT);
591 gfar_local_mdio_write(regs, tbipa, MII_ADVERTISE,
592 ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
593 ADVERTISE_1000XPSE_ASYM);
595 gfar_local_mdio_write(regs, tbipa, MII_BMCR, BMCR_ANENABLE |
596 BMCR_ANRESTART | BMCR_FULLDPLX | BMCR_SPEED1000);
599 static void init_registers(struct net_device *dev)
601 struct gfar_private *priv = netdev_priv(dev);
604 gfar_write(&priv->regs->ievent, IEVENT_INIT_CLEAR);
606 /* Initialize IMASK */
607 gfar_write(&priv->regs->imask, IMASK_INIT_CLEAR);
609 /* Init hash registers to zero */
610 gfar_write(&priv->regs->igaddr0, 0);
611 gfar_write(&priv->regs->igaddr1, 0);
612 gfar_write(&priv->regs->igaddr2, 0);
613 gfar_write(&priv->regs->igaddr3, 0);
614 gfar_write(&priv->regs->igaddr4, 0);
615 gfar_write(&priv->regs->igaddr5, 0);
616 gfar_write(&priv->regs->igaddr6, 0);
617 gfar_write(&priv->regs->igaddr7, 0);
619 gfar_write(&priv->regs->gaddr0, 0);
620 gfar_write(&priv->regs->gaddr1, 0);
621 gfar_write(&priv->regs->gaddr2, 0);
622 gfar_write(&priv->regs->gaddr3, 0);
623 gfar_write(&priv->regs->gaddr4, 0);
624 gfar_write(&priv->regs->gaddr5, 0);
625 gfar_write(&priv->regs->gaddr6, 0);
626 gfar_write(&priv->regs->gaddr7, 0);
628 /* Zero out the rmon mib registers if it has them */
629 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_RMON) {
630 memset_io(&(priv->regs->rmon), 0, sizeof (struct rmon_mib));
632 /* Mask off the CAM interrupts */
633 gfar_write(&priv->regs->rmon.cam1, 0xffffffff);
634 gfar_write(&priv->regs->rmon.cam2, 0xffffffff);
637 /* Initialize the max receive buffer length */
638 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
640 /* Initialize the Minimum Frame Length Register */
641 gfar_write(&priv->regs->minflr, MINFLR_INIT_SETTINGS);
645 /* Halt the receive and transmit queues */
646 static void gfar_halt_nodisable(struct net_device *dev)
648 struct gfar_private *priv = netdev_priv(dev);
649 struct gfar __iomem *regs = priv->regs;
652 /* Mask all interrupts */
653 gfar_write(®s->imask, IMASK_INIT_CLEAR);
655 /* Clear all interrupts */
656 gfar_write(®s->ievent, IEVENT_INIT_CLEAR);
658 /* Stop the DMA, and wait for it to stop */
659 tempval = gfar_read(&priv->regs->dmactrl);
660 if ((tempval & (DMACTRL_GRS | DMACTRL_GTS))
661 != (DMACTRL_GRS | DMACTRL_GTS)) {
662 tempval |= (DMACTRL_GRS | DMACTRL_GTS);
663 gfar_write(&priv->regs->dmactrl, tempval);
665 while (!(gfar_read(&priv->regs->ievent) &
666 (IEVENT_GRSC | IEVENT_GTSC)))
671 /* Halt the receive and transmit queues */
672 void gfar_halt(struct net_device *dev)
674 struct gfar_private *priv = netdev_priv(dev);
675 struct gfar __iomem *regs = priv->regs;
678 gfar_halt_nodisable(dev);
680 /* Disable Rx and Tx */
681 tempval = gfar_read(®s->maccfg1);
682 tempval &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
683 gfar_write(®s->maccfg1, tempval);
686 void stop_gfar(struct net_device *dev)
688 struct gfar_private *priv = netdev_priv(dev);
689 struct gfar __iomem *regs = priv->regs;
692 phy_stop(priv->phydev);
695 spin_lock_irqsave(&priv->txlock, flags);
696 spin_lock(&priv->rxlock);
700 spin_unlock(&priv->rxlock);
701 spin_unlock_irqrestore(&priv->txlock, flags);
704 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
705 free_irq(priv->interruptError, dev);
706 free_irq(priv->interruptTransmit, dev);
707 free_irq(priv->interruptReceive, dev);
709 free_irq(priv->interruptTransmit, dev);
712 free_skb_resources(priv);
714 dma_free_coherent(&dev->dev,
715 sizeof(struct txbd8)*priv->tx_ring_size
716 + sizeof(struct rxbd8)*priv->rx_ring_size,
718 gfar_read(®s->tbase0));
721 /* If there are any tx skbs or rx skbs still around, free them.
722 * Then free tx_skbuff and rx_skbuff */
723 static void free_skb_resources(struct gfar_private *priv)
729 /* Go through all the buffer descriptors and free their data buffers */
730 txbdp = priv->tx_bd_base;
732 for (i = 0; i < priv->tx_ring_size; i++) {
734 if (priv->tx_skbuff[i]) {
735 dma_unmap_single(&priv->dev->dev, txbdp->bufPtr,
738 dev_kfree_skb_any(priv->tx_skbuff[i]);
739 priv->tx_skbuff[i] = NULL;
745 kfree(priv->tx_skbuff);
747 rxbdp = priv->rx_bd_base;
749 /* rx_skbuff is not guaranteed to be allocated, so only
750 * free it and its contents if it is allocated */
751 if(priv->rx_skbuff != NULL) {
752 for (i = 0; i < priv->rx_ring_size; i++) {
753 if (priv->rx_skbuff[i]) {
754 dma_unmap_single(&priv->dev->dev, rxbdp->bufPtr,
755 priv->rx_buffer_size,
758 dev_kfree_skb_any(priv->rx_skbuff[i]);
759 priv->rx_skbuff[i] = NULL;
769 kfree(priv->rx_skbuff);
773 void gfar_start(struct net_device *dev)
775 struct gfar_private *priv = netdev_priv(dev);
776 struct gfar __iomem *regs = priv->regs;
779 /* Enable Rx and Tx in MACCFG1 */
780 tempval = gfar_read(®s->maccfg1);
781 tempval |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
782 gfar_write(®s->maccfg1, tempval);
784 /* Initialize DMACTRL to have WWR and WOP */
785 tempval = gfar_read(&priv->regs->dmactrl);
786 tempval |= DMACTRL_INIT_SETTINGS;
787 gfar_write(&priv->regs->dmactrl, tempval);
789 /* Make sure we aren't stopped */
790 tempval = gfar_read(&priv->regs->dmactrl);
791 tempval &= ~(DMACTRL_GRS | DMACTRL_GTS);
792 gfar_write(&priv->regs->dmactrl, tempval);
794 /* Clear THLT/RHLT, so that the DMA starts polling now */
795 gfar_write(®s->tstat, TSTAT_CLEAR_THALT);
796 gfar_write(®s->rstat, RSTAT_CLEAR_RHALT);
798 /* Unmask the interrupts we look for */
799 gfar_write(®s->imask, IMASK_DEFAULT);
802 /* Bring the controller up and running */
803 int startup_gfar(struct net_device *dev)
810 struct gfar_private *priv = netdev_priv(dev);
811 struct gfar __iomem *regs = priv->regs;
816 gfar_write(®s->imask, IMASK_INIT_CLEAR);
818 /* Allocate memory for the buffer descriptors */
819 vaddr = (unsigned long) dma_alloc_coherent(&dev->dev,
820 sizeof (struct txbd8) * priv->tx_ring_size +
821 sizeof (struct rxbd8) * priv->rx_ring_size,
825 if (netif_msg_ifup(priv))
826 printk(KERN_ERR "%s: Could not allocate buffer descriptors!\n",
831 priv->tx_bd_base = (struct txbd8 *) vaddr;
833 /* enet DMA only understands physical addresses */
834 gfar_write(®s->tbase0, addr);
836 /* Start the rx descriptor ring where the tx ring leaves off */
837 addr = addr + sizeof (struct txbd8) * priv->tx_ring_size;
838 vaddr = vaddr + sizeof (struct txbd8) * priv->tx_ring_size;
839 priv->rx_bd_base = (struct rxbd8 *) vaddr;
840 gfar_write(®s->rbase0, addr);
842 /* Setup the skbuff rings */
844 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
845 priv->tx_ring_size, GFP_KERNEL);
847 if (NULL == priv->tx_skbuff) {
848 if (netif_msg_ifup(priv))
849 printk(KERN_ERR "%s: Could not allocate tx_skbuff\n",
855 for (i = 0; i < priv->tx_ring_size; i++)
856 priv->tx_skbuff[i] = NULL;
859 (struct sk_buff **) kmalloc(sizeof (struct sk_buff *) *
860 priv->rx_ring_size, GFP_KERNEL);
862 if (NULL == priv->rx_skbuff) {
863 if (netif_msg_ifup(priv))
864 printk(KERN_ERR "%s: Could not allocate rx_skbuff\n",
870 for (i = 0; i < priv->rx_ring_size; i++)
871 priv->rx_skbuff[i] = NULL;
873 /* Initialize some variables in our dev structure */
874 priv->dirty_tx = priv->cur_tx = priv->tx_bd_base;
875 priv->cur_rx = priv->rx_bd_base;
876 priv->skb_curtx = priv->skb_dirtytx = 0;
879 /* Initialize Transmit Descriptor Ring */
880 txbdp = priv->tx_bd_base;
881 for (i = 0; i < priv->tx_ring_size; i++) {
888 /* Set the last descriptor in the ring to indicate wrap */
890 txbdp->status |= TXBD_WRAP;
892 rxbdp = priv->rx_bd_base;
893 for (i = 0; i < priv->rx_ring_size; i++) {
896 skb = gfar_new_skb(dev);
899 printk(KERN_ERR "%s: Can't allocate RX buffers\n",
902 goto err_rxalloc_fail;
905 priv->rx_skbuff[i] = skb;
907 gfar_new_rxbdp(dev, rxbdp, skb);
912 /* Set the last descriptor in the ring to wrap */
914 rxbdp->status |= RXBD_WRAP;
916 /* If the device has multiple interrupts, register for
917 * them. Otherwise, only register for the one */
918 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
919 /* Install our interrupt handlers for Error,
920 * Transmit, and Receive */
921 if (request_irq(priv->interruptError, gfar_error,
922 0, "enet_error", dev) < 0) {
923 if (netif_msg_intr(priv))
924 printk(KERN_ERR "%s: Can't get IRQ %d\n",
925 dev->name, priv->interruptError);
931 if (request_irq(priv->interruptTransmit, gfar_transmit,
932 0, "enet_tx", dev) < 0) {
933 if (netif_msg_intr(priv))
934 printk(KERN_ERR "%s: Can't get IRQ %d\n",
935 dev->name, priv->interruptTransmit);
942 if (request_irq(priv->interruptReceive, gfar_receive,
943 0, "enet_rx", dev) < 0) {
944 if (netif_msg_intr(priv))
945 printk(KERN_ERR "%s: Can't get IRQ %d (receive0)\n",
946 dev->name, priv->interruptReceive);
952 if (request_irq(priv->interruptTransmit, gfar_interrupt,
953 0, "gfar_interrupt", dev) < 0) {
954 if (netif_msg_intr(priv))
955 printk(KERN_ERR "%s: Can't get IRQ %d\n",
956 dev->name, priv->interruptError);
963 phy_start(priv->phydev);
965 /* Configure the coalescing support */
966 if (priv->txcoalescing)
967 gfar_write(®s->txic,
968 mk_ic_value(priv->txcount, priv->txtime));
970 gfar_write(®s->txic, 0);
972 if (priv->rxcoalescing)
973 gfar_write(®s->rxic,
974 mk_ic_value(priv->rxcount, priv->rxtime));
976 gfar_write(®s->rxic, 0);
978 if (priv->rx_csum_enable)
979 rctrl |= RCTRL_CHECKSUMMING;
981 if (priv->extended_hash) {
982 rctrl |= RCTRL_EXTHASH;
984 gfar_clear_exact_match(dev);
988 if (priv->vlan_enable)
992 rctrl &= ~RCTRL_PAL_MASK;
993 rctrl |= RCTRL_PADDING(priv->padding);
996 /* Init rctrl based on our settings */
997 gfar_write(&priv->regs->rctrl, rctrl);
999 if (dev->features & NETIF_F_IP_CSUM)
1000 gfar_write(&priv->regs->tctrl, TCTRL_INIT_CSUM);
1002 /* Set the extraction length and index */
1003 attrs = ATTRELI_EL(priv->rx_stash_size) |
1004 ATTRELI_EI(priv->rx_stash_index);
1006 gfar_write(&priv->regs->attreli, attrs);
1008 /* Start with defaults, and add stashing or locking
1009 * depending on the approprate variables */
1010 attrs = ATTR_INIT_SETTINGS;
1012 if (priv->bd_stash_en)
1013 attrs |= ATTR_BDSTASH;
1015 if (priv->rx_stash_size != 0)
1016 attrs |= ATTR_BUFSTASH;
1018 gfar_write(&priv->regs->attr, attrs);
1020 gfar_write(&priv->regs->fifo_tx_thr, priv->fifo_threshold);
1021 gfar_write(&priv->regs->fifo_tx_starve, priv->fifo_starve);
1022 gfar_write(&priv->regs->fifo_tx_starve_shutoff, priv->fifo_starve_off);
1024 /* Start the controller */
1030 free_irq(priv->interruptTransmit, dev);
1032 free_irq(priv->interruptError, dev);
1036 free_skb_resources(priv);
1038 dma_free_coherent(&dev->dev,
1039 sizeof(struct txbd8)*priv->tx_ring_size
1040 + sizeof(struct rxbd8)*priv->rx_ring_size,
1042 gfar_read(®s->tbase0));
1047 /* Called when something needs to use the ethernet device */
1048 /* Returns 0 for success. */
1049 static int gfar_enet_open(struct net_device *dev)
1051 struct gfar_private *priv = netdev_priv(dev);
1054 napi_enable(&priv->napi);
1056 /* Initialize a bunch of registers */
1057 init_registers(dev);
1059 gfar_set_mac_address(dev);
1061 err = init_phy(dev);
1064 napi_disable(&priv->napi);
1068 err = startup_gfar(dev);
1070 napi_disable(&priv->napi);
1074 netif_start_queue(dev);
1079 static inline struct txfcb *gfar_add_fcb(struct sk_buff *skb, struct txbd8 *bdp)
1081 struct txfcb *fcb = (struct txfcb *)skb_push (skb, GMAC_FCB_LEN);
1083 memset(fcb, 0, GMAC_FCB_LEN);
1088 static inline void gfar_tx_checksum(struct sk_buff *skb, struct txfcb *fcb)
1092 /* If we're here, it's a IP packet with a TCP or UDP
1093 * payload. We set it to checksum, using a pseudo-header
1096 flags = TXFCB_DEFAULT;
1098 /* Tell the controller what the protocol is */
1099 /* And provide the already calculated phcs */
1100 if (ip_hdr(skb)->protocol == IPPROTO_UDP) {
1102 fcb->phcs = udp_hdr(skb)->check;
1104 fcb->phcs = tcp_hdr(skb)->check;
1106 /* l3os is the distance between the start of the
1107 * frame (skb->data) and the start of the IP hdr.
1108 * l4os is the distance between the start of the
1109 * l3 hdr and the l4 hdr */
1110 fcb->l3os = (u16)(skb_network_offset(skb) - GMAC_FCB_LEN);
1111 fcb->l4os = skb_network_header_len(skb);
1116 void inline gfar_tx_vlan(struct sk_buff *skb, struct txfcb *fcb)
1118 fcb->flags |= TXFCB_VLN;
1119 fcb->vlctl = vlan_tx_tag_get(skb);
1122 /* This is called by the kernel when a frame is ready for transmission. */
1123 /* It is pointed to by the dev->hard_start_xmit function pointer */
1124 static int gfar_start_xmit(struct sk_buff *skb, struct net_device *dev)
1126 struct gfar_private *priv = netdev_priv(dev);
1127 struct txfcb *fcb = NULL;
1128 struct txbd8 *txbdp;
1130 unsigned long flags;
1132 /* Update transmit stats */
1133 dev->stats.tx_bytes += skb->len;
1136 spin_lock_irqsave(&priv->txlock, flags);
1138 /* Point at the first free tx descriptor */
1139 txbdp = priv->cur_tx;
1141 /* Clear all but the WRAP status flags */
1142 status = txbdp->status & TXBD_WRAP;
1144 /* Set up checksumming */
1145 if (likely((dev->features & NETIF_F_IP_CSUM)
1146 && (CHECKSUM_PARTIAL == skb->ip_summed))) {
1147 fcb = gfar_add_fcb(skb, txbdp);
1149 gfar_tx_checksum(skb, fcb);
1152 if (priv->vlan_enable &&
1153 unlikely(priv->vlgrp && vlan_tx_tag_present(skb))) {
1154 if (unlikely(NULL == fcb)) {
1155 fcb = gfar_add_fcb(skb, txbdp);
1159 gfar_tx_vlan(skb, fcb);
1162 /* Set buffer length and pointer */
1163 txbdp->length = skb->len;
1164 txbdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1165 skb->len, DMA_TO_DEVICE);
1167 /* Save the skb pointer so we can free it later */
1168 priv->tx_skbuff[priv->skb_curtx] = skb;
1170 /* Update the current skb pointer (wrapping if this was the last) */
1172 (priv->skb_curtx + 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1174 /* Flag the BD as interrupt-causing */
1175 status |= TXBD_INTERRUPT;
1177 /* Flag the BD as ready to go, last in frame, and */
1178 /* in need of CRC */
1179 status |= (TXBD_READY | TXBD_LAST | TXBD_CRC);
1181 dev->trans_start = jiffies;
1183 /* The powerpc-specific eieio() is used, as wmb() has too strong
1184 * semantics (it requires synchronization between cacheable and
1185 * uncacheable mappings, which eieio doesn't provide and which we
1186 * don't need), thus requiring a more expensive sync instruction. At
1187 * some point, the set of architecture-independent barrier functions
1188 * should be expanded to include weaker barriers.
1192 txbdp->status = status;
1194 /* If this was the last BD in the ring, the next one */
1195 /* is at the beginning of the ring */
1196 if (txbdp->status & TXBD_WRAP)
1197 txbdp = priv->tx_bd_base;
1201 /* If the next BD still needs to be cleaned up, then the bds
1202 are full. We need to tell the kernel to stop sending us stuff. */
1203 if (txbdp == priv->dirty_tx) {
1204 netif_stop_queue(dev);
1206 dev->stats.tx_fifo_errors++;
1209 /* Update the current txbd to the next one */
1210 priv->cur_tx = txbdp;
1212 /* Tell the DMA to go go go */
1213 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
1216 spin_unlock_irqrestore(&priv->txlock, flags);
1221 /* Stops the kernel queue, and halts the controller */
1222 static int gfar_close(struct net_device *dev)
1224 struct gfar_private *priv = netdev_priv(dev);
1226 napi_disable(&priv->napi);
1228 cancel_work_sync(&priv->reset_task);
1231 /* Disconnect from the PHY */
1232 phy_disconnect(priv->phydev);
1233 priv->phydev = NULL;
1235 netif_stop_queue(dev);
1240 /* Changes the mac address if the controller is not running. */
1241 static int gfar_set_mac_address(struct net_device *dev)
1243 gfar_set_mac_for_addr(dev, 0, dev->dev_addr);
1249 /* Enables and disables VLAN insertion/extraction */
1250 static void gfar_vlan_rx_register(struct net_device *dev,
1251 struct vlan_group *grp)
1253 struct gfar_private *priv = netdev_priv(dev);
1254 unsigned long flags;
1257 spin_lock_irqsave(&priv->rxlock, flags);
1262 /* Enable VLAN tag insertion */
1263 tempval = gfar_read(&priv->regs->tctrl);
1264 tempval |= TCTRL_VLINS;
1266 gfar_write(&priv->regs->tctrl, tempval);
1268 /* Enable VLAN tag extraction */
1269 tempval = gfar_read(&priv->regs->rctrl);
1270 tempval |= RCTRL_VLEX;
1271 gfar_write(&priv->regs->rctrl, tempval);
1273 /* Disable VLAN tag insertion */
1274 tempval = gfar_read(&priv->regs->tctrl);
1275 tempval &= ~TCTRL_VLINS;
1276 gfar_write(&priv->regs->tctrl, tempval);
1278 /* Disable VLAN tag extraction */
1279 tempval = gfar_read(&priv->regs->rctrl);
1280 tempval &= ~RCTRL_VLEX;
1281 gfar_write(&priv->regs->rctrl, tempval);
1284 spin_unlock_irqrestore(&priv->rxlock, flags);
1287 static int gfar_change_mtu(struct net_device *dev, int new_mtu)
1289 int tempsize, tempval;
1290 struct gfar_private *priv = netdev_priv(dev);
1291 int oldsize = priv->rx_buffer_size;
1292 int frame_size = new_mtu + ETH_HLEN;
1294 if (priv->vlan_enable)
1295 frame_size += VLAN_HLEN;
1297 if (gfar_uses_fcb(priv))
1298 frame_size += GMAC_FCB_LEN;
1300 frame_size += priv->padding;
1302 if ((frame_size < 64) || (frame_size > JUMBO_FRAME_SIZE)) {
1303 if (netif_msg_drv(priv))
1304 printk(KERN_ERR "%s: Invalid MTU setting\n",
1310 (frame_size & ~(INCREMENTAL_BUFFER_SIZE - 1)) +
1311 INCREMENTAL_BUFFER_SIZE;
1313 /* Only stop and start the controller if it isn't already
1314 * stopped, and we changed something */
1315 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1318 priv->rx_buffer_size = tempsize;
1322 gfar_write(&priv->regs->mrblr, priv->rx_buffer_size);
1323 gfar_write(&priv->regs->maxfrm, priv->rx_buffer_size);
1325 /* If the mtu is larger than the max size for standard
1326 * ethernet frames (ie, a jumbo frame), then set maccfg2
1327 * to allow huge frames, and to check the length */
1328 tempval = gfar_read(&priv->regs->maccfg2);
1330 if (priv->rx_buffer_size > DEFAULT_RX_BUFFER_SIZE)
1331 tempval |= (MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1333 tempval &= ~(MACCFG2_HUGEFRAME | MACCFG2_LENGTHCHECK);
1335 gfar_write(&priv->regs->maccfg2, tempval);
1337 if ((oldsize != tempsize) && (dev->flags & IFF_UP))
1343 /* gfar_reset_task gets scheduled when a packet has not been
1344 * transmitted after a set amount of time.
1345 * For now, assume that clearing out all the structures, and
1346 * starting over will fix the problem.
1348 static void gfar_reset_task(struct work_struct *work)
1350 struct gfar_private *priv = container_of(work, struct gfar_private,
1352 struct net_device *dev = priv->dev;
1354 if (dev->flags & IFF_UP) {
1359 netif_tx_schedule_all(dev);
1362 static void gfar_timeout(struct net_device *dev)
1364 struct gfar_private *priv = netdev_priv(dev);
1366 dev->stats.tx_errors++;
1367 schedule_work(&priv->reset_task);
1370 /* Interrupt Handler for Transmit complete */
1371 static int gfar_clean_tx_ring(struct net_device *dev)
1374 struct gfar_private *priv = netdev_priv(dev);
1377 bdp = priv->dirty_tx;
1378 while ((bdp->status & TXBD_READY) == 0) {
1379 /* If dirty_tx and cur_tx are the same, then either the */
1380 /* ring is empty or full now (it could only be full in the beginning, */
1381 /* obviously). If it is empty, we are done. */
1382 if ((bdp == priv->cur_tx) && (netif_queue_stopped(dev) == 0))
1387 /* Deferred means some collisions occurred during transmit, */
1388 /* but we eventually sent the packet. */
1389 if (bdp->status & TXBD_DEF)
1390 dev->stats.collisions++;
1392 /* Free the sk buffer associated with this TxBD */
1393 dev_kfree_skb_irq(priv->tx_skbuff[priv->skb_dirtytx]);
1395 priv->tx_skbuff[priv->skb_dirtytx] = NULL;
1397 (priv->skb_dirtytx +
1398 1) & TX_RING_MOD_MASK(priv->tx_ring_size);
1400 /* Clean BD length for empty detection */
1403 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1404 if (bdp->status & TXBD_WRAP)
1405 bdp = priv->tx_bd_base;
1409 /* Move dirty_tx to be the next bd */
1410 priv->dirty_tx = bdp;
1412 /* We freed a buffer, so now we can restart transmission */
1413 if (netif_queue_stopped(dev))
1414 netif_wake_queue(dev);
1415 } /* while ((bdp->status & TXBD_READY) == 0) */
1417 dev->stats.tx_packets += howmany;
1422 /* Interrupt Handler for Transmit complete */
1423 static irqreturn_t gfar_transmit(int irq, void *dev_id)
1425 struct net_device *dev = (struct net_device *) dev_id;
1426 struct gfar_private *priv = netdev_priv(dev);
1429 gfar_write(&priv->regs->ievent, IEVENT_TX_MASK);
1432 spin_lock(&priv->txlock);
1434 gfar_clean_tx_ring(dev);
1436 /* If we are coalescing the interrupts, reset the timer */
1437 /* Otherwise, clear it */
1438 if (likely(priv->txcoalescing)) {
1439 gfar_write(&priv->regs->txic, 0);
1440 gfar_write(&priv->regs->txic,
1441 mk_ic_value(priv->txcount, priv->txtime));
1444 spin_unlock(&priv->txlock);
1449 static void gfar_new_rxbdp(struct net_device *dev, struct rxbd8 *bdp,
1450 struct sk_buff *skb)
1452 struct gfar_private *priv = netdev_priv(dev);
1453 u32 * status_len = (u32 *)bdp;
1456 bdp->bufPtr = dma_map_single(&dev->dev, skb->data,
1457 priv->rx_buffer_size, DMA_FROM_DEVICE);
1459 flags = RXBD_EMPTY | RXBD_INTERRUPT;
1461 if (bdp == priv->rx_bd_base + priv->rx_ring_size - 1)
1466 *status_len = (u32)flags << 16;
1470 struct sk_buff * gfar_new_skb(struct net_device *dev)
1472 unsigned int alignamount;
1473 struct gfar_private *priv = netdev_priv(dev);
1474 struct sk_buff *skb = NULL;
1476 /* We have to allocate the skb, so keep trying till we succeed */
1477 skb = netdev_alloc_skb(dev, priv->rx_buffer_size + RXBUF_ALIGNMENT);
1482 alignamount = RXBUF_ALIGNMENT -
1483 (((unsigned long) skb->data) & (RXBUF_ALIGNMENT - 1));
1485 /* We need the data buffer to be aligned properly. We will reserve
1486 * as many bytes as needed to align the data properly
1488 skb_reserve(skb, alignamount);
1493 static inline void count_errors(unsigned short status, struct net_device *dev)
1495 struct gfar_private *priv = netdev_priv(dev);
1496 struct net_device_stats *stats = &dev->stats;
1497 struct gfar_extra_stats *estats = &priv->extra_stats;
1499 /* If the packet was truncated, none of the other errors
1501 if (status & RXBD_TRUNCATED) {
1502 stats->rx_length_errors++;
1508 /* Count the errors, if there were any */
1509 if (status & (RXBD_LARGE | RXBD_SHORT)) {
1510 stats->rx_length_errors++;
1512 if (status & RXBD_LARGE)
1517 if (status & RXBD_NONOCTET) {
1518 stats->rx_frame_errors++;
1519 estats->rx_nonoctet++;
1521 if (status & RXBD_CRCERR) {
1522 estats->rx_crcerr++;
1523 stats->rx_crc_errors++;
1525 if (status & RXBD_OVERRUN) {
1526 estats->rx_overrun++;
1527 stats->rx_crc_errors++;
1531 irqreturn_t gfar_receive(int irq, void *dev_id)
1533 struct net_device *dev = (struct net_device *) dev_id;
1534 struct gfar_private *priv = netdev_priv(dev);
1538 /* Clear IEVENT, so interrupts aren't called again
1539 * because of the packets that have already arrived */
1540 gfar_write(&priv->regs->ievent, IEVENT_RTX_MASK);
1542 if (netif_rx_schedule_prep(dev, &priv->napi)) {
1543 tempval = gfar_read(&priv->regs->imask);
1544 tempval &= IMASK_RTX_DISABLED;
1545 gfar_write(&priv->regs->imask, tempval);
1547 __netif_rx_schedule(dev, &priv->napi);
1549 if (netif_msg_rx_err(priv))
1550 printk(KERN_DEBUG "%s: receive called twice (%x)[%x]\n",
1551 dev->name, gfar_read(&priv->regs->ievent),
1552 gfar_read(&priv->regs->imask));
1558 static inline void gfar_rx_checksum(struct sk_buff *skb, struct rxfcb *fcb)
1560 /* If valid headers were found, and valid sums
1561 * were verified, then we tell the kernel that no
1562 * checksumming is necessary. Otherwise, it is */
1563 if ((fcb->flags & RXFCB_CSUM_MASK) == (RXFCB_CIP | RXFCB_CTU))
1564 skb->ip_summed = CHECKSUM_UNNECESSARY;
1566 skb->ip_summed = CHECKSUM_NONE;
1570 static inline struct rxfcb *gfar_get_fcb(struct sk_buff *skb)
1572 struct rxfcb *fcb = (struct rxfcb *)skb->data;
1574 /* Remove the FCB from the skb */
1575 skb_pull(skb, GMAC_FCB_LEN);
1580 /* gfar_process_frame() -- handle one incoming packet if skb
1582 static int gfar_process_frame(struct net_device *dev, struct sk_buff *skb,
1585 struct gfar_private *priv = netdev_priv(dev);
1586 struct rxfcb *fcb = NULL;
1589 if (netif_msg_rx_err(priv))
1590 printk(KERN_WARNING "%s: Missing skb!!.\n", dev->name);
1591 dev->stats.rx_dropped++;
1592 priv->extra_stats.rx_skbmissing++;
1596 /* Prep the skb for the packet */
1597 skb_put(skb, length);
1599 /* Grab the FCB if there is one */
1600 if (gfar_uses_fcb(priv))
1601 fcb = gfar_get_fcb(skb);
1603 /* Remove the padded bytes, if there are any */
1605 skb_pull(skb, priv->padding);
1607 if (priv->rx_csum_enable)
1608 gfar_rx_checksum(skb, fcb);
1610 /* Tell the skb what kind of packet this is */
1611 skb->protocol = eth_type_trans(skb, dev);
1613 /* Send the packet up the stack */
1614 if (unlikely(priv->vlgrp && (fcb->flags & RXFCB_VLN))) {
1615 ret = vlan_hwaccel_receive_skb(skb, priv->vlgrp,
1618 ret = netif_receive_skb(skb);
1620 if (NET_RX_DROP == ret)
1621 priv->extra_stats.kernel_dropped++;
1627 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1628 * until the budget/quota has been reached. Returns the number
1631 int gfar_clean_rx_ring(struct net_device *dev, int rx_work_limit)
1634 struct sk_buff *skb;
1637 struct gfar_private *priv = netdev_priv(dev);
1639 /* Get the first full descriptor */
1642 while (!((bdp->status & RXBD_EMPTY) || (--rx_work_limit < 0))) {
1643 struct sk_buff *newskb;
1646 /* Add another skb for the future */
1647 newskb = gfar_new_skb(dev);
1649 skb = priv->rx_skbuff[priv->skb_currx];
1651 /* We drop the frame if we failed to allocate a new buffer */
1652 if (unlikely(!newskb || !(bdp->status & RXBD_LAST) ||
1653 bdp->status & RXBD_ERR)) {
1654 count_errors(bdp->status, dev);
1656 if (unlikely(!newskb))
1660 dma_unmap_single(&priv->dev->dev,
1662 priv->rx_buffer_size,
1665 dev_kfree_skb_any(skb);
1668 /* Increment the number of packets */
1669 dev->stats.rx_packets++;
1672 /* Remove the FCS from the packet length */
1673 pkt_len = bdp->length - 4;
1675 gfar_process_frame(dev, skb, pkt_len);
1677 dev->stats.rx_bytes += pkt_len;
1680 dev->last_rx = jiffies;
1682 priv->rx_skbuff[priv->skb_currx] = newskb;
1684 /* Setup the new bdp */
1685 gfar_new_rxbdp(dev, bdp, newskb);
1687 /* Update to the next pointer */
1688 if (bdp->status & RXBD_WRAP)
1689 bdp = priv->rx_bd_base;
1693 /* update to point at the next skb */
1695 (priv->skb_currx + 1) &
1696 RX_RING_MOD_MASK(priv->rx_ring_size);
1699 /* Update the current rxbd pointer to be the next one */
1705 static int gfar_poll(struct napi_struct *napi, int budget)
1707 struct gfar_private *priv = container_of(napi, struct gfar_private, napi);
1708 struct net_device *dev = priv->dev;
1710 unsigned long flags;
1712 /* If we fail to get the lock, don't bother with the TX BDs */
1713 if (spin_trylock_irqsave(&priv->txlock, flags)) {
1714 gfar_clean_tx_ring(dev);
1715 spin_unlock_irqrestore(&priv->txlock, flags);
1718 howmany = gfar_clean_rx_ring(dev, budget);
1720 if (howmany < budget) {
1721 netif_rx_complete(dev, napi);
1723 /* Clear the halt bit in RSTAT */
1724 gfar_write(&priv->regs->rstat, RSTAT_CLEAR_RHALT);
1726 gfar_write(&priv->regs->imask, IMASK_DEFAULT);
1728 /* If we are coalescing interrupts, update the timer */
1729 /* Otherwise, clear it */
1730 if (likely(priv->rxcoalescing)) {
1731 gfar_write(&priv->regs->rxic, 0);
1732 gfar_write(&priv->regs->rxic,
1733 mk_ic_value(priv->rxcount, priv->rxtime));
1740 #ifdef CONFIG_NET_POLL_CONTROLLER
1742 * Polling 'interrupt' - used by things like netconsole to send skbs
1743 * without having to re-enable interrupts. It's not called while
1744 * the interrupt routine is executing.
1746 static void gfar_netpoll(struct net_device *dev)
1748 struct gfar_private *priv = netdev_priv(dev);
1750 /* If the device has multiple interrupts, run tx/rx */
1751 if (priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MULTI_INTR) {
1752 disable_irq(priv->interruptTransmit);
1753 disable_irq(priv->interruptReceive);
1754 disable_irq(priv->interruptError);
1755 gfar_interrupt(priv->interruptTransmit, dev);
1756 enable_irq(priv->interruptError);
1757 enable_irq(priv->interruptReceive);
1758 enable_irq(priv->interruptTransmit);
1760 disable_irq(priv->interruptTransmit);
1761 gfar_interrupt(priv->interruptTransmit, dev);
1762 enable_irq(priv->interruptTransmit);
1767 /* The interrupt handler for devices with one interrupt */
1768 static irqreturn_t gfar_interrupt(int irq, void *dev_id)
1770 struct net_device *dev = dev_id;
1771 struct gfar_private *priv = netdev_priv(dev);
1773 /* Save ievent for future reference */
1774 u32 events = gfar_read(&priv->regs->ievent);
1776 /* Check for reception */
1777 if (events & IEVENT_RX_MASK)
1778 gfar_receive(irq, dev_id);
1780 /* Check for transmit completion */
1781 if (events & IEVENT_TX_MASK)
1782 gfar_transmit(irq, dev_id);
1784 /* Check for errors */
1785 if (events & IEVENT_ERR_MASK)
1786 gfar_error(irq, dev_id);
1791 /* Called every time the controller might need to be made
1792 * aware of new link state. The PHY code conveys this
1793 * information through variables in the phydev structure, and this
1794 * function converts those variables into the appropriate
1795 * register values, and can bring down the device if needed.
1797 static void adjust_link(struct net_device *dev)
1799 struct gfar_private *priv = netdev_priv(dev);
1800 struct gfar __iomem *regs = priv->regs;
1801 unsigned long flags;
1802 struct phy_device *phydev = priv->phydev;
1805 spin_lock_irqsave(&priv->txlock, flags);
1807 u32 tempval = gfar_read(®s->maccfg2);
1808 u32 ecntrl = gfar_read(®s->ecntrl);
1810 /* Now we make sure that we can be in full duplex mode.
1811 * If not, we operate in half-duplex mode. */
1812 if (phydev->duplex != priv->oldduplex) {
1814 if (!(phydev->duplex))
1815 tempval &= ~(MACCFG2_FULL_DUPLEX);
1817 tempval |= MACCFG2_FULL_DUPLEX;
1819 priv->oldduplex = phydev->duplex;
1822 if (phydev->speed != priv->oldspeed) {
1824 switch (phydev->speed) {
1827 ((tempval & ~(MACCFG2_IF)) | MACCFG2_GMII);
1832 ((tempval & ~(MACCFG2_IF)) | MACCFG2_MII);
1834 /* Reduced mode distinguishes
1835 * between 10 and 100 */
1836 if (phydev->speed == SPEED_100)
1837 ecntrl |= ECNTRL_R100;
1839 ecntrl &= ~(ECNTRL_R100);
1842 if (netif_msg_link(priv))
1844 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1845 dev->name, phydev->speed);
1849 priv->oldspeed = phydev->speed;
1852 gfar_write(®s->maccfg2, tempval);
1853 gfar_write(®s->ecntrl, ecntrl);
1855 if (!priv->oldlink) {
1859 } else if (priv->oldlink) {
1863 priv->oldduplex = -1;
1866 if (new_state && netif_msg_link(priv))
1867 phy_print_status(phydev);
1869 spin_unlock_irqrestore(&priv->txlock, flags);
1872 /* Update the hash table based on the current list of multicast
1873 * addresses we subscribe to. Also, change the promiscuity of
1874 * the device based on the flags (this function is called
1875 * whenever dev->flags is changed */
1876 static void gfar_set_multi(struct net_device *dev)
1878 struct dev_mc_list *mc_ptr;
1879 struct gfar_private *priv = netdev_priv(dev);
1880 struct gfar __iomem *regs = priv->regs;
1883 if(dev->flags & IFF_PROMISC) {
1884 /* Set RCTRL to PROM */
1885 tempval = gfar_read(®s->rctrl);
1886 tempval |= RCTRL_PROM;
1887 gfar_write(®s->rctrl, tempval);
1889 /* Set RCTRL to not PROM */
1890 tempval = gfar_read(®s->rctrl);
1891 tempval &= ~(RCTRL_PROM);
1892 gfar_write(®s->rctrl, tempval);
1895 if(dev->flags & IFF_ALLMULTI) {
1896 /* Set the hash to rx all multicast frames */
1897 gfar_write(®s->igaddr0, 0xffffffff);
1898 gfar_write(®s->igaddr1, 0xffffffff);
1899 gfar_write(®s->igaddr2, 0xffffffff);
1900 gfar_write(®s->igaddr3, 0xffffffff);
1901 gfar_write(®s->igaddr4, 0xffffffff);
1902 gfar_write(®s->igaddr5, 0xffffffff);
1903 gfar_write(®s->igaddr6, 0xffffffff);
1904 gfar_write(®s->igaddr7, 0xffffffff);
1905 gfar_write(®s->gaddr0, 0xffffffff);
1906 gfar_write(®s->gaddr1, 0xffffffff);
1907 gfar_write(®s->gaddr2, 0xffffffff);
1908 gfar_write(®s->gaddr3, 0xffffffff);
1909 gfar_write(®s->gaddr4, 0xffffffff);
1910 gfar_write(®s->gaddr5, 0xffffffff);
1911 gfar_write(®s->gaddr6, 0xffffffff);
1912 gfar_write(®s->gaddr7, 0xffffffff);
1917 /* zero out the hash */
1918 gfar_write(®s->igaddr0, 0x0);
1919 gfar_write(®s->igaddr1, 0x0);
1920 gfar_write(®s->igaddr2, 0x0);
1921 gfar_write(®s->igaddr3, 0x0);
1922 gfar_write(®s->igaddr4, 0x0);
1923 gfar_write(®s->igaddr5, 0x0);
1924 gfar_write(®s->igaddr6, 0x0);
1925 gfar_write(®s->igaddr7, 0x0);
1926 gfar_write(®s->gaddr0, 0x0);
1927 gfar_write(®s->gaddr1, 0x0);
1928 gfar_write(®s->gaddr2, 0x0);
1929 gfar_write(®s->gaddr3, 0x0);
1930 gfar_write(®s->gaddr4, 0x0);
1931 gfar_write(®s->gaddr5, 0x0);
1932 gfar_write(®s->gaddr6, 0x0);
1933 gfar_write(®s->gaddr7, 0x0);
1935 /* If we have extended hash tables, we need to
1936 * clear the exact match registers to prepare for
1938 if (priv->extended_hash) {
1939 em_num = GFAR_EM_NUM + 1;
1940 gfar_clear_exact_match(dev);
1947 if(dev->mc_count == 0)
1950 /* Parse the list, and set the appropriate bits */
1951 for(mc_ptr = dev->mc_list; mc_ptr; mc_ptr = mc_ptr->next) {
1953 gfar_set_mac_for_addr(dev, idx,
1957 gfar_set_hash_for_addr(dev, mc_ptr->dmi_addr);
1965 /* Clears each of the exact match registers to zero, so they
1966 * don't interfere with normal reception */
1967 static void gfar_clear_exact_match(struct net_device *dev)
1970 u8 zero_arr[MAC_ADDR_LEN] = {0,0,0,0,0,0};
1972 for(idx = 1;idx < GFAR_EM_NUM + 1;idx++)
1973 gfar_set_mac_for_addr(dev, idx, (u8 *)zero_arr);
1976 /* Set the appropriate hash bit for the given addr */
1977 /* The algorithm works like so:
1978 * 1) Take the Destination Address (ie the multicast address), and
1979 * do a CRC on it (little endian), and reverse the bits of the
1981 * 2) Use the 8 most significant bits as a hash into a 256-entry
1982 * table. The table is controlled through 8 32-bit registers:
1983 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1984 * gaddr7. This means that the 3 most significant bits in the
1985 * hash index which gaddr register to use, and the 5 other bits
1986 * indicate which bit (assuming an IBM numbering scheme, which
1987 * for PowerPC (tm) is usually the case) in the register holds
1989 static void gfar_set_hash_for_addr(struct net_device *dev, u8 *addr)
1992 struct gfar_private *priv = netdev_priv(dev);
1993 u32 result = ether_crc(MAC_ADDR_LEN, addr);
1994 int width = priv->hash_width;
1995 u8 whichbit = (result >> (32 - width)) & 0x1f;
1996 u8 whichreg = result >> (32 - width + 5);
1997 u32 value = (1 << (31-whichbit));
1999 tempval = gfar_read(priv->hash_regs[whichreg]);
2001 gfar_write(priv->hash_regs[whichreg], tempval);
2007 /* There are multiple MAC Address register pairs on some controllers
2008 * This function sets the numth pair to a given address
2010 static void gfar_set_mac_for_addr(struct net_device *dev, int num, u8 *addr)
2012 struct gfar_private *priv = netdev_priv(dev);
2014 char tmpbuf[MAC_ADDR_LEN];
2016 u32 __iomem *macptr = &priv->regs->macstnaddr1;
2020 /* Now copy it into the mac registers backwards, cuz */
2021 /* little endian is silly */
2022 for (idx = 0; idx < MAC_ADDR_LEN; idx++)
2023 tmpbuf[MAC_ADDR_LEN - 1 - idx] = addr[idx];
2025 gfar_write(macptr, *((u32 *) (tmpbuf)));
2027 tempval = *((u32 *) (tmpbuf + 4));
2029 gfar_write(macptr+1, tempval);
2032 /* GFAR error interrupt handler */
2033 static irqreturn_t gfar_error(int irq, void *dev_id)
2035 struct net_device *dev = dev_id;
2036 struct gfar_private *priv = netdev_priv(dev);
2038 /* Save ievent for future reference */
2039 u32 events = gfar_read(&priv->regs->ievent);
2042 gfar_write(&priv->regs->ievent, events & IEVENT_ERR_MASK);
2044 /* Magic Packet is not an error. */
2045 if ((priv->einfo->device_flags & FSL_GIANFAR_DEV_HAS_MAGIC_PACKET) &&
2046 (events & IEVENT_MAG))
2047 events &= ~IEVENT_MAG;
2050 if (netif_msg_rx_err(priv) || netif_msg_tx_err(priv))
2051 printk(KERN_DEBUG "%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
2052 dev->name, events, gfar_read(&priv->regs->imask));
2054 /* Update the error counters */
2055 if (events & IEVENT_TXE) {
2056 dev->stats.tx_errors++;
2058 if (events & IEVENT_LC)
2059 dev->stats.tx_window_errors++;
2060 if (events & IEVENT_CRL)
2061 dev->stats.tx_aborted_errors++;
2062 if (events & IEVENT_XFUN) {
2063 if (netif_msg_tx_err(priv))
2064 printk(KERN_DEBUG "%s: TX FIFO underrun, "
2065 "packet dropped.\n", dev->name);
2066 dev->stats.tx_dropped++;
2067 priv->extra_stats.tx_underrun++;
2069 /* Reactivate the Tx Queues */
2070 gfar_write(&priv->regs->tstat, TSTAT_CLEAR_THALT);
2072 if (netif_msg_tx_err(priv))
2073 printk(KERN_DEBUG "%s: Transmit Error\n", dev->name);
2075 if (events & IEVENT_BSY) {
2076 dev->stats.rx_errors++;
2077 priv->extra_stats.rx_bsy++;
2079 gfar_receive(irq, dev_id);
2081 if (netif_msg_rx_err(priv))
2082 printk(KERN_DEBUG "%s: busy error (rstat: %x)\n",
2083 dev->name, gfar_read(&priv->regs->rstat));
2085 if (events & IEVENT_BABR) {
2086 dev->stats.rx_errors++;
2087 priv->extra_stats.rx_babr++;
2089 if (netif_msg_rx_err(priv))
2090 printk(KERN_DEBUG "%s: babbling RX error\n", dev->name);
2092 if (events & IEVENT_EBERR) {
2093 priv->extra_stats.eberr++;
2094 if (netif_msg_rx_err(priv))
2095 printk(KERN_DEBUG "%s: bus error\n", dev->name);
2097 if ((events & IEVENT_RXC) && netif_msg_rx_status(priv))
2098 printk(KERN_DEBUG "%s: control frame\n", dev->name);
2100 if (events & IEVENT_BABT) {
2101 priv->extra_stats.tx_babt++;
2102 if (netif_msg_tx_err(priv))
2103 printk(KERN_DEBUG "%s: babbling TX error\n", dev->name);
2108 /* work with hotplug and coldplug */
2109 MODULE_ALIAS("platform:fsl-gianfar");
2111 /* Structure for a device driver */
2112 static struct platform_driver gfar_driver = {
2113 .probe = gfar_probe,
2114 .remove = gfar_remove,
2115 .suspend = gfar_suspend,
2116 .resume = gfar_resume,
2118 .name = "fsl-gianfar",
2119 .owner = THIS_MODULE,
2123 static int __init gfar_init(void)
2125 int err = gfar_mdio_init();
2130 err = platform_driver_register(&gfar_driver);
2138 static void __exit gfar_exit(void)
2140 platform_driver_unregister(&gfar_driver);
2144 module_init(gfar_init);
2145 module_exit(gfar_exit);