2 * Driver for Xilinx TEMAC Ethernet device
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/mii.h>
33 #include <linux/module.h>
34 #include <linux/mutex.h>
35 #include <linux/netdevice.h>
36 #include <linux/if_ether.h>
38 #include <linux/of_device.h>
39 #include <linux/of_irq.h>
40 #include <linux/of_mdio.h>
41 #include <linux/of_net.h>
42 #include <linux/of_platform.h>
43 #include <linux/of_address.h>
44 #include <linux/skbuff.h>
45 #include <linux/spinlock.h>
46 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */
47 #include <linux/udp.h> /* needed for sizeof(udphdr) */
48 #include <linux/phy.h>
52 #include <linux/slab.h>
53 #include <linux/interrupt.h>
54 #include <linux/dma-mapping.h>
55 #include <linux/platform_data/xilinx-ll-temac.h>
62 /* ---------------------------------------------------------------------
63 * Low level register access functions
66 static u32 _temac_ior_be(struct temac_local *lp, int offset)
68 return ioread32be(lp->regs + offset);
71 static void _temac_iow_be(struct temac_local *lp, int offset, u32 value)
73 return iowrite32be(value, lp->regs + offset);
76 static u32 _temac_ior_le(struct temac_local *lp, int offset)
78 return ioread32(lp->regs + offset);
81 static void _temac_iow_le(struct temac_local *lp, int offset, u32 value)
83 return iowrite32(value, lp->regs + offset);
86 int temac_indirect_busywait(struct temac_local *lp)
88 unsigned long end = jiffies + 2;
90 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
91 if (time_before_eq(end, jiffies)) {
95 usleep_range(500, 1000);
101 * temac_indirect_in32
103 * lp->indirect_mutex must be held when calling this function
105 u32 temac_indirect_in32(struct temac_local *lp, int reg)
109 if (temac_indirect_busywait(lp))
111 temac_iow(lp, XTE_CTL0_OFFSET, reg);
112 if (temac_indirect_busywait(lp))
114 val = temac_ior(lp, XTE_LSW0_OFFSET);
120 * temac_indirect_out32
122 * lp->indirect_mutex must be held when calling this function
124 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
126 if (temac_indirect_busywait(lp))
128 temac_iow(lp, XTE_LSW0_OFFSET, value);
129 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
130 temac_indirect_busywait(lp);
134 * temac_dma_in32_* - Memory mapped DMA read, these function expects a
135 * register input that is based on DCR word addresses which are then
136 * converted to memory mapped byte addresses. To be assigned to
139 static u32 temac_dma_in32_be(struct temac_local *lp, int reg)
141 return ioread32be(lp->sdma_regs + (reg << 2));
144 static u32 temac_dma_in32_le(struct temac_local *lp, int reg)
146 return ioread32(lp->sdma_regs + (reg << 2));
150 * temac_dma_out32_* - Memory mapped DMA read, these function expects
151 * a register input that is based on DCR word addresses which are then
152 * converted to memory mapped byte addresses. To be assigned to
155 static void temac_dma_out32_be(struct temac_local *lp, int reg, u32 value)
157 iowrite32be(value, lp->sdma_regs + (reg << 2));
160 static void temac_dma_out32_le(struct temac_local *lp, int reg, u32 value)
162 iowrite32(value, lp->sdma_regs + (reg << 2));
165 /* DMA register access functions can be DCR based or memory mapped.
166 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
169 #ifdef CONFIG_PPC_DCR
172 * temac_dma_dcr_in32 - DCR based DMA read
174 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
176 return dcr_read(lp->sdma_dcrs, reg);
180 * temac_dma_dcr_out32 - DCR based DMA write
182 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
184 dcr_write(lp->sdma_dcrs, reg, value);
188 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
191 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
192 struct device_node *np)
196 /* setup the dcr address mapping if it's in the device tree */
198 dcrs = dcr_resource_start(np, 0);
200 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
201 lp->dma_in = temac_dma_dcr_in;
202 lp->dma_out = temac_dma_dcr_out;
203 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
206 /* no DCR in the device tree, indicate a failure */
213 * temac_dcr_setup - This is a stub for when DCR is not supported,
214 * such as with MicroBlaze and x86
216 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
217 struct device_node *np)
225 * temac_dma_bd_release - Release buffer descriptor rings
227 static void temac_dma_bd_release(struct net_device *ndev)
229 struct temac_local *lp = netdev_priv(ndev);
232 /* Reset Local Link (DMA) */
233 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
235 for (i = 0; i < RX_BD_NUM; i++) {
239 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
240 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
241 dev_kfree_skb(lp->rx_skb[i]);
245 dma_free_coherent(ndev->dev.parent,
246 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
247 lp->rx_bd_v, lp->rx_bd_p);
249 dma_free_coherent(ndev->dev.parent,
250 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
251 lp->tx_bd_v, lp->tx_bd_p);
255 * temac_dma_bd_init - Setup buffer descriptor rings
257 static int temac_dma_bd_init(struct net_device *ndev)
259 struct temac_local *lp = netdev_priv(ndev);
261 dma_addr_t skb_dma_addr;
264 lp->rx_skb = devm_kcalloc(&ndev->dev, RX_BD_NUM, sizeof(*lp->rx_skb),
269 /* allocate the tx and rx ring buffer descriptors. */
270 /* returns a virtual address and a physical address. */
271 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
272 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
273 &lp->tx_bd_p, GFP_KERNEL);
277 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
278 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
279 &lp->rx_bd_p, GFP_KERNEL);
283 for (i = 0; i < TX_BD_NUM; i++) {
284 lp->tx_bd_v[i].next = cpu_to_be32(lp->tx_bd_p
285 + sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM));
288 for (i = 0; i < RX_BD_NUM; i++) {
289 lp->rx_bd_v[i].next = cpu_to_be32(lp->rx_bd_p
290 + sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM));
292 skb = netdev_alloc_skb_ip_align(ndev,
293 XTE_MAX_JUMBO_FRAME_SIZE);
298 /* returns physical address of skb->data */
299 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
300 XTE_MAX_JUMBO_FRAME_SIZE,
302 lp->rx_bd_v[i].phys = cpu_to_be32(skb_dma_addr);
303 lp->rx_bd_v[i].len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
304 lp->rx_bd_v[i].app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
307 /* Configure DMA channel (irq setup) */
308 lp->dma_out(lp, TX_CHNL_CTRL, lp->tx_chnl_ctrl |
309 0x00000400 | // Use 1 Bit Wide Counters. Currently Not Used!
310 CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN |
311 CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN);
312 lp->dma_out(lp, RX_CHNL_CTRL, lp->rx_chnl_ctrl |
314 CHNL_CTRL_IRQ_EN | CHNL_CTRL_IRQ_ERR_EN |
315 CHNL_CTRL_IRQ_DLY_EN | CHNL_CTRL_IRQ_COAL_EN);
317 /* Init descriptor indexes */
323 /* Enable RX DMA transfers */
325 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
326 lp->dma_out(lp, RX_TAILDESC_PTR,
327 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
329 /* Prepare for TX DMA transfer */
330 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
335 temac_dma_bd_release(ndev);
339 /* ---------------------------------------------------------------------
343 static void temac_do_set_mac_address(struct net_device *ndev)
345 struct temac_local *lp = netdev_priv(ndev);
347 /* set up unicast MAC address filter set its mac address */
348 mutex_lock(lp->indirect_mutex);
349 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
350 (ndev->dev_addr[0]) |
351 (ndev->dev_addr[1] << 8) |
352 (ndev->dev_addr[2] << 16) |
353 (ndev->dev_addr[3] << 24));
354 /* There are reserved bits in EUAW1
355 * so don't affect them Set MAC bits [47:32] in EUAW1 */
356 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
357 (ndev->dev_addr[4] & 0x000000ff) |
358 (ndev->dev_addr[5] << 8));
359 mutex_unlock(lp->indirect_mutex);
362 static int temac_init_mac_address(struct net_device *ndev, const void *address)
364 ether_addr_copy(ndev->dev_addr, address);
365 if (!is_valid_ether_addr(ndev->dev_addr))
366 eth_hw_addr_random(ndev);
367 temac_do_set_mac_address(ndev);
371 static int temac_set_mac_address(struct net_device *ndev, void *p)
373 struct sockaddr *addr = p;
375 if (!is_valid_ether_addr(addr->sa_data))
376 return -EADDRNOTAVAIL;
377 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
378 temac_do_set_mac_address(ndev);
382 static void temac_set_multicast_list(struct net_device *ndev)
384 struct temac_local *lp = netdev_priv(ndev);
385 u32 multi_addr_msw, multi_addr_lsw, val;
388 mutex_lock(lp->indirect_mutex);
389 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
390 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
392 * We must make the kernel realise we had to move
393 * into promisc mode or we start all out war on
394 * the cable. If it was a promisc request the
395 * flag is already set. If not we assert it.
397 ndev->flags |= IFF_PROMISC;
398 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
399 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
400 } else if (!netdev_mc_empty(ndev)) {
401 struct netdev_hw_addr *ha;
404 netdev_for_each_mc_addr(ha, ndev) {
405 if (i >= MULTICAST_CAM_TABLE_NUM)
407 multi_addr_msw = ((ha->addr[3] << 24) |
408 (ha->addr[2] << 16) |
411 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
413 multi_addr_lsw = ((ha->addr[5] << 8) |
414 (ha->addr[4]) | (i << 16));
415 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
420 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
421 temac_indirect_out32(lp, XTE_AFM_OFFSET,
422 val & ~XTE_AFM_EPPRM_MASK);
423 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
424 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
425 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
427 mutex_unlock(lp->indirect_mutex);
430 static struct temac_option {
436 } temac_options[] = {
437 /* Turn on jumbo packet support for both Rx and Tx */
439 .opt = XTE_OPTION_JUMBO,
440 .reg = XTE_TXC_OFFSET,
441 .m_or = XTE_TXC_TXJMBO_MASK,
444 .opt = XTE_OPTION_JUMBO,
445 .reg = XTE_RXC1_OFFSET,
446 .m_or =XTE_RXC1_RXJMBO_MASK,
448 /* Turn on VLAN packet support for both Rx and Tx */
450 .opt = XTE_OPTION_VLAN,
451 .reg = XTE_TXC_OFFSET,
452 .m_or =XTE_TXC_TXVLAN_MASK,
455 .opt = XTE_OPTION_VLAN,
456 .reg = XTE_RXC1_OFFSET,
457 .m_or =XTE_RXC1_RXVLAN_MASK,
459 /* Turn on FCS stripping on receive packets */
461 .opt = XTE_OPTION_FCS_STRIP,
462 .reg = XTE_RXC1_OFFSET,
463 .m_or =XTE_RXC1_RXFCS_MASK,
465 /* Turn on FCS insertion on transmit packets */
467 .opt = XTE_OPTION_FCS_INSERT,
468 .reg = XTE_TXC_OFFSET,
469 .m_or =XTE_TXC_TXFCS_MASK,
471 /* Turn on length/type field checking on receive packets */
473 .opt = XTE_OPTION_LENTYPE_ERR,
474 .reg = XTE_RXC1_OFFSET,
475 .m_or =XTE_RXC1_RXLT_MASK,
477 /* Turn on flow control */
479 .opt = XTE_OPTION_FLOW_CONTROL,
480 .reg = XTE_FCC_OFFSET,
481 .m_or =XTE_FCC_RXFLO_MASK,
483 /* Turn on flow control */
485 .opt = XTE_OPTION_FLOW_CONTROL,
486 .reg = XTE_FCC_OFFSET,
487 .m_or =XTE_FCC_TXFLO_MASK,
489 /* Turn on promiscuous frame filtering (all frames are received ) */
491 .opt = XTE_OPTION_PROMISC,
492 .reg = XTE_AFM_OFFSET,
493 .m_or =XTE_AFM_EPPRM_MASK,
495 /* Enable transmitter if not already enabled */
497 .opt = XTE_OPTION_TXEN,
498 .reg = XTE_TXC_OFFSET,
499 .m_or =XTE_TXC_TXEN_MASK,
501 /* Enable receiver? */
503 .opt = XTE_OPTION_RXEN,
504 .reg = XTE_RXC1_OFFSET,
505 .m_or =XTE_RXC1_RXEN_MASK,
513 static u32 temac_setoptions(struct net_device *ndev, u32 options)
515 struct temac_local *lp = netdev_priv(ndev);
516 struct temac_option *tp = &temac_options[0];
519 mutex_lock(lp->indirect_mutex);
521 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
522 if (options & tp->opt)
524 temac_indirect_out32(lp, tp->reg, reg);
527 lp->options |= options;
528 mutex_unlock(lp->indirect_mutex);
533 /* Initialize temac */
534 static void temac_device_reset(struct net_device *ndev)
536 struct temac_local *lp = netdev_priv(ndev);
540 /* Perform a software reset */
542 /* 0x300 host enable bit ? */
543 /* reset PHY through control register ?:1 */
545 dev_dbg(&ndev->dev, "%s()\n", __func__);
547 mutex_lock(lp->indirect_mutex);
548 /* Reset the receiver and wait for it to finish reset */
549 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
551 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
553 if (--timeout == 0) {
555 "temac_device_reset RX reset timeout!!\n");
560 /* Reset the transmitter and wait for it to finish reset */
561 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
563 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
565 if (--timeout == 0) {
567 "temac_device_reset TX reset timeout!!\n");
572 /* Disable the receiver */
573 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
574 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
576 /* Reset Local Link (DMA) */
577 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
579 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
581 if (--timeout == 0) {
583 "temac_device_reset DMA reset timeout!!\n");
587 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
589 if (temac_dma_bd_init(ndev)) {
591 "temac_device_reset descriptor allocation failed\n");
594 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
595 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
596 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
597 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
599 mutex_unlock(lp->indirect_mutex);
601 /* Sync default options with HW
602 * but leave receiver and transmitter disabled. */
603 temac_setoptions(ndev,
604 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
606 temac_do_set_mac_address(ndev);
608 /* Set address filter table */
609 temac_set_multicast_list(ndev);
610 if (temac_setoptions(ndev, lp->options))
611 dev_err(&ndev->dev, "Error setting TEMAC options\n");
613 /* Init Driver variable */
614 netif_trans_update(ndev); /* prevent tx timeout */
617 static void temac_adjust_link(struct net_device *ndev)
619 struct temac_local *lp = netdev_priv(ndev);
620 struct phy_device *phy = ndev->phydev;
624 /* hash together the state values to decide if something has changed */
625 link_state = phy->speed | (phy->duplex << 1) | phy->link;
627 mutex_lock(lp->indirect_mutex);
628 if (lp->last_link != link_state) {
629 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
630 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
632 switch (phy->speed) {
633 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
634 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
635 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
638 /* Write new speed setting out to TEMAC */
639 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
640 lp->last_link = link_state;
641 phy_print_status(phy);
643 mutex_unlock(lp->indirect_mutex);
648 static void ptr_to_txbd(void *p, struct cdmac_bd *bd)
650 bd->app3 = (u32)(((u64)p) >> 32);
651 bd->app4 = (u32)((u64)p & 0xFFFFFFFF);
654 static void *ptr_from_txbd(struct cdmac_bd *bd)
656 return (void *)(((u64)(bd->app3) << 32) | bd->app4);
661 static void ptr_to_txbd(void *p, struct cdmac_bd *bd)
666 static void *ptr_from_txbd(struct cdmac_bd *bd)
668 return (void *)(bd->app4);
673 static void temac_start_xmit_done(struct net_device *ndev)
675 struct temac_local *lp = netdev_priv(ndev);
676 struct cdmac_bd *cur_p;
677 unsigned int stat = 0;
680 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
681 stat = be32_to_cpu(cur_p->app0);
683 while (stat & STS_CTRL_APP0_CMPLT) {
684 dma_unmap_single(ndev->dev.parent, be32_to_cpu(cur_p->phys),
685 be32_to_cpu(cur_p->len), DMA_TO_DEVICE);
686 skb = (struct sk_buff *)ptr_from_txbd(cur_p);
688 dev_consume_skb_irq(skb);
695 ndev->stats.tx_packets++;
696 ndev->stats.tx_bytes += be32_to_cpu(cur_p->len);
699 if (lp->tx_bd_ci >= TX_BD_NUM)
702 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
703 stat = be32_to_cpu(cur_p->app0);
706 netif_wake_queue(ndev);
709 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
711 struct cdmac_bd *cur_p;
714 tail = lp->tx_bd_tail;
715 cur_p = &lp->tx_bd_v[tail];
719 return NETDEV_TX_BUSY;
722 if (tail >= TX_BD_NUM)
725 cur_p = &lp->tx_bd_v[tail];
727 } while (num_frag >= 0);
733 temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
735 struct temac_local *lp = netdev_priv(ndev);
736 struct cdmac_bd *cur_p;
737 dma_addr_t start_p, tail_p, skb_dma_addr;
739 unsigned long num_frag;
742 num_frag = skb_shinfo(skb)->nr_frags;
743 frag = &skb_shinfo(skb)->frags[0];
744 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
745 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
747 if (temac_check_tx_bd_space(lp, num_frag + 1)) {
748 if (!netif_queue_stopped(ndev))
749 netif_stop_queue(ndev);
750 return NETDEV_TX_BUSY;
754 if (skb->ip_summed == CHECKSUM_PARTIAL) {
755 unsigned int csum_start_off = skb_checksum_start_offset(skb);
756 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
758 cur_p->app0 |= cpu_to_be32(0x000001); /* TX Checksum Enabled */
759 cur_p->app1 = cpu_to_be32((csum_start_off << 16)
761 cur_p->app2 = 0; /* initial checksum seed */
764 cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_SOP);
765 skb_dma_addr = dma_map_single(ndev->dev.parent, skb->data,
766 skb_headlen(skb), DMA_TO_DEVICE);
767 cur_p->len = cpu_to_be32(skb_headlen(skb));
768 cur_p->phys = cpu_to_be32(skb_dma_addr);
769 ptr_to_txbd((void *)skb, cur_p);
771 for (ii = 0; ii < num_frag; ii++) {
773 if (lp->tx_bd_tail >= TX_BD_NUM)
776 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
777 skb_dma_addr = dma_map_single(ndev->dev.parent,
778 skb_frag_address(frag),
781 cur_p->phys = cpu_to_be32(skb_dma_addr);
782 cur_p->len = cpu_to_be32(skb_frag_size(frag));
786 cur_p->app0 |= cpu_to_be32(STS_CTRL_APP0_EOP);
788 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
790 if (lp->tx_bd_tail >= TX_BD_NUM)
793 skb_tx_timestamp(skb);
795 /* Kick off the transfer */
797 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
803 static void ll_temac_recv(struct net_device *ndev)
805 struct temac_local *lp = netdev_priv(ndev);
806 struct sk_buff *skb, *new_skb;
808 struct cdmac_bd *cur_p;
809 dma_addr_t tail_p, skb_dma_addr;
813 spin_lock_irqsave(&lp->rx_lock, flags);
815 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
816 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
818 bdstat = be32_to_cpu(cur_p->app0);
819 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
821 skb = lp->rx_skb[lp->rx_bd_ci];
822 length = be32_to_cpu(cur_p->app4) & 0x3FFF;
824 dma_unmap_single(ndev->dev.parent, be32_to_cpu(cur_p->phys),
825 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
827 skb_put(skb, length);
828 skb->protocol = eth_type_trans(skb, ndev);
829 skb_checksum_none_assert(skb);
831 /* if we're doing rx csum offload, set it up */
832 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
833 (skb->protocol == htons(ETH_P_IP)) &&
836 /* Convert from device endianness (be32) to cpu
837 * endiannes, and if necessary swap the bytes
838 * (back) for proper IP checksum byte order
841 skb->csum = htons(be32_to_cpu(cur_p->app3) & 0xFFFF);
842 skb->ip_summed = CHECKSUM_COMPLETE;
845 if (!skb_defer_rx_timestamp(skb))
848 ndev->stats.rx_packets++;
849 ndev->stats.rx_bytes += length;
851 new_skb = netdev_alloc_skb_ip_align(ndev,
852 XTE_MAX_JUMBO_FRAME_SIZE);
854 spin_unlock_irqrestore(&lp->rx_lock, flags);
858 cur_p->app0 = cpu_to_be32(STS_CTRL_APP0_IRQONEND);
859 skb_dma_addr = dma_map_single(ndev->dev.parent, new_skb->data,
860 XTE_MAX_JUMBO_FRAME_SIZE,
862 cur_p->phys = cpu_to_be32(skb_dma_addr);
863 cur_p->len = cpu_to_be32(XTE_MAX_JUMBO_FRAME_SIZE);
864 lp->rx_skb[lp->rx_bd_ci] = new_skb;
867 if (lp->rx_bd_ci >= RX_BD_NUM)
870 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
871 bdstat = be32_to_cpu(cur_p->app0);
873 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
875 spin_unlock_irqrestore(&lp->rx_lock, flags);
878 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
880 struct net_device *ndev = _ndev;
881 struct temac_local *lp = netdev_priv(ndev);
884 status = lp->dma_in(lp, TX_IRQ_REG);
885 lp->dma_out(lp, TX_IRQ_REG, status);
887 if (status & (IRQ_COAL | IRQ_DLY))
888 temac_start_xmit_done(lp->ndev);
889 if (status & (IRQ_ERR | IRQ_DMAERR))
890 dev_err_ratelimited(&ndev->dev,
891 "TX error 0x%x TX_CHNL_STS=0x%08x\n",
892 status, lp->dma_in(lp, TX_CHNL_STS));
897 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
899 struct net_device *ndev = _ndev;
900 struct temac_local *lp = netdev_priv(ndev);
903 /* Read and clear the status registers */
904 status = lp->dma_in(lp, RX_IRQ_REG);
905 lp->dma_out(lp, RX_IRQ_REG, status);
907 if (status & (IRQ_COAL | IRQ_DLY))
908 ll_temac_recv(lp->ndev);
909 if (status & (IRQ_ERR | IRQ_DMAERR))
910 dev_err_ratelimited(&ndev->dev,
911 "RX error 0x%x RX_CHNL_STS=0x%08x\n",
912 status, lp->dma_in(lp, RX_CHNL_STS));
917 static int temac_open(struct net_device *ndev)
919 struct temac_local *lp = netdev_priv(ndev);
920 struct phy_device *phydev = NULL;
923 dev_dbg(&ndev->dev, "temac_open()\n");
926 phydev = of_phy_connect(lp->ndev, lp->phy_node,
927 temac_adjust_link, 0, 0);
929 dev_err(lp->dev, "of_phy_connect() failed\n");
933 } else if (strlen(lp->phy_name) > 0) {
934 phydev = phy_connect(lp->ndev, lp->phy_name, temac_adjust_link,
936 if (IS_ERR(phydev)) {
937 dev_err(lp->dev, "phy_connect() failed\n");
938 return PTR_ERR(phydev);
943 temac_device_reset(ndev);
945 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
948 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
955 free_irq(lp->tx_irq, ndev);
958 phy_disconnect(phydev);
959 dev_err(lp->dev, "request_irq() failed\n");
963 static int temac_stop(struct net_device *ndev)
965 struct temac_local *lp = netdev_priv(ndev);
966 struct phy_device *phydev = ndev->phydev;
968 dev_dbg(&ndev->dev, "temac_close()\n");
970 free_irq(lp->tx_irq, ndev);
971 free_irq(lp->rx_irq, ndev);
974 phy_disconnect(phydev);
976 temac_dma_bd_release(ndev);
981 #ifdef CONFIG_NET_POLL_CONTROLLER
983 temac_poll_controller(struct net_device *ndev)
985 struct temac_local *lp = netdev_priv(ndev);
987 disable_irq(lp->tx_irq);
988 disable_irq(lp->rx_irq);
990 ll_temac_rx_irq(lp->tx_irq, ndev);
991 ll_temac_tx_irq(lp->rx_irq, ndev);
993 enable_irq(lp->tx_irq);
994 enable_irq(lp->rx_irq);
998 static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
1000 if (!netif_running(ndev))
1006 return phy_mii_ioctl(ndev->phydev, rq, cmd);
1009 static const struct net_device_ops temac_netdev_ops = {
1010 .ndo_open = temac_open,
1011 .ndo_stop = temac_stop,
1012 .ndo_start_xmit = temac_start_xmit,
1013 .ndo_set_mac_address = temac_set_mac_address,
1014 .ndo_validate_addr = eth_validate_addr,
1015 .ndo_do_ioctl = temac_ioctl,
1016 #ifdef CONFIG_NET_POLL_CONTROLLER
1017 .ndo_poll_controller = temac_poll_controller,
1021 /* ---------------------------------------------------------------------
1022 * SYSFS device attributes
1024 static ssize_t temac_show_llink_regs(struct device *dev,
1025 struct device_attribute *attr, char *buf)
1027 struct net_device *ndev = dev_get_drvdata(dev);
1028 struct temac_local *lp = netdev_priv(ndev);
1031 for (i = 0; i < 0x11; i++)
1032 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
1033 (i % 8) == 7 ? "\n" : " ");
1034 len += sprintf(buf + len, "\n");
1039 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
1041 static struct attribute *temac_device_attrs[] = {
1042 &dev_attr_llink_regs.attr,
1046 static const struct attribute_group temac_attr_group = {
1047 .attrs = temac_device_attrs,
1050 /* ethtool support */
1051 static const struct ethtool_ops temac_ethtool_ops = {
1052 .nway_reset = phy_ethtool_nway_reset,
1053 .get_link = ethtool_op_get_link,
1054 .get_ts_info = ethtool_op_get_ts_info,
1055 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1056 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1059 static int temac_probe(struct platform_device *pdev)
1061 struct ll_temac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1062 struct device_node *temac_np = dev_of_node(&pdev->dev), *dma_np;
1063 struct temac_local *lp;
1064 struct net_device *ndev;
1065 struct resource *res;
1071 /* Init network device structure */
1072 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*lp));
1076 platform_set_drvdata(pdev, ndev);
1077 SET_NETDEV_DEV(ndev, &pdev->dev);
1078 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1079 ndev->features = NETIF_F_SG;
1080 ndev->netdev_ops = &temac_netdev_ops;
1081 ndev->ethtool_ops = &temac_ethtool_ops;
1083 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1084 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1085 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1086 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1087 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */
1088 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */
1089 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */
1090 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1091 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1092 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1093 ndev->features |= NETIF_F_LRO; /* large receive offload */
1096 /* setup temac private info structure */
1097 lp = netdev_priv(ndev);
1099 lp->dev = &pdev->dev;
1100 lp->options = XTE_OPTION_DEFAULTS;
1101 spin_lock_init(&lp->rx_lock);
1103 /* Setup mutex for synchronization of indirect register access */
1105 if (!pdata->indirect_mutex) {
1107 "indirect_mutex missing in platform_data\n");
1110 lp->indirect_mutex = pdata->indirect_mutex;
1112 lp->indirect_mutex = devm_kmalloc(&pdev->dev,
1113 sizeof(*lp->indirect_mutex),
1115 mutex_init(lp->indirect_mutex);
1118 /* map device registers */
1119 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1120 lp->regs = devm_ioremap_nocache(&pdev->dev, res->start,
1121 resource_size(res));
1122 if (IS_ERR(lp->regs)) {
1123 dev_err(&pdev->dev, "could not map TEMAC registers\n");
1124 return PTR_ERR(lp->regs);
1127 /* Select register access functions with the specified
1128 * endianness mode. Default for OF devices is big-endian.
1130 little_endian = false;
1132 if (of_get_property(temac_np, "little-endian", NULL))
1133 little_endian = true;
1135 little_endian = pdata->reg_little_endian;
1137 if (little_endian) {
1138 lp->temac_ior = _temac_ior_le;
1139 lp->temac_iow = _temac_iow_le;
1141 lp->temac_ior = _temac_ior_be;
1142 lp->temac_iow = _temac_iow_be;
1145 /* Setup checksum offload, but default to off if not specified */
1146 lp->temac_features = 0;
1148 p = (__be32 *)of_get_property(temac_np, "xlnx,txcsum", NULL);
1149 if (p && be32_to_cpu(*p))
1150 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1151 p = (__be32 *)of_get_property(temac_np, "xlnx,rxcsum", NULL);
1152 if (p && be32_to_cpu(*p))
1153 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1156 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1158 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1160 if (lp->temac_features & TEMAC_FEATURE_TX_CSUM)
1161 /* Can checksum TCP/UDP over IPv4. */
1162 ndev->features |= NETIF_F_IP_CSUM;
1164 /* Setup LocalLink DMA */
1166 /* Find the DMA node, map the DMA registers, and
1167 * decode the DMA IRQs.
1169 dma_np = of_parse_phandle(temac_np, "llink-connected", 0);
1171 dev_err(&pdev->dev, "could not find DMA node\n");
1175 /* Setup the DMA register accesses, could be DCR or
1178 if (temac_dcr_setup(lp, pdev, dma_np)) {
1179 /* no DCR in the device tree, try non-DCR */
1180 lp->sdma_regs = devm_of_iomap(&pdev->dev, dma_np, 0,
1182 if (IS_ERR(lp->sdma_regs)) {
1184 "unable to map DMA registers\n");
1185 of_node_put(dma_np);
1186 return PTR_ERR(lp->sdma_regs);
1188 if (of_get_property(dma_np, "little-endian", NULL)) {
1189 lp->dma_in = temac_dma_in32_le;
1190 lp->dma_out = temac_dma_out32_le;
1192 lp->dma_in = temac_dma_in32_be;
1193 lp->dma_out = temac_dma_out32_be;
1195 dev_dbg(&pdev->dev, "MEM base: %p\n", lp->sdma_regs);
1198 /* Get DMA RX and TX interrupts */
1199 lp->rx_irq = irq_of_parse_and_map(dma_np, 0);
1200 lp->tx_irq = irq_of_parse_and_map(dma_np, 1);
1202 /* Use defaults for IRQ delay/coalescing setup. These
1203 * are configuration values, so does not belong in
1206 lp->tx_chnl_ctrl = 0x10220000;
1207 lp->rx_chnl_ctrl = 0xff070000;
1209 /* Finished with the DMA node; drop the reference */
1210 of_node_put(dma_np);
1212 /* 2nd memory resource specifies DMA registers */
1213 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1214 lp->sdma_regs = devm_ioremap_nocache(&pdev->dev, res->start,
1215 resource_size(res));
1216 if (IS_ERR(lp->sdma_regs)) {
1218 "could not map DMA registers\n");
1219 return PTR_ERR(lp->sdma_regs);
1221 if (pdata->dma_little_endian) {
1222 lp->dma_in = temac_dma_in32_le;
1223 lp->dma_out = temac_dma_out32_le;
1225 lp->dma_in = temac_dma_in32_be;
1226 lp->dma_out = temac_dma_out32_be;
1229 /* Get DMA RX and TX interrupts */
1230 lp->rx_irq = platform_get_irq(pdev, 0);
1231 lp->tx_irq = platform_get_irq(pdev, 1);
1233 /* IRQ delay/coalescing setup */
1234 if (pdata->tx_irq_timeout || pdata->tx_irq_count)
1235 lp->tx_chnl_ctrl = (pdata->tx_irq_timeout << 24) |
1236 (pdata->tx_irq_count << 16);
1238 lp->tx_chnl_ctrl = 0x10220000;
1239 if (pdata->rx_irq_timeout || pdata->rx_irq_count)
1240 lp->rx_chnl_ctrl = (pdata->rx_irq_timeout << 24) |
1241 (pdata->rx_irq_count << 16);
1243 lp->rx_chnl_ctrl = 0xff070000;
1246 /* Error handle returned DMA RX and TX interrupts */
1247 if (lp->rx_irq < 0) {
1248 if (lp->rx_irq != -EPROBE_DEFER)
1249 dev_err(&pdev->dev, "could not get DMA RX irq\n");
1252 if (lp->tx_irq < 0) {
1253 if (lp->tx_irq != -EPROBE_DEFER)
1254 dev_err(&pdev->dev, "could not get DMA TX irq\n");
1259 /* Retrieve the MAC address */
1260 addr = of_get_mac_address(temac_np);
1262 dev_err(&pdev->dev, "could not find MAC address\n");
1265 temac_init_mac_address(ndev, addr);
1267 temac_init_mac_address(ndev, pdata->mac_addr);
1270 rc = temac_mdio_setup(lp, pdev);
1272 dev_warn(&pdev->dev, "error registering MDIO bus\n");
1275 lp->phy_node = of_parse_phandle(temac_np, "phy-handle", 0);
1277 dev_dbg(lp->dev, "using PHY node %pOF\n", temac_np);
1279 snprintf(lp->phy_name, sizeof(lp->phy_name),
1280 PHY_ID_FMT, lp->mii_bus->id, pdata->phy_addr);
1281 lp->phy_interface = pdata->phy_interface;
1284 /* Add the device attributes */
1285 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1287 dev_err(lp->dev, "Error creating sysfs files\n");
1288 goto err_sysfs_create;
1291 rc = register_netdev(lp->ndev);
1293 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1294 goto err_register_ndev;
1300 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1303 of_node_put(lp->phy_node);
1304 temac_mdio_teardown(lp);
1308 static int temac_remove(struct platform_device *pdev)
1310 struct net_device *ndev = platform_get_drvdata(pdev);
1311 struct temac_local *lp = netdev_priv(ndev);
1313 unregister_netdev(ndev);
1314 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1316 of_node_put(lp->phy_node);
1317 temac_mdio_teardown(lp);
1321 static const struct of_device_id temac_of_match[] = {
1322 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1323 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1324 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1325 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1328 MODULE_DEVICE_TABLE(of, temac_of_match);
1330 static struct platform_driver temac_driver = {
1331 .probe = temac_probe,
1332 .remove = temac_remove,
1334 .name = "xilinx_temac",
1335 .of_match_table = temac_of_match,
1339 module_platform_driver(temac_driver);
1341 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1342 MODULE_AUTHOR("Yoshio Kashiwagi");
1343 MODULE_LICENSE("GPL");