2 * Driver for Xilinx TEMAC Ethernet device
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/init.h>
33 #include <linux/mii.h>
34 #include <linux/module.h>
35 #include <linux/mutex.h>
36 #include <linux/netdevice.h>
38 #include <linux/of_device.h>
39 #include <linux/of_mdio.h>
40 #include <linux/of_platform.h>
41 #include <linux/of_address.h>
42 #include <linux/skbuff.h>
43 #include <linux/spinlock.h>
44 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */
45 #include <linux/udp.h> /* needed for sizeof(udphdr) */
46 #include <linux/phy.h>
50 #include <linux/slab.h>
51 #include <linux/interrupt.h>
52 #include <linux/dma-mapping.h>
59 /* ---------------------------------------------------------------------
60 * Low level register access functions
63 u32 temac_ior(struct temac_local *lp, int offset)
65 return in_be32((u32 *)(lp->regs + offset));
68 void temac_iow(struct temac_local *lp, int offset, u32 value)
70 out_be32((u32 *) (lp->regs + offset), value);
73 int temac_indirect_busywait(struct temac_local *lp)
75 long end = jiffies + 2;
77 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
78 if (end - jiffies <= 0) {
90 * lp->indirect_mutex must be held when calling this function
92 u32 temac_indirect_in32(struct temac_local *lp, int reg)
96 if (temac_indirect_busywait(lp))
98 temac_iow(lp, XTE_CTL0_OFFSET, reg);
99 if (temac_indirect_busywait(lp))
101 val = temac_ior(lp, XTE_LSW0_OFFSET);
107 * temac_indirect_out32
109 * lp->indirect_mutex must be held when calling this function
111 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
113 if (temac_indirect_busywait(lp))
115 temac_iow(lp, XTE_LSW0_OFFSET, value);
116 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
117 temac_indirect_busywait(lp);
121 * temac_dma_in32 - Memory mapped DMA read, this function expects a
122 * register input that is based on DCR word addresses which
123 * are then converted to memory mapped byte addresses
125 static u32 temac_dma_in32(struct temac_local *lp, int reg)
127 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
131 * temac_dma_out32 - Memory mapped DMA read, this function expects a
132 * register input that is based on DCR word addresses which
133 * are then converted to memory mapped byte addresses
135 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
137 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
140 /* DMA register access functions can be DCR based or memory mapped.
141 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
144 #ifdef CONFIG_PPC_DCR
147 * temac_dma_dcr_in32 - DCR based DMA read
149 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
151 return dcr_read(lp->sdma_dcrs, reg);
155 * temac_dma_dcr_out32 - DCR based DMA write
157 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
159 dcr_write(lp->sdma_dcrs, reg, value);
163 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
166 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
167 struct device_node *np)
171 /* setup the dcr address mapping if it's in the device tree */
173 dcrs = dcr_resource_start(np, 0);
175 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
176 lp->dma_in = temac_dma_dcr_in;
177 lp->dma_out = temac_dma_dcr_out;
178 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
181 /* no DCR in the device tree, indicate a failure */
188 * temac_dcr_setup - This is a stub for when DCR is not supported,
189 * such as with MicroBlaze
191 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
192 struct device_node *np)
200 * * temac_dma_bd_release - Release buffer descriptor rings
202 static void temac_dma_bd_release(struct net_device *ndev)
204 struct temac_local *lp = netdev_priv(ndev);
207 /* Reset Local Link (DMA) */
208 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
210 for (i = 0; i < RX_BD_NUM; i++) {
214 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
215 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
216 dev_kfree_skb(lp->rx_skb[i]);
220 dma_free_coherent(ndev->dev.parent,
221 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
222 lp->rx_bd_v, lp->rx_bd_p);
224 dma_free_coherent(ndev->dev.parent,
225 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
226 lp->tx_bd_v, lp->tx_bd_p);
232 * temac_dma_bd_init - Setup buffer descriptor rings
234 static int temac_dma_bd_init(struct net_device *ndev)
236 struct temac_local *lp = netdev_priv(ndev);
240 lp->rx_skb = kzalloc(sizeof(*lp->rx_skb) * RX_BD_NUM, GFP_KERNEL);
243 "can't allocate memory for DMA RX buffer\n");
246 /* allocate the tx and rx ring buffer descriptors. */
247 /* returns a virtual address and a physical address. */
248 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
249 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
250 &lp->tx_bd_p, GFP_KERNEL);
253 "unable to allocate DMA TX buffer descriptors");
256 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
257 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
258 &lp->rx_bd_p, GFP_KERNEL);
261 "unable to allocate DMA RX buffer descriptors");
265 memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
266 for (i = 0; i < TX_BD_NUM; i++) {
267 lp->tx_bd_v[i].next = lp->tx_bd_p +
268 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
271 memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
272 for (i = 0; i < RX_BD_NUM; i++) {
273 lp->rx_bd_v[i].next = lp->rx_bd_p +
274 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
276 skb = netdev_alloc_skb_ip_align(ndev,
277 XTE_MAX_JUMBO_FRAME_SIZE);
280 dev_err(&ndev->dev, "alloc_skb error %d\n", i);
284 /* returns physical address of skb->data */
285 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
287 XTE_MAX_JUMBO_FRAME_SIZE,
289 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
290 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
293 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
295 CHNL_CTRL_IRQ_DLY_EN |
296 CHNL_CTRL_IRQ_COAL_EN);
299 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
301 CHNL_CTRL_IRQ_DLY_EN |
302 CHNL_CTRL_IRQ_COAL_EN |
306 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
307 lp->dma_out(lp, RX_TAILDESC_PTR,
308 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
309 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
314 temac_dma_bd_release(ndev);
318 /* ---------------------------------------------------------------------
322 static int temac_set_mac_address(struct net_device *ndev, void *address)
324 struct temac_local *lp = netdev_priv(ndev);
327 memcpy(ndev->dev_addr, address, ETH_ALEN);
329 if (!is_valid_ether_addr(ndev->dev_addr))
330 random_ether_addr(ndev->dev_addr);
332 /* set up unicast MAC address filter set its mac address */
333 mutex_lock(&lp->indirect_mutex);
334 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
335 (ndev->dev_addr[0]) |
336 (ndev->dev_addr[1] << 8) |
337 (ndev->dev_addr[2] << 16) |
338 (ndev->dev_addr[3] << 24));
339 /* There are reserved bits in EUAW1
340 * so don't affect them Set MAC bits [47:32] in EUAW1 */
341 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
342 (ndev->dev_addr[4] & 0x000000ff) |
343 (ndev->dev_addr[5] << 8));
344 mutex_unlock(&lp->indirect_mutex);
349 static int netdev_set_mac_address(struct net_device *ndev, void *p)
351 struct sockaddr *addr = p;
353 return temac_set_mac_address(ndev, addr->sa_data);
356 static void temac_set_multicast_list(struct net_device *ndev)
358 struct temac_local *lp = netdev_priv(ndev);
359 u32 multi_addr_msw, multi_addr_lsw, val;
362 mutex_lock(&lp->indirect_mutex);
363 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
364 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
366 * We must make the kernel realise we had to move
367 * into promisc mode or we start all out war on
368 * the cable. If it was a promisc request the
369 * flag is already set. If not we assert it.
371 ndev->flags |= IFF_PROMISC;
372 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
373 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
374 } else if (!netdev_mc_empty(ndev)) {
375 struct netdev_hw_addr *ha;
378 netdev_for_each_mc_addr(ha, ndev) {
379 if (i >= MULTICAST_CAM_TABLE_NUM)
381 multi_addr_msw = ((ha->addr[3] << 24) |
382 (ha->addr[2] << 16) |
385 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
387 multi_addr_lsw = ((ha->addr[5] << 8) |
388 (ha->addr[4]) | (i << 16));
389 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
394 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
395 temac_indirect_out32(lp, XTE_AFM_OFFSET,
396 val & ~XTE_AFM_EPPRM_MASK);
397 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
398 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
399 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
401 mutex_unlock(&lp->indirect_mutex);
404 struct temac_option {
410 } temac_options[] = {
411 /* Turn on jumbo packet support for both Rx and Tx */
413 .opt = XTE_OPTION_JUMBO,
414 .reg = XTE_TXC_OFFSET,
415 .m_or = XTE_TXC_TXJMBO_MASK,
418 .opt = XTE_OPTION_JUMBO,
419 .reg = XTE_RXC1_OFFSET,
420 .m_or =XTE_RXC1_RXJMBO_MASK,
422 /* Turn on VLAN packet support for both Rx and Tx */
424 .opt = XTE_OPTION_VLAN,
425 .reg = XTE_TXC_OFFSET,
426 .m_or =XTE_TXC_TXVLAN_MASK,
429 .opt = XTE_OPTION_VLAN,
430 .reg = XTE_RXC1_OFFSET,
431 .m_or =XTE_RXC1_RXVLAN_MASK,
433 /* Turn on FCS stripping on receive packets */
435 .opt = XTE_OPTION_FCS_STRIP,
436 .reg = XTE_RXC1_OFFSET,
437 .m_or =XTE_RXC1_RXFCS_MASK,
439 /* Turn on FCS insertion on transmit packets */
441 .opt = XTE_OPTION_FCS_INSERT,
442 .reg = XTE_TXC_OFFSET,
443 .m_or =XTE_TXC_TXFCS_MASK,
445 /* Turn on length/type field checking on receive packets */
447 .opt = XTE_OPTION_LENTYPE_ERR,
448 .reg = XTE_RXC1_OFFSET,
449 .m_or =XTE_RXC1_RXLT_MASK,
451 /* Turn on flow control */
453 .opt = XTE_OPTION_FLOW_CONTROL,
454 .reg = XTE_FCC_OFFSET,
455 .m_or =XTE_FCC_RXFLO_MASK,
457 /* Turn on flow control */
459 .opt = XTE_OPTION_FLOW_CONTROL,
460 .reg = XTE_FCC_OFFSET,
461 .m_or =XTE_FCC_TXFLO_MASK,
463 /* Turn on promiscuous frame filtering (all frames are received ) */
465 .opt = XTE_OPTION_PROMISC,
466 .reg = XTE_AFM_OFFSET,
467 .m_or =XTE_AFM_EPPRM_MASK,
469 /* Enable transmitter if not already enabled */
471 .opt = XTE_OPTION_TXEN,
472 .reg = XTE_TXC_OFFSET,
473 .m_or =XTE_TXC_TXEN_MASK,
475 /* Enable receiver? */
477 .opt = XTE_OPTION_RXEN,
478 .reg = XTE_RXC1_OFFSET,
479 .m_or =XTE_RXC1_RXEN_MASK,
487 static u32 temac_setoptions(struct net_device *ndev, u32 options)
489 struct temac_local *lp = netdev_priv(ndev);
490 struct temac_option *tp = &temac_options[0];
493 mutex_lock(&lp->indirect_mutex);
495 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
496 if (options & tp->opt)
498 temac_indirect_out32(lp, tp->reg, reg);
501 lp->options |= options;
502 mutex_unlock(&lp->indirect_mutex);
507 /* Initialize temac */
508 static void temac_device_reset(struct net_device *ndev)
510 struct temac_local *lp = netdev_priv(ndev);
514 /* Perform a software reset */
516 /* 0x300 host enable bit ? */
517 /* reset PHY through control register ?:1 */
519 dev_dbg(&ndev->dev, "%s()\n", __func__);
521 mutex_lock(&lp->indirect_mutex);
522 /* Reset the receiver and wait for it to finish reset */
523 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
525 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
527 if (--timeout == 0) {
529 "temac_device_reset RX reset timeout!!\n");
534 /* Reset the transmitter and wait for it to finish reset */
535 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
537 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
539 if (--timeout == 0) {
541 "temac_device_reset TX reset timeout!!\n");
546 /* Disable the receiver */
547 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
548 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
550 /* Reset Local Link (DMA) */
551 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
553 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
555 if (--timeout == 0) {
557 "temac_device_reset DMA reset timeout!!\n");
561 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
563 if (temac_dma_bd_init(ndev)) {
565 "temac_device_reset descriptor allocation failed\n");
568 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
569 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
570 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
571 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
573 mutex_unlock(&lp->indirect_mutex);
575 /* Sync default options with HW
576 * but leave receiver and transmitter disabled. */
577 temac_setoptions(ndev,
578 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
580 temac_set_mac_address(ndev, NULL);
582 /* Set address filter table */
583 temac_set_multicast_list(ndev);
584 if (temac_setoptions(ndev, lp->options))
585 dev_err(&ndev->dev, "Error setting TEMAC options\n");
587 /* Init Driver variable */
588 ndev->trans_start = jiffies; /* prevent tx timeout */
591 void temac_adjust_link(struct net_device *ndev)
593 struct temac_local *lp = netdev_priv(ndev);
594 struct phy_device *phy = lp->phy_dev;
598 /* hash together the state values to decide if something has changed */
599 link_state = phy->speed | (phy->duplex << 1) | phy->link;
601 mutex_lock(&lp->indirect_mutex);
602 if (lp->last_link != link_state) {
603 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
604 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
606 switch (phy->speed) {
607 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
608 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
609 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
612 /* Write new speed setting out to TEMAC */
613 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
614 lp->last_link = link_state;
615 phy_print_status(phy);
617 mutex_unlock(&lp->indirect_mutex);
620 static void temac_start_xmit_done(struct net_device *ndev)
622 struct temac_local *lp = netdev_priv(ndev);
623 struct cdmac_bd *cur_p;
624 unsigned int stat = 0;
626 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
629 while (stat & STS_CTRL_APP0_CMPLT) {
630 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
633 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
640 ndev->stats.tx_packets++;
641 ndev->stats.tx_bytes += cur_p->len;
644 if (lp->tx_bd_ci >= TX_BD_NUM)
647 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
651 netif_wake_queue(ndev);
654 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
656 struct cdmac_bd *cur_p;
659 tail = lp->tx_bd_tail;
660 cur_p = &lp->tx_bd_v[tail];
664 return NETDEV_TX_BUSY;
667 if (tail >= TX_BD_NUM)
670 cur_p = &lp->tx_bd_v[tail];
672 } while (num_frag >= 0);
677 static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
679 struct temac_local *lp = netdev_priv(ndev);
680 struct cdmac_bd *cur_p;
681 dma_addr_t start_p, tail_p;
683 unsigned long num_frag;
686 num_frag = skb_shinfo(skb)->nr_frags;
687 frag = &skb_shinfo(skb)->frags[0];
688 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
689 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
691 if (temac_check_tx_bd_space(lp, num_frag)) {
692 if (!netif_queue_stopped(ndev)) {
693 netif_stop_queue(ndev);
694 return NETDEV_TX_BUSY;
696 return NETDEV_TX_BUSY;
700 if (skb->ip_summed == CHECKSUM_PARTIAL) {
701 unsigned int csum_start_off = skb_checksum_start_offset(skb);
702 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
704 cur_p->app0 |= 1; /* TX Checksum Enabled */
705 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
706 cur_p->app2 = 0; /* initial checksum seed */
709 cur_p->app0 |= STS_CTRL_APP0_SOP;
710 cur_p->len = skb_headlen(skb);
711 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
713 cur_p->app4 = (unsigned long)skb;
715 for (ii = 0; ii < num_frag; ii++) {
717 if (lp->tx_bd_tail >= TX_BD_NUM)
720 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
721 cur_p->phys = dma_map_single(ndev->dev.parent,
722 skb_frag_address(frag),
723 skb_frag_size(frag), DMA_TO_DEVICE);
724 cur_p->len = skb_frag_size(frag);
728 cur_p->app0 |= STS_CTRL_APP0_EOP;
730 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
732 if (lp->tx_bd_tail >= TX_BD_NUM)
735 skb_tx_timestamp(skb);
737 /* Kick off the transfer */
738 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
744 static void ll_temac_recv(struct net_device *ndev)
746 struct temac_local *lp = netdev_priv(ndev);
747 struct sk_buff *skb, *new_skb;
749 struct cdmac_bd *cur_p;
754 spin_lock_irqsave(&lp->rx_lock, flags);
756 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
757 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
759 bdstat = cur_p->app0;
760 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
762 skb = lp->rx_skb[lp->rx_bd_ci];
763 length = cur_p->app4 & 0x3FFF;
765 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
768 skb_put(skb, length);
770 skb->protocol = eth_type_trans(skb, ndev);
771 skb_checksum_none_assert(skb);
773 /* if we're doing rx csum offload, set it up */
774 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
775 (skb->protocol == __constant_htons(ETH_P_IP)) &&
778 skb->csum = cur_p->app3 & 0xFFFF;
779 skb->ip_summed = CHECKSUM_COMPLETE;
782 if (!skb_defer_rx_timestamp(skb))
785 ndev->stats.rx_packets++;
786 ndev->stats.rx_bytes += length;
788 new_skb = netdev_alloc_skb_ip_align(ndev,
789 XTE_MAX_JUMBO_FRAME_SIZE);
792 dev_err(&ndev->dev, "no memory for new sk_buff\n");
793 spin_unlock_irqrestore(&lp->rx_lock, flags);
797 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
798 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
799 XTE_MAX_JUMBO_FRAME_SIZE,
801 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
802 lp->rx_skb[lp->rx_bd_ci] = new_skb;
805 if (lp->rx_bd_ci >= RX_BD_NUM)
808 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
809 bdstat = cur_p->app0;
811 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
813 spin_unlock_irqrestore(&lp->rx_lock, flags);
816 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
818 struct net_device *ndev = _ndev;
819 struct temac_local *lp = netdev_priv(ndev);
822 status = lp->dma_in(lp, TX_IRQ_REG);
823 lp->dma_out(lp, TX_IRQ_REG, status);
825 if (status & (IRQ_COAL | IRQ_DLY))
826 temac_start_xmit_done(lp->ndev);
828 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
833 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
835 struct net_device *ndev = _ndev;
836 struct temac_local *lp = netdev_priv(ndev);
839 /* Read and clear the status registers */
840 status = lp->dma_in(lp, RX_IRQ_REG);
841 lp->dma_out(lp, RX_IRQ_REG, status);
843 if (status & (IRQ_COAL | IRQ_DLY))
844 ll_temac_recv(lp->ndev);
849 static int temac_open(struct net_device *ndev)
851 struct temac_local *lp = netdev_priv(ndev);
854 dev_dbg(&ndev->dev, "temac_open()\n");
857 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
858 temac_adjust_link, 0, 0);
860 dev_err(lp->dev, "of_phy_connect() failed\n");
864 phy_start(lp->phy_dev);
867 temac_device_reset(ndev);
869 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
872 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
879 free_irq(lp->tx_irq, ndev);
882 phy_disconnect(lp->phy_dev);
884 dev_err(lp->dev, "request_irq() failed\n");
888 static int temac_stop(struct net_device *ndev)
890 struct temac_local *lp = netdev_priv(ndev);
892 dev_dbg(&ndev->dev, "temac_close()\n");
894 free_irq(lp->tx_irq, ndev);
895 free_irq(lp->rx_irq, ndev);
898 phy_disconnect(lp->phy_dev);
901 temac_dma_bd_release(ndev);
906 #ifdef CONFIG_NET_POLL_CONTROLLER
908 temac_poll_controller(struct net_device *ndev)
910 struct temac_local *lp = netdev_priv(ndev);
912 disable_irq(lp->tx_irq);
913 disable_irq(lp->rx_irq);
915 ll_temac_rx_irq(lp->tx_irq, ndev);
916 ll_temac_tx_irq(lp->rx_irq, ndev);
918 enable_irq(lp->tx_irq);
919 enable_irq(lp->rx_irq);
923 static const struct net_device_ops temac_netdev_ops = {
924 .ndo_open = temac_open,
925 .ndo_stop = temac_stop,
926 .ndo_start_xmit = temac_start_xmit,
927 .ndo_set_mac_address = netdev_set_mac_address,
928 .ndo_validate_addr = eth_validate_addr,
929 #ifdef CONFIG_NET_POLL_CONTROLLER
930 .ndo_poll_controller = temac_poll_controller,
934 /* ---------------------------------------------------------------------
935 * SYSFS device attributes
937 static ssize_t temac_show_llink_regs(struct device *dev,
938 struct device_attribute *attr, char *buf)
940 struct net_device *ndev = dev_get_drvdata(dev);
941 struct temac_local *lp = netdev_priv(ndev);
944 for (i = 0; i < 0x11; i++)
945 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
946 (i % 8) == 7 ? "\n" : " ");
947 len += sprintf(buf + len, "\n");
952 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
954 static struct attribute *temac_device_attrs[] = {
955 &dev_attr_llink_regs.attr,
959 static const struct attribute_group temac_attr_group = {
960 .attrs = temac_device_attrs,
963 /* ethtool support */
964 static int temac_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
966 struct temac_local *lp = netdev_priv(ndev);
967 return phy_ethtool_gset(lp->phy_dev, cmd);
970 static int temac_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
972 struct temac_local *lp = netdev_priv(ndev);
973 return phy_ethtool_sset(lp->phy_dev, cmd);
976 static int temac_nway_reset(struct net_device *ndev)
978 struct temac_local *lp = netdev_priv(ndev);
979 return phy_start_aneg(lp->phy_dev);
982 static const struct ethtool_ops temac_ethtool_ops = {
983 .get_settings = temac_get_settings,
984 .set_settings = temac_set_settings,
985 .nway_reset = temac_nway_reset,
986 .get_link = ethtool_op_get_link,
989 static int __devinit temac_of_probe(struct platform_device *op)
991 struct device_node *np;
992 struct temac_local *lp;
993 struct net_device *ndev;
998 /* Init network device structure */
999 ndev = alloc_etherdev(sizeof(*lp));
1001 dev_err(&op->dev, "could not allocate device.\n");
1005 dev_set_drvdata(&op->dev, ndev);
1006 SET_NETDEV_DEV(ndev, &op->dev);
1007 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1008 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
1009 ndev->netdev_ops = &temac_netdev_ops;
1010 ndev->ethtool_ops = &temac_ethtool_ops;
1012 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1013 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1014 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1015 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1016 ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
1017 ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
1018 ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
1019 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1020 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1021 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1022 ndev->features |= NETIF_F_LRO; /* large receive offload */
1025 /* setup temac private info structure */
1026 lp = netdev_priv(ndev);
1029 lp->options = XTE_OPTION_DEFAULTS;
1030 spin_lock_init(&lp->rx_lock);
1031 mutex_init(&lp->indirect_mutex);
1033 /* map device registers */
1034 lp->regs = of_iomap(op->dev.of_node, 0);
1036 dev_err(&op->dev, "could not map temac regs.\n");
1040 /* Setup checksum offload, but default to off if not specified */
1041 lp->temac_features = 0;
1042 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1043 if (p && be32_to_cpu(*p)) {
1044 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1045 /* Can checksum TCP/UDP over IPv4. */
1046 ndev->features |= NETIF_F_IP_CSUM;
1048 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1049 if (p && be32_to_cpu(*p))
1050 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1052 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1053 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
1055 dev_err(&op->dev, "could not find DMA node\n");
1059 /* Setup the DMA register accesses, could be DCR or memory mapped */
1060 if (temac_dcr_setup(lp, op, np)) {
1062 /* no DCR in the device tree, try non-DCR */
1063 lp->sdma_regs = of_iomap(np, 0);
1064 if (lp->sdma_regs) {
1065 lp->dma_in = temac_dma_in32;
1066 lp->dma_out = temac_dma_out32;
1067 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1069 dev_err(&op->dev, "unable to map DMA registers\n");
1075 lp->rx_irq = irq_of_parse_and_map(np, 0);
1076 lp->tx_irq = irq_of_parse_and_map(np, 1);
1078 of_node_put(np); /* Finished with the DMA node; drop the reference */
1080 if ((lp->rx_irq == NO_IRQ) || (lp->tx_irq == NO_IRQ)) {
1081 dev_err(&op->dev, "could not determine irqs\n");
1087 /* Retrieve the MAC address */
1088 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
1089 if ((!addr) || (size != 6)) {
1090 dev_err(&op->dev, "could not find MAC address\n");
1094 temac_set_mac_address(ndev, (void *)addr);
1096 rc = temac_mdio_setup(lp, op->dev.of_node);
1098 dev_warn(&op->dev, "error registering MDIO bus\n");
1100 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
1102 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1104 /* Add the device attributes */
1105 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1107 dev_err(lp->dev, "Error creating sysfs files\n");
1111 rc = register_netdev(lp->ndev);
1113 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1114 goto err_register_ndev;
1120 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1123 iounmap(lp->sdma_regs);
1132 static int __devexit temac_of_remove(struct platform_device *op)
1134 struct net_device *ndev = dev_get_drvdata(&op->dev);
1135 struct temac_local *lp = netdev_priv(ndev);
1137 temac_mdio_teardown(lp);
1138 unregister_netdev(ndev);
1139 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1141 of_node_put(lp->phy_node);
1142 lp->phy_node = NULL;
1143 dev_set_drvdata(&op->dev, NULL);
1146 iounmap(lp->sdma_regs);
1151 static struct of_device_id temac_of_match[] __devinitdata = {
1152 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1153 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1154 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1155 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1158 MODULE_DEVICE_TABLE(of, temac_of_match);
1160 static struct platform_driver temac_of_driver = {
1161 .probe = temac_of_probe,
1162 .remove = __devexit_p(temac_of_remove),
1164 .owner = THIS_MODULE,
1165 .name = "xilinx_temac",
1166 .of_match_table = temac_of_match,
1170 static int __init temac_init(void)
1172 return platform_driver_register(&temac_of_driver);
1174 module_init(temac_init);
1176 static void __exit temac_exit(void)
1178 platform_driver_unregister(&temac_of_driver);
1180 module_exit(temac_exit);
1182 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1183 MODULE_AUTHOR("Yoshio Kashiwagi");
1184 MODULE_LICENSE("GPL");