2 * Driver for Xilinx TEMAC Ethernet device
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/mii.h>
33 #include <linux/module.h>
34 #include <linux/mutex.h>
35 #include <linux/netdevice.h>
36 #include <linux/if_ether.h>
38 #include <linux/of_device.h>
39 #include <linux/of_irq.h>
40 #include <linux/of_mdio.h>
41 #include <linux/of_net.h>
42 #include <linux/of_platform.h>
43 #include <linux/of_address.h>
44 #include <linux/skbuff.h>
45 #include <linux/spinlock.h>
46 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */
47 #include <linux/udp.h> /* needed for sizeof(udphdr) */
48 #include <linux/phy.h>
52 #include <linux/slab.h>
53 #include <linux/interrupt.h>
54 #include <linux/dma-mapping.h>
55 #include <linux/platform_data/xilinx-ll-temac.h>
62 /* ---------------------------------------------------------------------
63 * Low level register access functions
66 u32 _temac_ior_be(struct temac_local *lp, int offset)
68 return ioread32be(lp->regs + offset);
71 void _temac_iow_be(struct temac_local *lp, int offset, u32 value)
73 return iowrite32be(value, lp->regs + offset);
76 u32 _temac_ior_le(struct temac_local *lp, int offset)
78 return ioread32(lp->regs + offset);
81 void _temac_iow_le(struct temac_local *lp, int offset, u32 value)
83 return iowrite32(value, lp->regs + offset);
86 int temac_indirect_busywait(struct temac_local *lp)
88 unsigned long end = jiffies + 2;
90 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
91 if (time_before_eq(end, jiffies)) {
101 * temac_indirect_in32
103 * lp->indirect_mutex must be held when calling this function
105 u32 temac_indirect_in32(struct temac_local *lp, int reg)
109 if (temac_indirect_busywait(lp))
111 temac_iow(lp, XTE_CTL0_OFFSET, reg);
112 if (temac_indirect_busywait(lp))
114 val = temac_ior(lp, XTE_LSW0_OFFSET);
120 * temac_indirect_out32
122 * lp->indirect_mutex must be held when calling this function
124 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
126 if (temac_indirect_busywait(lp))
128 temac_iow(lp, XTE_LSW0_OFFSET, value);
129 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
130 temac_indirect_busywait(lp);
134 * temac_dma_in32_* - Memory mapped DMA read, these function expects a
135 * register input that is based on DCR word addresses which are then
136 * converted to memory mapped byte addresses. To be assigned to
139 static u32 temac_dma_in32_be(struct temac_local *lp, int reg)
141 return ioread32be(lp->sdma_regs + (reg << 2));
144 static u32 temac_dma_in32_le(struct temac_local *lp, int reg)
146 return ioread32(lp->sdma_regs + (reg << 2));
150 * temac_dma_out32_* - Memory mapped DMA read, these function expects
151 * a register input that is based on DCR word addresses which are then
152 * converted to memory mapped byte addresses. To be assigned to
155 static void temac_dma_out32_be(struct temac_local *lp, int reg, u32 value)
157 iowrite32be(value, lp->sdma_regs + (reg << 2));
160 static void temac_dma_out32_le(struct temac_local *lp, int reg, u32 value)
162 iowrite32(value, lp->sdma_regs + (reg << 2));
165 /* DMA register access functions can be DCR based or memory mapped.
166 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
169 #ifdef CONFIG_PPC_DCR
172 * temac_dma_dcr_in32 - DCR based DMA read
174 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
176 return dcr_read(lp->sdma_dcrs, reg);
180 * temac_dma_dcr_out32 - DCR based DMA write
182 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
184 dcr_write(lp->sdma_dcrs, reg, value);
188 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
191 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
192 struct device_node *np)
196 /* setup the dcr address mapping if it's in the device tree */
198 dcrs = dcr_resource_start(np, 0);
200 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
201 lp->dma_in = temac_dma_dcr_in;
202 lp->dma_out = temac_dma_dcr_out;
203 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
206 /* no DCR in the device tree, indicate a failure */
213 * temac_dcr_setup - This is a stub for when DCR is not supported,
214 * such as with MicroBlaze and x86
216 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
217 struct device_node *np)
225 * temac_dma_bd_release - Release buffer descriptor rings
227 static void temac_dma_bd_release(struct net_device *ndev)
229 struct temac_local *lp = netdev_priv(ndev);
232 /* Reset Local Link (DMA) */
233 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
235 for (i = 0; i < RX_BD_NUM; i++) {
239 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
240 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
241 dev_kfree_skb(lp->rx_skb[i]);
245 dma_free_coherent(ndev->dev.parent,
246 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
247 lp->rx_bd_v, lp->rx_bd_p);
249 dma_free_coherent(ndev->dev.parent,
250 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
251 lp->tx_bd_v, lp->tx_bd_p);
255 * temac_dma_bd_init - Setup buffer descriptor rings
257 static int temac_dma_bd_init(struct net_device *ndev)
259 struct temac_local *lp = netdev_priv(ndev);
263 lp->rx_skb = devm_kcalloc(&ndev->dev, RX_BD_NUM, sizeof(*lp->rx_skb),
268 /* allocate the tx and rx ring buffer descriptors. */
269 /* returns a virtual address and a physical address. */
270 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
271 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
272 &lp->tx_bd_p, GFP_KERNEL);
276 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
277 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
278 &lp->rx_bd_p, GFP_KERNEL);
282 for (i = 0; i < TX_BD_NUM; i++) {
283 lp->tx_bd_v[i].next = lp->tx_bd_p +
284 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
287 for (i = 0; i < RX_BD_NUM; i++) {
288 lp->rx_bd_v[i].next = lp->rx_bd_p +
289 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
291 skb = netdev_alloc_skb_ip_align(ndev,
292 XTE_MAX_JUMBO_FRAME_SIZE);
297 /* returns physical address of skb->data */
298 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
300 XTE_MAX_JUMBO_FRAME_SIZE,
302 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
303 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
306 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
308 CHNL_CTRL_IRQ_DLY_EN |
309 CHNL_CTRL_IRQ_COAL_EN);
312 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
314 CHNL_CTRL_IRQ_DLY_EN |
315 CHNL_CTRL_IRQ_COAL_EN |
319 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
320 lp->dma_out(lp, RX_TAILDESC_PTR,
321 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
322 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
324 /* Init descriptor indexes */
333 temac_dma_bd_release(ndev);
337 /* ---------------------------------------------------------------------
341 static void temac_do_set_mac_address(struct net_device *ndev)
343 struct temac_local *lp = netdev_priv(ndev);
345 /* set up unicast MAC address filter set its mac address */
346 mutex_lock(&lp->indirect_mutex);
347 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
348 (ndev->dev_addr[0]) |
349 (ndev->dev_addr[1] << 8) |
350 (ndev->dev_addr[2] << 16) |
351 (ndev->dev_addr[3] << 24));
352 /* There are reserved bits in EUAW1
353 * so don't affect them Set MAC bits [47:32] in EUAW1 */
354 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
355 (ndev->dev_addr[4] & 0x000000ff) |
356 (ndev->dev_addr[5] << 8));
357 mutex_unlock(&lp->indirect_mutex);
360 static int temac_init_mac_address(struct net_device *ndev, const void *address)
362 memcpy(ndev->dev_addr, address, ETH_ALEN);
363 if (!is_valid_ether_addr(ndev->dev_addr))
364 eth_hw_addr_random(ndev);
365 temac_do_set_mac_address(ndev);
369 static int temac_set_mac_address(struct net_device *ndev, void *p)
371 struct sockaddr *addr = p;
373 if (!is_valid_ether_addr(addr->sa_data))
374 return -EADDRNOTAVAIL;
375 memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN);
376 temac_do_set_mac_address(ndev);
380 static void temac_set_multicast_list(struct net_device *ndev)
382 struct temac_local *lp = netdev_priv(ndev);
383 u32 multi_addr_msw, multi_addr_lsw, val;
386 mutex_lock(&lp->indirect_mutex);
387 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
388 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
390 * We must make the kernel realise we had to move
391 * into promisc mode or we start all out war on
392 * the cable. If it was a promisc request the
393 * flag is already set. If not we assert it.
395 ndev->flags |= IFF_PROMISC;
396 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
397 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
398 } else if (!netdev_mc_empty(ndev)) {
399 struct netdev_hw_addr *ha;
402 netdev_for_each_mc_addr(ha, ndev) {
403 if (i >= MULTICAST_CAM_TABLE_NUM)
405 multi_addr_msw = ((ha->addr[3] << 24) |
406 (ha->addr[2] << 16) |
409 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
411 multi_addr_lsw = ((ha->addr[5] << 8) |
412 (ha->addr[4]) | (i << 16));
413 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
418 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
419 temac_indirect_out32(lp, XTE_AFM_OFFSET,
420 val & ~XTE_AFM_EPPRM_MASK);
421 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
422 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
423 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
425 mutex_unlock(&lp->indirect_mutex);
428 static struct temac_option {
434 } temac_options[] = {
435 /* Turn on jumbo packet support for both Rx and Tx */
437 .opt = XTE_OPTION_JUMBO,
438 .reg = XTE_TXC_OFFSET,
439 .m_or = XTE_TXC_TXJMBO_MASK,
442 .opt = XTE_OPTION_JUMBO,
443 .reg = XTE_RXC1_OFFSET,
444 .m_or =XTE_RXC1_RXJMBO_MASK,
446 /* Turn on VLAN packet support for both Rx and Tx */
448 .opt = XTE_OPTION_VLAN,
449 .reg = XTE_TXC_OFFSET,
450 .m_or =XTE_TXC_TXVLAN_MASK,
453 .opt = XTE_OPTION_VLAN,
454 .reg = XTE_RXC1_OFFSET,
455 .m_or =XTE_RXC1_RXVLAN_MASK,
457 /* Turn on FCS stripping on receive packets */
459 .opt = XTE_OPTION_FCS_STRIP,
460 .reg = XTE_RXC1_OFFSET,
461 .m_or =XTE_RXC1_RXFCS_MASK,
463 /* Turn on FCS insertion on transmit packets */
465 .opt = XTE_OPTION_FCS_INSERT,
466 .reg = XTE_TXC_OFFSET,
467 .m_or =XTE_TXC_TXFCS_MASK,
469 /* Turn on length/type field checking on receive packets */
471 .opt = XTE_OPTION_LENTYPE_ERR,
472 .reg = XTE_RXC1_OFFSET,
473 .m_or =XTE_RXC1_RXLT_MASK,
475 /* Turn on flow control */
477 .opt = XTE_OPTION_FLOW_CONTROL,
478 .reg = XTE_FCC_OFFSET,
479 .m_or =XTE_FCC_RXFLO_MASK,
481 /* Turn on flow control */
483 .opt = XTE_OPTION_FLOW_CONTROL,
484 .reg = XTE_FCC_OFFSET,
485 .m_or =XTE_FCC_TXFLO_MASK,
487 /* Turn on promiscuous frame filtering (all frames are received ) */
489 .opt = XTE_OPTION_PROMISC,
490 .reg = XTE_AFM_OFFSET,
491 .m_or =XTE_AFM_EPPRM_MASK,
493 /* Enable transmitter if not already enabled */
495 .opt = XTE_OPTION_TXEN,
496 .reg = XTE_TXC_OFFSET,
497 .m_or =XTE_TXC_TXEN_MASK,
499 /* Enable receiver? */
501 .opt = XTE_OPTION_RXEN,
502 .reg = XTE_RXC1_OFFSET,
503 .m_or =XTE_RXC1_RXEN_MASK,
511 static u32 temac_setoptions(struct net_device *ndev, u32 options)
513 struct temac_local *lp = netdev_priv(ndev);
514 struct temac_option *tp = &temac_options[0];
517 mutex_lock(&lp->indirect_mutex);
519 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
520 if (options & tp->opt)
522 temac_indirect_out32(lp, tp->reg, reg);
525 lp->options |= options;
526 mutex_unlock(&lp->indirect_mutex);
531 /* Initialize temac */
532 static void temac_device_reset(struct net_device *ndev)
534 struct temac_local *lp = netdev_priv(ndev);
538 /* Perform a software reset */
540 /* 0x300 host enable bit ? */
541 /* reset PHY through control register ?:1 */
543 dev_dbg(&ndev->dev, "%s()\n", __func__);
545 mutex_lock(&lp->indirect_mutex);
546 /* Reset the receiver and wait for it to finish reset */
547 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
549 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
551 if (--timeout == 0) {
553 "temac_device_reset RX reset timeout!!\n");
558 /* Reset the transmitter and wait for it to finish reset */
559 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
561 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
563 if (--timeout == 0) {
565 "temac_device_reset TX reset timeout!!\n");
570 /* Disable the receiver */
571 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
572 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
574 /* Reset Local Link (DMA) */
575 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
577 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
579 if (--timeout == 0) {
581 "temac_device_reset DMA reset timeout!!\n");
585 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
587 if (temac_dma_bd_init(ndev)) {
589 "temac_device_reset descriptor allocation failed\n");
592 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
593 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
594 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
595 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
597 mutex_unlock(&lp->indirect_mutex);
599 /* Sync default options with HW
600 * but leave receiver and transmitter disabled. */
601 temac_setoptions(ndev,
602 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
604 temac_do_set_mac_address(ndev);
606 /* Set address filter table */
607 temac_set_multicast_list(ndev);
608 if (temac_setoptions(ndev, lp->options))
609 dev_err(&ndev->dev, "Error setting TEMAC options\n");
611 /* Init Driver variable */
612 netif_trans_update(ndev); /* prevent tx timeout */
615 static void temac_adjust_link(struct net_device *ndev)
617 struct temac_local *lp = netdev_priv(ndev);
618 struct phy_device *phy = ndev->phydev;
622 /* hash together the state values to decide if something has changed */
623 link_state = phy->speed | (phy->duplex << 1) | phy->link;
625 mutex_lock(&lp->indirect_mutex);
626 if (lp->last_link != link_state) {
627 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
628 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
630 switch (phy->speed) {
631 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
632 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
633 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
636 /* Write new speed setting out to TEMAC */
637 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
638 lp->last_link = link_state;
639 phy_print_status(phy);
641 mutex_unlock(&lp->indirect_mutex);
646 void ptr_to_txbd(void *p, struct cdmac_bd *bd)
648 bd->app3 = (u32)(((u64)p) >> 32);
649 bd->app4 = (u32)((u64)p & 0xFFFFFFFF);
652 void *ptr_from_txbd(struct cdmac_bd *bd)
654 return (void *)(((u64)(bd->app3) << 32) | bd->app4);
659 void ptr_to_txbd(void *p, struct cmdac_bd *bd)
664 void *ptr_from_txbd(struct cdmac_bd *bd)
666 return (void *)(bd->app4);
671 static void temac_start_xmit_done(struct net_device *ndev)
673 struct temac_local *lp = netdev_priv(ndev);
674 struct cdmac_bd *cur_p;
675 unsigned int stat = 0;
678 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
681 while (stat & STS_CTRL_APP0_CMPLT) {
682 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
684 skb = (struct sk_buff *)ptr_from_txbd(cur_p);
686 dev_consume_skb_irq(skb);
693 ndev->stats.tx_packets++;
694 ndev->stats.tx_bytes += cur_p->len;
697 if (lp->tx_bd_ci >= TX_BD_NUM)
700 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
704 netif_wake_queue(ndev);
707 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
709 struct cdmac_bd *cur_p;
712 tail = lp->tx_bd_tail;
713 cur_p = &lp->tx_bd_v[tail];
717 return NETDEV_TX_BUSY;
720 if (tail >= TX_BD_NUM)
723 cur_p = &lp->tx_bd_v[tail];
725 } while (num_frag >= 0);
731 temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
733 struct temac_local *lp = netdev_priv(ndev);
734 struct cdmac_bd *cur_p;
735 dma_addr_t start_p, tail_p;
737 unsigned long num_frag;
740 num_frag = skb_shinfo(skb)->nr_frags;
741 frag = &skb_shinfo(skb)->frags[0];
742 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
743 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
745 if (temac_check_tx_bd_space(lp, num_frag)) {
746 if (!netif_queue_stopped(ndev))
747 netif_stop_queue(ndev);
748 return NETDEV_TX_BUSY;
752 if (skb->ip_summed == CHECKSUM_PARTIAL) {
753 unsigned int csum_start_off = skb_checksum_start_offset(skb);
754 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
756 cur_p->app0 |= 1; /* TX Checksum Enabled */
757 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
758 cur_p->app2 = 0; /* initial checksum seed */
761 cur_p->app0 |= STS_CTRL_APP0_SOP;
762 cur_p->len = skb_headlen(skb);
763 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data,
764 skb_headlen(skb), DMA_TO_DEVICE);
765 ptr_to_txbd((void *)skb, cur_p);
767 for (ii = 0; ii < num_frag; ii++) {
769 if (lp->tx_bd_tail >= TX_BD_NUM)
772 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
773 cur_p->phys = dma_map_single(ndev->dev.parent,
774 skb_frag_address(frag),
775 skb_frag_size(frag), DMA_TO_DEVICE);
776 cur_p->len = skb_frag_size(frag);
780 cur_p->app0 |= STS_CTRL_APP0_EOP;
782 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
784 if (lp->tx_bd_tail >= TX_BD_NUM)
787 skb_tx_timestamp(skb);
789 /* Kick off the transfer */
790 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
796 static void ll_temac_recv(struct net_device *ndev)
798 struct temac_local *lp = netdev_priv(ndev);
799 struct sk_buff *skb, *new_skb;
801 struct cdmac_bd *cur_p;
806 spin_lock_irqsave(&lp->rx_lock, flags);
808 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
809 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
811 bdstat = cur_p->app0;
812 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
814 skb = lp->rx_skb[lp->rx_bd_ci];
815 length = cur_p->app4 & 0x3FFF;
817 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
820 skb_put(skb, length);
821 skb->protocol = eth_type_trans(skb, ndev);
822 skb_checksum_none_assert(skb);
824 /* if we're doing rx csum offload, set it up */
825 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
826 (skb->protocol == htons(ETH_P_IP)) &&
829 skb->csum = cur_p->app3 & 0xFFFF;
830 skb->ip_summed = CHECKSUM_COMPLETE;
833 if (!skb_defer_rx_timestamp(skb))
836 ndev->stats.rx_packets++;
837 ndev->stats.rx_bytes += length;
839 new_skb = netdev_alloc_skb_ip_align(ndev,
840 XTE_MAX_JUMBO_FRAME_SIZE);
842 spin_unlock_irqrestore(&lp->rx_lock, flags);
846 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
847 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
848 XTE_MAX_JUMBO_FRAME_SIZE,
850 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
851 lp->rx_skb[lp->rx_bd_ci] = new_skb;
854 if (lp->rx_bd_ci >= RX_BD_NUM)
857 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
858 bdstat = cur_p->app0;
860 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
862 spin_unlock_irqrestore(&lp->rx_lock, flags);
865 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
867 struct net_device *ndev = _ndev;
868 struct temac_local *lp = netdev_priv(ndev);
871 status = lp->dma_in(lp, TX_IRQ_REG);
872 lp->dma_out(lp, TX_IRQ_REG, status);
874 if (status & (IRQ_COAL | IRQ_DLY))
875 temac_start_xmit_done(lp->ndev);
877 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
882 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
884 struct net_device *ndev = _ndev;
885 struct temac_local *lp = netdev_priv(ndev);
888 /* Read and clear the status registers */
889 status = lp->dma_in(lp, RX_IRQ_REG);
890 lp->dma_out(lp, RX_IRQ_REG, status);
892 if (status & (IRQ_COAL | IRQ_DLY))
893 ll_temac_recv(lp->ndev);
898 static int temac_open(struct net_device *ndev)
900 struct temac_local *lp = netdev_priv(ndev);
901 struct phy_device *phydev = NULL;
904 dev_dbg(&ndev->dev, "temac_open()\n");
907 phydev = of_phy_connect(lp->ndev, lp->phy_node,
908 temac_adjust_link, 0, 0);
910 dev_err(lp->dev, "of_phy_connect() failed\n");
914 } else if (strlen(lp->phy_name) > 0) {
915 phydev = phy_connect(lp->ndev, lp->phy_name, temac_adjust_link,
918 dev_err(lp->dev, "phy_connect() failed\n");
924 temac_device_reset(ndev);
926 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
929 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
936 free_irq(lp->tx_irq, ndev);
939 phy_disconnect(phydev);
940 dev_err(lp->dev, "request_irq() failed\n");
944 static int temac_stop(struct net_device *ndev)
946 struct temac_local *lp = netdev_priv(ndev);
947 struct phy_device *phydev = ndev->phydev;
949 dev_dbg(&ndev->dev, "temac_close()\n");
951 free_irq(lp->tx_irq, ndev);
952 free_irq(lp->rx_irq, ndev);
955 phy_disconnect(phydev);
957 temac_dma_bd_release(ndev);
962 #ifdef CONFIG_NET_POLL_CONTROLLER
964 temac_poll_controller(struct net_device *ndev)
966 struct temac_local *lp = netdev_priv(ndev);
968 disable_irq(lp->tx_irq);
969 disable_irq(lp->rx_irq);
971 ll_temac_rx_irq(lp->tx_irq, ndev);
972 ll_temac_tx_irq(lp->rx_irq, ndev);
974 enable_irq(lp->tx_irq);
975 enable_irq(lp->rx_irq);
979 static int temac_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
981 if (!netif_running(ndev))
987 return phy_mii_ioctl(ndev->phydev, rq, cmd);
990 static const struct net_device_ops temac_netdev_ops = {
991 .ndo_open = temac_open,
992 .ndo_stop = temac_stop,
993 .ndo_start_xmit = temac_start_xmit,
994 .ndo_set_mac_address = temac_set_mac_address,
995 .ndo_validate_addr = eth_validate_addr,
996 .ndo_do_ioctl = temac_ioctl,
997 #ifdef CONFIG_NET_POLL_CONTROLLER
998 .ndo_poll_controller = temac_poll_controller,
1002 /* ---------------------------------------------------------------------
1003 * SYSFS device attributes
1005 static ssize_t temac_show_llink_regs(struct device *dev,
1006 struct device_attribute *attr, char *buf)
1008 struct net_device *ndev = dev_get_drvdata(dev);
1009 struct temac_local *lp = netdev_priv(ndev);
1012 for (i = 0; i < 0x11; i++)
1013 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
1014 (i % 8) == 7 ? "\n" : " ");
1015 len += sprintf(buf + len, "\n");
1020 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
1022 static struct attribute *temac_device_attrs[] = {
1023 &dev_attr_llink_regs.attr,
1027 static const struct attribute_group temac_attr_group = {
1028 .attrs = temac_device_attrs,
1031 /* ethtool support */
1032 static const struct ethtool_ops temac_ethtool_ops = {
1033 .nway_reset = phy_ethtool_nway_reset,
1034 .get_link = ethtool_op_get_link,
1035 .get_ts_info = ethtool_op_get_ts_info,
1036 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1037 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1040 static int temac_probe(struct platform_device *pdev)
1042 struct ll_temac_platform_data *pdata = dev_get_platdata(&pdev->dev);
1043 struct device_node *temac_np = dev_of_node(&pdev->dev), *dma_np;
1044 struct temac_local *lp;
1045 struct net_device *ndev;
1046 struct resource *res;
1052 /* Init network device structure */
1053 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*lp));
1057 platform_set_drvdata(pdev, ndev);
1058 SET_NETDEV_DEV(ndev, &pdev->dev);
1059 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
1060 ndev->features = NETIF_F_SG;
1061 ndev->netdev_ops = &temac_netdev_ops;
1062 ndev->ethtool_ops = &temac_ethtool_ops;
1064 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
1065 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
1066 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
1067 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
1068 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; /* Transmit VLAN hw accel */
1069 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; /* Receive VLAN hw acceleration */
1070 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; /* Receive VLAN filtering */
1071 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
1072 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
1073 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
1074 ndev->features |= NETIF_F_LRO; /* large receive offload */
1077 /* setup temac private info structure */
1078 lp = netdev_priv(ndev);
1080 lp->dev = &pdev->dev;
1081 lp->options = XTE_OPTION_DEFAULTS;
1082 spin_lock_init(&lp->rx_lock);
1083 mutex_init(&lp->indirect_mutex);
1085 /* map device registers */
1086 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1087 lp->regs = devm_ioremap_nocache(&pdev->dev, res->start,
1088 resource_size(res));
1089 if (IS_ERR(lp->regs)) {
1090 dev_err(&pdev->dev, "could not map TEMAC registers\n");
1091 return PTR_ERR(lp->regs);
1094 /* Select register access functions with the specified
1095 * endianness mode. Default for OF devices is big-endian.
1097 little_endian = false;
1099 if (of_get_property(temac_np, "little-endian", NULL))
1100 little_endian = true;
1102 little_endian = pdata->reg_little_endian;
1104 if (little_endian) {
1105 lp->temac_ior = _temac_ior_le;
1106 lp->temac_iow = _temac_iow_le;
1108 lp->temac_ior = _temac_ior_be;
1109 lp->temac_iow = _temac_iow_be;
1112 /* Setup checksum offload, but default to off if not specified */
1113 lp->temac_features = 0;
1115 p = (__be32 *)of_get_property(temac_np, "xlnx,txcsum", NULL);
1116 if (p && be32_to_cpu(*p))
1117 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1118 p = (__be32 *)of_get_property(temac_np, "xlnx,rxcsum", NULL);
1119 if (p && be32_to_cpu(*p))
1120 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1123 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1125 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1127 if (lp->temac_features & TEMAC_FEATURE_TX_CSUM)
1128 /* Can checksum TCP/UDP over IPv4. */
1129 ndev->features |= NETIF_F_IP_CSUM;
1131 /* Setup LocalLink DMA */
1133 /* Find the DMA node, map the DMA registers, and
1134 * decode the DMA IRQs.
1136 dma_np = of_parse_phandle(temac_np, "llink-connected", 0);
1138 dev_err(&pdev->dev, "could not find DMA node\n");
1142 /* Setup the DMA register accesses, could be DCR or
1145 if (temac_dcr_setup(lp, pdev, dma_np)) {
1146 /* no DCR in the device tree, try non-DCR */
1147 lp->sdma_regs = devm_of_iomap(&pdev->dev, dma_np, 0,
1149 if (IS_ERR(lp->sdma_regs)) {
1151 "unable to map DMA registers\n");
1152 of_node_put(dma_np);
1153 return PTR_ERR(lp->sdma_regs);
1155 if (of_get_property(dma_np, "little-endian", NULL)) {
1156 lp->dma_in = temac_dma_in32_le;
1157 lp->dma_out = temac_dma_out32_le;
1159 lp->dma_in = temac_dma_in32_be;
1160 lp->dma_out = temac_dma_out32_be;
1162 dev_dbg(&pdev->dev, "MEM base: %p\n", lp->sdma_regs);
1165 /* Get DMA RX and TX interrupts */
1166 lp->rx_irq = irq_of_parse_and_map(dma_np, 0);
1167 lp->tx_irq = irq_of_parse_and_map(dma_np, 1);
1169 /* Finished with the DMA node; drop the reference */
1170 of_node_put(dma_np);
1172 /* 2nd memory resource specifies DMA registers */
1173 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1174 lp->sdma_regs = devm_ioremap_nocache(&pdev->dev, res->start,
1175 resource_size(res));
1176 if (IS_ERR(lp->sdma_regs)) {
1178 "could not map DMA registers\n");
1179 return PTR_ERR(lp->sdma_regs);
1181 if (pdata->dma_little_endian) {
1182 lp->dma_in = temac_dma_in32_le;
1183 lp->dma_out = temac_dma_out32_le;
1185 lp->dma_in = temac_dma_in32_be;
1186 lp->dma_out = temac_dma_out32_be;
1189 /* Get DMA RX and TX interrupts */
1190 lp->rx_irq = platform_get_irq(pdev, 0);
1191 lp->tx_irq = platform_get_irq(pdev, 1);
1194 /* Error handle returned DMA RX and TX interrupts */
1195 if (lp->rx_irq < 0) {
1196 if (lp->rx_irq != -EPROBE_DEFER)
1197 dev_err(&pdev->dev, "could not get DMA RX irq\n");
1200 if (lp->tx_irq < 0) {
1201 if (lp->tx_irq != -EPROBE_DEFER)
1202 dev_err(&pdev->dev, "could not get DMA TX irq\n");
1207 /* Retrieve the MAC address */
1208 addr = of_get_mac_address(temac_np);
1210 dev_err(&pdev->dev, "could not find MAC address\n");
1213 temac_init_mac_address(ndev, addr);
1215 temac_init_mac_address(ndev, pdata->mac_addr);
1218 rc = temac_mdio_setup(lp, pdev);
1220 dev_warn(&pdev->dev, "error registering MDIO bus\n");
1223 lp->phy_node = of_parse_phandle(temac_np, "phy-handle", 0);
1225 dev_dbg(lp->dev, "using PHY node %pOF\n", temac_np);
1227 snprintf(lp->phy_name, sizeof(lp->phy_name),
1228 PHY_ID_FMT, lp->mii_bus->id, pdata->phy_addr);
1229 lp->phy_interface = pdata->phy_interface;
1232 /* Add the device attributes */
1233 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1235 dev_err(lp->dev, "Error creating sysfs files\n");
1236 goto err_sysfs_create;
1239 rc = register_netdev(lp->ndev);
1241 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1242 goto err_register_ndev;
1248 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1251 of_node_put(lp->phy_node);
1252 temac_mdio_teardown(lp);
1256 static int temac_remove(struct platform_device *pdev)
1258 struct net_device *ndev = platform_get_drvdata(pdev);
1259 struct temac_local *lp = netdev_priv(ndev);
1261 unregister_netdev(ndev);
1262 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1264 of_node_put(lp->phy_node);
1265 temac_mdio_teardown(lp);
1269 static const struct of_device_id temac_of_match[] = {
1270 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1271 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1272 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1273 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1276 MODULE_DEVICE_TABLE(of, temac_of_match);
1278 static struct platform_driver temac_driver = {
1279 .probe = temac_probe,
1280 .remove = temac_remove,
1282 .name = "xilinx_temac",
1283 .of_match_table = temac_of_match,
1287 module_platform_driver(temac_driver);
1289 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1290 MODULE_AUTHOR("Yoshio Kashiwagi");
1291 MODULE_LICENSE("GPL");