1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */
4 #include <linux/etherdevice.h>
5 #include <net/ip6_checksum.h>
6 #include <net/page_pool/helpers.h>
7 #include <net/inet_ecn.h>
8 #include <linux/iopoll.h>
9 #include <linux/sctp.h>
10 #include <linux/pci.h>
18 /* Lookup table mapping the HW PTYPE to the bit field for decoding */
19 static struct wx_dec_ptype wx_ptype_lookup[256] = {
21 [0x11] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
22 [0x12] = WX_PTT(L2, NONE, NONE, NONE, TS, PAY2),
23 [0x13] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
24 [0x14] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
25 [0x15] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
26 [0x16] = WX_PTT(L2, NONE, NONE, NONE, NONE, PAY2),
27 [0x17] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
29 /* L2: ethertype filter */
30 [0x18 ... 0x1F] = WX_PTT(L2, NONE, NONE, NONE, NONE, NONE),
32 /* L3: ip non-tunnel */
33 [0x21] = WX_PTT(IP, FGV4, NONE, NONE, NONE, PAY3),
34 [0x22] = WX_PTT(IP, IPV4, NONE, NONE, NONE, PAY3),
35 [0x23] = WX_PTT(IP, IPV4, NONE, NONE, UDP, PAY4),
36 [0x24] = WX_PTT(IP, IPV4, NONE, NONE, TCP, PAY4),
37 [0x25] = WX_PTT(IP, IPV4, NONE, NONE, SCTP, PAY4),
38 [0x29] = WX_PTT(IP, FGV6, NONE, NONE, NONE, PAY3),
39 [0x2A] = WX_PTT(IP, IPV6, NONE, NONE, NONE, PAY3),
40 [0x2B] = WX_PTT(IP, IPV6, NONE, NONE, UDP, PAY3),
41 [0x2C] = WX_PTT(IP, IPV6, NONE, NONE, TCP, PAY4),
42 [0x2D] = WX_PTT(IP, IPV6, NONE, NONE, SCTP, PAY4),
45 [0x30 ... 0x34] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3),
46 [0x38 ... 0x3C] = WX_PTT(FCOE, NONE, NONE, NONE, NONE, PAY3),
48 /* IPv4 --> IPv4/IPv6 */
49 [0x81] = WX_PTT(IP, IPV4, IPIP, FGV4, NONE, PAY3),
50 [0x82] = WX_PTT(IP, IPV4, IPIP, IPV4, NONE, PAY3),
51 [0x83] = WX_PTT(IP, IPV4, IPIP, IPV4, UDP, PAY4),
52 [0x84] = WX_PTT(IP, IPV4, IPIP, IPV4, TCP, PAY4),
53 [0x85] = WX_PTT(IP, IPV4, IPIP, IPV4, SCTP, PAY4),
54 [0x89] = WX_PTT(IP, IPV4, IPIP, FGV6, NONE, PAY3),
55 [0x8A] = WX_PTT(IP, IPV4, IPIP, IPV6, NONE, PAY3),
56 [0x8B] = WX_PTT(IP, IPV4, IPIP, IPV6, UDP, PAY4),
57 [0x8C] = WX_PTT(IP, IPV4, IPIP, IPV6, TCP, PAY4),
58 [0x8D] = WX_PTT(IP, IPV4, IPIP, IPV6, SCTP, PAY4),
60 /* IPv4 --> GRE/NAT --> NONE/IPv4/IPv6 */
61 [0x90] = WX_PTT(IP, IPV4, IG, NONE, NONE, PAY3),
62 [0x91] = WX_PTT(IP, IPV4, IG, FGV4, NONE, PAY3),
63 [0x92] = WX_PTT(IP, IPV4, IG, IPV4, NONE, PAY3),
64 [0x93] = WX_PTT(IP, IPV4, IG, IPV4, UDP, PAY4),
65 [0x94] = WX_PTT(IP, IPV4, IG, IPV4, TCP, PAY4),
66 [0x95] = WX_PTT(IP, IPV4, IG, IPV4, SCTP, PAY4),
67 [0x99] = WX_PTT(IP, IPV4, IG, FGV6, NONE, PAY3),
68 [0x9A] = WX_PTT(IP, IPV4, IG, IPV6, NONE, PAY3),
69 [0x9B] = WX_PTT(IP, IPV4, IG, IPV6, UDP, PAY4),
70 [0x9C] = WX_PTT(IP, IPV4, IG, IPV6, TCP, PAY4),
71 [0x9D] = WX_PTT(IP, IPV4, IG, IPV6, SCTP, PAY4),
73 /* IPv4 --> GRE/NAT --> MAC --> NONE/IPv4/IPv6 */
74 [0xA0] = WX_PTT(IP, IPV4, IGM, NONE, NONE, PAY3),
75 [0xA1] = WX_PTT(IP, IPV4, IGM, FGV4, NONE, PAY3),
76 [0xA2] = WX_PTT(IP, IPV4, IGM, IPV4, NONE, PAY3),
77 [0xA3] = WX_PTT(IP, IPV4, IGM, IPV4, UDP, PAY4),
78 [0xA4] = WX_PTT(IP, IPV4, IGM, IPV4, TCP, PAY4),
79 [0xA5] = WX_PTT(IP, IPV4, IGM, IPV4, SCTP, PAY4),
80 [0xA9] = WX_PTT(IP, IPV4, IGM, FGV6, NONE, PAY3),
81 [0xAA] = WX_PTT(IP, IPV4, IGM, IPV6, NONE, PAY3),
82 [0xAB] = WX_PTT(IP, IPV4, IGM, IPV6, UDP, PAY4),
83 [0xAC] = WX_PTT(IP, IPV4, IGM, IPV6, TCP, PAY4),
84 [0xAD] = WX_PTT(IP, IPV4, IGM, IPV6, SCTP, PAY4),
86 /* IPv4 --> GRE/NAT --> MAC+VLAN --> NONE/IPv4/IPv6 */
87 [0xB0] = WX_PTT(IP, IPV4, IGMV, NONE, NONE, PAY3),
88 [0xB1] = WX_PTT(IP, IPV4, IGMV, FGV4, NONE, PAY3),
89 [0xB2] = WX_PTT(IP, IPV4, IGMV, IPV4, NONE, PAY3),
90 [0xB3] = WX_PTT(IP, IPV4, IGMV, IPV4, UDP, PAY4),
91 [0xB4] = WX_PTT(IP, IPV4, IGMV, IPV4, TCP, PAY4),
92 [0xB5] = WX_PTT(IP, IPV4, IGMV, IPV4, SCTP, PAY4),
93 [0xB9] = WX_PTT(IP, IPV4, IGMV, FGV6, NONE, PAY3),
94 [0xBA] = WX_PTT(IP, IPV4, IGMV, IPV6, NONE, PAY3),
95 [0xBB] = WX_PTT(IP, IPV4, IGMV, IPV6, UDP, PAY4),
96 [0xBC] = WX_PTT(IP, IPV4, IGMV, IPV6, TCP, PAY4),
97 [0xBD] = WX_PTT(IP, IPV4, IGMV, IPV6, SCTP, PAY4),
99 /* IPv6 --> IPv4/IPv6 */
100 [0xC1] = WX_PTT(IP, IPV6, IPIP, FGV4, NONE, PAY3),
101 [0xC2] = WX_PTT(IP, IPV6, IPIP, IPV4, NONE, PAY3),
102 [0xC3] = WX_PTT(IP, IPV6, IPIP, IPV4, UDP, PAY4),
103 [0xC4] = WX_PTT(IP, IPV6, IPIP, IPV4, TCP, PAY4),
104 [0xC5] = WX_PTT(IP, IPV6, IPIP, IPV4, SCTP, PAY4),
105 [0xC9] = WX_PTT(IP, IPV6, IPIP, FGV6, NONE, PAY3),
106 [0xCA] = WX_PTT(IP, IPV6, IPIP, IPV6, NONE, PAY3),
107 [0xCB] = WX_PTT(IP, IPV6, IPIP, IPV6, UDP, PAY4),
108 [0xCC] = WX_PTT(IP, IPV6, IPIP, IPV6, TCP, PAY4),
109 [0xCD] = WX_PTT(IP, IPV6, IPIP, IPV6, SCTP, PAY4),
111 /* IPv6 --> GRE/NAT -> NONE/IPv4/IPv6 */
112 [0xD0] = WX_PTT(IP, IPV6, IG, NONE, NONE, PAY3),
113 [0xD1] = WX_PTT(IP, IPV6, IG, FGV4, NONE, PAY3),
114 [0xD2] = WX_PTT(IP, IPV6, IG, IPV4, NONE, PAY3),
115 [0xD3] = WX_PTT(IP, IPV6, IG, IPV4, UDP, PAY4),
116 [0xD4] = WX_PTT(IP, IPV6, IG, IPV4, TCP, PAY4),
117 [0xD5] = WX_PTT(IP, IPV6, IG, IPV4, SCTP, PAY4),
118 [0xD9] = WX_PTT(IP, IPV6, IG, FGV6, NONE, PAY3),
119 [0xDA] = WX_PTT(IP, IPV6, IG, IPV6, NONE, PAY3),
120 [0xDB] = WX_PTT(IP, IPV6, IG, IPV6, UDP, PAY4),
121 [0xDC] = WX_PTT(IP, IPV6, IG, IPV6, TCP, PAY4),
122 [0xDD] = WX_PTT(IP, IPV6, IG, IPV6, SCTP, PAY4),
124 /* IPv6 --> GRE/NAT -> MAC -> NONE/IPv4/IPv6 */
125 [0xE0] = WX_PTT(IP, IPV6, IGM, NONE, NONE, PAY3),
126 [0xE1] = WX_PTT(IP, IPV6, IGM, FGV4, NONE, PAY3),
127 [0xE2] = WX_PTT(IP, IPV6, IGM, IPV4, NONE, PAY3),
128 [0xE3] = WX_PTT(IP, IPV6, IGM, IPV4, UDP, PAY4),
129 [0xE4] = WX_PTT(IP, IPV6, IGM, IPV4, TCP, PAY4),
130 [0xE5] = WX_PTT(IP, IPV6, IGM, IPV4, SCTP, PAY4),
131 [0xE9] = WX_PTT(IP, IPV6, IGM, FGV6, NONE, PAY3),
132 [0xEA] = WX_PTT(IP, IPV6, IGM, IPV6, NONE, PAY3),
133 [0xEB] = WX_PTT(IP, IPV6, IGM, IPV6, UDP, PAY4),
134 [0xEC] = WX_PTT(IP, IPV6, IGM, IPV6, TCP, PAY4),
135 [0xED] = WX_PTT(IP, IPV6, IGM, IPV6, SCTP, PAY4),
137 /* IPv6 --> GRE/NAT -> MAC--> NONE/IPv */
138 [0xF0] = WX_PTT(IP, IPV6, IGMV, NONE, NONE, PAY3),
139 [0xF1] = WX_PTT(IP, IPV6, IGMV, FGV4, NONE, PAY3),
140 [0xF2] = WX_PTT(IP, IPV6, IGMV, IPV4, NONE, PAY3),
141 [0xF3] = WX_PTT(IP, IPV6, IGMV, IPV4, UDP, PAY4),
142 [0xF4] = WX_PTT(IP, IPV6, IGMV, IPV4, TCP, PAY4),
143 [0xF5] = WX_PTT(IP, IPV6, IGMV, IPV4, SCTP, PAY4),
144 [0xF9] = WX_PTT(IP, IPV6, IGMV, FGV6, NONE, PAY3),
145 [0xFA] = WX_PTT(IP, IPV6, IGMV, IPV6, NONE, PAY3),
146 [0xFB] = WX_PTT(IP, IPV6, IGMV, IPV6, UDP, PAY4),
147 [0xFC] = WX_PTT(IP, IPV6, IGMV, IPV6, TCP, PAY4),
148 [0xFD] = WX_PTT(IP, IPV6, IGMV, IPV6, SCTP, PAY4),
151 static struct wx_dec_ptype wx_decode_ptype(const u8 ptype)
153 return wx_ptype_lookup[ptype];
156 /* wx_test_staterr - tests bits in Rx descriptor status and error fields */
157 static __le32 wx_test_staterr(union wx_rx_desc *rx_desc,
158 const u32 stat_err_bits)
160 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
163 static void wx_dma_sync_frag(struct wx_ring *rx_ring,
164 struct wx_rx_buffer *rx_buffer)
166 struct sk_buff *skb = rx_buffer->skb;
167 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
169 dma_sync_single_range_for_cpu(rx_ring->dev,
175 /* If the page was released, just unmap it. */
176 if (unlikely(WX_CB(skb)->page_released))
177 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
180 static struct wx_rx_buffer *wx_get_rx_buffer(struct wx_ring *rx_ring,
181 union wx_rx_desc *rx_desc,
182 struct sk_buff **skb,
183 int *rx_buffer_pgcnt)
185 struct wx_rx_buffer *rx_buffer;
188 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
189 size = le16_to_cpu(rx_desc->wb.upper.length);
191 #if (PAGE_SIZE < 8192)
192 *rx_buffer_pgcnt = page_count(rx_buffer->page);
194 *rx_buffer_pgcnt = 0;
197 prefetchw(rx_buffer->page);
198 *skb = rx_buffer->skb;
200 /* Delay unmapping of the first packet. It carries the header
201 * information, HW may still access the header after the writeback.
202 * Only unmap it when EOP is reached
204 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)) {
209 wx_dma_sync_frag(rx_ring, rx_buffer);
212 /* we are reusing so sync this buffer for CPU use */
213 dma_sync_single_range_for_cpu(rx_ring->dev,
215 rx_buffer->page_offset,
222 static void wx_put_rx_buffer(struct wx_ring *rx_ring,
223 struct wx_rx_buffer *rx_buffer,
227 if (!IS_ERR(skb) && WX_CB(skb)->dma == rx_buffer->dma)
228 /* the page has been released from the ring */
229 WX_CB(skb)->page_released = true;
231 /* clear contents of rx_buffer */
232 rx_buffer->page = NULL;
233 rx_buffer->skb = NULL;
236 static struct sk_buff *wx_build_skb(struct wx_ring *rx_ring,
237 struct wx_rx_buffer *rx_buffer,
238 union wx_rx_desc *rx_desc)
240 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
241 #if (PAGE_SIZE < 8192)
242 unsigned int truesize = WX_RX_BUFSZ;
244 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
246 struct sk_buff *skb = rx_buffer->skb;
249 void *page_addr = page_address(rx_buffer->page) +
250 rx_buffer->page_offset;
252 /* prefetch first cache line of first page */
254 #if L1_CACHE_BYTES < 128
255 prefetch(page_addr + L1_CACHE_BYTES);
258 /* allocate a skb to store the frags */
259 skb = napi_alloc_skb(&rx_ring->q_vector->napi, WX_RXBUFFER_256);
263 /* we will be copying header into skb->data in
264 * pskb_may_pull so it is in our interest to prefetch
265 * it now to avoid a possible cache miss
267 prefetchw(skb->data);
269 if (size <= WX_RXBUFFER_256) {
270 memcpy(__skb_put(skb, size), page_addr,
271 ALIGN(size, sizeof(long)));
272 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, true);
276 skb_mark_for_recycle(skb);
278 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_EOP))
279 WX_CB(skb)->dma = rx_buffer->dma;
281 skb_add_rx_frag(skb, 0, rx_buffer->page,
282 rx_buffer->page_offset,
287 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
288 rx_buffer->page_offset, size, truesize);
292 #if (PAGE_SIZE < 8192)
293 /* flip page offset to other buffer */
294 rx_buffer->page_offset ^= truesize;
296 /* move offset up to the next cache line */
297 rx_buffer->page_offset += truesize;
303 static bool wx_alloc_mapped_page(struct wx_ring *rx_ring,
304 struct wx_rx_buffer *bi)
306 struct page *page = bi->page;
309 /* since we are recycling buffers we should seldom need to alloc */
313 page = page_pool_dev_alloc_pages(rx_ring->page_pool);
315 dma = page_pool_get_dma_addr(page);
325 * wx_alloc_rx_buffers - Replace used receive buffers
326 * @rx_ring: ring to place buffers on
327 * @cleaned_count: number of buffers to replace
329 void wx_alloc_rx_buffers(struct wx_ring *rx_ring, u16 cleaned_count)
331 u16 i = rx_ring->next_to_use;
332 union wx_rx_desc *rx_desc;
333 struct wx_rx_buffer *bi;
339 rx_desc = WX_RX_DESC(rx_ring, i);
340 bi = &rx_ring->rx_buffer_info[i];
344 if (!wx_alloc_mapped_page(rx_ring, bi))
347 /* sync the buffer for use by the device */
348 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
353 rx_desc->read.pkt_addr =
354 cpu_to_le64(bi->page_dma + bi->page_offset);
360 rx_desc = WX_RX_DESC(rx_ring, 0);
361 bi = rx_ring->rx_buffer_info;
365 /* clear the status bits for the next_to_use descriptor */
366 rx_desc->wb.upper.status_error = 0;
369 } while (cleaned_count);
373 if (rx_ring->next_to_use != i) {
374 rx_ring->next_to_use = i;
375 /* update next to alloc since we have filled the ring */
376 rx_ring->next_to_alloc = i;
378 /* Force memory writes to complete before letting h/w
379 * know there are new descriptors to fetch. (Only
380 * applicable for weak-ordered memory model archs,
384 writel(i, rx_ring->tail);
388 u16 wx_desc_unused(struct wx_ring *ring)
390 u16 ntc = ring->next_to_clean;
391 u16 ntu = ring->next_to_use;
393 return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
397 * wx_is_non_eop - process handling of non-EOP buffers
398 * @rx_ring: Rx ring being processed
399 * @rx_desc: Rx descriptor for current buffer
400 * @skb: Current socket buffer containing buffer in progress
402 * This function updates next to clean. If the buffer is an EOP buffer
403 * this function exits returning false, otherwise it will place the
404 * sk_buff in the next buffer to be chained and return true indicating
405 * that this is in fact a non-EOP buffer.
407 static bool wx_is_non_eop(struct wx_ring *rx_ring,
408 union wx_rx_desc *rx_desc,
411 u32 ntc = rx_ring->next_to_clean + 1;
413 /* fetch, update, and store next to clean */
414 ntc = (ntc < rx_ring->count) ? ntc : 0;
415 rx_ring->next_to_clean = ntc;
417 prefetch(WX_RX_DESC(rx_ring, ntc));
419 /* if we are the last buffer then there is nothing else to do */
420 if (likely(wx_test_staterr(rx_desc, WX_RXD_STAT_EOP)))
423 rx_ring->rx_buffer_info[ntc].skb = skb;
424 rx_ring->rx_stats.non_eop_descs++;
429 static void wx_pull_tail(struct sk_buff *skb)
431 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
432 unsigned int pull_len;
435 /* it is valid to use page_address instead of kmap since we are
436 * working with pages allocated out of the lomem pool per
437 * alloc_page(GFP_ATOMIC)
439 va = skb_frag_address(frag);
441 /* we need the header to contain the greater of either ETH_HLEN or
442 * 60 bytes if the skb->len is less than 60 for skb_pad.
444 pull_len = eth_get_headlen(skb->dev, va, WX_RXBUFFER_256);
446 /* align pull length to size of long to optimize memcpy performance */
447 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
449 /* update all of the pointers */
450 skb_frag_size_sub(frag, pull_len);
451 skb_frag_off_add(frag, pull_len);
452 skb->data_len -= pull_len;
453 skb->tail += pull_len;
457 * wx_cleanup_headers - Correct corrupted or empty headers
458 * @rx_ring: rx descriptor ring packet is being transacted on
459 * @rx_desc: pointer to the EOP Rx descriptor
460 * @skb: pointer to current skb being fixed
462 * Check for corrupted packet headers caused by senders on the local L2
463 * embedded NIC switch not setting up their Tx Descriptors right. These
464 * should be very rare.
466 * Also address the case where we are pulling data in on pages only
467 * and as such no data is present in the skb header.
469 * In addition if skb is not at least 60 bytes we need to pad it so that
470 * it is large enough to qualify as a valid Ethernet frame.
472 * Returns true if an error was encountered and skb was freed.
474 static bool wx_cleanup_headers(struct wx_ring *rx_ring,
475 union wx_rx_desc *rx_desc,
478 struct net_device *netdev = rx_ring->netdev;
480 /* verify that the packet does not have any known errors */
482 unlikely(wx_test_staterr(rx_desc, WX_RXD_ERR_RXE) &&
483 !(netdev->features & NETIF_F_RXALL))) {
484 dev_kfree_skb_any(skb);
488 /* place header in linear portion of buffer */
489 if (!skb_headlen(skb))
492 /* if eth_skb_pad returns an error the skb was freed */
493 if (eth_skb_pad(skb))
499 static void wx_rx_hash(struct wx_ring *ring,
500 union wx_rx_desc *rx_desc,
505 if (!(ring->netdev->features & NETIF_F_RXHASH))
508 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
514 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
515 (WX_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
516 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
520 * wx_rx_checksum - indicate in skb if hw indicated a good cksum
521 * @ring: structure containing ring specific data
522 * @rx_desc: current Rx descriptor being processed
523 * @skb: skb currently being received and modified
525 static void wx_rx_checksum(struct wx_ring *ring,
526 union wx_rx_desc *rx_desc,
529 struct wx_dec_ptype dptype = wx_decode_ptype(WX_RXD_PKTTYPE(rx_desc));
531 skb_checksum_none_assert(skb);
532 /* Rx csum disabled */
533 if (!(ring->netdev->features & NETIF_F_RXCSUM))
536 /* if IPv4 header checksum error */
537 if ((wx_test_staterr(rx_desc, WX_RXD_STAT_IPCS) &&
538 wx_test_staterr(rx_desc, WX_RXD_ERR_IPE)) ||
539 (wx_test_staterr(rx_desc, WX_RXD_STAT_OUTERIPCS) &&
540 wx_test_staterr(rx_desc, WX_RXD_ERR_OUTERIPER))) {
541 ring->rx_stats.csum_err++;
545 /* L4 checksum offload flag must set for the below code to work */
546 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_L4CS))
549 /* Hardware can't guarantee csum if IPv6 Dest Header found */
550 if (dptype.prot != WX_DEC_PTYPE_PROT_SCTP && WX_RXD_IPV6EX(rx_desc))
553 /* if L4 checksum error */
554 if (wx_test_staterr(rx_desc, WX_RXD_ERR_TCPE)) {
555 ring->rx_stats.csum_err++;
559 /* It must be a TCP or UDP or SCTP packet with a valid checksum */
560 skb->ip_summed = CHECKSUM_UNNECESSARY;
562 /* If there is an outer header present that might contain a checksum
563 * we need to bump the checksum level by 1 to reflect the fact that
564 * we are indicating we validated the inner checksum.
566 if (dptype.etype >= WX_DEC_PTYPE_ETYPE_IG)
567 __skb_incr_checksum_unnecessary(skb);
568 ring->rx_stats.csum_good_cnt++;
571 static void wx_rx_vlan(struct wx_ring *ring, union wx_rx_desc *rx_desc,
577 if ((ring->netdev->features &
578 (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) &&
579 wx_test_staterr(rx_desc, WX_RXD_STAT_VP)) {
580 idx = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
582 ethertype = ring->q_vector->wx->tpid[idx];
583 __vlan_hwaccel_put_tag(skb, htons(ethertype),
584 le16_to_cpu(rx_desc->wb.upper.vlan));
589 * wx_process_skb_fields - Populate skb header fields from Rx descriptor
590 * @rx_ring: rx descriptor ring packet is being transacted on
591 * @rx_desc: pointer to the EOP Rx descriptor
592 * @skb: pointer to current skb being populated
594 * This function checks the ring, descriptor, and packet information in
595 * order to populate the hash, checksum, protocol, and
596 * other fields within the skb.
598 static void wx_process_skb_fields(struct wx_ring *rx_ring,
599 union wx_rx_desc *rx_desc,
602 wx_rx_hash(rx_ring, rx_desc, skb);
603 wx_rx_checksum(rx_ring, rx_desc, skb);
604 wx_rx_vlan(rx_ring, rx_desc, skb);
605 skb_record_rx_queue(skb, rx_ring->queue_index);
606 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
610 * wx_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
611 * @q_vector: structure containing interrupt and ring information
612 * @rx_ring: rx descriptor ring to transact packets on
613 * @budget: Total limit on number of packets to process
615 * This function provides a "bounce buffer" approach to Rx interrupt
616 * processing. The advantage to this is that on systems that have
617 * expensive overhead for IOMMU access this provides a means of avoiding
618 * it by maintaining the mapping of the page to the system.
620 * Returns amount of work completed.
622 static int wx_clean_rx_irq(struct wx_q_vector *q_vector,
623 struct wx_ring *rx_ring,
626 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
627 u16 cleaned_count = wx_desc_unused(rx_ring);
630 struct wx_rx_buffer *rx_buffer;
631 union wx_rx_desc *rx_desc;
635 /* return some buffers to hardware, one at a time is too slow */
636 if (cleaned_count >= WX_RX_BUFFER_WRITE) {
637 wx_alloc_rx_buffers(rx_ring, cleaned_count);
641 rx_desc = WX_RX_DESC(rx_ring, rx_ring->next_to_clean);
642 if (!wx_test_staterr(rx_desc, WX_RXD_STAT_DD))
645 /* This memory barrier is needed to keep us from reading
646 * any other fields out of the rx_desc until we know the
647 * descriptor has been written back
651 rx_buffer = wx_get_rx_buffer(rx_ring, rx_desc, &skb, &rx_buffer_pgcnt);
653 /* retrieve a buffer from the ring */
654 skb = wx_build_skb(rx_ring, rx_buffer, rx_desc);
656 /* exit if we failed to retrieve a buffer */
658 rx_ring->rx_stats.alloc_rx_buff_failed++;
662 wx_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt);
665 /* place incomplete frames back on ring for completion */
666 if (wx_is_non_eop(rx_ring, rx_desc, skb))
669 /* verify the packet layout is correct */
670 if (wx_cleanup_headers(rx_ring, rx_desc, skb))
673 /* probably a little skewed due to removing CRC */
674 total_rx_bytes += skb->len;
676 /* populate checksum, timestamp, VLAN, and protocol */
677 wx_process_skb_fields(rx_ring, rx_desc, skb);
678 napi_gro_receive(&q_vector->napi, skb);
680 /* update budget accounting */
682 } while (likely(total_rx_packets < budget));
684 u64_stats_update_begin(&rx_ring->syncp);
685 rx_ring->stats.packets += total_rx_packets;
686 rx_ring->stats.bytes += total_rx_bytes;
687 u64_stats_update_end(&rx_ring->syncp);
688 q_vector->rx.total_packets += total_rx_packets;
689 q_vector->rx.total_bytes += total_rx_bytes;
691 return total_rx_packets;
694 static struct netdev_queue *wx_txring_txq(const struct wx_ring *ring)
696 return netdev_get_tx_queue(ring->netdev, ring->queue_index);
700 * wx_clean_tx_irq - Reclaim resources after transmit completes
701 * @q_vector: structure containing interrupt and ring information
702 * @tx_ring: tx ring to clean
703 * @napi_budget: Used to determine if we are in netpoll
705 static bool wx_clean_tx_irq(struct wx_q_vector *q_vector,
706 struct wx_ring *tx_ring, int napi_budget)
708 unsigned int budget = q_vector->wx->tx_work_limit;
709 unsigned int total_bytes = 0, total_packets = 0;
710 unsigned int i = tx_ring->next_to_clean;
711 struct wx_tx_buffer *tx_buffer;
712 union wx_tx_desc *tx_desc;
714 if (!netif_carrier_ok(tx_ring->netdev))
717 tx_buffer = &tx_ring->tx_buffer_info[i];
718 tx_desc = WX_TX_DESC(tx_ring, i);
722 union wx_tx_desc *eop_desc = tx_buffer->next_to_watch;
724 /* if next_to_watch is not set then there is no work pending */
728 /* prevent any other reads prior to eop_desc */
731 /* if DD is not set pending work has not been completed */
732 if (!(eop_desc->wb.status & cpu_to_le32(WX_TXD_STAT_DD)))
735 /* clear next_to_watch to prevent false hangs */
736 tx_buffer->next_to_watch = NULL;
738 /* update the statistics for this packet */
739 total_bytes += tx_buffer->bytecount;
740 total_packets += tx_buffer->gso_segs;
743 napi_consume_skb(tx_buffer->skb, napi_budget);
745 /* unmap skb header data */
746 dma_unmap_single(tx_ring->dev,
747 dma_unmap_addr(tx_buffer, dma),
748 dma_unmap_len(tx_buffer, len),
751 /* clear tx_buffer data */
752 dma_unmap_len_set(tx_buffer, len, 0);
754 /* unmap remaining buffers */
755 while (tx_desc != eop_desc) {
761 tx_buffer = tx_ring->tx_buffer_info;
762 tx_desc = WX_TX_DESC(tx_ring, 0);
765 /* unmap any remaining paged data */
766 if (dma_unmap_len(tx_buffer, len)) {
767 dma_unmap_page(tx_ring->dev,
768 dma_unmap_addr(tx_buffer, dma),
769 dma_unmap_len(tx_buffer, len),
771 dma_unmap_len_set(tx_buffer, len, 0);
775 /* move us one more past the eop_desc for start of next pkt */
781 tx_buffer = tx_ring->tx_buffer_info;
782 tx_desc = WX_TX_DESC(tx_ring, 0);
785 /* issue prefetch for next Tx descriptor */
788 /* update budget accounting */
790 } while (likely(budget));
793 tx_ring->next_to_clean = i;
794 u64_stats_update_begin(&tx_ring->syncp);
795 tx_ring->stats.bytes += total_bytes;
796 tx_ring->stats.packets += total_packets;
797 u64_stats_update_end(&tx_ring->syncp);
798 q_vector->tx.total_bytes += total_bytes;
799 q_vector->tx.total_packets += total_packets;
801 netdev_tx_completed_queue(wx_txring_txq(tx_ring),
802 total_packets, total_bytes);
804 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
805 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
806 (wx_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
807 /* Make sure that anybody stopping the queue after this
808 * sees the new next_to_clean.
812 if (__netif_subqueue_stopped(tx_ring->netdev,
813 tx_ring->queue_index) &&
814 netif_running(tx_ring->netdev)) {
815 netif_wake_subqueue(tx_ring->netdev,
816 tx_ring->queue_index);
817 ++tx_ring->tx_stats.restart_queue;
825 * wx_poll - NAPI polling RX/TX cleanup routine
826 * @napi: napi struct with our devices info in it
827 * @budget: amount of work driver is allowed to do this pass, in packets
829 * This function will clean all queues associated with a q_vector.
831 static int wx_poll(struct napi_struct *napi, int budget)
833 struct wx_q_vector *q_vector = container_of(napi, struct wx_q_vector, napi);
834 int per_ring_budget, work_done = 0;
835 struct wx *wx = q_vector->wx;
836 bool clean_complete = true;
837 struct wx_ring *ring;
839 wx_for_each_ring(ring, q_vector->tx) {
840 if (!wx_clean_tx_irq(q_vector, ring, budget))
841 clean_complete = false;
844 /* Exit if we are called by netpoll */
848 /* attempt to distribute budget to each queue fairly, but don't allow
849 * the budget to go below 1 because we'll exit polling
851 if (q_vector->rx.count > 1)
852 per_ring_budget = max(budget / q_vector->rx.count, 1);
854 per_ring_budget = budget;
856 wx_for_each_ring(ring, q_vector->rx) {
857 int cleaned = wx_clean_rx_irq(q_vector, ring, per_ring_budget);
859 work_done += cleaned;
860 if (cleaned >= per_ring_budget)
861 clean_complete = false;
864 /* If all work not completed, return budget and keep polling */
868 /* all work done, exit the polling mode */
869 if (likely(napi_complete_done(napi, work_done))) {
870 if (netif_running(wx->netdev))
871 wx_intr_enable(wx, WX_INTR_Q(q_vector->v_idx));
874 return min(work_done, budget - 1);
877 static int wx_maybe_stop_tx(struct wx_ring *tx_ring, u16 size)
879 if (likely(wx_desc_unused(tx_ring) >= size))
882 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
884 /* For the next check */
887 /* We need to check again in a case another CPU has just
888 * made room available.
890 if (likely(wx_desc_unused(tx_ring) < size))
893 /* A reprieve! - use start_queue because it doesn't call schedule */
894 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
895 ++tx_ring->tx_stats.restart_queue;
900 static u32 wx_tx_cmd_type(u32 tx_flags)
902 /* set type for advanced descriptor with frame checksum insertion */
903 u32 cmd_type = WX_TXD_DTYP_DATA | WX_TXD_IFCS;
905 /* set HW vlan bit if vlan is present */
906 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_HW_VLAN, WX_TXD_VLE);
907 /* set segmentation enable bits for TSO/FSO */
908 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSO, WX_TXD_TSE);
909 /* set timestamp bit if present */
910 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_TSTAMP, WX_TXD_MAC_TSTAMP);
911 cmd_type |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_LINKSEC, WX_TXD_LINKSEC);
916 static void wx_tx_olinfo_status(union wx_tx_desc *tx_desc,
917 u32 tx_flags, unsigned int paylen)
919 u32 olinfo_status = paylen << WX_TXD_PAYLEN_SHIFT;
921 /* enable L4 checksum for TSO and TX checksum offload */
922 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CSUM, WX_TXD_L4CS);
923 /* enable IPv4 checksum for TSO */
924 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPV4, WX_TXD_IIPCS);
925 /* enable outer IPv4 checksum for TSO */
926 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_OUTER_IPV4,
928 /* Check Context must be set if Tx switch is enabled, which it
929 * always is for case where virtual functions are running
931 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_CC, WX_TXD_CC);
932 olinfo_status |= WX_SET_FLAG(tx_flags, WX_TX_FLAGS_IPSEC,
934 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
937 static void wx_tx_map(struct wx_ring *tx_ring,
938 struct wx_tx_buffer *first,
941 struct sk_buff *skb = first->skb;
942 struct wx_tx_buffer *tx_buffer;
943 u32 tx_flags = first->tx_flags;
944 u16 i = tx_ring->next_to_use;
945 unsigned int data_len, size;
946 union wx_tx_desc *tx_desc;
951 cmd_type = wx_tx_cmd_type(tx_flags);
952 tx_desc = WX_TX_DESC(tx_ring, i);
953 wx_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
955 size = skb_headlen(skb);
956 data_len = skb->data_len;
957 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
961 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
962 if (dma_mapping_error(tx_ring->dev, dma))
965 /* record length, and DMA address */
966 dma_unmap_len_set(tx_buffer, len, size);
967 dma_unmap_addr_set(tx_buffer, dma, dma);
969 tx_desc->read.buffer_addr = cpu_to_le64(dma);
971 while (unlikely(size > WX_MAX_DATA_PER_TXD)) {
972 tx_desc->read.cmd_type_len =
973 cpu_to_le32(cmd_type ^ WX_MAX_DATA_PER_TXD);
977 if (i == tx_ring->count) {
978 tx_desc = WX_TX_DESC(tx_ring, 0);
981 tx_desc->read.olinfo_status = 0;
983 dma += WX_MAX_DATA_PER_TXD;
984 size -= WX_MAX_DATA_PER_TXD;
986 tx_desc->read.buffer_addr = cpu_to_le64(dma);
989 if (likely(!data_len))
992 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
996 if (i == tx_ring->count) {
997 tx_desc = WX_TX_DESC(tx_ring, 0);
1000 tx_desc->read.olinfo_status = 0;
1002 size = skb_frag_size(frag);
1006 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
1009 tx_buffer = &tx_ring->tx_buffer_info[i];
1012 /* write last descriptor with RS and EOP bits */
1013 cmd_type |= size | WX_TXD_EOP | WX_TXD_RS;
1014 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
1016 netdev_tx_sent_queue(wx_txring_txq(tx_ring), first->bytecount);
1018 skb_tx_timestamp(skb);
1020 /* Force memory writes to complete before letting h/w know there
1021 * are new descriptors to fetch. (Only applicable for weak-ordered
1022 * memory model archs, such as IA-64).
1024 * We also need this memory barrier to make certain all of the
1025 * status bits have been updated before next_to_watch is written.
1029 /* set next_to_watch value indicating a packet is present */
1030 first->next_to_watch = tx_desc;
1033 if (i == tx_ring->count)
1036 tx_ring->next_to_use = i;
1038 wx_maybe_stop_tx(tx_ring, DESC_NEEDED);
1040 if (netif_xmit_stopped(wx_txring_txq(tx_ring)) || !netdev_xmit_more())
1041 writel(i, tx_ring->tail);
1045 dev_err(tx_ring->dev, "TX DMA map failed\n");
1047 /* clear dma mappings for failed tx_buffer_info map */
1049 tx_buffer = &tx_ring->tx_buffer_info[i];
1050 if (dma_unmap_len(tx_buffer, len))
1051 dma_unmap_page(tx_ring->dev,
1052 dma_unmap_addr(tx_buffer, dma),
1053 dma_unmap_len(tx_buffer, len),
1055 dma_unmap_len_set(tx_buffer, len, 0);
1056 if (tx_buffer == first)
1059 i += tx_ring->count;
1063 dev_kfree_skb_any(first->skb);
1066 tx_ring->next_to_use = i;
1069 static void wx_tx_ctxtdesc(struct wx_ring *tx_ring, u32 vlan_macip_lens,
1070 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
1072 struct wx_tx_context_desc *context_desc;
1073 u16 i = tx_ring->next_to_use;
1075 context_desc = WX_TX_CTXTDESC(tx_ring, i);
1077 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1079 /* set bits to identify this as an advanced context descriptor */
1080 type_tucmd |= WX_TXD_DTYP_CTXT;
1081 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
1082 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
1083 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
1084 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
1087 static void wx_get_ipv6_proto(struct sk_buff *skb, int offset, u8 *nexthdr)
1089 struct ipv6hdr *hdr = (struct ipv6hdr *)(skb->data + offset);
1091 *nexthdr = hdr->nexthdr;
1092 offset += sizeof(struct ipv6hdr);
1093 while (ipv6_ext_hdr(*nexthdr)) {
1094 struct ipv6_opt_hdr _hdr, *hp;
1096 if (*nexthdr == NEXTHDR_NONE)
1098 hp = skb_header_pointer(skb, offset, sizeof(_hdr), &_hdr);
1101 if (*nexthdr == NEXTHDR_FRAGMENT)
1103 *nexthdr = hp->nexthdr;
1107 union network_header {
1109 struct ipv6hdr *ipv6;
1113 static u8 wx_encode_tx_desc_ptype(const struct wx_tx_buffer *first)
1115 u8 tun_prot = 0, l4_prot = 0, ptype = 0;
1116 struct sk_buff *skb = first->skb;
1118 if (skb->encapsulation) {
1119 union network_header hdr;
1121 switch (first->protocol) {
1122 case htons(ETH_P_IP):
1123 tun_prot = ip_hdr(skb)->protocol;
1124 ptype = WX_PTYPE_TUN_IPV4;
1126 case htons(ETH_P_IPV6):
1127 wx_get_ipv6_proto(skb, skb_network_offset(skb), &tun_prot);
1128 ptype = WX_PTYPE_TUN_IPV6;
1134 if (tun_prot == IPPROTO_IPIP) {
1135 hdr.raw = (void *)inner_ip_hdr(skb);
1136 ptype |= WX_PTYPE_PKT_IPIP;
1137 } else if (tun_prot == IPPROTO_UDP) {
1138 hdr.raw = (void *)inner_ip_hdr(skb);
1139 if (skb->inner_protocol_type != ENCAP_TYPE_ETHER ||
1140 skb->inner_protocol != htons(ETH_P_TEB)) {
1141 ptype |= WX_PTYPE_PKT_IG;
1143 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto
1144 == htons(ETH_P_8021Q))
1145 ptype |= WX_PTYPE_PKT_IGMV;
1147 ptype |= WX_PTYPE_PKT_IGM;
1150 } else if (tun_prot == IPPROTO_GRE) {
1151 hdr.raw = (void *)inner_ip_hdr(skb);
1152 if (skb->inner_protocol == htons(ETH_P_IP) ||
1153 skb->inner_protocol == htons(ETH_P_IPV6)) {
1154 ptype |= WX_PTYPE_PKT_IG;
1156 if (((struct ethhdr *)skb_inner_mac_header(skb))->h_proto
1157 == htons(ETH_P_8021Q))
1158 ptype |= WX_PTYPE_PKT_IGMV;
1160 ptype |= WX_PTYPE_PKT_IGM;
1166 switch (hdr.ipv4->version) {
1168 l4_prot = hdr.ipv4->protocol;
1171 wx_get_ipv6_proto(skb, skb_inner_network_offset(skb), &l4_prot);
1172 ptype |= WX_PTYPE_PKT_IPV6;
1178 switch (first->protocol) {
1179 case htons(ETH_P_IP):
1180 l4_prot = ip_hdr(skb)->protocol;
1181 ptype = WX_PTYPE_PKT_IP;
1183 case htons(ETH_P_IPV6):
1184 wx_get_ipv6_proto(skb, skb_network_offset(skb), &l4_prot);
1185 ptype = WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6;
1188 return WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC;
1193 ptype |= WX_PTYPE_TYP_TCP;
1196 ptype |= WX_PTYPE_TYP_UDP;
1199 ptype |= WX_PTYPE_TYP_SCTP;
1202 ptype |= WX_PTYPE_TYP_IP;
1209 static int wx_tso(struct wx_ring *tx_ring, struct wx_tx_buffer *first,
1210 u8 *hdr_len, u8 ptype)
1212 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
1213 struct net_device *netdev = tx_ring->netdev;
1214 u32 l4len, tunhdr_eiplen_tunlen = 0;
1215 struct sk_buff *skb = first->skb;
1216 bool enc = skb->encapsulation;
1217 struct ipv6hdr *ipv6h;
1218 struct tcphdr *tcph;
1223 if (skb->ip_summed != CHECKSUM_PARTIAL)
1226 if (!skb_is_gso(skb))
1229 err = skb_cow_head(skb, 0);
1233 /* indicates the inner headers in the skbuff are valid. */
1234 iph = enc ? inner_ip_hdr(skb) : ip_hdr(skb);
1235 if (iph->version == 4) {
1236 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1239 tcph->check = ~csum_tcpudp_magic(iph->saddr,
1242 first->tx_flags |= WX_TX_FLAGS_TSO |
1246 } else if (iph->version == 6 && skb_is_gso_v6(skb)) {
1247 ipv6h = enc ? inner_ipv6_hdr(skb) : ipv6_hdr(skb);
1248 tcph = enc ? inner_tcp_hdr(skb) : tcp_hdr(skb);
1249 ipv6h->payload_len = 0;
1250 tcph->check = ~csum_ipv6_magic(&ipv6h->saddr,
1253 first->tx_flags |= WX_TX_FLAGS_TSO |
1258 /* compute header lengths */
1259 l4len = enc ? inner_tcp_hdrlen(skb) : tcp_hdrlen(skb);
1260 *hdr_len = enc ? skb_inner_transport_offset(skb) :
1261 skb_transport_offset(skb);
1264 /* update gso size and bytecount with header size */
1265 first->gso_segs = skb_shinfo(skb)->gso_segs;
1266 first->bytecount += (first->gso_segs - 1) * *hdr_len;
1268 /* mss_l4len_id: use 0 as index for TSO */
1269 mss_l4len_idx = l4len << WX_TXD_L4LEN_SHIFT;
1270 mss_l4len_idx |= skb_shinfo(skb)->gso_size << WX_TXD_MSS_SHIFT;
1272 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
1274 switch (first->protocol) {
1275 case htons(ETH_P_IP):
1276 tun_prot = ip_hdr(skb)->protocol;
1277 first->tx_flags |= WX_TX_FLAGS_OUTER_IPV4;
1279 case htons(ETH_P_IPV6):
1280 tun_prot = ipv6_hdr(skb)->nexthdr;
1287 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP;
1288 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1289 WX_TXD_OUTER_IPLEN_SHIFT) |
1290 (((skb_inner_mac_header(skb) -
1291 skb_transport_header(skb)) >> 1) <<
1292 WX_TXD_TUNNEL_LEN_SHIFT);
1295 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE;
1296 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1297 WX_TXD_OUTER_IPLEN_SHIFT) |
1298 (((skb_inner_mac_header(skb) -
1299 skb_transport_header(skb)) >> 1) <<
1300 WX_TXD_TUNNEL_LEN_SHIFT);
1303 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) -
1304 (char *)ip_hdr(skb)) >> 2) <<
1305 WX_TXD_OUTER_IPLEN_SHIFT;
1310 vlan_macip_lens = skb_inner_network_header_len(skb) >> 1;
1312 vlan_macip_lens = skb_network_header_len(skb) >> 1;
1315 vlan_macip_lens |= skb_network_offset(skb) << WX_TXD_MACLEN_SHIFT;
1316 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK;
1318 type_tucmd = ptype << 24;
1319 if (skb->vlan_proto == htons(ETH_P_8021AD) &&
1320 netdev->features & NETIF_F_HW_VLAN_STAG_TX)
1321 type_tucmd |= WX_SET_FLAG(first->tx_flags,
1322 WX_TX_FLAGS_HW_VLAN,
1323 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT);
1324 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen,
1325 type_tucmd, mss_l4len_idx);
1330 static void wx_tx_csum(struct wx_ring *tx_ring, struct wx_tx_buffer *first,
1333 u32 tunhdr_eiplen_tunlen = 0, vlan_macip_lens = 0;
1334 struct net_device *netdev = tx_ring->netdev;
1335 u32 mss_l4len_idx = 0, type_tucmd;
1336 struct sk_buff *skb = first->skb;
1339 if (skb->ip_summed != CHECKSUM_PARTIAL) {
1340 if (!(first->tx_flags & WX_TX_FLAGS_HW_VLAN) &&
1341 !(first->tx_flags & WX_TX_FLAGS_CC))
1343 vlan_macip_lens = skb_network_offset(skb) <<
1344 WX_TXD_MACLEN_SHIFT;
1349 struct ipv6hdr *ipv6;
1353 struct tcphdr *tcphdr;
1357 if (skb->encapsulation) {
1358 network_hdr.raw = skb_inner_network_header(skb);
1359 transport_hdr.raw = skb_inner_transport_header(skb);
1360 vlan_macip_lens = skb_network_offset(skb) <<
1361 WX_TXD_MACLEN_SHIFT;
1362 switch (first->protocol) {
1363 case htons(ETH_P_IP):
1364 tun_prot = ip_hdr(skb)->protocol;
1366 case htons(ETH_P_IPV6):
1367 tun_prot = ipv6_hdr(skb)->nexthdr;
1374 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_UDP;
1375 tunhdr_eiplen_tunlen |=
1376 ((skb_network_header_len(skb) >> 2) <<
1377 WX_TXD_OUTER_IPLEN_SHIFT) |
1378 (((skb_inner_mac_header(skb) -
1379 skb_transport_header(skb)) >> 1) <<
1380 WX_TXD_TUNNEL_LEN_SHIFT);
1383 tunhdr_eiplen_tunlen = WX_TXD_TUNNEL_GRE;
1384 tunhdr_eiplen_tunlen |= ((skb_network_header_len(skb) >> 2) <<
1385 WX_TXD_OUTER_IPLEN_SHIFT) |
1386 (((skb_inner_mac_header(skb) -
1387 skb_transport_header(skb)) >> 1) <<
1388 WX_TXD_TUNNEL_LEN_SHIFT);
1391 tunhdr_eiplen_tunlen = (((char *)inner_ip_hdr(skb) -
1392 (char *)ip_hdr(skb)) >> 2) <<
1393 WX_TXD_OUTER_IPLEN_SHIFT;
1400 network_hdr.raw = skb_network_header(skb);
1401 transport_hdr.raw = skb_transport_header(skb);
1402 vlan_macip_lens = skb_network_offset(skb) <<
1403 WX_TXD_MACLEN_SHIFT;
1406 switch (network_hdr.ipv4->version) {
1408 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1;
1409 l4_prot = network_hdr.ipv4->protocol;
1412 vlan_macip_lens |= (transport_hdr.raw - network_hdr.raw) >> 1;
1413 l4_prot = network_hdr.ipv6->nexthdr;
1421 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
1425 mss_l4len_idx = sizeof(struct sctphdr) <<
1429 mss_l4len_idx = sizeof(struct udphdr) <<
1436 /* update TX checksum flag */
1437 first->tx_flags |= WX_TX_FLAGS_CSUM;
1439 first->tx_flags |= WX_TX_FLAGS_CC;
1440 /* vlan_macip_lens: MACLEN, VLAN tag */
1441 vlan_macip_lens |= first->tx_flags & WX_TX_FLAGS_VLAN_MASK;
1443 type_tucmd = ptype << 24;
1444 if (skb->vlan_proto == htons(ETH_P_8021AD) &&
1445 netdev->features & NETIF_F_HW_VLAN_STAG_TX)
1446 type_tucmd |= WX_SET_FLAG(first->tx_flags,
1447 WX_TX_FLAGS_HW_VLAN,
1448 0x1 << WX_TXD_TAG_TPID_SEL_SHIFT);
1449 wx_tx_ctxtdesc(tx_ring, vlan_macip_lens, tunhdr_eiplen_tunlen,
1450 type_tucmd, mss_l4len_idx);
1453 static netdev_tx_t wx_xmit_frame_ring(struct sk_buff *skb,
1454 struct wx_ring *tx_ring)
1456 u16 count = TXD_USE_COUNT(skb_headlen(skb));
1457 struct wx_tx_buffer *first;
1458 u8 hdr_len = 0, ptype;
1463 /* need: 1 descriptor per page * PAGE_SIZE/WX_MAX_DATA_PER_TXD,
1464 * + 1 desc for skb_headlen/WX_MAX_DATA_PER_TXD,
1465 * + 2 desc gap to keep tail from touching head,
1466 * + 1 desc for context descriptor,
1467 * otherwise try next time
1469 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
1470 count += TXD_USE_COUNT(skb_frag_size(&skb_shinfo(skb)->
1473 if (wx_maybe_stop_tx(tx_ring, count + 3)) {
1474 tx_ring->tx_stats.tx_busy++;
1475 return NETDEV_TX_BUSY;
1478 /* record the location of the first descriptor for this packet */
1479 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
1481 first->bytecount = skb->len;
1482 first->gso_segs = 1;
1484 /* if we have a HW VLAN tag being added default to the HW one */
1485 if (skb_vlan_tag_present(skb)) {
1486 tx_flags |= skb_vlan_tag_get(skb) << WX_TX_FLAGS_VLAN_SHIFT;
1487 tx_flags |= WX_TX_FLAGS_HW_VLAN;
1490 /* record initial flags and protocol */
1491 first->tx_flags = tx_flags;
1492 first->protocol = vlan_get_protocol(skb);
1494 ptype = wx_encode_tx_desc_ptype(first);
1496 tso = wx_tso(tx_ring, first, &hdr_len, ptype);
1500 wx_tx_csum(tx_ring, first, ptype);
1501 wx_tx_map(tx_ring, first, hdr_len);
1503 return NETDEV_TX_OK;
1505 dev_kfree_skb_any(first->skb);
1508 return NETDEV_TX_OK;
1511 netdev_tx_t wx_xmit_frame(struct sk_buff *skb,
1512 struct net_device *netdev)
1514 unsigned int r_idx = skb->queue_mapping;
1515 struct wx *wx = netdev_priv(netdev);
1516 struct wx_ring *tx_ring;
1518 if (!netif_carrier_ok(netdev)) {
1519 dev_kfree_skb_any(skb);
1520 return NETDEV_TX_OK;
1523 /* The minimum packet size for olinfo paylen is 17 so pad the skb
1524 * in order to meet this minimum size requirement.
1526 if (skb_put_padto(skb, 17))
1527 return NETDEV_TX_OK;
1529 if (r_idx >= wx->num_tx_queues)
1530 r_idx = r_idx % wx->num_tx_queues;
1531 tx_ring = wx->tx_ring[r_idx];
1533 return wx_xmit_frame_ring(skb, tx_ring);
1535 EXPORT_SYMBOL(wx_xmit_frame);
1537 void wx_napi_enable_all(struct wx *wx)
1539 struct wx_q_vector *q_vector;
1542 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) {
1543 q_vector = wx->q_vector[q_idx];
1544 napi_enable(&q_vector->napi);
1547 EXPORT_SYMBOL(wx_napi_enable_all);
1549 void wx_napi_disable_all(struct wx *wx)
1551 struct wx_q_vector *q_vector;
1554 for (q_idx = 0; q_idx < wx->num_q_vectors; q_idx++) {
1555 q_vector = wx->q_vector[q_idx];
1556 napi_disable(&q_vector->napi);
1559 EXPORT_SYMBOL(wx_napi_disable_all);
1562 * wx_set_rss_queues: Allocate queues for RSS
1563 * @wx: board private structure to initialize
1565 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
1566 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
1569 static void wx_set_rss_queues(struct wx *wx)
1571 struct wx_ring_feature *f;
1573 /* set mask for 16 queue limit of RSS */
1574 f = &wx->ring_feature[RING_F_RSS];
1575 f->indices = f->limit;
1577 wx->num_rx_queues = f->limit;
1578 wx->num_tx_queues = f->limit;
1581 static void wx_set_num_queues(struct wx *wx)
1583 /* Start with base case */
1584 wx->num_rx_queues = 1;
1585 wx->num_tx_queues = 1;
1586 wx->queues_per_pool = 1;
1588 wx_set_rss_queues(wx);
1592 * wx_acquire_msix_vectors - acquire MSI-X vectors
1593 * @wx: board private structure
1595 * Attempts to acquire a suitable range of MSI-X vector interrupts. Will
1596 * return a negative error code if unable to acquire MSI-X vectors for any
1599 static int wx_acquire_msix_vectors(struct wx *wx)
1601 struct irq_affinity affd = { .pre_vectors = 1 };
1604 /* We start by asking for one vector per queue pair */
1605 nvecs = max(wx->num_rx_queues, wx->num_tx_queues);
1606 nvecs = min_t(int, nvecs, num_online_cpus());
1607 nvecs = min_t(int, nvecs, wx->mac.max_msix_vectors);
1609 wx->msix_q_entries = kcalloc(nvecs, sizeof(struct msix_entry),
1611 if (!wx->msix_q_entries)
1614 /* One for non-queue interrupts */
1617 wx->msix_entry = kcalloc(1, sizeof(struct msix_entry),
1619 if (!wx->msix_entry) {
1620 kfree(wx->msix_q_entries);
1621 wx->msix_q_entries = NULL;
1625 nvecs = pci_alloc_irq_vectors_affinity(wx->pdev, nvecs,
1627 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY,
1630 wx_err(wx, "Failed to allocate MSI-X interrupts. Err: %d\n", nvecs);
1631 kfree(wx->msix_q_entries);
1632 wx->msix_q_entries = NULL;
1633 kfree(wx->msix_entry);
1634 wx->msix_entry = NULL;
1638 wx->msix_entry->entry = 0;
1639 wx->msix_entry->vector = pci_irq_vector(wx->pdev, 0);
1641 for (i = 0; i < nvecs; i++) {
1642 wx->msix_q_entries[i].entry = i;
1643 wx->msix_q_entries[i].vector = pci_irq_vector(wx->pdev, i + 1);
1646 wx->num_q_vectors = nvecs;
1652 * wx_set_interrupt_capability - set MSI-X or MSI if supported
1653 * @wx: board private structure to initialize
1655 * Attempt to configure the interrupts using the best available
1656 * capabilities of the hardware and the kernel.
1658 static int wx_set_interrupt_capability(struct wx *wx)
1660 struct pci_dev *pdev = wx->pdev;
1663 /* We will try to get MSI-X interrupts first */
1664 ret = wx_acquire_msix_vectors(wx);
1665 if (ret == 0 || (ret == -ENOMEM))
1669 dev_warn(&wx->pdev->dev, "Disabling RSS support\n");
1670 wx->ring_feature[RING_F_RSS].limit = 1;
1672 wx_set_num_queues(wx);
1674 /* minmum one for queue, one for misc*/
1676 nvecs = pci_alloc_irq_vectors(pdev, nvecs,
1677 nvecs, PCI_IRQ_MSI | PCI_IRQ_LEGACY);
1679 if (pdev->msi_enabled)
1680 wx_err(wx, "Fallback to MSI.\n");
1682 wx_err(wx, "Fallback to LEGACY.\n");
1684 wx_err(wx, "Failed to allocate MSI/LEGACY interrupts. Error: %d\n", nvecs);
1688 pdev->irq = pci_irq_vector(pdev, 0);
1694 * wx_cache_ring_rss - Descriptor ring to register mapping for RSS
1695 * @wx: board private structure to initialize
1697 * Cache the descriptor ring offsets for RSS, ATR, FCoE, and SR-IOV.
1700 static void wx_cache_ring_rss(struct wx *wx)
1704 for (i = 0; i < wx->num_rx_queues; i++)
1705 wx->rx_ring[i]->reg_idx = i;
1707 for (i = 0; i < wx->num_tx_queues; i++)
1708 wx->tx_ring[i]->reg_idx = i;
1711 static void wx_add_ring(struct wx_ring *ring, struct wx_ring_container *head)
1713 ring->next = head->ring;
1719 * wx_alloc_q_vector - Allocate memory for a single interrupt vector
1720 * @wx: board private structure to initialize
1721 * @v_count: q_vectors allocated on wx, used for ring interleaving
1722 * @v_idx: index of vector in wx struct
1723 * @txr_count: total number of Tx rings to allocate
1724 * @txr_idx: index of first Tx ring to allocate
1725 * @rxr_count: total number of Rx rings to allocate
1726 * @rxr_idx: index of first Rx ring to allocate
1728 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1730 static int wx_alloc_q_vector(struct wx *wx,
1731 unsigned int v_count, unsigned int v_idx,
1732 unsigned int txr_count, unsigned int txr_idx,
1733 unsigned int rxr_count, unsigned int rxr_idx)
1735 struct wx_q_vector *q_vector;
1736 int ring_count, default_itr;
1737 struct wx_ring *ring;
1739 /* note this will allocate space for the ring structure as well! */
1740 ring_count = txr_count + rxr_count;
1742 q_vector = kzalloc(struct_size(q_vector, ring, ring_count),
1747 /* initialize NAPI */
1748 netif_napi_add(wx->netdev, &q_vector->napi,
1751 /* tie q_vector and wx together */
1752 wx->q_vector[v_idx] = q_vector;
1754 q_vector->v_idx = v_idx;
1755 if (cpu_online(v_idx))
1756 q_vector->numa_node = cpu_to_node(v_idx);
1758 /* initialize pointer to rings */
1759 ring = q_vector->ring;
1761 if (wx->mac.type == wx_mac_sp)
1762 default_itr = WX_12K_ITR;
1764 default_itr = WX_7K_ITR;
1765 /* initialize ITR */
1766 if (txr_count && !rxr_count)
1767 /* tx only vector */
1768 q_vector->itr = wx->tx_itr_setting ?
1769 default_itr : wx->tx_itr_setting;
1771 /* rx or rx/tx vector */
1772 q_vector->itr = wx->rx_itr_setting ?
1773 default_itr : wx->rx_itr_setting;
1776 /* assign generic ring traits */
1777 ring->dev = &wx->pdev->dev;
1778 ring->netdev = wx->netdev;
1780 /* configure backlink on ring */
1781 ring->q_vector = q_vector;
1783 /* update q_vector Tx values */
1784 wx_add_ring(ring, &q_vector->tx);
1786 /* apply Tx specific ring traits */
1787 ring->count = wx->tx_ring_count;
1789 ring->queue_index = txr_idx;
1791 /* assign ring to wx */
1792 wx->tx_ring[txr_idx] = ring;
1794 /* update count and index */
1798 /* push pointer to next ring */
1803 /* assign generic ring traits */
1804 ring->dev = &wx->pdev->dev;
1805 ring->netdev = wx->netdev;
1807 /* configure backlink on ring */
1808 ring->q_vector = q_vector;
1810 /* update q_vector Rx values */
1811 wx_add_ring(ring, &q_vector->rx);
1813 /* apply Rx specific ring traits */
1814 ring->count = wx->rx_ring_count;
1815 ring->queue_index = rxr_idx;
1817 /* assign ring to wx */
1818 wx->rx_ring[rxr_idx] = ring;
1820 /* update count and index */
1824 /* push pointer to next ring */
1832 * wx_free_q_vector - Free memory allocated for specific interrupt vector
1833 * @wx: board private structure to initialize
1834 * @v_idx: Index of vector to be freed
1836 * This function frees the memory allocated to the q_vector. In addition if
1837 * NAPI is enabled it will delete any references to the NAPI struct prior
1838 * to freeing the q_vector.
1840 static void wx_free_q_vector(struct wx *wx, int v_idx)
1842 struct wx_q_vector *q_vector = wx->q_vector[v_idx];
1843 struct wx_ring *ring;
1845 wx_for_each_ring(ring, q_vector->tx)
1846 wx->tx_ring[ring->queue_index] = NULL;
1848 wx_for_each_ring(ring, q_vector->rx)
1849 wx->rx_ring[ring->queue_index] = NULL;
1851 wx->q_vector[v_idx] = NULL;
1852 netif_napi_del(&q_vector->napi);
1853 kfree_rcu(q_vector, rcu);
1857 * wx_alloc_q_vectors - Allocate memory for interrupt vectors
1858 * @wx: board private structure to initialize
1860 * We allocate one q_vector per queue interrupt. If allocation fails we
1863 static int wx_alloc_q_vectors(struct wx *wx)
1865 unsigned int rxr_idx = 0, txr_idx = 0, v_idx = 0;
1866 unsigned int rxr_remaining = wx->num_rx_queues;
1867 unsigned int txr_remaining = wx->num_tx_queues;
1868 unsigned int q_vectors = wx->num_q_vectors;
1872 for (; v_idx < q_vectors; v_idx++) {
1873 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx);
1874 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx);
1875 err = wx_alloc_q_vector(wx, q_vectors, v_idx,
1882 /* update counts and index */
1883 rxr_remaining -= rqpv;
1884 txr_remaining -= tqpv;
1892 wx->num_tx_queues = 0;
1893 wx->num_rx_queues = 0;
1894 wx->num_q_vectors = 0;
1897 wx_free_q_vector(wx, v_idx);
1903 * wx_free_q_vectors - Free memory allocated for interrupt vectors
1904 * @wx: board private structure to initialize
1906 * This function frees the memory allocated to the q_vectors. In addition if
1907 * NAPI is enabled it will delete any references to the NAPI struct prior
1908 * to freeing the q_vector.
1910 static void wx_free_q_vectors(struct wx *wx)
1912 int v_idx = wx->num_q_vectors;
1914 wx->num_tx_queues = 0;
1915 wx->num_rx_queues = 0;
1916 wx->num_q_vectors = 0;
1919 wx_free_q_vector(wx, v_idx);
1922 void wx_reset_interrupt_capability(struct wx *wx)
1924 struct pci_dev *pdev = wx->pdev;
1926 if (!pdev->msi_enabled && !pdev->msix_enabled)
1929 if (pdev->msix_enabled) {
1930 kfree(wx->msix_q_entries);
1931 wx->msix_q_entries = NULL;
1932 kfree(wx->msix_entry);
1933 wx->msix_entry = NULL;
1935 pci_free_irq_vectors(wx->pdev);
1937 EXPORT_SYMBOL(wx_reset_interrupt_capability);
1940 * wx_clear_interrupt_scheme - Clear the current interrupt scheme settings
1941 * @wx: board private structure to clear interrupt scheme on
1943 * We go through and clear interrupt specific resources and reset the structure
1944 * to pre-load conditions
1946 void wx_clear_interrupt_scheme(struct wx *wx)
1948 wx_free_q_vectors(wx);
1949 wx_reset_interrupt_capability(wx);
1951 EXPORT_SYMBOL(wx_clear_interrupt_scheme);
1953 int wx_init_interrupt_scheme(struct wx *wx)
1957 /* Number of supported queues */
1958 wx_set_num_queues(wx);
1960 /* Set interrupt mode */
1961 ret = wx_set_interrupt_capability(wx);
1963 wx_err(wx, "Allocate irq vectors for failed.\n");
1967 /* Allocate memory for queues */
1968 ret = wx_alloc_q_vectors(wx);
1970 wx_err(wx, "Unable to allocate memory for queue vectors.\n");
1971 wx_reset_interrupt_capability(wx);
1975 wx_cache_ring_rss(wx);
1979 EXPORT_SYMBOL(wx_init_interrupt_scheme);
1981 irqreturn_t wx_msix_clean_rings(int __always_unused irq, void *data)
1983 struct wx_q_vector *q_vector = data;
1985 /* EIAM disabled interrupts (on this vector) for us */
1986 if (q_vector->rx.ring || q_vector->tx.ring)
1987 napi_schedule_irqoff(&q_vector->napi);
1991 EXPORT_SYMBOL(wx_msix_clean_rings);
1993 void wx_free_irq(struct wx *wx)
1995 struct pci_dev *pdev = wx->pdev;
1998 if (!(pdev->msix_enabled)) {
1999 free_irq(pdev->irq, wx);
2003 for (vector = 0; vector < wx->num_q_vectors; vector++) {
2004 struct wx_q_vector *q_vector = wx->q_vector[vector];
2005 struct msix_entry *entry = &wx->msix_q_entries[vector];
2007 /* free only the irqs that were actually requested */
2008 if (!q_vector->rx.ring && !q_vector->tx.ring)
2011 free_irq(entry->vector, q_vector);
2014 if (wx->mac.type == wx_mac_em)
2015 free_irq(wx->msix_entry->vector, wx);
2017 EXPORT_SYMBOL(wx_free_irq);
2020 * wx_setup_isb_resources - allocate interrupt status resources
2021 * @wx: board private structure
2023 * Return 0 on success, negative on failure
2025 int wx_setup_isb_resources(struct wx *wx)
2027 struct pci_dev *pdev = wx->pdev;
2029 wx->isb_mem = dma_alloc_coherent(&pdev->dev,
2034 wx_err(wx, "Alloc isb_mem failed\n");
2040 EXPORT_SYMBOL(wx_setup_isb_resources);
2043 * wx_free_isb_resources - allocate all queues Rx resources
2044 * @wx: board private structure
2046 * Return 0 on success, negative on failure
2048 void wx_free_isb_resources(struct wx *wx)
2050 struct pci_dev *pdev = wx->pdev;
2052 dma_free_coherent(&pdev->dev, sizeof(u32) * 4,
2053 wx->isb_mem, wx->isb_dma);
2056 EXPORT_SYMBOL(wx_free_isb_resources);
2058 u32 wx_misc_isb(struct wx *wx, enum wx_isb_idx idx)
2062 cur_tag = wx->isb_mem[WX_ISB_HEADER];
2063 wx->isb_tag[idx] = cur_tag;
2065 return (__force u32)cpu_to_le32(wx->isb_mem[idx]);
2067 EXPORT_SYMBOL(wx_misc_isb);
2070 * wx_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
2071 * @wx: pointer to wx struct
2072 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
2073 * @queue: queue to map the corresponding interrupt to
2074 * @msix_vector: the vector to map to the corresponding queue
2077 static void wx_set_ivar(struct wx *wx, s8 direction,
2078 u16 queue, u16 msix_vector)
2082 if (direction == -1) {
2084 msix_vector |= WX_PX_IVAR_ALLOC_VAL;
2086 ivar = rd32(wx, WX_PX_MISC_IVAR);
2087 ivar &= ~(0xFF << index);
2088 ivar |= (msix_vector << index);
2089 wr32(wx, WX_PX_MISC_IVAR, ivar);
2091 /* tx or rx causes */
2092 msix_vector += 1; /* offset for queue vectors */
2093 msix_vector |= WX_PX_IVAR_ALLOC_VAL;
2094 index = ((16 * (queue & 1)) + (8 * direction));
2095 ivar = rd32(wx, WX_PX_IVAR(queue >> 1));
2096 ivar &= ~(0xFF << index);
2097 ivar |= (msix_vector << index);
2098 wr32(wx, WX_PX_IVAR(queue >> 1), ivar);
2103 * wx_write_eitr - write EITR register in hardware specific way
2104 * @q_vector: structure containing interrupt and ring information
2106 * This function is made to be called by ethtool and by the driver
2107 * when it needs to update EITR registers at runtime. Hardware
2108 * specific quirks/differences are taken care of here.
2110 void wx_write_eitr(struct wx_q_vector *q_vector)
2112 struct wx *wx = q_vector->wx;
2113 int v_idx = q_vector->v_idx;
2116 if (wx->mac.type == wx_mac_sp)
2117 itr_reg = q_vector->itr & WX_SP_MAX_EITR;
2119 itr_reg = q_vector->itr & WX_EM_MAX_EITR;
2121 itr_reg |= WX_PX_ITR_CNT_WDIS;
2123 wr32(wx, WX_PX_ITR(v_idx + 1), itr_reg);
2127 * wx_configure_vectors - Configure vectors for hardware
2128 * @wx: board private structure
2130 * wx_configure_vectors sets up the hardware to properly generate MSI-X/MSI/LEGACY
2133 void wx_configure_vectors(struct wx *wx)
2135 struct pci_dev *pdev = wx->pdev;
2139 if (pdev->msix_enabled) {
2140 /* Populate MSIX to EITR Select */
2141 wr32(wx, WX_PX_ITRSEL, eitrsel);
2142 /* use EIAM to auto-mask when MSI-X interrupt is asserted
2143 * this saves a register write for every interrupt
2145 wr32(wx, WX_PX_GPIE, WX_PX_GPIE_MODEL);
2147 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2148 * specifically only auto mask tx and rx interrupts.
2150 wr32(wx, WX_PX_GPIE, 0);
2153 /* Populate the IVAR table and set the ITR values to the
2154 * corresponding register.
2156 for (v_idx = 0; v_idx < wx->num_q_vectors; v_idx++) {
2157 struct wx_q_vector *q_vector = wx->q_vector[v_idx];
2158 struct wx_ring *ring;
2160 wx_for_each_ring(ring, q_vector->rx)
2161 wx_set_ivar(wx, 0, ring->reg_idx, v_idx);
2163 wx_for_each_ring(ring, q_vector->tx)
2164 wx_set_ivar(wx, 1, ring->reg_idx, v_idx);
2166 wx_write_eitr(q_vector);
2169 wx_set_ivar(wx, -1, 0, 0);
2170 if (pdev->msix_enabled)
2171 wr32(wx, WX_PX_ITR(0), 1950);
2173 EXPORT_SYMBOL(wx_configure_vectors);
2176 * wx_clean_rx_ring - Free Rx Buffers per Queue
2177 * @rx_ring: ring to free buffers from
2179 static void wx_clean_rx_ring(struct wx_ring *rx_ring)
2181 struct wx_rx_buffer *rx_buffer;
2182 u16 i = rx_ring->next_to_clean;
2184 rx_buffer = &rx_ring->rx_buffer_info[i];
2186 /* Free all the Rx ring sk_buffs */
2187 while (i != rx_ring->next_to_alloc) {
2188 if (rx_buffer->skb) {
2189 struct sk_buff *skb = rx_buffer->skb;
2191 if (WX_CB(skb)->page_released)
2192 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
2197 /* Invalidate cache lines that may have been written to by
2198 * device so that we avoid corrupting memory.
2200 dma_sync_single_range_for_cpu(rx_ring->dev,
2202 rx_buffer->page_offset,
2206 /* free resources associated with mapping */
2207 page_pool_put_full_page(rx_ring->page_pool, rx_buffer->page, false);
2211 if (i == rx_ring->count) {
2213 rx_buffer = rx_ring->rx_buffer_info;
2217 rx_ring->next_to_alloc = 0;
2218 rx_ring->next_to_clean = 0;
2219 rx_ring->next_to_use = 0;
2223 * wx_clean_all_rx_rings - Free Rx Buffers for all queues
2224 * @wx: board private structure
2226 void wx_clean_all_rx_rings(struct wx *wx)
2230 for (i = 0; i < wx->num_rx_queues; i++)
2231 wx_clean_rx_ring(wx->rx_ring[i]);
2233 EXPORT_SYMBOL(wx_clean_all_rx_rings);
2236 * wx_free_rx_resources - Free Rx Resources
2237 * @rx_ring: ring to clean the resources from
2239 * Free all receive software resources
2241 static void wx_free_rx_resources(struct wx_ring *rx_ring)
2243 wx_clean_rx_ring(rx_ring);
2244 kvfree(rx_ring->rx_buffer_info);
2245 rx_ring->rx_buffer_info = NULL;
2247 /* if not set, then don't free */
2251 dma_free_coherent(rx_ring->dev, rx_ring->size,
2252 rx_ring->desc, rx_ring->dma);
2254 rx_ring->desc = NULL;
2256 if (rx_ring->page_pool) {
2257 page_pool_destroy(rx_ring->page_pool);
2258 rx_ring->page_pool = NULL;
2263 * wx_free_all_rx_resources - Free Rx Resources for All Queues
2264 * @wx: pointer to hardware structure
2266 * Free all receive software resources
2268 static void wx_free_all_rx_resources(struct wx *wx)
2272 for (i = 0; i < wx->num_rx_queues; i++)
2273 wx_free_rx_resources(wx->rx_ring[i]);
2277 * wx_clean_tx_ring - Free Tx Buffers
2278 * @tx_ring: ring to be cleaned
2280 static void wx_clean_tx_ring(struct wx_ring *tx_ring)
2282 struct wx_tx_buffer *tx_buffer;
2283 u16 i = tx_ring->next_to_clean;
2285 tx_buffer = &tx_ring->tx_buffer_info[i];
2287 while (i != tx_ring->next_to_use) {
2288 union wx_tx_desc *eop_desc, *tx_desc;
2290 /* Free all the Tx ring sk_buffs */
2291 dev_kfree_skb_any(tx_buffer->skb);
2293 /* unmap skb header data */
2294 dma_unmap_single(tx_ring->dev,
2295 dma_unmap_addr(tx_buffer, dma),
2296 dma_unmap_len(tx_buffer, len),
2299 /* check for eop_desc to determine the end of the packet */
2300 eop_desc = tx_buffer->next_to_watch;
2301 tx_desc = WX_TX_DESC(tx_ring, i);
2303 /* unmap remaining buffers */
2304 while (tx_desc != eop_desc) {
2308 if (unlikely(i == tx_ring->count)) {
2310 tx_buffer = tx_ring->tx_buffer_info;
2311 tx_desc = WX_TX_DESC(tx_ring, 0);
2314 /* unmap any remaining paged data */
2315 if (dma_unmap_len(tx_buffer, len))
2316 dma_unmap_page(tx_ring->dev,
2317 dma_unmap_addr(tx_buffer, dma),
2318 dma_unmap_len(tx_buffer, len),
2322 /* move us one more past the eop_desc for start of next pkt */
2325 if (unlikely(i == tx_ring->count)) {
2327 tx_buffer = tx_ring->tx_buffer_info;
2331 netdev_tx_reset_queue(wx_txring_txq(tx_ring));
2333 /* reset next_to_use and next_to_clean */
2334 tx_ring->next_to_use = 0;
2335 tx_ring->next_to_clean = 0;
2339 * wx_clean_all_tx_rings - Free Tx Buffers for all queues
2340 * @wx: board private structure
2342 void wx_clean_all_tx_rings(struct wx *wx)
2346 for (i = 0; i < wx->num_tx_queues; i++)
2347 wx_clean_tx_ring(wx->tx_ring[i]);
2349 EXPORT_SYMBOL(wx_clean_all_tx_rings);
2352 * wx_free_tx_resources - Free Tx Resources per Queue
2353 * @tx_ring: Tx descriptor ring for a specific queue
2355 * Free all transmit software resources
2357 static void wx_free_tx_resources(struct wx_ring *tx_ring)
2359 wx_clean_tx_ring(tx_ring);
2360 kvfree(tx_ring->tx_buffer_info);
2361 tx_ring->tx_buffer_info = NULL;
2363 /* if not set, then don't free */
2367 dma_free_coherent(tx_ring->dev, tx_ring->size,
2368 tx_ring->desc, tx_ring->dma);
2369 tx_ring->desc = NULL;
2373 * wx_free_all_tx_resources - Free Tx Resources for All Queues
2374 * @wx: pointer to hardware structure
2376 * Free all transmit software resources
2378 static void wx_free_all_tx_resources(struct wx *wx)
2382 for (i = 0; i < wx->num_tx_queues; i++)
2383 wx_free_tx_resources(wx->tx_ring[i]);
2386 void wx_free_resources(struct wx *wx)
2388 wx_free_isb_resources(wx);
2389 wx_free_all_rx_resources(wx);
2390 wx_free_all_tx_resources(wx);
2392 EXPORT_SYMBOL(wx_free_resources);
2394 static int wx_alloc_page_pool(struct wx_ring *rx_ring)
2398 struct page_pool_params pp_params = {
2399 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV,
2401 .pool_size = rx_ring->size,
2402 .nid = dev_to_node(rx_ring->dev),
2403 .dev = rx_ring->dev,
2404 .dma_dir = DMA_FROM_DEVICE,
2406 .max_len = PAGE_SIZE,
2409 rx_ring->page_pool = page_pool_create(&pp_params);
2410 if (IS_ERR(rx_ring->page_pool)) {
2411 ret = PTR_ERR(rx_ring->page_pool);
2412 rx_ring->page_pool = NULL;
2419 * wx_setup_rx_resources - allocate Rx resources (Descriptors)
2420 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2422 * Returns 0 on success, negative on failure
2424 static int wx_setup_rx_resources(struct wx_ring *rx_ring)
2426 struct device *dev = rx_ring->dev;
2427 int orig_node = dev_to_node(dev);
2428 int numa_node = NUMA_NO_NODE;
2431 size = sizeof(struct wx_rx_buffer) * rx_ring->count;
2433 if (rx_ring->q_vector)
2434 numa_node = rx_ring->q_vector->numa_node;
2436 rx_ring->rx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node);
2437 if (!rx_ring->rx_buffer_info)
2438 rx_ring->rx_buffer_info = kvmalloc(size, GFP_KERNEL);
2439 if (!rx_ring->rx_buffer_info)
2442 /* Round up to nearest 4K */
2443 rx_ring->size = rx_ring->count * sizeof(union wx_rx_desc);
2444 rx_ring->size = ALIGN(rx_ring->size, 4096);
2446 set_dev_node(dev, numa_node);
2447 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2448 &rx_ring->dma, GFP_KERNEL);
2449 if (!rx_ring->desc) {
2450 set_dev_node(dev, orig_node);
2451 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
2452 &rx_ring->dma, GFP_KERNEL);
2458 rx_ring->next_to_clean = 0;
2459 rx_ring->next_to_use = 0;
2461 ret = wx_alloc_page_pool(rx_ring);
2463 dev_err(rx_ring->dev, "Page pool creation failed: %d\n", ret);
2470 dma_free_coherent(dev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2472 kvfree(rx_ring->rx_buffer_info);
2473 rx_ring->rx_buffer_info = NULL;
2474 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
2479 * wx_setup_all_rx_resources - allocate all queues Rx resources
2480 * @wx: pointer to hardware structure
2482 * If this function returns with an error, then it's possible one or
2483 * more of the rings is populated (while the rest are not). It is the
2484 * callers duty to clean those orphaned rings.
2486 * Return 0 on success, negative on failure
2488 static int wx_setup_all_rx_resources(struct wx *wx)
2492 for (i = 0; i < wx->num_rx_queues; i++) {
2493 err = wx_setup_rx_resources(wx->rx_ring[i]);
2497 wx_err(wx, "Allocation for Rx Queue %u failed\n", i);
2503 /* rewind the index freeing the rings as we go */
2505 wx_free_rx_resources(wx->rx_ring[i]);
2510 * wx_setup_tx_resources - allocate Tx resources (Descriptors)
2511 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2513 * Return 0 on success, negative on failure
2515 static int wx_setup_tx_resources(struct wx_ring *tx_ring)
2517 struct device *dev = tx_ring->dev;
2518 int orig_node = dev_to_node(dev);
2519 int numa_node = NUMA_NO_NODE;
2522 size = sizeof(struct wx_tx_buffer) * tx_ring->count;
2524 if (tx_ring->q_vector)
2525 numa_node = tx_ring->q_vector->numa_node;
2527 tx_ring->tx_buffer_info = kvmalloc_node(size, GFP_KERNEL, numa_node);
2528 if (!tx_ring->tx_buffer_info)
2529 tx_ring->tx_buffer_info = kvmalloc(size, GFP_KERNEL);
2530 if (!tx_ring->tx_buffer_info)
2533 /* round up to nearest 4K */
2534 tx_ring->size = tx_ring->count * sizeof(union wx_tx_desc);
2535 tx_ring->size = ALIGN(tx_ring->size, 4096);
2537 set_dev_node(dev, numa_node);
2538 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2539 &tx_ring->dma, GFP_KERNEL);
2540 if (!tx_ring->desc) {
2541 set_dev_node(dev, orig_node);
2542 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
2543 &tx_ring->dma, GFP_KERNEL);
2549 tx_ring->next_to_use = 0;
2550 tx_ring->next_to_clean = 0;
2555 kvfree(tx_ring->tx_buffer_info);
2556 tx_ring->tx_buffer_info = NULL;
2557 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
2562 * wx_setup_all_tx_resources - allocate all queues Tx resources
2563 * @wx: pointer to private structure
2565 * If this function returns with an error, then it's possible one or
2566 * more of the rings is populated (while the rest are not). It is the
2567 * callers duty to clean those orphaned rings.
2569 * Return 0 on success, negative on failure
2571 static int wx_setup_all_tx_resources(struct wx *wx)
2575 for (i = 0; i < wx->num_tx_queues; i++) {
2576 err = wx_setup_tx_resources(wx->tx_ring[i]);
2580 wx_err(wx, "Allocation for Tx Queue %u failed\n", i);
2586 /* rewind the index freeing the rings as we go */
2588 wx_free_tx_resources(wx->tx_ring[i]);
2592 int wx_setup_resources(struct wx *wx)
2596 /* allocate transmit descriptors */
2597 err = wx_setup_all_tx_resources(wx);
2601 /* allocate receive descriptors */
2602 err = wx_setup_all_rx_resources(wx);
2606 err = wx_setup_isb_resources(wx);
2613 wx_free_all_rx_resources(wx);
2615 wx_free_all_tx_resources(wx);
2619 EXPORT_SYMBOL(wx_setup_resources);
2622 * wx_get_stats64 - Get System Network Statistics
2623 * @netdev: network interface device structure
2624 * @stats: storage space for 64bit statistics
2626 void wx_get_stats64(struct net_device *netdev,
2627 struct rtnl_link_stats64 *stats)
2629 struct wx *wx = netdev_priv(netdev);
2630 struct wx_hw_stats *hwstats;
2633 wx_update_stats(wx);
2636 for (i = 0; i < wx->num_rx_queues; i++) {
2637 struct wx_ring *ring = READ_ONCE(wx->rx_ring[i]);
2643 start = u64_stats_fetch_begin(&ring->syncp);
2644 packets = ring->stats.packets;
2645 bytes = ring->stats.bytes;
2646 } while (u64_stats_fetch_retry(&ring->syncp, start));
2647 stats->rx_packets += packets;
2648 stats->rx_bytes += bytes;
2652 for (i = 0; i < wx->num_tx_queues; i++) {
2653 struct wx_ring *ring = READ_ONCE(wx->tx_ring[i]);
2659 start = u64_stats_fetch_begin(&ring->syncp);
2660 packets = ring->stats.packets;
2661 bytes = ring->stats.bytes;
2662 } while (u64_stats_fetch_retry(&ring->syncp,
2664 stats->tx_packets += packets;
2665 stats->tx_bytes += bytes;
2671 hwstats = &wx->stats;
2672 stats->rx_errors = hwstats->crcerrs + hwstats->rlec;
2673 stats->multicast = hwstats->qmprc;
2674 stats->rx_length_errors = hwstats->rlec;
2675 stats->rx_crc_errors = hwstats->crcerrs;
2677 EXPORT_SYMBOL(wx_get_stats64);
2679 int wx_set_features(struct net_device *netdev, netdev_features_t features)
2681 netdev_features_t changed = netdev->features ^ features;
2682 struct wx *wx = netdev_priv(netdev);
2684 if (features & NETIF_F_RXHASH) {
2685 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN,
2686 WX_RDB_RA_CTL_RSS_EN);
2687 wx->rss_enabled = true;
2689 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 0);
2690 wx->rss_enabled = false;
2694 (NETIF_F_HW_VLAN_CTAG_RX |
2695 NETIF_F_HW_VLAN_STAG_RX))
2696 wx_set_rx_mode(netdev);
2700 EXPORT_SYMBOL(wx_set_features);
2702 void wx_set_ring(struct wx *wx, u32 new_tx_count,
2703 u32 new_rx_count, struct wx_ring *temp_ring)
2707 /* Setup new Tx resources and free the old Tx resources in that order.
2708 * We can then assign the new resources to the rings via a memcpy.
2709 * The advantage to this approach is that we are guaranteed to still
2710 * have resources even in the case of an allocation failure.
2712 if (new_tx_count != wx->tx_ring_count) {
2713 for (i = 0; i < wx->num_tx_queues; i++) {
2714 memcpy(&temp_ring[i], wx->tx_ring[i],
2715 sizeof(struct wx_ring));
2717 temp_ring[i].count = new_tx_count;
2718 err = wx_setup_tx_resources(&temp_ring[i]);
2720 wx_err(wx, "setup new tx resources failed, keep using the old config\n");
2723 wx_free_tx_resources(&temp_ring[i]);
2729 for (i = 0; i < wx->num_tx_queues; i++) {
2730 wx_free_tx_resources(wx->tx_ring[i]);
2732 memcpy(wx->tx_ring[i], &temp_ring[i],
2733 sizeof(struct wx_ring));
2736 wx->tx_ring_count = new_tx_count;
2739 /* Repeat the process for the Rx rings if needed */
2740 if (new_rx_count != wx->rx_ring_count) {
2741 for (i = 0; i < wx->num_rx_queues; i++) {
2742 memcpy(&temp_ring[i], wx->rx_ring[i],
2743 sizeof(struct wx_ring));
2745 temp_ring[i].count = new_rx_count;
2746 err = wx_setup_rx_resources(&temp_ring[i]);
2748 wx_err(wx, "setup new rx resources failed, keep using the old config\n");
2751 wx_free_rx_resources(&temp_ring[i]);
2757 for (i = 0; i < wx->num_rx_queues; i++) {
2758 wx_free_rx_resources(wx->rx_ring[i]);
2759 memcpy(wx->rx_ring[i], &temp_ring[i],
2760 sizeof(struct wx_ring));
2763 wx->rx_ring_count = new_rx_count;
2766 EXPORT_SYMBOL(wx_set_ring);
2768 MODULE_DESCRIPTION("Common library for Wangxun(R) Ethernet drivers.");
2769 MODULE_LICENSE("GPL");