2 * DaVinci Ethernet Medium Access Controller
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 * Copyright (C) 2009 Texas Instruments.
8 * ---------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/spinlock.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/clk.h>
54 #include <linux/platform_device.h>
55 #include <linux/semaphore.h>
56 #include <linux/phy.h>
57 #include <linux/bitops.h>
59 #include <linux/uaccess.h>
60 #include <linux/pm_runtime.h>
61 #include <linux/davinci_emac.h>
63 #include <linux/of_address.h>
64 #include <linux/of_device.h>
65 #include <linux/of_irq.h>
66 #include <linux/of_net.h>
71 #include "davinci_cpdma.h"
73 static int debug_level;
74 module_param(debug_level, int, 0);
75 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
77 /* Netif debug messages possible */
78 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
86 NETIF_MSG_TX_QUEUED | \
89 NETIF_MSG_RX_STATUS | \
95 #define EMAC_MAJOR_VERSION 6
96 #define EMAC_MINOR_VERSION 1
97 #define EMAC_MODULE_VERSION "6.1"
98 MODULE_VERSION(EMAC_MODULE_VERSION);
99 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
101 /* Configuration items */
102 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
103 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
104 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
105 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
106 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
107 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
108 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
109 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
110 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
111 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
112 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
113 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
115 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
116 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
118 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
119 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
120 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
121 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
122 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
123 #define EMAC_DEF_RX_NUM_DESC (128)
124 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
125 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
126 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
128 /* Buffer descriptor parameters */
129 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
130 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
132 /* EMAC register related defines */
133 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
134 #define EMAC_NUM_MULTICAST_BITS (64)
135 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
136 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
137 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
138 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
139 #define EMAC_INT_MASK_CLEAR (0xFF)
141 /* RX MBP register bit positions */
142 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
143 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
144 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
145 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
146 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
147 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
148 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
149 #define EMAC_RXMBP_PROMCH_SHIFT (16)
150 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
151 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
152 #define EMAC_RXMBP_BROADCH_SHIFT (8)
153 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
154 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
155 #define EMAC_RXMBP_MULTICH_SHIFT (0)
156 #define EMAC_RXMBP_MULTICH_MASK (0x7)
157 #define EMAC_RXMBP_CHMASK (0x7)
159 /* EMAC register definitions/bit maps used */
160 # define EMAC_MBP_RXPROMISC (0x00200000)
161 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
162 # define EMAC_MBP_RXBCAST (0x00002000)
163 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
164 # define EMAC_MBP_RXMCAST (0x00000020)
165 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
167 /* EMAC mac_control register */
168 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
169 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
170 #define EMAC_MACCONTROL_GMIIEN BIT(5)
171 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
172 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
173 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
175 /* GIGABIT MODE related bits */
176 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
177 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
179 /* EMAC mac_status register */
180 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
181 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
182 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
183 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
184 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
185 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
186 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
187 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
189 /* EMAC RX register masks */
190 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
191 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
193 /* MAC_IN_VECTOR (0x180) register bit fields */
194 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
195 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
196 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
197 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
199 /** NOTE:: For DM646x the IN_VECTOR has changed */
200 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
201 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
202 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
203 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
205 /* CPPI bit positions */
206 #define EMAC_CPPI_SOP_BIT BIT(31)
207 #define EMAC_CPPI_EOP_BIT BIT(30)
208 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
209 #define EMAC_CPPI_EOQ_BIT BIT(28)
210 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
211 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
212 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
213 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
214 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
216 /* Max hardware defines */
217 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
218 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
220 /* EMAC Peripheral Device Register Memory Layout structure */
221 #define EMAC_MACINVECTOR 0x90
223 #define EMAC_DM646X_MACEOIVECTOR 0x94
225 #define EMAC_MACINTSTATRAW 0xB0
226 #define EMAC_MACINTSTATMASKED 0xB4
227 #define EMAC_MACINTMASKSET 0xB8
228 #define EMAC_MACINTMASKCLEAR 0xBC
230 #define EMAC_RXMBPENABLE 0x100
231 #define EMAC_RXUNICASTSET 0x104
232 #define EMAC_RXUNICASTCLEAR 0x108
233 #define EMAC_RXMAXLEN 0x10C
234 #define EMAC_RXBUFFEROFFSET 0x110
235 #define EMAC_RXFILTERLOWTHRESH 0x114
237 #define EMAC_MACCONTROL 0x160
238 #define EMAC_MACSTATUS 0x164
239 #define EMAC_EMCONTROL 0x168
240 #define EMAC_FIFOCONTROL 0x16C
241 #define EMAC_MACCONFIG 0x170
242 #define EMAC_SOFTRESET 0x174
243 #define EMAC_MACSRCADDRLO 0x1D0
244 #define EMAC_MACSRCADDRHI 0x1D4
245 #define EMAC_MACHASH1 0x1D8
246 #define EMAC_MACHASH2 0x1DC
247 #define EMAC_MACADDRLO 0x500
248 #define EMAC_MACADDRHI 0x504
249 #define EMAC_MACINDEX 0x508
251 /* EMAC statistics registers */
252 #define EMAC_RXGOODFRAMES 0x200
253 #define EMAC_RXBCASTFRAMES 0x204
254 #define EMAC_RXMCASTFRAMES 0x208
255 #define EMAC_RXPAUSEFRAMES 0x20C
256 #define EMAC_RXCRCERRORS 0x210
257 #define EMAC_RXALIGNCODEERRORS 0x214
258 #define EMAC_RXOVERSIZED 0x218
259 #define EMAC_RXJABBER 0x21C
260 #define EMAC_RXUNDERSIZED 0x220
261 #define EMAC_RXFRAGMENTS 0x224
262 #define EMAC_RXFILTERED 0x228
263 #define EMAC_RXQOSFILTERED 0x22C
264 #define EMAC_RXOCTETS 0x230
265 #define EMAC_TXGOODFRAMES 0x234
266 #define EMAC_TXBCASTFRAMES 0x238
267 #define EMAC_TXMCASTFRAMES 0x23C
268 #define EMAC_TXPAUSEFRAMES 0x240
269 #define EMAC_TXDEFERRED 0x244
270 #define EMAC_TXCOLLISION 0x248
271 #define EMAC_TXSINGLECOLL 0x24C
272 #define EMAC_TXMULTICOLL 0x250
273 #define EMAC_TXEXCESSIVECOLL 0x254
274 #define EMAC_TXLATECOLL 0x258
275 #define EMAC_TXUNDERRUN 0x25C
276 #define EMAC_TXCARRIERSENSE 0x260
277 #define EMAC_TXOCTETS 0x264
278 #define EMAC_NETOCTETS 0x280
279 #define EMAC_RXSOFOVERRUNS 0x284
280 #define EMAC_RXMOFOVERRUNS 0x288
281 #define EMAC_RXDMAOVERRUNS 0x28C
283 /* EMAC DM644x control registers */
284 #define EMAC_CTRL_EWCTL (0x4)
285 #define EMAC_CTRL_EWINTTCNT (0x8)
287 /* EMAC DM644x control module masks */
288 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
289 #define EMAC_DM644X_INTMIN_INTVL 0x1
290 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
292 /* EMAC DM646X control module registers */
293 #define EMAC_DM646X_CMINTCTRL 0x0C
294 #define EMAC_DM646X_CMRXINTEN 0x14
295 #define EMAC_DM646X_CMTXINTEN 0x18
296 #define EMAC_DM646X_CMRXINTMAX 0x70
297 #define EMAC_DM646X_CMTXINTMAX 0x74
299 /* EMAC DM646X control module masks */
300 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
301 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
302 #define EMAC_DM646X_CMINTMAX_CNT 63
303 #define EMAC_DM646X_CMINTMIN_CNT 2
304 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
305 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
308 /* EMAC EOI codes for C0 */
309 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
310 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
312 /* EMAC Stats Clear Mask */
313 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
315 /* emac_priv: EMAC private data structure
317 * EMAC adapter private data structure
321 struct net_device *ndev;
322 struct platform_device *pdev;
323 struct napi_struct napi;
325 void __iomem *remap_addr;
327 void __iomem *emac_base;
328 void __iomem *ctrl_base;
329 struct cpdma_ctlr *dma;
330 struct cpdma_chan *txchan;
331 struct cpdma_chan *rxchan;
332 u32 link; /* 1=link on, 0=link off */
333 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
334 u32 duplex; /* Link duplex: 0=Half, 1=Full */
343 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
347 struct device_node *phy_node;
349 struct phy_device *phydev;
351 /*platform specific members*/
352 void (*int_enable) (void);
353 void (*int_disable) (void);
356 /* EMAC TX Host Error description strings */
357 static char *emac_txhost_errcodes[16] = {
358 "No error", "SOP error", "Ownership bit not set in SOP buffer",
359 "Zero Next Buffer Descriptor Pointer Without EOP",
360 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
361 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
362 "Reserved", "Reserved", "Reserved", "Reserved"
365 /* EMAC RX Host Error description strings */
366 static char *emac_rxhost_errcodes[16] = {
367 "No error", "Reserved", "Ownership bit not set in input buffer",
368 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
369 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
370 "Reserved", "Reserved", "Reserved", "Reserved"
374 #define emac_read(reg) ioread32(priv->emac_base + (reg))
375 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
377 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
378 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
381 * emac_dump_regs - Dump important EMAC registers to debug terminal
382 * @priv: The DaVinci EMAC private adapter structure
384 * Executes ethtool set cmd & sets phy mode
387 static void emac_dump_regs(struct emac_priv *priv)
389 struct device *emac_dev = &priv->ndev->dev;
391 /* Print important registers in EMAC */
392 dev_info(emac_dev, "EMAC Basic registers\n");
393 if (priv->version == EMAC_VERSION_1) {
394 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
395 emac_ctrl_read(EMAC_CTRL_EWCTL),
396 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
398 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
399 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
400 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
401 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
402 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
403 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
404 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
405 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
406 dev_info(emac_dev, "EMAC Statistics\n");
407 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
408 emac_read(EMAC_RXGOODFRAMES));
409 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
410 emac_read(EMAC_RXBCASTFRAMES));
411 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
412 emac_read(EMAC_RXMCASTFRAMES));
413 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
414 emac_read(EMAC_RXPAUSEFRAMES));
415 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
416 emac_read(EMAC_RXCRCERRORS));
417 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
418 emac_read(EMAC_RXALIGNCODEERRORS));
419 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
420 emac_read(EMAC_RXOVERSIZED));
421 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
422 emac_read(EMAC_RXJABBER));
423 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
424 emac_read(EMAC_RXUNDERSIZED));
425 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
426 emac_read(EMAC_RXFRAGMENTS));
427 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
428 emac_read(EMAC_RXFILTERED));
429 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
430 emac_read(EMAC_RXQOSFILTERED));
431 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
432 emac_read(EMAC_RXOCTETS));
433 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
434 emac_read(EMAC_TXGOODFRAMES));
435 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
436 emac_read(EMAC_TXBCASTFRAMES));
437 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
438 emac_read(EMAC_TXMCASTFRAMES));
439 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
440 emac_read(EMAC_TXPAUSEFRAMES));
441 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
442 emac_read(EMAC_TXDEFERRED));
443 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
444 emac_read(EMAC_TXCOLLISION));
445 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
446 emac_read(EMAC_TXSINGLECOLL));
447 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
448 emac_read(EMAC_TXMULTICOLL));
449 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
450 emac_read(EMAC_TXEXCESSIVECOLL));
451 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
452 emac_read(EMAC_TXLATECOLL));
453 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
454 emac_read(EMAC_TXUNDERRUN));
455 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
456 emac_read(EMAC_TXCARRIERSENSE));
457 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
458 emac_read(EMAC_TXOCTETS));
459 dev_info(emac_dev, "EMAC: net_octets:%d\n",
460 emac_read(EMAC_NETOCTETS));
461 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
462 emac_read(EMAC_RXSOFOVERRUNS));
463 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
464 emac_read(EMAC_RXMOFOVERRUNS));
465 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
466 emac_read(EMAC_RXDMAOVERRUNS));
468 cpdma_ctlr_dump(priv->dma);
472 * emac_get_drvinfo - Get EMAC driver information
473 * @ndev: The DaVinci EMAC network adapter
474 * @info: ethtool info structure containing name and version
476 * Returns EMAC driver information (name and version)
479 static void emac_get_drvinfo(struct net_device *ndev,
480 struct ethtool_drvinfo *info)
482 strlcpy(info->driver, emac_version_string, sizeof(info->driver));
483 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
487 * emac_get_settings - Get EMAC settings
488 * @ndev: The DaVinci EMAC network adapter
489 * @ecmd: ethtool command
491 * Executes ethool get command
494 static int emac_get_settings(struct net_device *ndev,
495 struct ethtool_cmd *ecmd)
497 struct emac_priv *priv = netdev_priv(ndev);
499 return phy_ethtool_gset(priv->phydev, ecmd);
506 * emac_set_settings - Set EMAC settings
507 * @ndev: The DaVinci EMAC network adapter
508 * @ecmd: ethtool command
510 * Executes ethool set command
513 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
515 struct emac_priv *priv = netdev_priv(ndev);
517 return phy_ethtool_sset(priv->phydev, ecmd);
524 * emac_get_coalesce - Get interrupt coalesce settings for this device
525 * @ndev : The DaVinci EMAC network adapter
526 * @coal : ethtool coalesce settings structure
528 * Fetch the current interrupt coalesce settings
531 static int emac_get_coalesce(struct net_device *ndev,
532 struct ethtool_coalesce *coal)
534 struct emac_priv *priv = netdev_priv(ndev);
536 coal->rx_coalesce_usecs = priv->coal_intvl;
542 * emac_set_coalesce - Set interrupt coalesce settings for this device
543 * @ndev : The DaVinci EMAC network adapter
544 * @coal : ethtool coalesce settings structure
546 * Set interrupt coalesce parameters
549 static int emac_set_coalesce(struct net_device *ndev,
550 struct ethtool_coalesce *coal)
552 struct emac_priv *priv = netdev_priv(ndev);
553 u32 int_ctrl, num_interrupts = 0;
554 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
556 if (!coal->rx_coalesce_usecs)
559 coal_intvl = coal->rx_coalesce_usecs;
561 switch (priv->version) {
563 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
564 prescale = priv->bus_freq_mhz * 4;
566 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
567 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
569 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
571 * Interrupt pacer works with 4us Pulse, we can
572 * throttle further by dilating the 4us pulse.
574 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
576 if (addnl_dvdr > 1) {
577 prescale *= addnl_dvdr;
578 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
580 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
584 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
588 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
590 int_ctrl |= EMAC_DM646X_INTPACEEN;
591 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
592 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
593 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
595 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
596 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
600 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
601 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
602 prescale = coal_intvl * priv->bus_freq_mhz;
603 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
604 prescale = EMAC_DM644X_EWINTCNT_MASK;
605 coal_intvl = prescale / priv->bus_freq_mhz;
607 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
612 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
613 priv->coal_intvl = coal_intvl;
620 /* ethtool_ops: DaVinci EMAC Ethtool structure
622 * Ethtool support for EMAC adapter
624 static const struct ethtool_ops ethtool_ops = {
625 .get_drvinfo = emac_get_drvinfo,
626 .get_settings = emac_get_settings,
627 .set_settings = emac_set_settings,
628 .get_link = ethtool_op_get_link,
629 .get_coalesce = emac_get_coalesce,
630 .set_coalesce = emac_set_coalesce,
631 .get_ts_info = ethtool_op_get_ts_info,
635 * emac_update_phystatus - Update Phy status
636 * @priv: The DaVinci EMAC private adapter structure
638 * Updates phy status and takes action for network queue if required
639 * based upon link status
642 static void emac_update_phystatus(struct emac_priv *priv)
647 struct net_device *ndev = priv->ndev;
649 mac_control = emac_read(EMAC_MACCONTROL);
650 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
651 DUPLEX_FULL : DUPLEX_HALF;
653 new_duplex = priv->phydev->duplex;
655 new_duplex = DUPLEX_FULL;
657 /* We get called only if link has changed (speed/duplex/status) */
658 if ((priv->link) && (new_duplex != cur_duplex)) {
659 priv->duplex = new_duplex;
660 if (DUPLEX_FULL == priv->duplex)
661 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
663 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
666 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
667 mac_control = emac_read(EMAC_MACCONTROL);
668 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
669 EMAC_DM646X_MACCONTORL_GIGFORCE);
671 /* Clear the GIG bit and GIGFORCE bit */
672 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
673 EMAC_DM646X_MACCONTORL_GIG);
675 if (priv->rmii_en && (priv->speed == SPEED_100))
676 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
678 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
681 /* Update mac_control if changed */
682 emac_write(EMAC_MACCONTROL, mac_control);
686 if (!netif_carrier_ok(ndev))
687 netif_carrier_on(ndev);
688 /* reactivate the transmit queue if it is stopped */
689 if (netif_running(ndev) && netif_queue_stopped(ndev))
690 netif_wake_queue(ndev);
693 if (netif_carrier_ok(ndev))
694 netif_carrier_off(ndev);
695 if (!netif_queue_stopped(ndev))
696 netif_stop_queue(ndev);
701 * hash_get - Calculate hash value from mac address
702 * @addr: mac address to delete from hash table
704 * Calculates hash value from mac address
707 static u32 hash_get(u8 *addr)
714 for (cnt = 0; cnt < 2; cnt++) {
716 hash ^= (tmpval >> 2) ^ (tmpval << 4);
718 hash ^= (tmpval >> 4) ^ (tmpval << 2);
720 hash ^= (tmpval >> 6) ^ (tmpval);
727 * hash_add - Hash function to add mac addr from hash table
728 * @priv: The DaVinci EMAC private adapter structure
729 * @mac_addr: mac address to delete from hash table
731 * Adds mac address to the internal hash table
734 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
736 struct device *emac_dev = &priv->ndev->dev;
739 u32 hash_value = hash_get(mac_addr);
741 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
742 if (netif_msg_drv(priv)) {
743 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
744 "Hash %08x, should not be greater than %08x",
745 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
750 /* set the hash bit only if not previously set */
751 if (priv->multicast_hash_cnt[hash_value] == 0) {
752 rc = 1; /* hash value changed */
753 if (hash_value < 32) {
754 hash_bit = BIT(hash_value);
755 priv->mac_hash1 |= hash_bit;
757 hash_bit = BIT((hash_value - 32));
758 priv->mac_hash2 |= hash_bit;
762 /* incr counter for num of mcast addr's mapped to "this" hash bit */
763 ++priv->multicast_hash_cnt[hash_value];
769 * hash_del - Hash function to delete mac addr from hash table
770 * @priv: The DaVinci EMAC private adapter structure
771 * @mac_addr: mac address to delete from hash table
773 * Removes mac address from the internal hash table
776 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
781 hash_value = hash_get(mac_addr);
782 if (priv->multicast_hash_cnt[hash_value] > 0) {
783 /* dec cntr for num of mcast addr's mapped to this hash bit */
784 --priv->multicast_hash_cnt[hash_value];
787 /* if counter still > 0, at least one multicast address refers
788 * to this hash bit. so return 0 */
789 if (priv->multicast_hash_cnt[hash_value] > 0)
792 if (hash_value < 32) {
793 hash_bit = BIT(hash_value);
794 priv->mac_hash1 &= ~hash_bit;
796 hash_bit = BIT((hash_value - 32));
797 priv->mac_hash2 &= ~hash_bit;
800 /* return 1 to indicate change in mac_hash registers reqd */
804 /* EMAC multicast operation */
805 #define EMAC_MULTICAST_ADD 0
806 #define EMAC_MULTICAST_DEL 1
807 #define EMAC_ALL_MULTI_SET 2
808 #define EMAC_ALL_MULTI_CLR 3
811 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
812 * @priv: The DaVinci EMAC private adapter structure
813 * @action: multicast operation to perform
814 * mac_addr: mac address to set
816 * Set multicast addresses in EMAC adapter - internal function
819 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
821 struct device *emac_dev = &priv->ndev->dev;
825 case EMAC_MULTICAST_ADD:
826 update = hash_add(priv, mac_addr);
828 case EMAC_MULTICAST_DEL:
829 update = hash_del(priv, mac_addr);
831 case EMAC_ALL_MULTI_SET:
833 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
834 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
836 case EMAC_ALL_MULTI_CLR:
840 memset(&(priv->multicast_hash_cnt[0]), 0,
841 sizeof(priv->multicast_hash_cnt[0]) *
842 EMAC_NUM_MULTICAST_BITS);
845 if (netif_msg_drv(priv))
846 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
847 ": bad operation %d", action);
851 /* write to the hardware only if the register status chances */
853 emac_write(EMAC_MACHASH1, priv->mac_hash1);
854 emac_write(EMAC_MACHASH2, priv->mac_hash2);
859 * emac_dev_mcast_set - Set multicast address in the EMAC adapter
860 * @ndev: The DaVinci EMAC network adapter
862 * Set multicast addresses in EMAC adapter
865 static void emac_dev_mcast_set(struct net_device *ndev)
868 struct emac_priv *priv = netdev_priv(ndev);
870 mbp_enable = emac_read(EMAC_RXMBPENABLE);
871 if (ndev->flags & IFF_PROMISC) {
872 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
873 mbp_enable |= (EMAC_MBP_RXPROMISC);
875 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
876 if ((ndev->flags & IFF_ALLMULTI) ||
877 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
878 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
879 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
880 } else if (!netdev_mc_empty(ndev)) {
881 struct netdev_hw_addr *ha;
883 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
884 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
885 /* program multicast address list into EMAC hardware */
886 netdev_for_each_mc_addr(ha, ndev) {
887 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
891 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
892 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
895 /* Set mbp config register */
896 emac_write(EMAC_RXMBPENABLE, mbp_enable);
899 /*************************************************************************
900 * EMAC Hardware manipulation
901 *************************************************************************/
904 * emac_int_disable - Disable EMAC module interrupt (from adapter)
905 * @priv: The DaVinci EMAC private adapter structure
907 * Disable EMAC interrupt on the adapter
910 static void emac_int_disable(struct emac_priv *priv)
912 if (priv->version == EMAC_VERSION_2) {
915 local_irq_save(flags);
917 /* Program C0_Int_En to zero to turn off
918 * interrupts to the CPU */
919 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
920 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
921 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
922 if (priv->int_disable)
925 local_irq_restore(flags);
928 /* Set DM644x control registers for interrupt control */
929 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
934 * emac_int_enable - Enable EMAC module interrupt (from adapter)
935 * @priv: The DaVinci EMAC private adapter structure
937 * Enable EMAC interrupt on the adapter
940 static void emac_int_enable(struct emac_priv *priv)
942 if (priv->version == EMAC_VERSION_2) {
943 if (priv->int_enable)
946 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
947 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
949 /* In addition to turning on interrupt Enable, we need
950 * ack by writing appropriate values to the EOI
953 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
955 /* ack rxen only then a new pulse will be generated */
956 emac_write(EMAC_DM646X_MACEOIVECTOR,
957 EMAC_DM646X_MAC_EOI_C0_RXEN);
959 /* ack txen- only then a new pulse will be generated */
960 emac_write(EMAC_DM646X_MACEOIVECTOR,
961 EMAC_DM646X_MAC_EOI_C0_TXEN);
964 /* Set DM644x control registers for interrupt control */
965 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
970 * emac_irq - EMAC interrupt handler
971 * @irq: interrupt number
972 * @dev_id: EMAC network adapter data structure ptr
974 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
975 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
977 * Returns interrupt handled condition
979 static irqreturn_t emac_irq(int irq, void *dev_id)
981 struct net_device *ndev = (struct net_device *)dev_id;
982 struct emac_priv *priv = netdev_priv(ndev);
985 if (likely(netif_running(priv->ndev))) {
986 emac_int_disable(priv);
987 napi_schedule(&priv->napi);
989 /* we are closing down, so dont process anything */
994 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
996 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
999 skb_reserve(skb, NET_IP_ALIGN);
1003 static void emac_rx_handler(void *token, int len, int status)
1005 struct sk_buff *skb = token;
1006 struct net_device *ndev = skb->dev;
1007 struct emac_priv *priv = netdev_priv(ndev);
1008 struct device *emac_dev = &ndev->dev;
1011 /* free and bail if we are shutting down */
1012 if (unlikely(!netif_running(ndev))) {
1013 dev_kfree_skb_any(skb);
1017 /* recycle on receive error */
1019 ndev->stats.rx_errors++;
1023 /* feed received packet up the stack */
1025 skb->protocol = eth_type_trans(skb, ndev);
1026 netif_receive_skb(skb);
1027 ndev->stats.rx_bytes += len;
1028 ndev->stats.rx_packets++;
1030 /* alloc a new packet for receive */
1031 skb = emac_rx_alloc(priv);
1033 if (netif_msg_rx_err(priv) && net_ratelimit())
1034 dev_err(emac_dev, "failed rx buffer alloc\n");
1039 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1040 skb_tailroom(skb), 0);
1042 WARN_ON(ret == -ENOMEM);
1043 if (unlikely(ret < 0))
1044 dev_kfree_skb_any(skb);
1047 static void emac_tx_handler(void *token, int len, int status)
1049 struct sk_buff *skb = token;
1050 struct net_device *ndev = skb->dev;
1052 /* Check whether the queue is stopped due to stalled tx dma, if the
1053 * queue is stopped then start the queue as we have free desc for tx
1055 if (unlikely(netif_queue_stopped(ndev)))
1056 netif_wake_queue(ndev);
1057 ndev->stats.tx_packets++;
1058 ndev->stats.tx_bytes += len;
1059 dev_kfree_skb_any(skb);
1063 * emac_dev_xmit - EMAC Transmit function
1065 * @ndev: The DaVinci EMAC network adapter
1067 * Called by the system to transmit a packet - we queue the packet in
1068 * EMAC hardware transmit queue
1070 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1072 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1074 struct device *emac_dev = &ndev->dev;
1076 struct emac_priv *priv = netdev_priv(ndev);
1078 /* If no link, return */
1079 if (unlikely(!priv->link)) {
1080 if (netif_msg_tx_err(priv) && net_ratelimit())
1081 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1085 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
1086 if (unlikely(ret_code < 0)) {
1087 if (netif_msg_tx_err(priv) && net_ratelimit())
1088 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
1092 skb_tx_timestamp(skb);
1094 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
1096 if (unlikely(ret_code != 0)) {
1097 if (netif_msg_tx_err(priv) && net_ratelimit())
1098 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
1102 /* If there is no more tx desc left free then we need to
1103 * tell the kernel to stop sending us tx frames.
1105 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan)))
1106 netif_stop_queue(ndev);
1108 return NETDEV_TX_OK;
1111 ndev->stats.tx_dropped++;
1112 netif_stop_queue(ndev);
1113 return NETDEV_TX_BUSY;
1117 * emac_dev_tx_timeout - EMAC Transmit timeout function
1118 * @ndev: The DaVinci EMAC network adapter
1120 * Called when system detects that a skb timeout period has expired
1121 * potentially due to a fault in the adapter in not being able to send
1122 * it out on the wire. We teardown the TX channel assuming a hardware
1123 * error and re-initialize the TX channel for hardware operation
1126 static void emac_dev_tx_timeout(struct net_device *ndev)
1128 struct emac_priv *priv = netdev_priv(ndev);
1129 struct device *emac_dev = &ndev->dev;
1131 if (netif_msg_tx_err(priv))
1132 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1134 emac_dump_regs(priv);
1136 ndev->stats.tx_errors++;
1137 emac_int_disable(priv);
1138 cpdma_chan_stop(priv->txchan);
1139 cpdma_chan_start(priv->txchan);
1140 emac_int_enable(priv);
1144 * emac_set_type0addr - Set EMAC Type0 mac address
1145 * @priv: The DaVinci EMAC private adapter structure
1146 * @ch: RX channel number
1147 * @mac_addr: MAC address to set in device
1149 * Called internally to set Type0 mac address of the adapter (Device)
1151 * Returns success (0) or appropriate error code (none as of now)
1153 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1156 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1157 emac_write(EMAC_MACSRCADDRLO, val);
1159 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1160 (mac_addr[1] << 8) | (mac_addr[0]));
1161 emac_write(EMAC_MACSRCADDRHI, val);
1162 val = emac_read(EMAC_RXUNICASTSET);
1164 emac_write(EMAC_RXUNICASTSET, val);
1165 val = emac_read(EMAC_RXUNICASTCLEAR);
1167 emac_write(EMAC_RXUNICASTCLEAR, val);
1171 * emac_set_type1addr - Set EMAC Type1 mac address
1172 * @priv: The DaVinci EMAC private adapter structure
1173 * @ch: RX channel number
1174 * @mac_addr: MAC address to set in device
1176 * Called internally to set Type1 mac address of the adapter (Device)
1178 * Returns success (0) or appropriate error code (none as of now)
1180 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1183 emac_write(EMAC_MACINDEX, ch);
1184 val = ((mac_addr[5] << 8) | mac_addr[4]);
1185 emac_write(EMAC_MACADDRLO, val);
1186 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1187 (mac_addr[1] << 8) | (mac_addr[0]));
1188 emac_write(EMAC_MACADDRHI, val);
1189 emac_set_type0addr(priv, ch, mac_addr);
1193 * emac_set_type2addr - Set EMAC Type2 mac address
1194 * @priv: The DaVinci EMAC private adapter structure
1195 * @ch: RX channel number
1196 * @mac_addr: MAC address to set in device
1197 * @index: index into RX address entries
1198 * @match: match parameter for RX address matching logic
1200 * Called internally to set Type2 mac address of the adapter (Device)
1202 * Returns success (0) or appropriate error code (none as of now)
1204 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1205 char *mac_addr, int index, int match)
1208 emac_write(EMAC_MACINDEX, index);
1209 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1210 (mac_addr[1] << 8) | (mac_addr[0]));
1211 emac_write(EMAC_MACADDRHI, val);
1212 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1213 (match << 19) | BIT(20));
1214 emac_write(EMAC_MACADDRLO, val);
1215 emac_set_type0addr(priv, ch, mac_addr);
1219 * emac_setmac - Set mac address in the adapter (internal function)
1220 * @priv: The DaVinci EMAC private adapter structure
1221 * @ch: RX channel number
1222 * @mac_addr: MAC address to set in device
1224 * Called internally to set the mac address of the adapter (Device)
1226 * Returns success (0) or appropriate error code (none as of now)
1228 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1230 struct device *emac_dev = &priv->ndev->dev;
1232 if (priv->rx_addr_type == 0) {
1233 emac_set_type0addr(priv, ch, mac_addr);
1234 } else if (priv->rx_addr_type == 1) {
1236 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1237 emac_set_type1addr(priv, ch, mac_addr);
1238 } else if (priv->rx_addr_type == 2) {
1239 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1240 emac_set_type0addr(priv, ch, mac_addr);
1242 if (netif_msg_drv(priv))
1243 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1248 * emac_dev_setmac_addr - Set mac address in the adapter
1249 * @ndev: The DaVinci EMAC network adapter
1250 * @addr: MAC address to set in device
1252 * Called by the system to set the mac address of the adapter (Device)
1254 * Returns success (0) or appropriate error code (none as of now)
1256 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1258 struct emac_priv *priv = netdev_priv(ndev);
1259 struct device *emac_dev = &priv->ndev->dev;
1260 struct sockaddr *sa = addr;
1262 if (!is_valid_ether_addr(sa->sa_data))
1263 return -EADDRNOTAVAIL;
1265 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1266 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1267 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1269 /* MAC address is configured only after the interface is enabled. */
1270 if (netif_running(ndev)) {
1271 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1274 if (netif_msg_drv(priv))
1275 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1282 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
1283 * @priv: The DaVinci EMAC private adapter structure
1285 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1286 * for packet reception and enables device interrupts and then NAPI
1288 * Returns success (0) or appropriate error code (none right now)
1290 static int emac_hw_enable(struct emac_priv *priv)
1292 u32 val, mbp_enable, mac_control;
1295 emac_write(EMAC_SOFTRESET, 1);
1296 while (emac_read(EMAC_SOFTRESET))
1299 /* Disable interrupt & Set pacing for more interrupts initially */
1300 emac_int_disable(priv);
1302 /* Full duplex enable bit set when auto negotiation happens */
1304 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1305 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1306 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1307 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1308 emac_write(EMAC_MACCONTROL, mac_control);
1311 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1312 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1313 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1314 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1315 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1316 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1317 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1318 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1319 EMAC_RXMBP_PROMCH_SHIFT) |
1320 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1321 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1322 EMAC_RXMBP_BROADCH_SHIFT) |
1323 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1324 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1325 EMAC_RXMBP_MULTICH_SHIFT));
1326 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1327 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1328 EMAC_RX_MAX_LEN_MASK));
1329 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1330 EMAC_RX_BUFFER_OFFSET_MASK));
1331 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1332 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1333 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1335 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1337 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1340 val = emac_read(EMAC_MACCONTROL);
1341 val |= (EMAC_MACCONTROL_GMIIEN);
1342 emac_write(EMAC_MACCONTROL, val);
1344 /* Enable NAPI and interrupts */
1345 napi_enable(&priv->napi);
1346 emac_int_enable(priv);
1352 * emac_poll - EMAC NAPI Poll function
1353 * @ndev: The DaVinci EMAC network adapter
1354 * @budget: Number of receive packets to process (as told by NAPI layer)
1356 * NAPI Poll function implemented to process packets as per budget. We check
1357 * the type of interrupt on the device and accordingly call the TX or RX
1358 * packet processing functions. We follow the budget for RX processing and
1359 * also put a cap on number of TX pkts processed through config param. The
1360 * NAPI schedule function is called if more packets pending.
1362 * Returns number of packets received (in most cases; else TX pkts - rarely)
1364 static int emac_poll(struct napi_struct *napi, int budget)
1367 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1368 struct net_device *ndev = priv->ndev;
1369 struct device *emac_dev = &ndev->dev;
1371 u32 num_tx_pkts = 0, num_rx_pkts = 0;
1373 /* Check interrupt vectors and call packet processing */
1374 status = emac_read(EMAC_MACINVECTOR);
1376 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1378 if (priv->version == EMAC_VERSION_2)
1379 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1381 if (status & mask) {
1382 num_tx_pkts = cpdma_chan_process(priv->txchan,
1383 EMAC_DEF_TX_MAX_SERVICE);
1384 } /* TX processing */
1386 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1388 if (priv->version == EMAC_VERSION_2)
1389 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1391 if (status & mask) {
1392 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1393 } /* RX processing */
1395 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1396 if (priv->version == EMAC_VERSION_2)
1397 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1399 if (unlikely(status & mask)) {
1401 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1402 netif_stop_queue(ndev);
1403 napi_disable(&priv->napi);
1405 status = emac_read(EMAC_MACSTATUS);
1406 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1407 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1409 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1410 EMAC_MACSTATUS_TXERRCH_SHIFT);
1411 if (net_ratelimit()) {
1412 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1413 &emac_txhost_errcodes[cause][0], ch);
1416 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1417 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1419 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1420 EMAC_MACSTATUS_RXERRCH_SHIFT);
1421 if (netif_msg_hw(priv) && net_ratelimit())
1422 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1423 &emac_rxhost_errcodes[cause][0], ch);
1425 } else if (num_rx_pkts < budget) {
1426 napi_complete(napi);
1427 emac_int_enable(priv);
1433 #ifdef CONFIG_NET_POLL_CONTROLLER
1435 * emac_poll_controller - EMAC Poll controller function
1436 * @ndev: The DaVinci EMAC network adapter
1438 * Polled functionality used by netconsole and others in non interrupt mode
1441 static void emac_poll_controller(struct net_device *ndev)
1443 struct emac_priv *priv = netdev_priv(ndev);
1445 emac_int_disable(priv);
1446 emac_irq(ndev->irq, ndev);
1447 emac_int_enable(priv);
1451 static void emac_adjust_link(struct net_device *ndev)
1453 struct emac_priv *priv = netdev_priv(ndev);
1454 struct phy_device *phydev = priv->phydev;
1455 unsigned long flags;
1458 spin_lock_irqsave(&priv->lock, flags);
1461 /* check the mode of operation - full/half duplex */
1462 if (phydev->duplex != priv->duplex) {
1464 priv->duplex = phydev->duplex;
1466 if (phydev->speed != priv->speed) {
1468 priv->speed = phydev->speed;
1475 } else if (priv->link) {
1482 emac_update_phystatus(priv);
1483 phy_print_status(priv->phydev);
1486 spin_unlock_irqrestore(&priv->lock, flags);
1489 /*************************************************************************
1490 * Linux Driver Model
1491 *************************************************************************/
1494 * emac_devioctl - EMAC adapter ioctl
1495 * @ndev: The DaVinci EMAC network adapter
1496 * @ifrq: request parameter
1497 * @cmd: command parameter
1499 * EMAC driver ioctl function
1501 * Returns success(0) or appropriate error code
1503 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1505 struct emac_priv *priv = netdev_priv(ndev);
1507 if (!(netif_running(ndev)))
1510 /* TODO: Add phy read and write and private statistics get feature */
1512 return phy_mii_ioctl(priv->phydev, ifrq, cmd);
1515 static int match_first_device(struct device *dev, void *data)
1517 return !strncmp(dev_name(dev), "davinci_mdio", 12);
1521 * emac_dev_open - EMAC device open
1522 * @ndev: The DaVinci EMAC network adapter
1524 * Called when system wants to start the interface. We init TX/RX channels
1525 * and enable the hardware for packet reception/transmission and start the
1528 * Returns 0 for a successful open, or appropriate error code
1530 static int emac_dev_open(struct net_device *ndev)
1532 struct device *emac_dev = &ndev->dev;
1534 struct resource *res;
1536 int res_num = 0, irq_num = 0;
1538 struct emac_priv *priv = netdev_priv(ndev);
1540 pm_runtime_get(&priv->pdev->dev);
1542 netif_carrier_off(ndev);
1543 for (cnt = 0; cnt < ETH_ALEN; cnt++)
1544 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1546 /* Configuration items */
1547 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1549 priv->mac_hash1 = 0;
1550 priv->mac_hash2 = 0;
1551 emac_write(EMAC_MACHASH1, 0);
1552 emac_write(EMAC_MACHASH2, 0);
1554 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1555 struct sk_buff *skb = emac_rx_alloc(priv);
1560 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1561 skb_tailroom(skb), 0);
1562 if (WARN_ON(ret < 0))
1567 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ,
1569 for (irq_num = res->start; irq_num <= res->end; irq_num++) {
1570 if (request_irq(irq_num, emac_irq, 0, ndev->name,
1573 "DaVinci EMAC: request_irq() failed\n");
1581 /* prepare counters for rollback in case of an error */
1585 /* Start/Enable EMAC hardware */
1586 emac_hw_enable(priv);
1588 /* Enable Interrupt pacing if configured */
1589 if (priv->coal_intvl != 0) {
1590 struct ethtool_coalesce coal;
1592 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1593 emac_set_coalesce(ndev, &coal);
1596 cpdma_ctlr_start(priv->dma);
1598 priv->phydev = NULL;
1599 /* use the first phy on the bus if pdata did not give us a phy id */
1600 if (!priv->phy_id) {
1603 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1604 match_first_device);
1606 priv->phy_id = dev_name(phy);
1609 if (priv->phy_id && *priv->phy_id) {
1610 priv->phydev = phy_connect(ndev, priv->phy_id,
1612 PHY_INTERFACE_MODE_MII);
1614 if (IS_ERR(priv->phydev)) {
1615 dev_err(emac_dev, "could not connect to phy %s\n",
1617 ret = PTR_ERR(priv->phydev);
1618 priv->phydev = NULL;
1626 dev_info(emac_dev, "attached PHY driver [%s] "
1627 "(mii_bus:phy_addr=%s, id=%x)\n",
1628 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
1629 priv->phydev->phy_id);
1631 /* No PHY , fix the link, speed and duplex settings */
1632 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1634 priv->speed = SPEED_100;
1635 priv->duplex = DUPLEX_FULL;
1636 emac_update_phystatus(priv);
1639 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
1640 emac_dump_regs(priv);
1642 if (netif_msg_drv(priv))
1643 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1646 phy_start(priv->phydev);
1651 emac_int_disable(priv);
1652 napi_disable(&priv->napi);
1655 for (q = res_num; q >= 0; q--) {
1656 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q);
1657 /* at the first iteration, irq_num is already set to the
1663 for (m = irq_num; m >= res->start; m--)
1666 cpdma_ctlr_stop(priv->dma);
1667 pm_runtime_put(&priv->pdev->dev);
1672 * emac_dev_stop - EMAC device stop
1673 * @ndev: The DaVinci EMAC network adapter
1675 * Called when system wants to stop or down the interface. We stop the network
1676 * queue, disable interrupts and cleanup TX/RX channels.
1678 * We return the statistics in net_device_stats structure pulled from emac
1680 static int emac_dev_stop(struct net_device *ndev)
1682 struct resource *res;
1685 struct emac_priv *priv = netdev_priv(ndev);
1686 struct device *emac_dev = &ndev->dev;
1688 /* inform the upper layers. */
1689 netif_stop_queue(ndev);
1690 napi_disable(&priv->napi);
1692 netif_carrier_off(ndev);
1693 emac_int_disable(priv);
1694 cpdma_ctlr_stop(priv->dma);
1695 emac_write(EMAC_SOFTRESET, 1);
1698 phy_disconnect(priv->phydev);
1701 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1702 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1703 free_irq(irq_num, priv->ndev);
1707 if (netif_msg_drv(priv))
1708 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1710 pm_runtime_put(&priv->pdev->dev);
1715 * emac_dev_getnetstats - EMAC get statistics function
1716 * @ndev: The DaVinci EMAC network adapter
1718 * Called when system wants to get statistics from the device.
1720 * We return the statistics in net_device_stats structure pulled from emac
1722 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1724 struct emac_priv *priv = netdev_priv(ndev);
1726 u32 stats_clear_mask;
1728 /* update emac hardware stats and reset the registers*/
1730 mac_control = emac_read(EMAC_MACCONTROL);
1732 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1733 stats_clear_mask = EMAC_STATS_CLR_MASK;
1735 stats_clear_mask = 0;
1737 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1738 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1740 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1741 emac_read(EMAC_TXSINGLECOLL) +
1742 emac_read(EMAC_TXMULTICOLL));
1743 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1744 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1745 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1747 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1748 emac_read(EMAC_RXJABBER) +
1749 emac_read(EMAC_RXUNDERSIZED));
1750 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1751 emac_write(EMAC_RXJABBER, stats_clear_mask);
1752 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1754 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1755 emac_read(EMAC_RXMOFOVERRUNS));
1756 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1757 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1759 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1760 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1762 ndev->stats.tx_carrier_errors +=
1763 emac_read(EMAC_TXCARRIERSENSE);
1764 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1766 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1767 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1769 return &ndev->stats;
1772 static const struct net_device_ops emac_netdev_ops = {
1773 .ndo_open = emac_dev_open,
1774 .ndo_stop = emac_dev_stop,
1775 .ndo_start_xmit = emac_dev_xmit,
1776 .ndo_set_rx_mode = emac_dev_mcast_set,
1777 .ndo_set_mac_address = emac_dev_setmac_addr,
1778 .ndo_do_ioctl = emac_devioctl,
1779 .ndo_tx_timeout = emac_dev_tx_timeout,
1780 .ndo_get_stats = emac_dev_getnetstats,
1781 #ifdef CONFIG_NET_POLL_CONTROLLER
1782 .ndo_poll_controller = emac_poll_controller,
1786 static const struct of_device_id davinci_emac_of_match[];
1788 static struct emac_platform_data *
1789 davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv)
1791 struct device_node *np;
1792 const struct of_device_id *match;
1793 const struct emac_platform_data *auxdata;
1794 struct emac_platform_data *pdata = NULL;
1797 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
1798 return dev_get_platdata(&pdev->dev);
1800 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1804 np = pdev->dev.of_node;
1805 pdata->version = EMAC_VERSION_2;
1807 if (!is_valid_ether_addr(pdata->mac_addr)) {
1808 mac_addr = of_get_mac_address(np);
1810 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
1813 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset",
1814 &pdata->ctrl_reg_offset);
1816 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
1817 &pdata->ctrl_mod_reg_offset);
1819 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset",
1820 &pdata->ctrl_ram_offset);
1822 of_property_read_u32(np, "ti,davinci-ctrl-ram-size",
1823 &pdata->ctrl_ram_size);
1825 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en);
1827 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram");
1829 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1830 if (!priv->phy_node)
1831 pdata->phy_id = NULL;
1833 auxdata = pdev->dev.platform_data;
1835 pdata->interrupt_enable = auxdata->interrupt_enable;
1836 pdata->interrupt_disable = auxdata->interrupt_disable;
1839 match = of_match_device(davinci_emac_of_match, &pdev->dev);
1840 if (match && match->data) {
1841 auxdata = match->data;
1842 pdata->version = auxdata->version;
1843 pdata->hw_ram_addr = auxdata->hw_ram_addr;
1846 pdev->dev.platform_data = pdata;
1852 * davinci_emac_probe - EMAC device probe
1853 * @pdev: The DaVinci EMAC device that we are removing
1855 * Called when probing for emac devicesr. We get details of instances and
1856 * resource information from platform init and register a network device
1857 * and allocate resources necessary for driver to perform
1859 static int davinci_emac_probe(struct platform_device *pdev)
1862 struct resource *res;
1863 struct net_device *ndev;
1864 struct emac_priv *priv;
1865 unsigned long hw_ram_addr;
1866 struct emac_platform_data *pdata;
1867 struct cpdma_params dma_params;
1868 struct clk *emac_clk;
1869 unsigned long emac_bus_frequency;
1872 /* obtain emac clock from kernel */
1873 emac_clk = devm_clk_get(&pdev->dev, NULL);
1874 if (IS_ERR(emac_clk)) {
1875 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1878 emac_bus_frequency = clk_get_rate(emac_clk);
1880 /* TODO: Probe PHY here if possible */
1882 ndev = alloc_etherdev(sizeof(struct emac_priv));
1886 platform_set_drvdata(pdev, ndev);
1887 priv = netdev_priv(ndev);
1890 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1892 spin_lock_init(&priv->lock);
1894 pdata = davinci_emac_of_get_pdata(pdev, priv);
1896 dev_err(&pdev->dev, "no platform data\n");
1901 /* MAC addr and PHY mask , RMII enable info from platform_data */
1902 memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN);
1903 priv->phy_id = pdata->phy_id;
1904 priv->rmii_en = pdata->rmii_en;
1905 priv->version = pdata->version;
1906 priv->int_enable = pdata->interrupt_enable;
1907 priv->int_disable = pdata->interrupt_disable;
1909 priv->coal_intvl = 0;
1910 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1912 /* Get EMAC platform data */
1913 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1914 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1915 priv->remap_addr = devm_ioremap_resource(&pdev->dev, res);
1916 if (IS_ERR(priv->remap_addr)) {
1917 rc = PTR_ERR(priv->remap_addr);
1920 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1921 ndev->base_addr = (unsigned long)priv->remap_addr;
1923 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1925 hw_ram_addr = pdata->hw_ram_addr;
1927 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1929 memset(&dma_params, 0, sizeof(dma_params));
1930 dma_params.dev = &pdev->dev;
1931 dma_params.dmaregs = priv->emac_base;
1932 dma_params.rxthresh = priv->emac_base + 0x120;
1933 dma_params.rxfree = priv->emac_base + 0x140;
1934 dma_params.txhdp = priv->emac_base + 0x600;
1935 dma_params.rxhdp = priv->emac_base + 0x620;
1936 dma_params.txcp = priv->emac_base + 0x640;
1937 dma_params.rxcp = priv->emac_base + 0x660;
1938 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1939 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1940 dma_params.desc_hw_addr = hw_ram_addr;
1941 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1942 dma_params.desc_align = 16;
1944 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1945 (u32 __force)res->start + pdata->ctrl_ram_offset;
1947 priv->dma = cpdma_ctlr_create(&dma_params);
1949 dev_err(&pdev->dev, "error initializing DMA\n");
1954 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
1956 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
1958 if (WARN_ON(!priv->txchan || !priv->rxchan)) {
1963 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1965 dev_err(&pdev->dev, "error getting irq res\n");
1969 ndev->irq = res->start;
1971 if (!is_valid_ether_addr(priv->mac_addr)) {
1972 /* Use random MAC if none passed */
1973 eth_hw_addr_random(ndev);
1974 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
1975 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1979 ndev->netdev_ops = &emac_netdev_ops;
1980 ndev->ethtool_ops = ðtool_ops;
1981 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
1983 /* register the network device */
1984 SET_NETDEV_DEV(ndev, &pdev->dev);
1985 rc = register_netdev(ndev);
1987 dev_err(&pdev->dev, "error in register_netdev\n");
1993 if (netif_msg_probe(priv)) {
1994 dev_notice(&pdev->dev, "DaVinci EMAC Probe found device "
1995 "(regs: %p, irq: %d)\n",
1996 (void *)priv->emac_base_phys, ndev->irq);
1999 pm_runtime_enable(&pdev->dev);
2000 pm_runtime_resume(&pdev->dev);
2006 cpdma_chan_destroy(priv->txchan);
2008 cpdma_chan_destroy(priv->rxchan);
2009 cpdma_ctlr_destroy(priv->dma);
2016 * davinci_emac_remove - EMAC device remove
2017 * @pdev: The DaVinci EMAC device that we are removing
2019 * Called when removing the device driver. We disable clock usage and release
2020 * the resources taken up by the driver and unregister network device
2022 static int davinci_emac_remove(struct platform_device *pdev)
2024 struct net_device *ndev = platform_get_drvdata(pdev);
2025 struct emac_priv *priv = netdev_priv(ndev);
2027 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2030 cpdma_chan_destroy(priv->txchan);
2032 cpdma_chan_destroy(priv->rxchan);
2033 cpdma_ctlr_destroy(priv->dma);
2035 unregister_netdev(ndev);
2041 static int davinci_emac_suspend(struct device *dev)
2043 struct platform_device *pdev = to_platform_device(dev);
2044 struct net_device *ndev = platform_get_drvdata(pdev);
2046 if (netif_running(ndev))
2047 emac_dev_stop(ndev);
2052 static int davinci_emac_resume(struct device *dev)
2054 struct platform_device *pdev = to_platform_device(dev);
2055 struct net_device *ndev = platform_get_drvdata(pdev);
2057 if (netif_running(ndev))
2058 emac_dev_open(ndev);
2063 static const struct dev_pm_ops davinci_emac_pm_ops = {
2064 .suspend = davinci_emac_suspend,
2065 .resume = davinci_emac_resume,
2068 #if IS_ENABLED(CONFIG_OF)
2069 static const struct emac_platform_data am3517_emac_data = {
2070 .version = EMAC_VERSION_2,
2071 .hw_ram_addr = 0x01e20000,
2074 static const struct of_device_id davinci_emac_of_match[] = {
2075 {.compatible = "ti,davinci-dm6467-emac", },
2076 {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, },
2079 MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2082 /* davinci_emac_driver: EMAC platform driver structure */
2083 static struct platform_driver davinci_emac_driver = {
2085 .name = "davinci_emac",
2086 .pm = &davinci_emac_pm_ops,
2087 .of_match_table = of_match_ptr(davinci_emac_of_match),
2089 .probe = davinci_emac_probe,
2090 .remove = davinci_emac_remove,
2094 * davinci_emac_init - EMAC driver module init
2096 * Called when initializing the driver. We register the driver with
2099 static int __init davinci_emac_init(void)
2101 return platform_driver_register(&davinci_emac_driver);
2103 late_initcall(davinci_emac_init);
2106 * davinci_emac_exit - EMAC driver module exit
2108 * Called when exiting the driver completely. We unregister the driver with
2109 * the platform and exit
2111 static void __exit davinci_emac_exit(void)
2113 platform_driver_unregister(&davinci_emac_driver);
2115 module_exit(davinci_emac_exit);
2117 MODULE_LICENSE("GPL");
2118 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2119 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2120 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");