2 * DaVinci Ethernet Medium Access Controller
4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine
6 * Copyright (C) 2009 Texas Instruments.
8 * ---------------------------------------------------------------------------
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * ---------------------------------------------------------------------------
25 * 0-5 A number of folks worked on this driver in bits and pieces but the major
26 * contribution came from Suraj Iyer and Anant Gole
27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions
28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features,
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/sched.h>
35 #include <linux/string.h>
36 #include <linux/timer.h>
37 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/init.h>
44 #include <linux/netdevice.h>
45 #include <linux/etherdevice.h>
46 #include <linux/skbuff.h>
47 #include <linux/ethtool.h>
48 #include <linux/highmem.h>
49 #include <linux/proc_fs.h>
50 #include <linux/ctype.h>
51 #include <linux/spinlock.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/clk.h>
54 #include <linux/platform_device.h>
55 #include <linux/semaphore.h>
56 #include <linux/phy.h>
57 #include <linux/bitops.h>
59 #include <linux/uaccess.h>
60 #include <linux/pm_runtime.h>
61 #include <linux/davinci_emac.h>
63 #include <linux/of_address.h>
64 #include <linux/of_irq.h>
65 #include <linux/of_net.h>
70 #include "davinci_cpdma.h"
72 static int debug_level;
73 module_param(debug_level, int, 0);
74 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
76 /* Netif debug messages possible */
77 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
85 NETIF_MSG_TX_QUEUED | \
88 NETIF_MSG_RX_STATUS | \
94 #define EMAC_MAJOR_VERSION 6
95 #define EMAC_MINOR_VERSION 1
96 #define EMAC_MODULE_VERSION "6.1"
97 MODULE_VERSION(EMAC_MODULE_VERSION);
98 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
100 /* Configuration items */
101 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */
102 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */
103 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */
104 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */
105 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */
106 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */
107 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */
108 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */
109 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */
110 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */
111 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */
112 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */
114 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */
115 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/
117 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */
118 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */
119 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
120 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
121 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
122 #define EMAC_DEF_RX_NUM_DESC (128)
123 #define EMAC_DEF_TX_NUM_DESC (128)
124 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
125 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
126 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
128 /* Buffer descriptor parameters */
129 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */
130 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */
132 /* EMAC register related defines */
133 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
134 #define EMAC_NUM_MULTICAST_BITS (64)
135 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
136 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
137 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
138 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
139 #define EMAC_INT_MASK_CLEAR (0xFF)
141 /* RX MBP register bit positions */
142 #define EMAC_RXMBP_PASSCRC_MASK BIT(30)
143 #define EMAC_RXMBP_QOSEN_MASK BIT(29)
144 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
145 #define EMAC_RXMBP_CMFEN_MASK BIT(24)
146 #define EMAC_RXMBP_CSFEN_MASK BIT(23)
147 #define EMAC_RXMBP_CEFEN_MASK BIT(22)
148 #define EMAC_RXMBP_CAFEN_MASK BIT(21)
149 #define EMAC_RXMBP_PROMCH_SHIFT (16)
150 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
151 #define EMAC_RXMBP_BROADEN_MASK BIT(13)
152 #define EMAC_RXMBP_BROADCH_SHIFT (8)
153 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
154 #define EMAC_RXMBP_MULTIEN_MASK BIT(5)
155 #define EMAC_RXMBP_MULTICH_SHIFT (0)
156 #define EMAC_RXMBP_MULTICH_MASK (0x7)
157 #define EMAC_RXMBP_CHMASK (0x7)
159 /* EMAC register definitions/bit maps used */
160 # define EMAC_MBP_RXPROMISC (0x00200000)
161 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
162 # define EMAC_MBP_RXBCAST (0x00002000)
163 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
164 # define EMAC_MBP_RXMCAST (0x00000020)
165 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
167 /* EMAC mac_control register */
168 #define EMAC_MACCONTROL_TXPTYPE BIT(9)
169 #define EMAC_MACCONTROL_TXPACEEN BIT(6)
170 #define EMAC_MACCONTROL_GMIIEN BIT(5)
171 #define EMAC_MACCONTROL_GIGABITEN BIT(7)
172 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
173 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
175 /* GIGABIT MODE related bits */
176 #define EMAC_DM646X_MACCONTORL_GIG BIT(7)
177 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
179 /* EMAC mac_status register */
180 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
181 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
182 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
183 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
184 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
185 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
186 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
187 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
189 /* EMAC RX register masks */
190 #define EMAC_RX_MAX_LEN_MASK (0xFFFF)
191 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
193 /* MAC_IN_VECTOR (0x180) register bit fields */
194 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
195 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
196 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
197 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
199 /** NOTE:: For DM646x the IN_VECTOR has changed */
200 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
201 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
202 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
203 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
205 /* CPPI bit positions */
206 #define EMAC_CPPI_SOP_BIT BIT(31)
207 #define EMAC_CPPI_EOP_BIT BIT(30)
208 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
209 #define EMAC_CPPI_EOQ_BIT BIT(28)
210 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
211 #define EMAC_CPPI_PASS_CRC_BIT BIT(26)
212 #define EMAC_RX_BD_BUF_SIZE (0xFFFF)
213 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */
214 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
216 /* Max hardware defines */
217 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */
218 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
220 /* EMAC Peripheral Device Register Memory Layout structure */
221 #define EMAC_MACINVECTOR 0x90
223 #define EMAC_DM646X_MACEOIVECTOR 0x94
225 #define EMAC_MACINTSTATRAW 0xB0
226 #define EMAC_MACINTSTATMASKED 0xB4
227 #define EMAC_MACINTMASKSET 0xB8
228 #define EMAC_MACINTMASKCLEAR 0xBC
230 #define EMAC_RXMBPENABLE 0x100
231 #define EMAC_RXUNICASTSET 0x104
232 #define EMAC_RXUNICASTCLEAR 0x108
233 #define EMAC_RXMAXLEN 0x10C
234 #define EMAC_RXBUFFEROFFSET 0x110
235 #define EMAC_RXFILTERLOWTHRESH 0x114
237 #define EMAC_MACCONTROL 0x160
238 #define EMAC_MACSTATUS 0x164
239 #define EMAC_EMCONTROL 0x168
240 #define EMAC_FIFOCONTROL 0x16C
241 #define EMAC_MACCONFIG 0x170
242 #define EMAC_SOFTRESET 0x174
243 #define EMAC_MACSRCADDRLO 0x1D0
244 #define EMAC_MACSRCADDRHI 0x1D4
245 #define EMAC_MACHASH1 0x1D8
246 #define EMAC_MACHASH2 0x1DC
247 #define EMAC_MACADDRLO 0x500
248 #define EMAC_MACADDRHI 0x504
249 #define EMAC_MACINDEX 0x508
251 /* EMAC statistics registers */
252 #define EMAC_RXGOODFRAMES 0x200
253 #define EMAC_RXBCASTFRAMES 0x204
254 #define EMAC_RXMCASTFRAMES 0x208
255 #define EMAC_RXPAUSEFRAMES 0x20C
256 #define EMAC_RXCRCERRORS 0x210
257 #define EMAC_RXALIGNCODEERRORS 0x214
258 #define EMAC_RXOVERSIZED 0x218
259 #define EMAC_RXJABBER 0x21C
260 #define EMAC_RXUNDERSIZED 0x220
261 #define EMAC_RXFRAGMENTS 0x224
262 #define EMAC_RXFILTERED 0x228
263 #define EMAC_RXQOSFILTERED 0x22C
264 #define EMAC_RXOCTETS 0x230
265 #define EMAC_TXGOODFRAMES 0x234
266 #define EMAC_TXBCASTFRAMES 0x238
267 #define EMAC_TXMCASTFRAMES 0x23C
268 #define EMAC_TXPAUSEFRAMES 0x240
269 #define EMAC_TXDEFERRED 0x244
270 #define EMAC_TXCOLLISION 0x248
271 #define EMAC_TXSINGLECOLL 0x24C
272 #define EMAC_TXMULTICOLL 0x250
273 #define EMAC_TXEXCESSIVECOLL 0x254
274 #define EMAC_TXLATECOLL 0x258
275 #define EMAC_TXUNDERRUN 0x25C
276 #define EMAC_TXCARRIERSENSE 0x260
277 #define EMAC_TXOCTETS 0x264
278 #define EMAC_NETOCTETS 0x280
279 #define EMAC_RXSOFOVERRUNS 0x284
280 #define EMAC_RXMOFOVERRUNS 0x288
281 #define EMAC_RXDMAOVERRUNS 0x28C
283 /* EMAC DM644x control registers */
284 #define EMAC_CTRL_EWCTL (0x4)
285 #define EMAC_CTRL_EWINTTCNT (0x8)
287 /* EMAC DM644x control module masks */
288 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
289 #define EMAC_DM644X_INTMIN_INTVL 0x1
290 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
292 /* EMAC DM646X control module registers */
293 #define EMAC_DM646X_CMINTCTRL 0x0C
294 #define EMAC_DM646X_CMRXINTEN 0x14
295 #define EMAC_DM646X_CMTXINTEN 0x18
296 #define EMAC_DM646X_CMRXINTMAX 0x70
297 #define EMAC_DM646X_CMTXINTMAX 0x74
299 /* EMAC DM646X control module masks */
300 #define EMAC_DM646X_INTPACEEN (0x3 << 16)
301 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
302 #define EMAC_DM646X_CMINTMAX_CNT 63
303 #define EMAC_DM646X_CMINTMIN_CNT 2
304 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
305 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
308 /* EMAC EOI codes for C0 */
309 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
310 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
312 /* EMAC Stats Clear Mask */
313 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
315 /* emac_priv: EMAC private data structure
317 * EMAC adapter private data structure
321 struct net_device *ndev;
322 struct platform_device *pdev;
323 struct napi_struct napi;
325 void __iomem *remap_addr;
327 void __iomem *emac_base;
328 void __iomem *ctrl_base;
329 struct cpdma_ctlr *dma;
330 struct cpdma_chan *txchan;
331 struct cpdma_chan *rxchan;
332 u32 link; /* 1=link on, 0=link off */
333 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
334 u32 duplex; /* Link duplex: 0=Half, 1=Full */
343 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
348 struct device_node *phy_node;
350 struct phy_device *phydev;
352 /*platform specific members*/
353 void (*int_enable) (void);
354 void (*int_disable) (void);
357 /* EMAC TX Host Error description strings */
358 static char *emac_txhost_errcodes[16] = {
359 "No error", "SOP error", "Ownership bit not set in SOP buffer",
360 "Zero Next Buffer Descriptor Pointer Without EOP",
361 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
362 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
363 "Reserved", "Reserved", "Reserved", "Reserved"
366 /* EMAC RX Host Error description strings */
367 static char *emac_rxhost_errcodes[16] = {
368 "No error", "Reserved", "Ownership bit not set in input buffer",
369 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
370 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
371 "Reserved", "Reserved", "Reserved", "Reserved"
375 #define emac_read(reg) ioread32(priv->emac_base + (reg))
376 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
378 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
379 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
382 * emac_dump_regs - Dump important EMAC registers to debug terminal
383 * @priv: The DaVinci EMAC private adapter structure
385 * Executes ethtool set cmd & sets phy mode
388 static void emac_dump_regs(struct emac_priv *priv)
390 struct device *emac_dev = &priv->ndev->dev;
392 /* Print important registers in EMAC */
393 dev_info(emac_dev, "EMAC Basic registers\n");
394 if (priv->version == EMAC_VERSION_1) {
395 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
396 emac_ctrl_read(EMAC_CTRL_EWCTL),
397 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
399 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
400 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
401 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
402 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
403 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
404 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
405 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
406 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
407 dev_info(emac_dev, "EMAC Statistics\n");
408 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
409 emac_read(EMAC_RXGOODFRAMES));
410 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
411 emac_read(EMAC_RXBCASTFRAMES));
412 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
413 emac_read(EMAC_RXMCASTFRAMES));
414 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
415 emac_read(EMAC_RXPAUSEFRAMES));
416 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
417 emac_read(EMAC_RXCRCERRORS));
418 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
419 emac_read(EMAC_RXALIGNCODEERRORS));
420 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
421 emac_read(EMAC_RXOVERSIZED));
422 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
423 emac_read(EMAC_RXJABBER));
424 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
425 emac_read(EMAC_RXUNDERSIZED));
426 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
427 emac_read(EMAC_RXFRAGMENTS));
428 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
429 emac_read(EMAC_RXFILTERED));
430 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
431 emac_read(EMAC_RXQOSFILTERED));
432 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
433 emac_read(EMAC_RXOCTETS));
434 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
435 emac_read(EMAC_TXGOODFRAMES));
436 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
437 emac_read(EMAC_TXBCASTFRAMES));
438 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
439 emac_read(EMAC_TXMCASTFRAMES));
440 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
441 emac_read(EMAC_TXPAUSEFRAMES));
442 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
443 emac_read(EMAC_TXDEFERRED));
444 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
445 emac_read(EMAC_TXCOLLISION));
446 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
447 emac_read(EMAC_TXSINGLECOLL));
448 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
449 emac_read(EMAC_TXMULTICOLL));
450 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
451 emac_read(EMAC_TXEXCESSIVECOLL));
452 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
453 emac_read(EMAC_TXLATECOLL));
454 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
455 emac_read(EMAC_TXUNDERRUN));
456 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
457 emac_read(EMAC_TXCARRIERSENSE));
458 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
459 emac_read(EMAC_TXOCTETS));
460 dev_info(emac_dev, "EMAC: net_octets:%d\n",
461 emac_read(EMAC_NETOCTETS));
462 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
463 emac_read(EMAC_RXSOFOVERRUNS));
464 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
465 emac_read(EMAC_RXMOFOVERRUNS));
466 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
467 emac_read(EMAC_RXDMAOVERRUNS));
469 cpdma_ctlr_dump(priv->dma);
473 * emac_get_drvinfo - Get EMAC driver information
474 * @ndev: The DaVinci EMAC network adapter
475 * @info: ethtool info structure containing name and version
477 * Returns EMAC driver information (name and version)
480 static void emac_get_drvinfo(struct net_device *ndev,
481 struct ethtool_drvinfo *info)
483 strlcpy(info->driver, emac_version_string, sizeof(info->driver));
484 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
488 * emac_get_settings - Get EMAC settings
489 * @ndev: The DaVinci EMAC network adapter
490 * @ecmd: ethtool command
492 * Executes ethool get command
495 static int emac_get_settings(struct net_device *ndev,
496 struct ethtool_cmd *ecmd)
498 struct emac_priv *priv = netdev_priv(ndev);
500 return phy_ethtool_gset(priv->phydev, ecmd);
507 * emac_set_settings - Set EMAC settings
508 * @ndev: The DaVinci EMAC network adapter
509 * @ecmd: ethtool command
511 * Executes ethool set command
514 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
516 struct emac_priv *priv = netdev_priv(ndev);
518 return phy_ethtool_sset(priv->phydev, ecmd);
525 * emac_get_coalesce - Get interrupt coalesce settings for this device
526 * @ndev : The DaVinci EMAC network adapter
527 * @coal : ethtool coalesce settings structure
529 * Fetch the current interrupt coalesce settings
532 static int emac_get_coalesce(struct net_device *ndev,
533 struct ethtool_coalesce *coal)
535 struct emac_priv *priv = netdev_priv(ndev);
537 coal->rx_coalesce_usecs = priv->coal_intvl;
543 * emac_set_coalesce - Set interrupt coalesce settings for this device
544 * @ndev : The DaVinci EMAC network adapter
545 * @coal : ethtool coalesce settings structure
547 * Set interrupt coalesce parameters
550 static int emac_set_coalesce(struct net_device *ndev,
551 struct ethtool_coalesce *coal)
553 struct emac_priv *priv = netdev_priv(ndev);
554 u32 int_ctrl, num_interrupts = 0;
555 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
557 if (!coal->rx_coalesce_usecs)
560 coal_intvl = coal->rx_coalesce_usecs;
562 switch (priv->version) {
564 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
565 prescale = priv->bus_freq_mhz * 4;
567 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
568 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
570 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
572 * Interrupt pacer works with 4us Pulse, we can
573 * throttle further by dilating the 4us pulse.
575 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
577 if (addnl_dvdr > 1) {
578 prescale *= addnl_dvdr;
579 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
581 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
585 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
589 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
591 int_ctrl |= EMAC_DM646X_INTPACEEN;
592 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
593 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
594 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
596 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
597 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
601 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
602 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
603 prescale = coal_intvl * priv->bus_freq_mhz;
604 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
605 prescale = EMAC_DM644X_EWINTCNT_MASK;
606 coal_intvl = prescale / priv->bus_freq_mhz;
608 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
613 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
614 priv->coal_intvl = coal_intvl;
621 /* ethtool_ops: DaVinci EMAC Ethtool structure
623 * Ethtool support for EMAC adapter
625 static const struct ethtool_ops ethtool_ops = {
626 .get_drvinfo = emac_get_drvinfo,
627 .get_settings = emac_get_settings,
628 .set_settings = emac_set_settings,
629 .get_link = ethtool_op_get_link,
630 .get_coalesce = emac_get_coalesce,
631 .set_coalesce = emac_set_coalesce,
632 .get_ts_info = ethtool_op_get_ts_info,
636 * emac_update_phystatus - Update Phy status
637 * @priv: The DaVinci EMAC private adapter structure
639 * Updates phy status and takes action for network queue if required
640 * based upon link status
643 static void emac_update_phystatus(struct emac_priv *priv)
648 struct net_device *ndev = priv->ndev;
650 mac_control = emac_read(EMAC_MACCONTROL);
651 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
652 DUPLEX_FULL : DUPLEX_HALF;
654 new_duplex = priv->phydev->duplex;
656 new_duplex = DUPLEX_FULL;
658 /* We get called only if link has changed (speed/duplex/status) */
659 if ((priv->link) && (new_duplex != cur_duplex)) {
660 priv->duplex = new_duplex;
661 if (DUPLEX_FULL == priv->duplex)
662 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
664 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
667 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
668 mac_control = emac_read(EMAC_MACCONTROL);
669 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
670 EMAC_DM646X_MACCONTORL_GIGFORCE);
672 /* Clear the GIG bit and GIGFORCE bit */
673 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
674 EMAC_DM646X_MACCONTORL_GIG);
676 if (priv->rmii_en && (priv->speed == SPEED_100))
677 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
679 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
682 /* Update mac_control if changed */
683 emac_write(EMAC_MACCONTROL, mac_control);
687 if (!netif_carrier_ok(ndev))
688 netif_carrier_on(ndev);
689 /* reactivate the transmit queue if it is stopped */
690 if (netif_running(ndev) && netif_queue_stopped(ndev))
691 netif_wake_queue(ndev);
694 if (netif_carrier_ok(ndev))
695 netif_carrier_off(ndev);
696 if (!netif_queue_stopped(ndev))
697 netif_stop_queue(ndev);
702 * hash_get - Calculate hash value from mac address
703 * @addr: mac address to delete from hash table
705 * Calculates hash value from mac address
708 static u32 hash_get(u8 *addr)
715 for (cnt = 0; cnt < 2; cnt++) {
717 hash ^= (tmpval >> 2) ^ (tmpval << 4);
719 hash ^= (tmpval >> 4) ^ (tmpval << 2);
721 hash ^= (tmpval >> 6) ^ (tmpval);
728 * hash_add - Hash function to add mac addr from hash table
729 * @priv: The DaVinci EMAC private adapter structure
730 * @mac_addr: mac address to delete from hash table
732 * Adds mac address to the internal hash table
735 static int hash_add(struct emac_priv *priv, u8 *mac_addr)
737 struct device *emac_dev = &priv->ndev->dev;
740 u32 hash_value = hash_get(mac_addr);
742 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
743 if (netif_msg_drv(priv)) {
744 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
745 "Hash %08x, should not be greater than %08x",
746 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
751 /* set the hash bit only if not previously set */
752 if (priv->multicast_hash_cnt[hash_value] == 0) {
753 rc = 1; /* hash value changed */
754 if (hash_value < 32) {
755 hash_bit = BIT(hash_value);
756 priv->mac_hash1 |= hash_bit;
758 hash_bit = BIT((hash_value - 32));
759 priv->mac_hash2 |= hash_bit;
763 /* incr counter for num of mcast addr's mapped to "this" hash bit */
764 ++priv->multicast_hash_cnt[hash_value];
770 * hash_del - Hash function to delete mac addr from hash table
771 * @priv: The DaVinci EMAC private adapter structure
772 * @mac_addr: mac address to delete from hash table
774 * Removes mac address from the internal hash table
777 static int hash_del(struct emac_priv *priv, u8 *mac_addr)
782 hash_value = hash_get(mac_addr);
783 if (priv->multicast_hash_cnt[hash_value] > 0) {
784 /* dec cntr for num of mcast addr's mapped to this hash bit */
785 --priv->multicast_hash_cnt[hash_value];
788 /* if counter still > 0, at least one multicast address refers
789 * to this hash bit. so return 0 */
790 if (priv->multicast_hash_cnt[hash_value] > 0)
793 if (hash_value < 32) {
794 hash_bit = BIT(hash_value);
795 priv->mac_hash1 &= ~hash_bit;
797 hash_bit = BIT((hash_value - 32));
798 priv->mac_hash2 &= ~hash_bit;
801 /* return 1 to indicate change in mac_hash registers reqd */
805 /* EMAC multicast operation */
806 #define EMAC_MULTICAST_ADD 0
807 #define EMAC_MULTICAST_DEL 1
808 #define EMAC_ALL_MULTI_SET 2
809 #define EMAC_ALL_MULTI_CLR 3
812 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal)
813 * @priv: The DaVinci EMAC private adapter structure
814 * @action: multicast operation to perform
815 * mac_addr: mac address to set
817 * Set multicast addresses in EMAC adapter - internal function
820 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
822 struct device *emac_dev = &priv->ndev->dev;
826 case EMAC_MULTICAST_ADD:
827 update = hash_add(priv, mac_addr);
829 case EMAC_MULTICAST_DEL:
830 update = hash_del(priv, mac_addr);
832 case EMAC_ALL_MULTI_SET:
834 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
835 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
837 case EMAC_ALL_MULTI_CLR:
841 memset(&(priv->multicast_hash_cnt[0]), 0,
842 sizeof(priv->multicast_hash_cnt[0]) *
843 EMAC_NUM_MULTICAST_BITS);
846 if (netif_msg_drv(priv))
847 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
848 ": bad operation %d", action);
852 /* write to the hardware only if the register status chances */
854 emac_write(EMAC_MACHASH1, priv->mac_hash1);
855 emac_write(EMAC_MACHASH2, priv->mac_hash2);
860 * emac_dev_mcast_set - Set multicast address in the EMAC adapter
861 * @ndev: The DaVinci EMAC network adapter
863 * Set multicast addresses in EMAC adapter
866 static void emac_dev_mcast_set(struct net_device *ndev)
869 struct emac_priv *priv = netdev_priv(ndev);
871 mbp_enable = emac_read(EMAC_RXMBPENABLE);
872 if (ndev->flags & IFF_PROMISC) {
873 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
874 mbp_enable |= (EMAC_MBP_RXPROMISC);
876 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
877 if ((ndev->flags & IFF_ALLMULTI) ||
878 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
879 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
880 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
882 if (!netdev_mc_empty(ndev)) {
883 struct netdev_hw_addr *ha;
885 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
886 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
887 /* program multicast address list into EMAC hardware */
888 netdev_for_each_mc_addr(ha, ndev) {
889 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
893 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
894 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
897 /* Set mbp config register */
898 emac_write(EMAC_RXMBPENABLE, mbp_enable);
901 /*************************************************************************
902 * EMAC Hardware manipulation
903 *************************************************************************/
906 * emac_int_disable - Disable EMAC module interrupt (from adapter)
907 * @priv: The DaVinci EMAC private adapter structure
909 * Disable EMAC interrupt on the adapter
912 static void emac_int_disable(struct emac_priv *priv)
914 if (priv->version == EMAC_VERSION_2) {
917 local_irq_save(flags);
919 /* Program C0_Int_En to zero to turn off
920 * interrupts to the CPU */
921 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
922 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
923 /* NOTE: Rx Threshold and Misc interrupts are not disabled */
924 if (priv->int_disable)
927 local_irq_restore(flags);
930 /* Set DM644x control registers for interrupt control */
931 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
936 * emac_int_enable - Enable EMAC module interrupt (from adapter)
937 * @priv: The DaVinci EMAC private adapter structure
939 * Enable EMAC interrupt on the adapter
942 static void emac_int_enable(struct emac_priv *priv)
944 if (priv->version == EMAC_VERSION_2) {
945 if (priv->int_enable)
948 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
949 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
951 /* In addition to turning on interrupt Enable, we need
952 * ack by writing appropriate values to the EOI
955 /* NOTE: Rx Threshold and Misc interrupts are not enabled */
957 /* ack rxen only then a new pulse will be generated */
958 emac_write(EMAC_DM646X_MACEOIVECTOR,
959 EMAC_DM646X_MAC_EOI_C0_RXEN);
961 /* ack txen- only then a new pulse will be generated */
962 emac_write(EMAC_DM646X_MACEOIVECTOR,
963 EMAC_DM646X_MAC_EOI_C0_TXEN);
966 /* Set DM644x control registers for interrupt control */
967 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
972 * emac_irq - EMAC interrupt handler
973 * @irq: interrupt number
974 * @dev_id: EMAC network adapter data structure ptr
976 * EMAC Interrupt handler - we only schedule NAPI and not process any packets
977 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function
979 * Returns interrupt handled condition
981 static irqreturn_t emac_irq(int irq, void *dev_id)
983 struct net_device *ndev = (struct net_device *)dev_id;
984 struct emac_priv *priv = netdev_priv(ndev);
987 if (likely(netif_running(priv->ndev))) {
988 emac_int_disable(priv);
989 napi_schedule(&priv->napi);
991 /* we are closing down, so dont process anything */
996 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
998 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
1001 skb_reserve(skb, NET_IP_ALIGN);
1005 static void emac_rx_handler(void *token, int len, int status)
1007 struct sk_buff *skb = token;
1008 struct net_device *ndev = skb->dev;
1009 struct emac_priv *priv = netdev_priv(ndev);
1010 struct device *emac_dev = &ndev->dev;
1013 /* free and bail if we are shutting down */
1014 if (unlikely(!netif_running(ndev))) {
1015 dev_kfree_skb_any(skb);
1019 /* recycle on receive error */
1021 ndev->stats.rx_errors++;
1025 /* feed received packet up the stack */
1027 skb->protocol = eth_type_trans(skb, ndev);
1028 netif_receive_skb(skb);
1029 ndev->stats.rx_bytes += len;
1030 ndev->stats.rx_packets++;
1032 /* alloc a new packet for receive */
1033 skb = emac_rx_alloc(priv);
1035 if (netif_msg_rx_err(priv) && net_ratelimit())
1036 dev_err(emac_dev, "failed rx buffer alloc\n");
1041 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1042 skb_tailroom(skb), GFP_KERNEL);
1044 WARN_ON(ret == -ENOMEM);
1045 if (unlikely(ret < 0))
1046 dev_kfree_skb_any(skb);
1049 static void emac_tx_handler(void *token, int len, int status)
1051 struct sk_buff *skb = token;
1052 struct net_device *ndev = skb->dev;
1053 struct emac_priv *priv = netdev_priv(ndev);
1055 atomic_dec(&priv->cur_tx);
1057 if (unlikely(netif_queue_stopped(ndev)))
1058 netif_start_queue(ndev);
1059 ndev->stats.tx_packets++;
1060 ndev->stats.tx_bytes += len;
1061 dev_kfree_skb_any(skb);
1065 * emac_dev_xmit - EMAC Transmit function
1067 * @ndev: The DaVinci EMAC network adapter
1069 * Called by the system to transmit a packet - we queue the packet in
1070 * EMAC hardware transmit queue
1072 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's)
1074 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1076 struct device *emac_dev = &ndev->dev;
1078 struct emac_priv *priv = netdev_priv(ndev);
1080 /* If no link, return */
1081 if (unlikely(!priv->link)) {
1082 if (netif_msg_tx_err(priv) && net_ratelimit())
1083 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1087 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
1088 if (unlikely(ret_code < 0)) {
1089 if (netif_msg_tx_err(priv) && net_ratelimit())
1090 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
1094 skb_tx_timestamp(skb);
1096 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
1098 if (unlikely(ret_code != 0)) {
1099 if (netif_msg_tx_err(priv) && net_ratelimit())
1100 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
1104 if (atomic_inc_return(&priv->cur_tx) >= EMAC_DEF_TX_NUM_DESC)
1105 netif_stop_queue(ndev);
1107 return NETDEV_TX_OK;
1110 ndev->stats.tx_dropped++;
1111 netif_stop_queue(ndev);
1112 return NETDEV_TX_BUSY;
1116 * emac_dev_tx_timeout - EMAC Transmit timeout function
1117 * @ndev: The DaVinci EMAC network adapter
1119 * Called when system detects that a skb timeout period has expired
1120 * potentially due to a fault in the adapter in not being able to send
1121 * it out on the wire. We teardown the TX channel assuming a hardware
1122 * error and re-initialize the TX channel for hardware operation
1125 static void emac_dev_tx_timeout(struct net_device *ndev)
1127 struct emac_priv *priv = netdev_priv(ndev);
1128 struct device *emac_dev = &ndev->dev;
1130 if (netif_msg_tx_err(priv))
1131 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1133 emac_dump_regs(priv);
1135 ndev->stats.tx_errors++;
1136 emac_int_disable(priv);
1137 cpdma_chan_stop(priv->txchan);
1138 cpdma_chan_start(priv->txchan);
1139 emac_int_enable(priv);
1143 * emac_set_type0addr - Set EMAC Type0 mac address
1144 * @priv: The DaVinci EMAC private adapter structure
1145 * @ch: RX channel number
1146 * @mac_addr: MAC address to set in device
1148 * Called internally to set Type0 mac address of the adapter (Device)
1150 * Returns success (0) or appropriate error code (none as of now)
1152 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1155 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1156 emac_write(EMAC_MACSRCADDRLO, val);
1158 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1159 (mac_addr[1] << 8) | (mac_addr[0]));
1160 emac_write(EMAC_MACSRCADDRHI, val);
1161 val = emac_read(EMAC_RXUNICASTSET);
1163 emac_write(EMAC_RXUNICASTSET, val);
1164 val = emac_read(EMAC_RXUNICASTCLEAR);
1166 emac_write(EMAC_RXUNICASTCLEAR, val);
1170 * emac_set_type1addr - Set EMAC Type1 mac address
1171 * @priv: The DaVinci EMAC private adapter structure
1172 * @ch: RX channel number
1173 * @mac_addr: MAC address to set in device
1175 * Called internally to set Type1 mac address of the adapter (Device)
1177 * Returns success (0) or appropriate error code (none as of now)
1179 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1182 emac_write(EMAC_MACINDEX, ch);
1183 val = ((mac_addr[5] << 8) | mac_addr[4]);
1184 emac_write(EMAC_MACADDRLO, val);
1185 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1186 (mac_addr[1] << 8) | (mac_addr[0]));
1187 emac_write(EMAC_MACADDRHI, val);
1188 emac_set_type0addr(priv, ch, mac_addr);
1192 * emac_set_type2addr - Set EMAC Type2 mac address
1193 * @priv: The DaVinci EMAC private adapter structure
1194 * @ch: RX channel number
1195 * @mac_addr: MAC address to set in device
1196 * @index: index into RX address entries
1197 * @match: match parameter for RX address matching logic
1199 * Called internally to set Type2 mac address of the adapter (Device)
1201 * Returns success (0) or appropriate error code (none as of now)
1203 static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1204 char *mac_addr, int index, int match)
1207 emac_write(EMAC_MACINDEX, index);
1208 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1209 (mac_addr[1] << 8) | (mac_addr[0]));
1210 emac_write(EMAC_MACADDRHI, val);
1211 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1212 (match << 19) | BIT(20));
1213 emac_write(EMAC_MACADDRLO, val);
1214 emac_set_type0addr(priv, ch, mac_addr);
1218 * emac_setmac - Set mac address in the adapter (internal function)
1219 * @priv: The DaVinci EMAC private adapter structure
1220 * @ch: RX channel number
1221 * @mac_addr: MAC address to set in device
1223 * Called internally to set the mac address of the adapter (Device)
1225 * Returns success (0) or appropriate error code (none as of now)
1227 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1229 struct device *emac_dev = &priv->ndev->dev;
1231 if (priv->rx_addr_type == 0) {
1232 emac_set_type0addr(priv, ch, mac_addr);
1233 } else if (priv->rx_addr_type == 1) {
1235 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1236 emac_set_type1addr(priv, ch, mac_addr);
1237 } else if (priv->rx_addr_type == 2) {
1238 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1239 emac_set_type0addr(priv, ch, mac_addr);
1241 if (netif_msg_drv(priv))
1242 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1247 * emac_dev_setmac_addr - Set mac address in the adapter
1248 * @ndev: The DaVinci EMAC network adapter
1249 * @addr: MAC address to set in device
1251 * Called by the system to set the mac address of the adapter (Device)
1253 * Returns success (0) or appropriate error code (none as of now)
1255 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1257 struct emac_priv *priv = netdev_priv(ndev);
1258 struct device *emac_dev = &priv->ndev->dev;
1259 struct sockaddr *sa = addr;
1261 if (!is_valid_ether_addr(sa->sa_data))
1262 return -EADDRNOTAVAIL;
1264 /* Store mac addr in priv and rx channel and set it in EMAC hw */
1265 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1266 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1268 /* MAC address is configured only after the interface is enabled. */
1269 if (netif_running(ndev)) {
1270 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1273 if (netif_msg_drv(priv))
1274 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1281 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception
1282 * @priv: The DaVinci EMAC private adapter structure
1284 * Enables EMAC hardware for packet processing - enables PHY, enables RX
1285 * for packet reception and enables device interrupts and then NAPI
1287 * Returns success (0) or appropriate error code (none right now)
1289 static int emac_hw_enable(struct emac_priv *priv)
1291 u32 val, mbp_enable, mac_control;
1294 emac_write(EMAC_SOFTRESET, 1);
1295 while (emac_read(EMAC_SOFTRESET))
1298 /* Disable interrupt & Set pacing for more interrupts initially */
1299 emac_int_disable(priv);
1301 /* Full duplex enable bit set when auto negotiation happens */
1303 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1304 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1305 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1306 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1307 emac_write(EMAC_MACCONTROL, mac_control);
1310 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1311 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1312 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1313 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1314 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1315 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1316 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1317 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1318 EMAC_RXMBP_PROMCH_SHIFT) |
1319 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1320 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1321 EMAC_RXMBP_BROADCH_SHIFT) |
1322 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1323 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1324 EMAC_RXMBP_MULTICH_SHIFT));
1325 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1326 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1327 EMAC_RX_MAX_LEN_MASK));
1328 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1329 EMAC_RX_BUFFER_OFFSET_MASK));
1330 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1331 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1332 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1334 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1336 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1339 val = emac_read(EMAC_MACCONTROL);
1340 val |= (EMAC_MACCONTROL_GMIIEN);
1341 emac_write(EMAC_MACCONTROL, val);
1343 /* Enable NAPI and interrupts */
1344 napi_enable(&priv->napi);
1345 emac_int_enable(priv);
1351 * emac_poll - EMAC NAPI Poll function
1352 * @ndev: The DaVinci EMAC network adapter
1353 * @budget: Number of receive packets to process (as told by NAPI layer)
1355 * NAPI Poll function implemented to process packets as per budget. We check
1356 * the type of interrupt on the device and accordingly call the TX or RX
1357 * packet processing functions. We follow the budget for RX processing and
1358 * also put a cap on number of TX pkts processed through config param. The
1359 * NAPI schedule function is called if more packets pending.
1361 * Returns number of packets received (in most cases; else TX pkts - rarely)
1363 static int emac_poll(struct napi_struct *napi, int budget)
1366 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1367 struct net_device *ndev = priv->ndev;
1368 struct device *emac_dev = &ndev->dev;
1370 u32 num_tx_pkts = 0, num_rx_pkts = 0;
1372 /* Check interrupt vectors and call packet processing */
1373 status = emac_read(EMAC_MACINVECTOR);
1375 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1377 if (priv->version == EMAC_VERSION_2)
1378 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1380 if (status & mask) {
1381 num_tx_pkts = cpdma_chan_process(priv->txchan,
1382 EMAC_DEF_TX_MAX_SERVICE);
1383 } /* TX processing */
1385 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1387 if (priv->version == EMAC_VERSION_2)
1388 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1390 if (status & mask) {
1391 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1392 } /* RX processing */
1394 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1395 if (priv->version == EMAC_VERSION_2)
1396 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1398 if (unlikely(status & mask)) {
1400 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1401 netif_stop_queue(ndev);
1402 napi_disable(&priv->napi);
1404 status = emac_read(EMAC_MACSTATUS);
1405 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1406 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1408 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1409 EMAC_MACSTATUS_TXERRCH_SHIFT);
1410 if (net_ratelimit()) {
1411 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1412 &emac_txhost_errcodes[cause][0], ch);
1415 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1416 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1418 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1419 EMAC_MACSTATUS_RXERRCH_SHIFT);
1420 if (netif_msg_hw(priv) && net_ratelimit())
1421 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1422 &emac_rxhost_errcodes[cause][0], ch);
1424 } else if (num_rx_pkts < budget) {
1425 napi_complete(napi);
1426 emac_int_enable(priv);
1432 #ifdef CONFIG_NET_POLL_CONTROLLER
1434 * emac_poll_controller - EMAC Poll controller function
1435 * @ndev: The DaVinci EMAC network adapter
1437 * Polled functionality used by netconsole and others in non interrupt mode
1440 void emac_poll_controller(struct net_device *ndev)
1442 struct emac_priv *priv = netdev_priv(ndev);
1444 emac_int_disable(priv);
1445 emac_irq(ndev->irq, ndev);
1446 emac_int_enable(priv);
1450 static void emac_adjust_link(struct net_device *ndev)
1452 struct emac_priv *priv = netdev_priv(ndev);
1453 struct phy_device *phydev = priv->phydev;
1454 unsigned long flags;
1457 spin_lock_irqsave(&priv->lock, flags);
1460 /* check the mode of operation - full/half duplex */
1461 if (phydev->duplex != priv->duplex) {
1463 priv->duplex = phydev->duplex;
1465 if (phydev->speed != priv->speed) {
1467 priv->speed = phydev->speed;
1474 } else if (priv->link) {
1481 emac_update_phystatus(priv);
1482 phy_print_status(priv->phydev);
1485 spin_unlock_irqrestore(&priv->lock, flags);
1488 /*************************************************************************
1489 * Linux Driver Model
1490 *************************************************************************/
1493 * emac_devioctl - EMAC adapter ioctl
1494 * @ndev: The DaVinci EMAC network adapter
1495 * @ifrq: request parameter
1496 * @cmd: command parameter
1498 * EMAC driver ioctl function
1500 * Returns success(0) or appropriate error code
1502 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1504 struct emac_priv *priv = netdev_priv(ndev);
1506 if (!(netif_running(ndev)))
1509 /* TODO: Add phy read and write and private statistics get feature */
1511 return phy_mii_ioctl(priv->phydev, ifrq, cmd);
1514 static int match_first_device(struct device *dev, void *data)
1516 return !strncmp(dev_name(dev), "davinci_mdio", 12);
1520 * emac_dev_open - EMAC device open
1521 * @ndev: The DaVinci EMAC network adapter
1523 * Called when system wants to start the interface. We init TX/RX channels
1524 * and enable the hardware for packet reception/transmission and start the
1527 * Returns 0 for a successful open, or appropriate error code
1529 static int emac_dev_open(struct net_device *ndev)
1531 struct device *emac_dev = &ndev->dev;
1533 struct resource *res;
1537 struct emac_priv *priv = netdev_priv(ndev);
1539 pm_runtime_get(&priv->pdev->dev);
1541 netif_carrier_off(ndev);
1542 for (cnt = 0; cnt < ETH_ALEN; cnt++)
1543 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1545 /* Configuration items */
1546 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1548 priv->mac_hash1 = 0;
1549 priv->mac_hash2 = 0;
1550 emac_write(EMAC_MACHASH1, 0);
1551 emac_write(EMAC_MACHASH2, 0);
1553 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1554 struct sk_buff *skb = emac_rx_alloc(priv);
1559 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1560 skb_tailroom(skb), GFP_KERNEL);
1561 if (WARN_ON(ret < 0))
1567 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
1568 for (i = res->start; i <= res->end; i++) {
1569 if (request_irq(i, emac_irq, IRQF_DISABLED,
1576 /* Start/Enable EMAC hardware */
1577 emac_hw_enable(priv);
1579 /* Enable Interrupt pacing if configured */
1580 if (priv->coal_intvl != 0) {
1581 struct ethtool_coalesce coal;
1583 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1584 emac_set_coalesce(ndev, &coal);
1587 cpdma_ctlr_start(priv->dma);
1589 priv->phydev = NULL;
1590 /* use the first phy on the bus if pdata did not give us a phy id */
1591 if (!priv->phy_id) {
1594 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1595 match_first_device);
1597 priv->phy_id = dev_name(phy);
1600 if (priv->phy_id && *priv->phy_id) {
1601 priv->phydev = phy_connect(ndev, priv->phy_id,
1602 &emac_adjust_link, 0,
1603 PHY_INTERFACE_MODE_MII);
1605 if (IS_ERR(priv->phydev)) {
1606 dev_err(emac_dev, "could not connect to phy %s\n",
1608 ret = PTR_ERR(priv->phydev);
1609 priv->phydev = NULL;
1617 dev_info(emac_dev, "attached PHY driver [%s] "
1618 "(mii_bus:phy_addr=%s, id=%x)\n",
1619 priv->phydev->drv->name, dev_name(&priv->phydev->dev),
1620 priv->phydev->phy_id);
1622 /* No PHY , fix the link, speed and duplex settings */
1623 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1625 priv->speed = SPEED_100;
1626 priv->duplex = DUPLEX_FULL;
1627 emac_update_phystatus(priv);
1630 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */
1631 emac_dump_regs(priv);
1633 if (netif_msg_drv(priv))
1634 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1637 phy_start(priv->phydev);
1643 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed");
1645 for (q = k; k >= 0; k--) {
1646 for (m = i; m >= res->start; m--)
1648 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1);
1654 pm_runtime_put(&priv->pdev->dev);
1659 * emac_dev_stop - EMAC device stop
1660 * @ndev: The DaVinci EMAC network adapter
1662 * Called when system wants to stop or down the interface. We stop the network
1663 * queue, disable interrupts and cleanup TX/RX channels.
1665 * We return the statistics in net_device_stats structure pulled from emac
1667 static int emac_dev_stop(struct net_device *ndev)
1669 struct resource *res;
1672 struct emac_priv *priv = netdev_priv(ndev);
1673 struct device *emac_dev = &ndev->dev;
1675 /* inform the upper layers. */
1676 netif_stop_queue(ndev);
1677 napi_disable(&priv->napi);
1679 netif_carrier_off(ndev);
1680 emac_int_disable(priv);
1681 cpdma_ctlr_stop(priv->dma);
1682 emac_write(EMAC_SOFTRESET, 1);
1685 phy_disconnect(priv->phydev);
1688 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1689 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1690 free_irq(irq_num, priv->ndev);
1694 if (netif_msg_drv(priv))
1695 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1697 pm_runtime_put(&priv->pdev->dev);
1702 * emac_dev_getnetstats - EMAC get statistics function
1703 * @ndev: The DaVinci EMAC network adapter
1705 * Called when system wants to get statistics from the device.
1707 * We return the statistics in net_device_stats structure pulled from emac
1709 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1711 struct emac_priv *priv = netdev_priv(ndev);
1713 u32 stats_clear_mask;
1715 /* update emac hardware stats and reset the registers*/
1717 mac_control = emac_read(EMAC_MACCONTROL);
1719 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1720 stats_clear_mask = EMAC_STATS_CLR_MASK;
1722 stats_clear_mask = 0;
1724 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1725 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1727 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1728 emac_read(EMAC_TXSINGLECOLL) +
1729 emac_read(EMAC_TXMULTICOLL));
1730 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1731 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1732 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1734 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1735 emac_read(EMAC_RXJABBER) +
1736 emac_read(EMAC_RXUNDERSIZED));
1737 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1738 emac_write(EMAC_RXJABBER, stats_clear_mask);
1739 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1741 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1742 emac_read(EMAC_RXMOFOVERRUNS));
1743 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1744 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1746 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1747 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1749 ndev->stats.tx_carrier_errors +=
1750 emac_read(EMAC_TXCARRIERSENSE);
1751 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1753 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1754 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1756 return &ndev->stats;
1759 static const struct net_device_ops emac_netdev_ops = {
1760 .ndo_open = emac_dev_open,
1761 .ndo_stop = emac_dev_stop,
1762 .ndo_start_xmit = emac_dev_xmit,
1763 .ndo_set_rx_mode = emac_dev_mcast_set,
1764 .ndo_set_mac_address = emac_dev_setmac_addr,
1765 .ndo_do_ioctl = emac_devioctl,
1766 .ndo_tx_timeout = emac_dev_tx_timeout,
1767 .ndo_get_stats = emac_dev_getnetstats,
1768 #ifdef CONFIG_NET_POLL_CONTROLLER
1769 .ndo_poll_controller = emac_poll_controller,
1774 static struct emac_platform_data
1775 *davinci_emac_of_get_pdata(struct platform_device *pdev,
1776 struct emac_priv *priv)
1778 struct device_node *np;
1779 struct emac_platform_data *pdata = NULL;
1784 pdata = pdev->dev.platform_data;
1786 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1791 np = pdev->dev.of_node;
1795 pdata->version = EMAC_VERSION_2;
1797 if (!is_valid_ether_addr(pdata->mac_addr)) {
1798 mac_addr = of_get_mac_address(np);
1800 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
1803 ret = of_property_read_u32(np, "ti,davinci-ctrl-reg-offset", &data);
1805 pdata->ctrl_reg_offset = data;
1807 ret = of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
1810 pdata->ctrl_mod_reg_offset = data;
1812 ret = of_property_read_u32(np, "ti,davinci-ctrl-ram-offset", &data);
1814 pdata->ctrl_ram_offset = data;
1816 ret = of_property_read_u32(np, "ti,davinci-ctrl-ram-size", &data);
1818 pdata->ctrl_ram_size = data;
1820 ret = of_property_read_u32(np, "ti,davinci-rmii-en", &data);
1822 pdata->rmii_en = data;
1824 ret = of_property_read_u32(np, "ti,davinci-no-bd-ram", &data);
1826 pdata->no_bd_ram = data;
1828 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1829 if (!priv->phy_node)
1832 pdev->dev.platform_data = pdata;
1837 static struct emac_platform_data
1838 *davinci_emac_of_get_pdata(struct platform_device *pdev,
1839 struct emac_priv *priv)
1841 return pdev->dev.platform_data;
1845 * davinci_emac_probe - EMAC device probe
1846 * @pdev: The DaVinci EMAC device that we are removing
1848 * Called when probing for emac devicesr. We get details of instances and
1849 * resource information from platform init and register a network device
1850 * and allocate resources necessary for driver to perform
1852 static int davinci_emac_probe(struct platform_device *pdev)
1855 struct resource *res;
1856 struct net_device *ndev;
1857 struct emac_priv *priv;
1858 unsigned long size, hw_ram_addr;
1859 struct emac_platform_data *pdata;
1860 struct device *emac_dev;
1861 struct cpdma_params dma_params;
1862 struct clk *emac_clk;
1863 unsigned long emac_bus_frequency;
1866 /* obtain emac clock from kernel */
1867 emac_clk = clk_get(&pdev->dev, NULL);
1868 if (IS_ERR(emac_clk)) {
1869 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1872 emac_bus_frequency = clk_get_rate(emac_clk);
1875 /* TODO: Probe PHY here if possible */
1877 ndev = alloc_etherdev(sizeof(struct emac_priv));
1883 platform_set_drvdata(pdev, ndev);
1884 priv = netdev_priv(ndev);
1887 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1889 spin_lock_init(&priv->lock);
1891 pdata = davinci_emac_of_get_pdata(pdev, priv);
1893 dev_err(&pdev->dev, "no platform data\n");
1898 /* MAC addr and PHY mask , RMII enable info from platform_data */
1899 memcpy(priv->mac_addr, pdata->mac_addr, 6);
1900 priv->phy_id = pdata->phy_id;
1901 priv->rmii_en = pdata->rmii_en;
1902 priv->version = pdata->version;
1903 priv->int_enable = pdata->interrupt_enable;
1904 priv->int_disable = pdata->interrupt_disable;
1906 priv->coal_intvl = 0;
1907 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1909 emac_dev = &ndev->dev;
1910 /* Get EMAC platform data */
1911 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1913 dev_err(&pdev->dev,"error getting res\n");
1918 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1919 size = resource_size(res);
1920 if (!request_mem_region(res->start, size, ndev->name)) {
1921 dev_err(&pdev->dev, "failed request_mem_region() for regs\n");
1926 priv->remap_addr = ioremap(res->start, size);
1927 if (!priv->remap_addr) {
1928 dev_err(&pdev->dev, "unable to map IO\n");
1930 release_mem_region(res->start, size);
1933 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1934 ndev->base_addr = (unsigned long)priv->remap_addr;
1936 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1938 hw_ram_addr = pdata->hw_ram_addr;
1940 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1942 memset(&dma_params, 0, sizeof(dma_params));
1943 dma_params.dev = emac_dev;
1944 dma_params.dmaregs = priv->emac_base;
1945 dma_params.rxthresh = priv->emac_base + 0x120;
1946 dma_params.rxfree = priv->emac_base + 0x140;
1947 dma_params.txhdp = priv->emac_base + 0x600;
1948 dma_params.rxhdp = priv->emac_base + 0x620;
1949 dma_params.txcp = priv->emac_base + 0x640;
1950 dma_params.rxcp = priv->emac_base + 0x660;
1951 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1952 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1953 dma_params.desc_hw_addr = hw_ram_addr;
1954 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1955 dma_params.desc_align = 16;
1957 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
1958 (u32 __force)res->start + pdata->ctrl_ram_offset;
1960 priv->dma = cpdma_ctlr_create(&dma_params);
1962 dev_err(&pdev->dev, "error initializing DMA\n");
1967 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
1969 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
1971 if (WARN_ON(!priv->txchan || !priv->rxchan)) {
1976 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1978 dev_err(&pdev->dev, "error getting irq res\n");
1982 ndev->irq = res->start;
1984 if (!is_valid_ether_addr(priv->mac_addr)) {
1985 /* Use random MAC if none passed */
1986 eth_hw_addr_random(ndev);
1987 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
1988 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
1992 ndev->netdev_ops = &emac_netdev_ops;
1993 SET_ETHTOOL_OPS(ndev, ðtool_ops);
1994 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
1996 /* register the network device */
1997 SET_NETDEV_DEV(ndev, &pdev->dev);
1998 rc = register_netdev(ndev);
2000 dev_err(&pdev->dev, "error in register_netdev\n");
2006 if (netif_msg_probe(priv)) {
2007 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\
2008 "(regs: %p, irq: %d)\n",
2009 (void *)priv->emac_base_phys, ndev->irq);
2012 pm_runtime_enable(&pdev->dev);
2013 pm_runtime_resume(&pdev->dev);
2019 cpdma_chan_destroy(priv->txchan);
2021 cpdma_chan_destroy(priv->rxchan);
2022 cpdma_ctlr_destroy(priv->dma);
2024 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2025 release_mem_region(res->start, resource_size(res));
2026 iounmap(priv->remap_addr);
2035 * davinci_emac_remove - EMAC device remove
2036 * @pdev: The DaVinci EMAC device that we are removing
2038 * Called when removing the device driver. We disable clock usage and release
2039 * the resources taken up by the driver and unregister network device
2041 static int davinci_emac_remove(struct platform_device *pdev)
2043 struct resource *res;
2044 struct net_device *ndev = platform_get_drvdata(pdev);
2045 struct emac_priv *priv = netdev_priv(ndev);
2047 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2049 platform_set_drvdata(pdev, NULL);
2050 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2053 cpdma_chan_destroy(priv->txchan);
2055 cpdma_chan_destroy(priv->rxchan);
2056 cpdma_ctlr_destroy(priv->dma);
2058 release_mem_region(res->start, resource_size(res));
2060 unregister_netdev(ndev);
2061 iounmap(priv->remap_addr);
2067 static int davinci_emac_suspend(struct device *dev)
2069 struct platform_device *pdev = to_platform_device(dev);
2070 struct net_device *ndev = platform_get_drvdata(pdev);
2072 if (netif_running(ndev))
2073 emac_dev_stop(ndev);
2078 static int davinci_emac_resume(struct device *dev)
2080 struct platform_device *pdev = to_platform_device(dev);
2081 struct net_device *ndev = platform_get_drvdata(pdev);
2083 if (netif_running(ndev))
2084 emac_dev_open(ndev);
2089 static const struct dev_pm_ops davinci_emac_pm_ops = {
2090 .suspend = davinci_emac_suspend,
2091 .resume = davinci_emac_resume,
2094 static const struct of_device_id davinci_emac_of_match[] = {
2095 {.compatible = "ti,davinci-dm6467-emac", },
2098 MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2100 /* davinci_emac_driver: EMAC platform driver structure */
2101 static struct platform_driver davinci_emac_driver = {
2103 .name = "davinci_emac",
2104 .owner = THIS_MODULE,
2105 .pm = &davinci_emac_pm_ops,
2106 .of_match_table = of_match_ptr(davinci_emac_of_match),
2108 .probe = davinci_emac_probe,
2109 .remove = davinci_emac_remove,
2113 * davinci_emac_init - EMAC driver module init
2115 * Called when initializing the driver. We register the driver with
2118 static int __init davinci_emac_init(void)
2120 return platform_driver_register(&davinci_emac_driver);
2122 late_initcall(davinci_emac_init);
2125 * davinci_emac_exit - EMAC driver module exit
2127 * Called when exiting the driver completely. We unregister the driver with
2128 * the platform and exit
2130 static void __exit davinci_emac_exit(void)
2132 platform_driver_unregister(&davinci_emac_driver);
2134 module_exit(davinci_emac_exit);
2136 MODULE_LICENSE("GPL");
2137 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2138 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2139 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");