2 * Texas Instruments Ethernet Switch Driver
4 * Copyright (C) 2012 Texas Instruments
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/timer.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/irqreturn.h>
23 #include <linux/interrupt.h>
24 #include <linux/if_ether.h>
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/net_tstamp.h>
28 #include <linux/phy.h>
29 #include <linux/workqueue.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
33 #include <linux/of_net.h>
34 #include <linux/of_device.h>
35 #include <linux/if_vlan.h>
36 #include <linux/mfd/syscon.h>
37 #include <linux/regmap.h>
39 #include <linux/pinctrl/consumer.h>
44 #include "davinci_cpdma.h"
46 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
47 NETIF_MSG_DRV | NETIF_MSG_LINK | \
48 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
49 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
50 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
51 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
52 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
55 #define cpsw_info(priv, type, format, ...) \
57 if (netif_msg_##type(priv) && net_ratelimit()) \
58 dev_info(priv->dev, format, ## __VA_ARGS__); \
61 #define cpsw_err(priv, type, format, ...) \
63 if (netif_msg_##type(priv) && net_ratelimit()) \
64 dev_err(priv->dev, format, ## __VA_ARGS__); \
67 #define cpsw_dbg(priv, type, format, ...) \
69 if (netif_msg_##type(priv) && net_ratelimit()) \
70 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
73 #define cpsw_notice(priv, type, format, ...) \
75 if (netif_msg_##type(priv) && net_ratelimit()) \
76 dev_notice(priv->dev, format, ## __VA_ARGS__); \
79 #define ALE_ALL_PORTS 0x7
81 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
82 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
83 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
85 #define CPSW_VERSION_1 0x19010a
86 #define CPSW_VERSION_2 0x19010c
87 #define CPSW_VERSION_3 0x19010f
88 #define CPSW_VERSION_4 0x190112
90 #define HOST_PORT_NUM 0
91 #define SLIVER_SIZE 0x40
93 #define CPSW1_HOST_PORT_OFFSET 0x028
94 #define CPSW1_SLAVE_OFFSET 0x050
95 #define CPSW1_SLAVE_SIZE 0x040
96 #define CPSW1_CPDMA_OFFSET 0x100
97 #define CPSW1_STATERAM_OFFSET 0x200
98 #define CPSW1_HW_STATS 0x400
99 #define CPSW1_CPTS_OFFSET 0x500
100 #define CPSW1_ALE_OFFSET 0x600
101 #define CPSW1_SLIVER_OFFSET 0x700
103 #define CPSW2_HOST_PORT_OFFSET 0x108
104 #define CPSW2_SLAVE_OFFSET 0x200
105 #define CPSW2_SLAVE_SIZE 0x100
106 #define CPSW2_CPDMA_OFFSET 0x800
107 #define CPSW2_HW_STATS 0x900
108 #define CPSW2_STATERAM_OFFSET 0xa00
109 #define CPSW2_CPTS_OFFSET 0xc00
110 #define CPSW2_ALE_OFFSET 0xd00
111 #define CPSW2_SLIVER_OFFSET 0xd80
112 #define CPSW2_BD_OFFSET 0x2000
114 #define CPDMA_RXTHRESH 0x0c0
115 #define CPDMA_RXFREE 0x0e0
116 #define CPDMA_TXHDP 0x00
117 #define CPDMA_RXHDP 0x20
118 #define CPDMA_TXCP 0x40
119 #define CPDMA_RXCP 0x60
121 #define CPSW_POLL_WEIGHT 64
122 #define CPSW_MIN_PACKET_SIZE 60
123 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4)
125 #define RX_PRIORITY_MAPPING 0x76543210
126 #define TX_PRIORITY_MAPPING 0x33221100
127 #define CPDMA_TX_PRIORITY_MAP 0x76543210
129 #define CPSW_VLAN_AWARE BIT(1)
130 #define CPSW_ALE_VLAN_AWARE 1
132 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
133 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
134 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
136 #define CPSW_INTPACEEN (0x3f << 16)
137 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
138 #define CPSW_CMINTMAX_CNT 63
139 #define CPSW_CMINTMIN_CNT 2
140 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
141 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
143 #define cpsw_enable_irq(priv) \
146 for (i = 0; i < priv->num_irqs; i++) \
147 enable_irq(priv->irqs_table[i]); \
149 #define cpsw_disable_irq(priv) \
152 for (i = 0; i < priv->num_irqs; i++) \
153 disable_irq_nosync(priv->irqs_table[i]); \
156 #define cpsw_slave_index(priv) \
157 ((priv->data.dual_emac) ? priv->emac_port : \
158 priv->data.active_slave)
160 static int debug_level;
161 module_param(debug_level, int, 0);
162 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
164 static int ale_ageout = 10;
165 module_param(ale_ageout, int, 0);
166 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
168 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
169 module_param(rx_packet_max, int, 0);
170 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
172 struct cpsw_wr_regs {
192 struct cpsw_ss_regs {
209 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
210 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
211 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
212 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
213 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
214 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
215 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
216 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
219 #define CPSW2_CONTROL 0x00 /* Control Register */
220 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
221 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
222 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
223 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
224 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
225 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
227 /* CPSW_PORT_V1 and V2 */
228 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
229 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
230 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
232 /* CPSW_PORT_V2 only */
233 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
234 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
235 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
236 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
237 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
238 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
239 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
240 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
242 /* Bit definitions for the CPSW2_CONTROL register */
243 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */
244 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */
245 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */
246 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */
247 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */
248 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */
249 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */
250 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */
251 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */
252 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */
253 #define TS_TTL_NONZERO (1<<8) /* Time Sync Time To Live Non-zero enable */
254 #define TS_ANNEX_F_EN (1<<6) /* Time Sync Annex F enable */
255 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */
256 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */
257 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */
258 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */
259 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */
261 #define CTRL_V2_TS_BITS \
262 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
263 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN)
265 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
266 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
267 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
270 #define CTRL_V3_TS_BITS \
271 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
272 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
275 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
276 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
277 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
279 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
280 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
281 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
282 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
283 #define TS_MSG_TYPE_EN_MASK (0xffff)
285 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
286 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
288 /* Bit definitions for the CPSW1_TS_CTL register */
289 #define CPSW_V1_TS_RX_EN BIT(0)
290 #define CPSW_V1_TS_TX_EN BIT(4)
291 #define CPSW_V1_MSG_TYPE_OFS 16
293 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
294 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
296 struct cpsw_host_regs {
302 u32 cpdma_tx_pri_map;
303 u32 cpdma_rx_chan_map;
306 struct cpsw_sliver_regs {
319 struct cpsw_hw_stats {
321 u32 rxbroadcastframes;
322 u32 rxmulticastframes;
325 u32 rxaligncodeerrors;
326 u32 rxoversizedframes;
328 u32 rxundersizedframes;
333 u32 txbroadcastframes;
334 u32 txmulticastframes;
336 u32 txdeferredframes;
337 u32 txcollisionframes;
338 u32 txsinglecollframes;
339 u32 txmultcollframes;
340 u32 txexcessivecollisions;
341 u32 txlatecollisions;
343 u32 txcarriersenseerrors;
346 u32 octetframes65t127;
347 u32 octetframes128t255;
348 u32 octetframes256t511;
349 u32 octetframes512t1023;
350 u32 octetframes1024tup;
359 struct cpsw_sliver_regs __iomem *sliver;
362 struct cpsw_slave_data *data;
363 struct phy_device *phy;
364 struct net_device *ndev;
369 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
371 return __raw_readl(slave->regs + offset);
374 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
376 __raw_writel(val, slave->regs + offset);
381 struct platform_device *pdev;
382 struct net_device *ndev;
383 struct napi_struct napi;
385 struct cpsw_platform_data data;
386 struct cpsw_ss_regs __iomem *regs;
387 struct cpsw_wr_regs __iomem *wr_regs;
388 u8 __iomem *hw_stats;
389 struct cpsw_host_regs __iomem *host_port_regs;
397 u8 mac_addr[ETH_ALEN];
398 struct cpsw_slave *slaves;
399 struct cpdma_ctlr *dma;
400 struct cpdma_chan *txch, *rxch;
401 struct cpsw_ale *ale;
404 /* snapshot of IRQ numbers */
413 char stat_string[ETH_GSTRING_LEN];
425 #define CPSW_STAT(m) CPSW_STATS, \
426 sizeof(((struct cpsw_hw_stats *)0)->m), \
427 offsetof(struct cpsw_hw_stats, m)
428 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \
429 sizeof(((struct cpdma_chan_stats *)0)->m), \
430 offsetof(struct cpdma_chan_stats, m)
431 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \
432 sizeof(((struct cpdma_chan_stats *)0)->m), \
433 offsetof(struct cpdma_chan_stats, m)
435 static const struct cpsw_stats cpsw_gstrings_stats[] = {
436 { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
437 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
438 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
439 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
440 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
441 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
442 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
443 { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
444 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
445 { "Rx Fragments", CPSW_STAT(rxfragments) },
446 { "Rx Octets", CPSW_STAT(rxoctets) },
447 { "Good Tx Frames", CPSW_STAT(txgoodframes) },
448 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
449 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
450 { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
451 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
452 { "Collisions", CPSW_STAT(txcollisionframes) },
453 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
454 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
455 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
456 { "Late Collisions", CPSW_STAT(txlatecollisions) },
457 { "Tx Underrun", CPSW_STAT(txunderrun) },
458 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
459 { "Tx Octets", CPSW_STAT(txoctets) },
460 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
461 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
462 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
463 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
464 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
465 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
466 { "Net Octets", CPSW_STAT(netoctets) },
467 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
468 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
469 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
470 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
471 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
472 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
473 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
474 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
475 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
476 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
477 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
478 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
479 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
480 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
481 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
482 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
483 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
484 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
485 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
486 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
487 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
488 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
489 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
490 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
491 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
492 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
493 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
494 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
495 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
498 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats)
500 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi)
501 #define for_each_slave(priv, func, arg...) \
503 struct cpsw_slave *slave; \
505 if (priv->data.dual_emac) \
506 (func)((priv)->slaves + priv->emac_port, ##arg);\
508 for (n = (priv)->data.slaves, \
509 slave = (priv)->slaves; \
511 (func)(slave++, ##arg); \
513 #define cpsw_get_slave_ndev(priv, __slave_no__) \
514 (priv->slaves[__slave_no__].ndev)
515 #define cpsw_get_slave_priv(priv, __slave_no__) \
516 ((priv->slaves[__slave_no__].ndev) ? \
517 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \
519 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \
521 if (!priv->data.dual_emac) \
523 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \
524 ndev = cpsw_get_slave_ndev(priv, 0); \
525 priv = netdev_priv(ndev); \
527 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \
528 ndev = cpsw_get_slave_ndev(priv, 1); \
529 priv = netdev_priv(ndev); \
533 #define cpsw_add_mcast(priv, addr) \
535 if (priv->data.dual_emac) { \
536 struct cpsw_slave *slave = priv->slaves + \
538 int slave_port = cpsw_get_slave_port(priv, \
540 cpsw_ale_add_mcast(priv->ale, addr, \
541 1 << slave_port | 1 << priv->host_port, \
542 ALE_VLAN, slave->port_vlan, 0); \
544 cpsw_ale_add_mcast(priv->ale, addr, \
545 ALE_ALL_PORTS << priv->host_port, \
550 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
552 if (priv->host_port == 0)
553 return slave_num + 1;
558 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
560 struct cpsw_priv *priv = netdev_priv(ndev);
561 struct cpsw_ale *ale = priv->ale;
564 if (priv->data.dual_emac) {
567 /* Enabling promiscuous mode for one interface will be
568 * common for both the interface as the interface shares
569 * the same hardware resource.
571 for (i = 0; i < priv->data.slaves; i++)
572 if (priv->slaves[i].ndev->flags & IFF_PROMISC)
575 if (!enable && flag) {
577 dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
582 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
584 dev_dbg(&ndev->dev, "promiscuity enabled\n");
587 cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
588 dev_dbg(&ndev->dev, "promiscuity disabled\n");
592 unsigned long timeout = jiffies + HZ;
594 /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
595 for (i = 0; i <= priv->data.slaves; i++) {
596 cpsw_ale_control_set(ale, i,
597 ALE_PORT_NOLEARN, 1);
598 cpsw_ale_control_set(ale, i,
599 ALE_PORT_NO_SA_UPDATE, 1);
602 /* Clear All Untouched entries */
603 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
606 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
608 } while (time_after(timeout, jiffies));
609 cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
611 /* Clear all mcast from ALE */
612 cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
613 priv->host_port, -1);
615 /* Flood All Unicast Packets to Host port */
616 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
617 dev_dbg(&ndev->dev, "promiscuity enabled\n");
619 /* Don't Flood All Unicast Packets to Host port */
620 cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
622 /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
623 for (i = 0; i <= priv->data.slaves; i++) {
624 cpsw_ale_control_set(ale, i,
625 ALE_PORT_NOLEARN, 0);
626 cpsw_ale_control_set(ale, i,
627 ALE_PORT_NO_SA_UPDATE, 0);
629 dev_dbg(&ndev->dev, "promiscuity disabled\n");
634 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
636 struct cpsw_priv *priv = netdev_priv(ndev);
639 if (priv->data.dual_emac)
640 vid = priv->slaves[priv->emac_port].port_vlan;
642 vid = priv->data.default_vlan;
644 if (ndev->flags & IFF_PROMISC) {
645 /* Enable promiscuous mode */
646 cpsw_set_promiscious(ndev, true);
647 cpsw_ale_set_allmulti(priv->ale, IFF_ALLMULTI);
650 /* Disable promiscuous mode */
651 cpsw_set_promiscious(ndev, false);
654 /* Restore allmulti on vlans if necessary */
655 cpsw_ale_set_allmulti(priv->ale, priv->ndev->flags & IFF_ALLMULTI);
657 /* Clear all mcast from ALE */
658 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port,
661 if (!netdev_mc_empty(ndev)) {
662 struct netdev_hw_addr *ha;
664 /* program multicast address list into ALE register */
665 netdev_for_each_mc_addr(ha, ndev) {
666 cpsw_add_mcast(priv, (u8 *)ha->addr);
671 static void cpsw_intr_enable(struct cpsw_priv *priv)
673 __raw_writel(0xFF, &priv->wr_regs->tx_en);
674 __raw_writel(0xFF, &priv->wr_regs->rx_en);
676 cpdma_ctlr_int_ctrl(priv->dma, true);
680 static void cpsw_intr_disable(struct cpsw_priv *priv)
682 __raw_writel(0, &priv->wr_regs->tx_en);
683 __raw_writel(0, &priv->wr_regs->rx_en);
685 cpdma_ctlr_int_ctrl(priv->dma, false);
689 static void cpsw_tx_handler(void *token, int len, int status)
691 struct sk_buff *skb = token;
692 struct net_device *ndev = skb->dev;
693 struct cpsw_priv *priv = netdev_priv(ndev);
695 /* Check whether the queue is stopped due to stalled tx dma, if the
696 * queue is stopped then start the queue as we have free desc for tx
698 if (unlikely(netif_queue_stopped(ndev)))
699 netif_wake_queue(ndev);
700 cpts_tx_timestamp(priv->cpts, skb);
701 ndev->stats.tx_packets++;
702 ndev->stats.tx_bytes += len;
703 dev_kfree_skb_any(skb);
706 static void cpsw_rx_handler(void *token, int len, int status)
708 struct sk_buff *skb = token;
709 struct sk_buff *new_skb;
710 struct net_device *ndev = skb->dev;
711 struct cpsw_priv *priv = netdev_priv(ndev);
714 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
716 if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
717 bool ndev_status = false;
718 struct cpsw_slave *slave = priv->slaves;
721 if (priv->data.dual_emac) {
722 /* In dual emac mode check for all interfaces */
723 for (n = priv->data.slaves; n; n--, slave++)
724 if (netif_running(slave->ndev))
728 if (ndev_status && (status >= 0)) {
729 /* The packet received is for the interface which
730 * is already down and the other interface is up
731 * and running, intead of freeing which results
732 * in reducing of the number of rx descriptor in
733 * DMA engine, requeue skb back to cpdma.
739 /* the interface is going down, skbs are purged */
740 dev_kfree_skb_any(skb);
744 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
747 cpts_rx_timestamp(priv->cpts, skb);
748 skb->protocol = eth_type_trans(skb, ndev);
749 netif_receive_skb(skb);
750 ndev->stats.rx_bytes += len;
751 ndev->stats.rx_packets++;
753 ndev->stats.rx_dropped++;
758 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
759 skb_tailroom(new_skb), 0);
760 if (WARN_ON(ret < 0))
761 dev_kfree_skb_any(new_skb);
764 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
766 struct cpsw_priv *priv = dev_id;
768 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
769 cpdma_chan_process(priv->txch, 128);
771 priv = cpsw_get_slave_priv(priv, 1);
773 cpdma_chan_process(priv->txch, 128);
778 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
780 struct cpsw_priv *priv = dev_id;
782 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
784 cpsw_intr_disable(priv);
785 if (priv->irq_enabled == true) {
786 cpsw_disable_irq(priv);
787 priv->irq_enabled = false;
790 if (netif_running(priv->ndev)) {
791 napi_schedule(&priv->napi);
795 priv = cpsw_get_slave_priv(priv, 1);
799 if (netif_running(priv->ndev)) {
800 napi_schedule(&priv->napi);
806 static int cpsw_poll(struct napi_struct *napi, int budget)
808 struct cpsw_priv *priv = napi_to_priv(napi);
811 num_tx = cpdma_chan_process(priv->txch, 128);
813 num_rx = cpdma_chan_process(priv->rxch, budget);
814 if (num_rx < budget) {
815 struct cpsw_priv *prim_cpsw;
818 cpsw_intr_enable(priv);
819 prim_cpsw = cpsw_get_slave_priv(priv, 0);
820 if (prim_cpsw->irq_enabled == false) {
821 prim_cpsw->irq_enabled = true;
822 cpsw_enable_irq(priv);
826 if (num_rx || num_tx)
827 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
833 static inline void soft_reset(const char *module, void __iomem *reg)
835 unsigned long timeout = jiffies + HZ;
837 __raw_writel(1, reg);
840 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
842 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
845 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
846 ((mac)[2] << 16) | ((mac)[3] << 24))
847 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
849 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
850 struct cpsw_priv *priv)
852 slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
853 slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
856 static void _cpsw_adjust_link(struct cpsw_slave *slave,
857 struct cpsw_priv *priv, bool *link)
859 struct phy_device *phy = slave->phy;
866 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
869 mac_control = priv->data.mac_control;
871 /* enable forwarding */
872 cpsw_ale_control_set(priv->ale, slave_port,
873 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
875 if (phy->speed == 1000)
876 mac_control |= BIT(7); /* GIGABITEN */
878 mac_control |= BIT(0); /* FULLDUPLEXEN */
880 /* set speed_in input in case RMII mode is used in 100Mbps */
881 if (phy->speed == 100)
882 mac_control |= BIT(15);
883 else if (phy->speed == 10)
884 mac_control |= BIT(18); /* In Band mode */
887 mac_control |= BIT(3);
890 mac_control |= BIT(4);
895 /* disable forwarding */
896 cpsw_ale_control_set(priv->ale, slave_port,
897 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
900 if (mac_control != slave->mac_control) {
901 phy_print_status(phy);
902 __raw_writel(mac_control, &slave->sliver->mac_control);
905 slave->mac_control = mac_control;
908 static void cpsw_adjust_link(struct net_device *ndev)
910 struct cpsw_priv *priv = netdev_priv(ndev);
913 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
916 netif_carrier_on(ndev);
917 if (netif_running(ndev))
918 netif_wake_queue(ndev);
920 netif_carrier_off(ndev);
921 netif_stop_queue(ndev);
925 static int cpsw_get_coalesce(struct net_device *ndev,
926 struct ethtool_coalesce *coal)
928 struct cpsw_priv *priv = netdev_priv(ndev);
930 coal->rx_coalesce_usecs = priv->coal_intvl;
934 static int cpsw_set_coalesce(struct net_device *ndev,
935 struct ethtool_coalesce *coal)
937 struct cpsw_priv *priv = netdev_priv(ndev);
939 u32 num_interrupts = 0;
944 coal_intvl = coal->rx_coalesce_usecs;
946 int_ctrl = readl(&priv->wr_regs->int_control);
947 prescale = priv->bus_freq_mhz * 4;
949 if (!coal->rx_coalesce_usecs) {
950 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
954 if (coal_intvl < CPSW_CMINTMIN_INTVL)
955 coal_intvl = CPSW_CMINTMIN_INTVL;
957 if (coal_intvl > CPSW_CMINTMAX_INTVL) {
958 /* Interrupt pacer works with 4us Pulse, we can
959 * throttle further by dilating the 4us pulse.
961 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
963 if (addnl_dvdr > 1) {
964 prescale *= addnl_dvdr;
965 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
966 coal_intvl = (CPSW_CMINTMAX_INTVL
970 coal_intvl = CPSW_CMINTMAX_INTVL;
974 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
975 writel(num_interrupts, &priv->wr_regs->rx_imax);
976 writel(num_interrupts, &priv->wr_regs->tx_imax);
978 int_ctrl |= CPSW_INTPACEEN;
979 int_ctrl &= (~CPSW_INTPRESCALE_MASK);
980 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
983 writel(int_ctrl, &priv->wr_regs->int_control);
985 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
986 if (priv->data.dual_emac) {
989 for (i = 0; i < priv->data.slaves; i++) {
990 priv = netdev_priv(priv->slaves[i].ndev);
991 priv->coal_intvl = coal_intvl;
994 priv->coal_intvl = coal_intvl;
1000 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1004 return CPSW_STATS_LEN;
1010 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1015 switch (stringset) {
1017 for (i = 0; i < CPSW_STATS_LEN; i++) {
1018 memcpy(p, cpsw_gstrings_stats[i].stat_string,
1020 p += ETH_GSTRING_LEN;
1026 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1027 struct ethtool_stats *stats, u64 *data)
1029 struct cpsw_priv *priv = netdev_priv(ndev);
1030 struct cpdma_chan_stats rx_stats;
1031 struct cpdma_chan_stats tx_stats;
1036 /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1037 cpdma_chan_get_stats(priv->rxch, &rx_stats);
1038 cpdma_chan_get_stats(priv->txch, &tx_stats);
1040 for (i = 0; i < CPSW_STATS_LEN; i++) {
1041 switch (cpsw_gstrings_stats[i].type) {
1043 val = readl(priv->hw_stats +
1044 cpsw_gstrings_stats[i].stat_offset);
1048 case CPDMA_RX_STATS:
1049 p = (u8 *)&rx_stats +
1050 cpsw_gstrings_stats[i].stat_offset;
1051 data[i] = *(u32 *)p;
1054 case CPDMA_TX_STATS:
1055 p = (u8 *)&tx_stats +
1056 cpsw_gstrings_stats[i].stat_offset;
1057 data[i] = *(u32 *)p;
1063 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1066 u32 usage_count = 0;
1068 if (!priv->data.dual_emac)
1071 for (i = 0; i < priv->data.slaves; i++)
1072 if (priv->slaves[i].open_stat)
1078 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1079 struct cpsw_priv *priv, struct sk_buff *skb)
1081 if (!priv->data.dual_emac)
1082 return cpdma_chan_submit(priv->txch, skb, skb->data,
1085 if (ndev == cpsw_get_slave_ndev(priv, 0))
1086 return cpdma_chan_submit(priv->txch, skb, skb->data,
1089 return cpdma_chan_submit(priv->txch, skb, skb->data,
1093 static inline void cpsw_add_dual_emac_def_ale_entries(
1094 struct cpsw_priv *priv, struct cpsw_slave *slave,
1097 u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1099 if (priv->version == CPSW_VERSION_1)
1100 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1102 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1103 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1104 port_mask, port_mask, 0);
1105 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1106 port_mask, ALE_VLAN, slave->port_vlan, 0);
1107 cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1108 priv->host_port, ALE_VLAN, slave->port_vlan);
1111 static void soft_reset_slave(struct cpsw_slave *slave)
1115 snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1116 soft_reset(name, &slave->sliver->soft_reset);
1119 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1123 soft_reset_slave(slave);
1125 /* setup priority mapping */
1126 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1128 switch (priv->version) {
1129 case CPSW_VERSION_1:
1130 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1132 case CPSW_VERSION_2:
1133 case CPSW_VERSION_3:
1134 case CPSW_VERSION_4:
1135 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1139 /* setup max packet size, and mac address */
1140 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1141 cpsw_set_slave_mac(slave, priv);
1143 slave->mac_control = 0; /* no link yet */
1145 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1147 if (priv->data.dual_emac)
1148 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1150 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1151 1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1153 slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1154 &cpsw_adjust_link, slave->data->phy_if);
1155 if (IS_ERR(slave->phy)) {
1156 dev_err(priv->dev, "phy %s not found on slave %d\n",
1157 slave->data->phy_id, slave->slave_num);
1160 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1161 slave->phy->phy_id);
1162 phy_start(slave->phy);
1164 /* Configure GMII_SEL register */
1165 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1170 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1172 const int vlan = priv->data.default_vlan;
1173 const int port = priv->host_port;
1176 int unreg_mcast_mask;
1178 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1181 writel(vlan, &priv->host_port_regs->port_vlan);
1183 for (i = 0; i < priv->data.slaves; i++)
1184 slave_write(priv->slaves + i, vlan, reg);
1186 if (priv->ndev->flags & IFF_ALLMULTI)
1187 unreg_mcast_mask = ALE_ALL_PORTS;
1189 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1191 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1192 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1193 unreg_mcast_mask << port);
1196 static void cpsw_init_host_port(struct cpsw_priv *priv)
1201 /* soft reset the controller and initialize ale */
1202 soft_reset("cpsw", &priv->regs->soft_reset);
1203 cpsw_ale_start(priv->ale);
1205 /* switch to vlan unaware mode */
1206 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1207 CPSW_ALE_VLAN_AWARE);
1208 control_reg = readl(&priv->regs->control);
1209 control_reg |= CPSW_VLAN_AWARE;
1210 writel(control_reg, &priv->regs->control);
1211 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1212 CPSW_FIFO_NORMAL_MODE;
1213 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1215 /* setup host port priority mapping */
1216 __raw_writel(CPDMA_TX_PRIORITY_MAP,
1217 &priv->host_port_regs->cpdma_tx_pri_map);
1218 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1220 cpsw_ale_control_set(priv->ale, priv->host_port,
1221 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1223 if (!priv->data.dual_emac) {
1224 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1226 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1227 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1231 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1235 slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1239 phy_stop(slave->phy);
1240 phy_disconnect(slave->phy);
1242 cpsw_ale_control_set(priv->ale, slave_port,
1243 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1246 static int cpsw_ndo_open(struct net_device *ndev)
1248 struct cpsw_priv *priv = netdev_priv(ndev);
1249 struct cpsw_priv *prim_cpsw;
1253 if (!cpsw_common_res_usage_state(priv))
1254 cpsw_intr_disable(priv);
1255 netif_carrier_off(ndev);
1257 pm_runtime_get_sync(&priv->pdev->dev);
1259 reg = priv->version;
1261 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1262 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1263 CPSW_RTL_VERSION(reg));
1265 /* initialize host and slave ports */
1266 if (!cpsw_common_res_usage_state(priv))
1267 cpsw_init_host_port(priv);
1268 for_each_slave(priv, cpsw_slave_open, priv);
1270 /* Add default VLAN */
1271 if (!priv->data.dual_emac)
1272 cpsw_add_default_vlan(priv);
1274 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1275 ALE_ALL_PORTS << priv->host_port,
1276 ALE_ALL_PORTS << priv->host_port, 0, 0);
1278 if (!cpsw_common_res_usage_state(priv)) {
1279 /* setup tx dma to fixed prio and zero offset */
1280 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1281 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1283 /* disable priority elevation */
1284 __raw_writel(0, &priv->regs->ptype);
1286 /* enable statistics collection only on all ports */
1287 __raw_writel(0x7, &priv->regs->stat_port_en);
1289 /* Enable internal fifo flow control */
1290 writel(0x7, &priv->regs->flow_control);
1292 if (WARN_ON(!priv->data.rx_descs))
1293 priv->data.rx_descs = 128;
1295 for (i = 0; i < priv->data.rx_descs; i++) {
1296 struct sk_buff *skb;
1299 skb = __netdev_alloc_skb_ip_align(priv->ndev,
1300 priv->rx_packet_max, GFP_KERNEL);
1303 ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1304 skb_tailroom(skb), 0);
1310 /* continue even if we didn't manage to submit all
1313 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1315 if (cpts_register(&priv->pdev->dev, priv->cpts,
1316 priv->data.cpts_clock_mult,
1317 priv->data.cpts_clock_shift))
1318 dev_err(priv->dev, "error registering cpts device\n");
1322 /* Enable Interrupt pacing if configured */
1323 if (priv->coal_intvl != 0) {
1324 struct ethtool_coalesce coal;
1326 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1327 cpsw_set_coalesce(ndev, &coal);
1330 napi_enable(&priv->napi);
1331 cpdma_ctlr_start(priv->dma);
1332 cpsw_intr_enable(priv);
1334 prim_cpsw = cpsw_get_slave_priv(priv, 0);
1335 if (prim_cpsw->irq_enabled == false) {
1336 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1337 prim_cpsw->irq_enabled = true;
1338 cpsw_enable_irq(prim_cpsw);
1342 if (priv->data.dual_emac)
1343 priv->slaves[priv->emac_port].open_stat = true;
1347 cpdma_ctlr_stop(priv->dma);
1348 for_each_slave(priv, cpsw_slave_stop, priv);
1349 pm_runtime_put_sync(&priv->pdev->dev);
1350 netif_carrier_off(priv->ndev);
1354 static int cpsw_ndo_stop(struct net_device *ndev)
1356 struct cpsw_priv *priv = netdev_priv(ndev);
1358 cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1359 netif_stop_queue(priv->ndev);
1360 napi_disable(&priv->napi);
1361 netif_carrier_off(priv->ndev);
1363 if (cpsw_common_res_usage_state(priv) <= 1) {
1364 cpts_unregister(priv->cpts);
1365 cpsw_intr_disable(priv);
1366 cpdma_ctlr_int_ctrl(priv->dma, false);
1367 cpdma_ctlr_stop(priv->dma);
1368 cpsw_ale_stop(priv->ale);
1370 for_each_slave(priv, cpsw_slave_stop, priv);
1371 pm_runtime_put_sync(&priv->pdev->dev);
1372 if (priv->data.dual_emac)
1373 priv->slaves[priv->emac_port].open_stat = false;
1377 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1378 struct net_device *ndev)
1380 struct cpsw_priv *priv = netdev_priv(ndev);
1383 ndev->trans_start = jiffies;
1385 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1386 cpsw_err(priv, tx_err, "packet pad failed\n");
1387 ndev->stats.tx_dropped++;
1388 return NETDEV_TX_OK;
1391 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1392 priv->cpts->tx_enable)
1393 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1395 skb_tx_timestamp(skb);
1397 ret = cpsw_tx_packet_submit(ndev, priv, skb);
1398 if (unlikely(ret != 0)) {
1399 cpsw_err(priv, tx_err, "desc submit failed\n");
1403 /* If there is no more tx desc left free then we need to
1404 * tell the kernel to stop sending us tx frames.
1406 if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1407 netif_stop_queue(ndev);
1409 return NETDEV_TX_OK;
1411 ndev->stats.tx_dropped++;
1412 netif_stop_queue(ndev);
1413 return NETDEV_TX_BUSY;
1416 #ifdef CONFIG_TI_CPTS
1418 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1420 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1423 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1424 slave_write(slave, 0, CPSW1_TS_CTL);
1428 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1429 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1431 if (priv->cpts->tx_enable)
1432 ts_en |= CPSW_V1_TS_TX_EN;
1434 if (priv->cpts->rx_enable)
1435 ts_en |= CPSW_V1_TS_RX_EN;
1437 slave_write(slave, ts_en, CPSW1_TS_CTL);
1438 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1441 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1443 struct cpsw_slave *slave;
1446 if (priv->data.dual_emac)
1447 slave = &priv->slaves[priv->emac_port];
1449 slave = &priv->slaves[priv->data.active_slave];
1451 ctrl = slave_read(slave, CPSW2_CONTROL);
1452 switch (priv->version) {
1453 case CPSW_VERSION_2:
1454 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1456 if (priv->cpts->tx_enable)
1457 ctrl |= CTRL_V2_TX_TS_BITS;
1459 if (priv->cpts->rx_enable)
1460 ctrl |= CTRL_V2_RX_TS_BITS;
1462 case CPSW_VERSION_3:
1464 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1466 if (priv->cpts->tx_enable)
1467 ctrl |= CTRL_V3_TX_TS_BITS;
1469 if (priv->cpts->rx_enable)
1470 ctrl |= CTRL_V3_RX_TS_BITS;
1474 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1476 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1477 slave_write(slave, ctrl, CPSW2_CONTROL);
1478 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1481 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1483 struct cpsw_priv *priv = netdev_priv(dev);
1484 struct cpts *cpts = priv->cpts;
1485 struct hwtstamp_config cfg;
1487 if (priv->version != CPSW_VERSION_1 &&
1488 priv->version != CPSW_VERSION_2 &&
1489 priv->version != CPSW_VERSION_3)
1492 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1495 /* reserved for future extensions */
1499 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1502 switch (cfg.rx_filter) {
1503 case HWTSTAMP_FILTER_NONE:
1504 cpts->rx_enable = 0;
1506 case HWTSTAMP_FILTER_ALL:
1507 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1508 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1509 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1511 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1512 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1513 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1514 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1515 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1516 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1517 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1518 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1519 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1520 cpts->rx_enable = 1;
1521 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1527 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1529 switch (priv->version) {
1530 case CPSW_VERSION_1:
1531 cpsw_hwtstamp_v1(priv);
1533 case CPSW_VERSION_2:
1534 case CPSW_VERSION_3:
1535 cpsw_hwtstamp_v2(priv);
1541 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1544 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1546 struct cpsw_priv *priv = netdev_priv(dev);
1547 struct cpts *cpts = priv->cpts;
1548 struct hwtstamp_config cfg;
1550 if (priv->version != CPSW_VERSION_1 &&
1551 priv->version != CPSW_VERSION_2 &&
1552 priv->version != CPSW_VERSION_3)
1556 cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1557 cfg.rx_filter = (cpts->rx_enable ?
1558 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1560 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1563 #endif /*CONFIG_TI_CPTS*/
1565 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1567 struct cpsw_priv *priv = netdev_priv(dev);
1568 int slave_no = cpsw_slave_index(priv);
1570 if (!netif_running(dev))
1574 #ifdef CONFIG_TI_CPTS
1576 return cpsw_hwtstamp_set(dev, req);
1578 return cpsw_hwtstamp_get(dev, req);
1582 if (!priv->slaves[slave_no].phy)
1584 return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1587 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1589 struct cpsw_priv *priv = netdev_priv(ndev);
1591 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1592 ndev->stats.tx_errors++;
1593 cpsw_intr_disable(priv);
1594 cpdma_ctlr_int_ctrl(priv->dma, false);
1595 cpdma_chan_stop(priv->txch);
1596 cpdma_chan_start(priv->txch);
1597 cpdma_ctlr_int_ctrl(priv->dma, true);
1598 cpsw_intr_enable(priv);
1601 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1603 struct cpsw_priv *priv = netdev_priv(ndev);
1604 struct sockaddr *addr = (struct sockaddr *)p;
1608 if (!is_valid_ether_addr(addr->sa_data))
1609 return -EADDRNOTAVAIL;
1611 if (priv->data.dual_emac) {
1612 vid = priv->slaves[priv->emac_port].port_vlan;
1616 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1618 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1621 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1622 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1623 for_each_slave(priv, cpsw_set_slave_mac, priv);
1628 #ifdef CONFIG_NET_POLL_CONTROLLER
1629 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1631 struct cpsw_priv *priv = netdev_priv(ndev);
1633 cpsw_intr_disable(priv);
1634 cpdma_ctlr_int_ctrl(priv->dma, false);
1635 cpsw_rx_interrupt(priv->irqs_table[0], priv);
1636 cpsw_tx_interrupt(priv->irqs_table[1], priv);
1637 cpdma_ctlr_int_ctrl(priv->dma, true);
1638 cpsw_intr_enable(priv);
1642 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1646 int unreg_mcast_mask;
1648 if (priv->ndev->flags & IFF_ALLMULTI)
1649 unreg_mcast_mask = ALE_ALL_PORTS;
1651 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1653 ret = cpsw_ale_add_vlan(priv->ale, vid,
1654 ALE_ALL_PORTS << priv->host_port,
1655 0, ALE_ALL_PORTS << priv->host_port,
1656 unreg_mcast_mask << priv->host_port);
1660 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1661 priv->host_port, ALE_VLAN, vid);
1665 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1666 ALE_ALL_PORTS << priv->host_port,
1669 goto clean_vlan_ucast;
1673 cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1674 priv->host_port, ALE_VLAN, vid);
1676 cpsw_ale_del_vlan(priv->ale, vid, 0);
1680 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1681 __be16 proto, u16 vid)
1683 struct cpsw_priv *priv = netdev_priv(ndev);
1685 if (vid == priv->data.default_vlan)
1688 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1689 return cpsw_add_vlan_ale_entry(priv, vid);
1692 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1693 __be16 proto, u16 vid)
1695 struct cpsw_priv *priv = netdev_priv(ndev);
1698 if (vid == priv->data.default_vlan)
1701 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1702 ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1706 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1707 priv->host_port, ALE_VLAN, vid);
1711 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1715 static const struct net_device_ops cpsw_netdev_ops = {
1716 .ndo_open = cpsw_ndo_open,
1717 .ndo_stop = cpsw_ndo_stop,
1718 .ndo_start_xmit = cpsw_ndo_start_xmit,
1719 .ndo_set_mac_address = cpsw_ndo_set_mac_address,
1720 .ndo_do_ioctl = cpsw_ndo_ioctl,
1721 .ndo_validate_addr = eth_validate_addr,
1722 .ndo_change_mtu = eth_change_mtu,
1723 .ndo_tx_timeout = cpsw_ndo_tx_timeout,
1724 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode,
1725 #ifdef CONFIG_NET_POLL_CONTROLLER
1726 .ndo_poll_controller = cpsw_ndo_poll_controller,
1728 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid,
1729 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid,
1732 static int cpsw_get_regs_len(struct net_device *ndev)
1734 struct cpsw_priv *priv = netdev_priv(ndev);
1736 return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1739 static void cpsw_get_regs(struct net_device *ndev,
1740 struct ethtool_regs *regs, void *p)
1742 struct cpsw_priv *priv = netdev_priv(ndev);
1745 /* update CPSW IP version */
1746 regs->version = priv->version;
1748 cpsw_ale_dump(priv->ale, reg);
1751 static void cpsw_get_drvinfo(struct net_device *ndev,
1752 struct ethtool_drvinfo *info)
1754 struct cpsw_priv *priv = netdev_priv(ndev);
1756 strlcpy(info->driver, "cpsw", sizeof(info->driver));
1757 strlcpy(info->version, "1.0", sizeof(info->version));
1758 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1759 info->regdump_len = cpsw_get_regs_len(ndev);
1762 static u32 cpsw_get_msglevel(struct net_device *ndev)
1764 struct cpsw_priv *priv = netdev_priv(ndev);
1765 return priv->msg_enable;
1768 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1770 struct cpsw_priv *priv = netdev_priv(ndev);
1771 priv->msg_enable = value;
1774 static int cpsw_get_ts_info(struct net_device *ndev,
1775 struct ethtool_ts_info *info)
1777 #ifdef CONFIG_TI_CPTS
1778 struct cpsw_priv *priv = netdev_priv(ndev);
1780 info->so_timestamping =
1781 SOF_TIMESTAMPING_TX_HARDWARE |
1782 SOF_TIMESTAMPING_TX_SOFTWARE |
1783 SOF_TIMESTAMPING_RX_HARDWARE |
1784 SOF_TIMESTAMPING_RX_SOFTWARE |
1785 SOF_TIMESTAMPING_SOFTWARE |
1786 SOF_TIMESTAMPING_RAW_HARDWARE;
1787 info->phc_index = priv->cpts->phc_index;
1789 (1 << HWTSTAMP_TX_OFF) |
1790 (1 << HWTSTAMP_TX_ON);
1792 (1 << HWTSTAMP_FILTER_NONE) |
1793 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1795 info->so_timestamping =
1796 SOF_TIMESTAMPING_TX_SOFTWARE |
1797 SOF_TIMESTAMPING_RX_SOFTWARE |
1798 SOF_TIMESTAMPING_SOFTWARE;
1799 info->phc_index = -1;
1801 info->rx_filters = 0;
1806 static int cpsw_get_settings(struct net_device *ndev,
1807 struct ethtool_cmd *ecmd)
1809 struct cpsw_priv *priv = netdev_priv(ndev);
1810 int slave_no = cpsw_slave_index(priv);
1812 if (priv->slaves[slave_no].phy)
1813 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1818 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1820 struct cpsw_priv *priv = netdev_priv(ndev);
1821 int slave_no = cpsw_slave_index(priv);
1823 if (priv->slaves[slave_no].phy)
1824 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1829 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1831 struct cpsw_priv *priv = netdev_priv(ndev);
1832 int slave_no = cpsw_slave_index(priv);
1837 if (priv->slaves[slave_no].phy)
1838 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1841 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1843 struct cpsw_priv *priv = netdev_priv(ndev);
1844 int slave_no = cpsw_slave_index(priv);
1846 if (priv->slaves[slave_no].phy)
1847 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1852 static void cpsw_get_pauseparam(struct net_device *ndev,
1853 struct ethtool_pauseparam *pause)
1855 struct cpsw_priv *priv = netdev_priv(ndev);
1857 pause->autoneg = AUTONEG_DISABLE;
1858 pause->rx_pause = priv->rx_pause ? true : false;
1859 pause->tx_pause = priv->tx_pause ? true : false;
1862 static int cpsw_set_pauseparam(struct net_device *ndev,
1863 struct ethtool_pauseparam *pause)
1865 struct cpsw_priv *priv = netdev_priv(ndev);
1868 priv->rx_pause = pause->rx_pause ? true : false;
1869 priv->tx_pause = pause->tx_pause ? true : false;
1871 for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1876 static const struct ethtool_ops cpsw_ethtool_ops = {
1877 .get_drvinfo = cpsw_get_drvinfo,
1878 .get_msglevel = cpsw_get_msglevel,
1879 .set_msglevel = cpsw_set_msglevel,
1880 .get_link = ethtool_op_get_link,
1881 .get_ts_info = cpsw_get_ts_info,
1882 .get_settings = cpsw_get_settings,
1883 .set_settings = cpsw_set_settings,
1884 .get_coalesce = cpsw_get_coalesce,
1885 .set_coalesce = cpsw_set_coalesce,
1886 .get_sset_count = cpsw_get_sset_count,
1887 .get_strings = cpsw_get_strings,
1888 .get_ethtool_stats = cpsw_get_ethtool_stats,
1889 .get_pauseparam = cpsw_get_pauseparam,
1890 .set_pauseparam = cpsw_set_pauseparam,
1891 .get_wol = cpsw_get_wol,
1892 .set_wol = cpsw_set_wol,
1893 .get_regs_len = cpsw_get_regs_len,
1894 .get_regs = cpsw_get_regs,
1897 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1898 u32 slave_reg_ofs, u32 sliver_reg_ofs)
1900 void __iomem *regs = priv->regs;
1901 int slave_num = slave->slave_num;
1902 struct cpsw_slave_data *data = priv->data.slave_data + slave_num;
1905 slave->regs = regs + slave_reg_ofs;
1906 slave->sliver = regs + sliver_reg_ofs;
1907 slave->port_vlan = data->dual_emac_res_vlan;
1910 #define AM33XX_CTRL_MAC_LO_REG(id) (0x630 + 0x8 * id)
1911 #define AM33XX_CTRL_MAC_HI_REG(id) (0x630 + 0x8 * id + 0x4)
1913 static int cpsw_am33xx_cm_get_macid(struct device *dev, int slave,
1918 struct regmap *syscon;
1920 syscon = syscon_regmap_lookup_by_phandle(dev->of_node, "syscon");
1921 if (IS_ERR(syscon)) {
1922 if (PTR_ERR(syscon) == -ENODEV)
1924 return PTR_ERR(syscon);
1927 regmap_read(syscon, AM33XX_CTRL_MAC_LO_REG(slave), &macid_lo);
1928 regmap_read(syscon, AM33XX_CTRL_MAC_HI_REG(slave), &macid_hi);
1930 mac_addr[5] = (macid_lo >> 8) & 0xff;
1931 mac_addr[4] = macid_lo & 0xff;
1932 mac_addr[3] = (macid_hi >> 24) & 0xff;
1933 mac_addr[2] = (macid_hi >> 16) & 0xff;
1934 mac_addr[1] = (macid_hi >> 8) & 0xff;
1935 mac_addr[0] = macid_hi & 0xff;
1940 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1941 struct platform_device *pdev)
1943 struct device_node *node = pdev->dev.of_node;
1944 struct device_node *slave_node;
1951 if (of_property_read_u32(node, "slaves", &prop)) {
1952 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1955 data->slaves = prop;
1957 if (of_property_read_u32(node, "active_slave", &prop)) {
1958 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1961 data->active_slave = prop;
1963 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1964 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1967 data->cpts_clock_mult = prop;
1969 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1970 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1973 data->cpts_clock_shift = prop;
1975 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1976 * sizeof(struct cpsw_slave_data),
1978 if (!data->slave_data)
1981 if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1982 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1985 data->channels = prop;
1987 if (of_property_read_u32(node, "ale_entries", &prop)) {
1988 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1991 data->ale_entries = prop;
1993 if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1994 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1997 data->bd_ram_size = prop;
1999 if (of_property_read_u32(node, "rx_descs", &prop)) {
2000 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
2003 data->rx_descs = prop;
2005 if (of_property_read_u32(node, "mac_control", &prop)) {
2006 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2009 data->mac_control = prop;
2011 if (of_property_read_bool(node, "dual_emac"))
2012 data->dual_emac = 1;
2015 * Populate all the child nodes here...
2017 ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2018 /* We do not want to force this, as in some cases may not have child */
2020 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2022 for_each_child_of_node(node, slave_node) {
2023 struct cpsw_slave_data *slave_data = data->slave_data + i;
2024 const void *mac_addr = NULL;
2028 struct device_node *mdio_node;
2029 struct platform_device *mdio;
2031 /* This is no slave child node, continue */
2032 if (strcmp(slave_node->name, "slave"))
2035 parp = of_get_property(slave_node, "phy_id", &lenp);
2036 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
2037 dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
2040 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2041 phyid = be32_to_cpup(parp+1);
2042 mdio = of_find_device_by_node(mdio_node);
2043 of_node_put(mdio_node);
2045 dev_err(&pdev->dev, "Missing mdio platform device\n");
2048 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2049 PHY_ID_FMT, mdio->name, phyid);
2051 slave_data->phy_if = of_get_phy_mode(slave_node);
2052 if (slave_data->phy_if < 0) {
2053 dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2055 return slave_data->phy_if;
2059 mac_addr = of_get_mac_address(slave_node);
2061 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2063 if (of_machine_is_compatible("ti,am33xx")) {
2064 ret = cpsw_am33xx_cm_get_macid(&pdev->dev, i,
2065 slave_data->mac_addr);
2070 if (data->dual_emac) {
2071 if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2073 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2074 slave_data->dual_emac_res_vlan = i+1;
2075 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2076 slave_data->dual_emac_res_vlan, i);
2078 slave_data->dual_emac_res_vlan = prop;
2083 if (i == data->slaves)
2090 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2091 struct cpsw_priv *priv)
2093 struct cpsw_platform_data *data = &priv->data;
2094 struct net_device *ndev;
2095 struct cpsw_priv *priv_sl2;
2098 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2100 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2104 priv_sl2 = netdev_priv(ndev);
2105 spin_lock_init(&priv_sl2->lock);
2106 priv_sl2->data = *data;
2107 priv_sl2->pdev = pdev;
2108 priv_sl2->ndev = ndev;
2109 priv_sl2->dev = &ndev->dev;
2110 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2111 priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2113 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2114 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2116 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2118 random_ether_addr(priv_sl2->mac_addr);
2119 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2121 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2123 priv_sl2->slaves = priv->slaves;
2124 priv_sl2->clk = priv->clk;
2126 priv_sl2->coal_intvl = 0;
2127 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2129 priv_sl2->regs = priv->regs;
2130 priv_sl2->host_port = priv->host_port;
2131 priv_sl2->host_port_regs = priv->host_port_regs;
2132 priv_sl2->wr_regs = priv->wr_regs;
2133 priv_sl2->hw_stats = priv->hw_stats;
2134 priv_sl2->dma = priv->dma;
2135 priv_sl2->txch = priv->txch;
2136 priv_sl2->rxch = priv->rxch;
2137 priv_sl2->ale = priv->ale;
2138 priv_sl2->emac_port = 1;
2139 priv->slaves[1].ndev = ndev;
2140 priv_sl2->cpts = priv->cpts;
2141 priv_sl2->version = priv->version;
2143 for (i = 0; i < priv->num_irqs; i++) {
2144 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2145 priv_sl2->num_irqs = priv->num_irqs;
2147 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2149 ndev->netdev_ops = &cpsw_netdev_ops;
2150 ndev->ethtool_ops = &cpsw_ethtool_ops;
2151 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2153 /* register the network device */
2154 SET_NETDEV_DEV(ndev, &pdev->dev);
2155 ret = register_netdev(ndev);
2157 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2165 static int cpsw_probe(struct platform_device *pdev)
2167 struct cpsw_platform_data *data;
2168 struct net_device *ndev;
2169 struct cpsw_priv *priv;
2170 struct cpdma_params dma_params;
2171 struct cpsw_ale_params ale_params;
2172 void __iomem *ss_regs;
2173 struct resource *res, *ss_res;
2174 u32 slave_offset, sliver_offset, slave_size;
2178 ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2180 dev_err(&pdev->dev, "error allocating net_device\n");
2184 platform_set_drvdata(pdev, ndev);
2185 priv = netdev_priv(ndev);
2186 spin_lock_init(&priv->lock);
2189 priv->dev = &ndev->dev;
2190 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2191 priv->rx_packet_max = max(rx_packet_max, 128);
2192 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2193 priv->irq_enabled = true;
2195 dev_err(&pdev->dev, "error allocating cpts\n");
2197 goto clean_ndev_ret;
2201 * This may be required here for child devices.
2203 pm_runtime_enable(&pdev->dev);
2205 /* Select default pin state */
2206 pinctrl_pm_select_default_state(&pdev->dev);
2208 if (cpsw_probe_dt(&priv->data, pdev)) {
2209 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2211 goto clean_runtime_disable_ret;
2215 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2216 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2217 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2219 eth_random_addr(priv->mac_addr);
2220 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2223 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2225 priv->slaves = devm_kzalloc(&pdev->dev,
2226 sizeof(struct cpsw_slave) * data->slaves,
2228 if (!priv->slaves) {
2230 goto clean_runtime_disable_ret;
2232 for (i = 0; i < data->slaves; i++)
2233 priv->slaves[i].slave_num = i;
2235 priv->slaves[0].ndev = ndev;
2236 priv->emac_port = 0;
2238 priv->clk = devm_clk_get(&pdev->dev, "fck");
2239 if (IS_ERR(priv->clk)) {
2240 dev_err(priv->dev, "fck is not found\n");
2242 goto clean_runtime_disable_ret;
2244 priv->coal_intvl = 0;
2245 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2247 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2248 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2249 if (IS_ERR(ss_regs)) {
2250 ret = PTR_ERR(ss_regs);
2251 goto clean_runtime_disable_ret;
2253 priv->regs = ss_regs;
2254 priv->host_port = HOST_PORT_NUM;
2256 /* Need to enable clocks with runtime PM api to access module
2259 pm_runtime_get_sync(&pdev->dev);
2260 priv->version = readl(&priv->regs->id_ver);
2261 pm_runtime_put_sync(&pdev->dev);
2263 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2264 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2265 if (IS_ERR(priv->wr_regs)) {
2266 ret = PTR_ERR(priv->wr_regs);
2267 goto clean_runtime_disable_ret;
2270 memset(&dma_params, 0, sizeof(dma_params));
2271 memset(&ale_params, 0, sizeof(ale_params));
2273 switch (priv->version) {
2274 case CPSW_VERSION_1:
2275 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2276 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET;
2277 priv->hw_stats = ss_regs + CPSW1_HW_STATS;
2278 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET;
2279 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET;
2280 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET;
2281 slave_offset = CPSW1_SLAVE_OFFSET;
2282 slave_size = CPSW1_SLAVE_SIZE;
2283 sliver_offset = CPSW1_SLIVER_OFFSET;
2284 dma_params.desc_mem_phys = 0;
2286 case CPSW_VERSION_2:
2287 case CPSW_VERSION_3:
2288 case CPSW_VERSION_4:
2289 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2290 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET;
2291 priv->hw_stats = ss_regs + CPSW2_HW_STATS;
2292 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET;
2293 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET;
2294 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET;
2295 slave_offset = CPSW2_SLAVE_OFFSET;
2296 slave_size = CPSW2_SLAVE_SIZE;
2297 sliver_offset = CPSW2_SLIVER_OFFSET;
2298 dma_params.desc_mem_phys =
2299 (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2302 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2304 goto clean_runtime_disable_ret;
2306 for (i = 0; i < priv->data.slaves; i++) {
2307 struct cpsw_slave *slave = &priv->slaves[i];
2308 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2309 slave_offset += slave_size;
2310 sliver_offset += SLIVER_SIZE;
2313 dma_params.dev = &pdev->dev;
2314 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH;
2315 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE;
2316 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP;
2317 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP;
2318 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP;
2320 dma_params.num_chan = data->channels;
2321 dma_params.has_soft_reset = true;
2322 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE;
2323 dma_params.desc_mem_size = data->bd_ram_size;
2324 dma_params.desc_align = 16;
2325 dma_params.has_ext_regs = true;
2326 dma_params.desc_hw_addr = dma_params.desc_mem_phys;
2328 priv->dma = cpdma_ctlr_create(&dma_params);
2330 dev_err(priv->dev, "error initializing dma\n");
2332 goto clean_runtime_disable_ret;
2335 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2337 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2340 if (WARN_ON(!priv->txch || !priv->rxch)) {
2341 dev_err(priv->dev, "error initializing dma channels\n");
2346 ale_params.dev = &ndev->dev;
2347 ale_params.ale_ageout = ale_ageout;
2348 ale_params.ale_entries = data->ale_entries;
2349 ale_params.ale_ports = data->slaves;
2351 priv->ale = cpsw_ale_create(&ale_params);
2353 dev_err(priv->dev, "error initializing ale engine\n");
2358 ndev->irq = platform_get_irq(pdev, 1);
2359 if (ndev->irq < 0) {
2360 dev_err(priv->dev, "error getting irq resource\n");
2365 /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
2366 * MISC IRQs which are always kept disabled with this driver so
2367 * we will not request them.
2369 * If anyone wants to implement support for those, make sure to
2370 * first request and append them to irqs_table array.
2374 irq = platform_get_irq(pdev, 1);
2378 priv->irqs_table[0] = irq;
2379 ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
2380 0, dev_name(&pdev->dev), priv);
2382 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2387 irq = platform_get_irq(pdev, 2);
2391 priv->irqs_table[1] = irq;
2392 ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
2393 0, dev_name(&pdev->dev), priv);
2395 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2400 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2402 ndev->netdev_ops = &cpsw_netdev_ops;
2403 ndev->ethtool_ops = &cpsw_ethtool_ops;
2404 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2406 /* register the network device */
2407 SET_NETDEV_DEV(ndev, &pdev->dev);
2408 ret = register_netdev(ndev);
2410 dev_err(priv->dev, "error registering net device\n");
2415 cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2416 &ss_res->start, ndev->irq);
2418 if (priv->data.dual_emac) {
2419 ret = cpsw_probe_dual_emac(pdev, priv);
2421 cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2429 cpsw_ale_destroy(priv->ale);
2431 cpdma_chan_destroy(priv->txch);
2432 cpdma_chan_destroy(priv->rxch);
2433 cpdma_ctlr_destroy(priv->dma);
2434 clean_runtime_disable_ret:
2435 pm_runtime_disable(&pdev->dev);
2437 free_netdev(priv->ndev);
2441 static int cpsw_remove_child_device(struct device *dev, void *c)
2443 struct platform_device *pdev = to_platform_device(dev);
2445 of_device_unregister(pdev);
2450 static int cpsw_remove(struct platform_device *pdev)
2452 struct net_device *ndev = platform_get_drvdata(pdev);
2453 struct cpsw_priv *priv = netdev_priv(ndev);
2455 if (priv->data.dual_emac)
2456 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2457 unregister_netdev(ndev);
2459 cpsw_ale_destroy(priv->ale);
2460 cpdma_chan_destroy(priv->txch);
2461 cpdma_chan_destroy(priv->rxch);
2462 cpdma_ctlr_destroy(priv->dma);
2463 pm_runtime_disable(&pdev->dev);
2464 device_for_each_child(&pdev->dev, NULL, cpsw_remove_child_device);
2465 if (priv->data.dual_emac)
2466 free_netdev(cpsw_get_slave_ndev(priv, 1));
2471 static int cpsw_suspend(struct device *dev)
2473 struct platform_device *pdev = to_platform_device(dev);
2474 struct net_device *ndev = platform_get_drvdata(pdev);
2475 struct cpsw_priv *priv = netdev_priv(ndev);
2477 if (priv->data.dual_emac) {
2480 for (i = 0; i < priv->data.slaves; i++) {
2481 if (netif_running(priv->slaves[i].ndev))
2482 cpsw_ndo_stop(priv->slaves[i].ndev);
2483 soft_reset_slave(priv->slaves + i);
2486 if (netif_running(ndev))
2487 cpsw_ndo_stop(ndev);
2488 for_each_slave(priv, soft_reset_slave);
2491 pm_runtime_put_sync(&pdev->dev);
2493 /* Select sleep pin state */
2494 pinctrl_pm_select_sleep_state(&pdev->dev);
2499 static int cpsw_resume(struct device *dev)
2501 struct platform_device *pdev = to_platform_device(dev);
2502 struct net_device *ndev = platform_get_drvdata(pdev);
2503 struct cpsw_priv *priv = netdev_priv(ndev);
2505 pm_runtime_get_sync(&pdev->dev);
2507 /* Select default pin state */
2508 pinctrl_pm_select_default_state(&pdev->dev);
2510 if (priv->data.dual_emac) {
2513 for (i = 0; i < priv->data.slaves; i++) {
2514 if (netif_running(priv->slaves[i].ndev))
2515 cpsw_ndo_open(priv->slaves[i].ndev);
2518 if (netif_running(ndev))
2519 cpsw_ndo_open(ndev);
2524 static const struct dev_pm_ops cpsw_pm_ops = {
2525 .suspend = cpsw_suspend,
2526 .resume = cpsw_resume,
2529 static const struct of_device_id cpsw_of_mtable[] = {
2530 { .compatible = "ti,cpsw", },
2533 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2535 static struct platform_driver cpsw_driver = {
2539 .of_match_table = cpsw_of_mtable,
2541 .probe = cpsw_probe,
2542 .remove = cpsw_remove,
2545 static int __init cpsw_init(void)
2547 return platform_driver_register(&cpsw_driver);
2549 late_initcall(cpsw_init);
2551 static void __exit cpsw_exit(void)
2553 platform_driver_unregister(&cpsw_driver);
2555 module_exit(cpsw_exit);
2557 MODULE_LICENSE("GPL");
2558 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2559 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2560 MODULE_DESCRIPTION("TI CPSW Ethernet driver");