drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mdio.h>
  35 #include <linux/of_net.h>
  36 #include <linux/of_device.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include <linux/pinctrl/consumer.h>
  40
  41 #include "cpsw.h"
  42 #include "cpsw_ale.h"
  43 #include "cpts.h"
  44 #include "davinci_cpdma.h"
  45
  46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  53                          NETIF_MSG_RX_STATUS)
  54
  55 #define cpsw_info(priv, type, format, ...)              \
  56 do {                                                            \
  57         if (netif_msg_##type(priv) && net_ratelimit())          \
  58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  59 } while (0)
  60
  61 #define cpsw_err(priv, type, format, ...)               \
  62 do {                                                            \
  63         if (netif_msg_##type(priv) && net_ratelimit())          \
  64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  65 } while (0)
  66
  67 #define cpsw_dbg(priv, type, format, ...)               \
  68 do {                                                            \
  69         if (netif_msg_##type(priv) && net_ratelimit())          \
  70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  71 } while (0)
  72
  73 #define cpsw_notice(priv, type, format, ...)            \
  74 do {                                                            \
  75         if (netif_msg_##type(priv) && net_ratelimit())          \
  76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  77 } while (0)
  78
  79 #define ALE_ALL_PORTS           0x7
  80
  81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  84
  85 #define CPSW_VERSION_1          0x19010a
  86 #define CPSW_VERSION_2          0x19010c
  87 #define CPSW_VERSION_3          0x19010f
  88 #define CPSW_VERSION_4          0x190112
  89
  90 #define HOST_PORT_NUM           0
  91 #define CPSW_ALE_PORTS_NUM      3
  92 #define SLIVER_SIZE             0x40
  93
  94 #define CPSW1_HOST_PORT_OFFSET  0x028
  95 #define CPSW1_SLAVE_OFFSET      0x050
  96 #define CPSW1_SLAVE_SIZE        0x040
  97 #define CPSW1_CPDMA_OFFSET      0x100
  98 #define CPSW1_STATERAM_OFFSET   0x200
  99 #define CPSW1_HW_STATS          0x400
 100 #define CPSW1_CPTS_OFFSET       0x500
 101 #define CPSW1_ALE_OFFSET        0x600
 102 #define CPSW1_SLIVER_OFFSET     0x700
 103
 104 #define CPSW2_HOST_PORT_OFFSET  0x108
 105 #define CPSW2_SLAVE_OFFSET      0x200
 106 #define CPSW2_SLAVE_SIZE        0x100
 107 #define CPSW2_CPDMA_OFFSET      0x800
 108 #define CPSW2_HW_STATS          0x900
 109 #define CPSW2_STATERAM_OFFSET   0xa00
 110 #define CPSW2_CPTS_OFFSET       0xc00
 111 #define CPSW2_ALE_OFFSET        0xd00
 112 #define CPSW2_SLIVER_OFFSET     0xd80
 113 #define CPSW2_BD_OFFSET         0x2000
 114
 115 #define CPDMA_RXTHRESH          0x0c0
 116 #define CPDMA_RXFREE            0x0e0
 117 #define CPDMA_TXHDP             0x00
 118 #define CPDMA_RXHDP             0x20
 119 #define CPDMA_TXCP              0x40
 120 #define CPDMA_RXCP              0x60
 121
 122 #define CPSW_POLL_WEIGHT        64
 123 #define CPSW_MIN_PACKET_SIZE    (VLAN_ETH_ZLEN)
 124 #define CPSW_MAX_PACKET_SIZE    (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
 125
 126 #define RX_PRIORITY_MAPPING     0x76543210
 127 #define TX_PRIORITY_MAPPING     0x33221100
 128 #define CPDMA_TX_PRIORITY_MAP   0x01234567
 129
 130 #define CPSW_VLAN_AWARE         BIT(1)
 131 #define CPSW_ALE_VLAN_AWARE     1
 132
 133 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 134 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 135 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 136
 137 #define CPSW_INTPACEEN          (0x3f << 16)
 138 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 139 #define CPSW_CMINTMAX_CNT       63
 140 #define CPSW_CMINTMIN_CNT       2
 141 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 142 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 143
 144 #define cpsw_slave_index(cpsw, priv)                            \
 145                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
 146                 cpsw->data.active_slave)
 147 #define IRQ_NUM                 2
 148 #define CPSW_MAX_QUEUES         8
 149 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
 150
 151 static int debug_level;
 152 module_param(debug_level, int, 0);
 153 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 154
 155 static int ale_ageout = 10;
 156 module_param(ale_ageout, int, 0);
 157 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 158
 159 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 160 module_param(rx_packet_max, int, 0);
 161 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 162
 163 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
 164 module_param(descs_pool_size, int, 0444);
 165 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
 166
 167 struct cpsw_wr_regs {
 168         u32     id_ver;
 169         u32     soft_reset;
 170         u32     control;
 171         u32     int_control;
 172         u32     rx_thresh_en;
 173         u32     rx_en;
 174         u32     tx_en;
 175         u32     misc_en;
 176         u32     mem_allign1[8];
 177         u32     rx_thresh_stat;
 178         u32     rx_stat;
 179         u32     tx_stat;
 180         u32     misc_stat;
 181         u32     mem_allign2[8];
 182         u32     rx_imax;
 183         u32     tx_imax;
 184
 185 };
 186
 187 struct cpsw_ss_regs {
 188         u32     id_ver;
 189         u32     control;
 190         u32     soft_reset;
 191         u32     stat_port_en;
 192         u32     ptype;
 193         u32     soft_idle;
 194         u32     thru_rate;
 195         u32     gap_thresh;
 196         u32     tx_start_wds;
 197         u32     flow_control;
 198         u32     vlan_ltype;
 199         u32     ts_ltype;
 200         u32     dlr_ltype;
 201 };
 202
 203 /* CPSW_PORT_V1 */
 204 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 205 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 206 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 207 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 208 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 209 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 210 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 211 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 212
 213 /* CPSW_PORT_V2 */
 214 #define CPSW2_CONTROL       0x00 /* Control Register */
 215 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 216 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 217 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 218 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 219 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 220 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 221
 222 /* CPSW_PORT_V1 and V2 */
 223 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 224 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 225 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 226
 227 /* CPSW_PORT_V2 only */
 228 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 229 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 230 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 231 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 234 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 235 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 236
 237 /* Bit definitions for the CPSW2_CONTROL register */
 238 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 239 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 240 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 241 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 242 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 243 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 244 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 245 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 246 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 247 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 248 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 249 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 250 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 251 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 252 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 253 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 254 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 255
 256 #define CTRL_V2_TS_BITS \
 257         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 258          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 259
 260 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 261 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 262 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 263
 264
 265 #define CTRL_V3_TS_BITS \
 266         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 267          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 268          TS_LTYPE1_EN)
 269
 270 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 271 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 272 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 273
 274 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 275 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 276 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 277 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 278 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 279
 280 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 281 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 282
 283 /* Bit definitions for the CPSW1_TS_CTL register */
 284 #define CPSW_V1_TS_RX_EN                BIT(0)
 285 #define CPSW_V1_TS_TX_EN                BIT(4)
 286 #define CPSW_V1_MSG_TYPE_OFS            16
 287
 288 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 289 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 290
 291 #define CPSW_MAX_BLKS_TX                15
 292 #define CPSW_MAX_BLKS_TX_SHIFT          4
 293 #define CPSW_MAX_BLKS_RX                5
 294
 295 struct cpsw_host_regs {
 296         u32     max_blks;
 297         u32     blk_cnt;
 298         u32     tx_in_ctl;
 299         u32     port_vlan;
 300         u32     tx_pri_map;
 301         u32     cpdma_tx_pri_map;
 302         u32     cpdma_rx_chan_map;
 303 };
 304
 305 struct cpsw_sliver_regs {
 306         u32     id_ver;
 307         u32     mac_control;
 308         u32     mac_status;
 309         u32     soft_reset;
 310         u32     rx_maxlen;
 311         u32     __reserved_0;
 312         u32     rx_pause;
 313         u32     tx_pause;
 314         u32     __reserved_1;
 315         u32     rx_pri_map;
 316 };
 317
 318 struct cpsw_hw_stats {
 319         u32     rxgoodframes;
 320         u32     rxbroadcastframes;
 321         u32     rxmulticastframes;
 322         u32     rxpauseframes;
 323         u32     rxcrcerrors;
 324         u32     rxaligncodeerrors;
 325         u32     rxoversizedframes;
 326         u32     rxjabberframes;
 327         u32     rxundersizedframes;
 328         u32     rxfragments;
 329         u32     __pad_0[2];
 330         u32     rxoctets;
 331         u32     txgoodframes;
 332         u32     txbroadcastframes;
 333         u32     txmulticastframes;
 334         u32     txpauseframes;
 335         u32     txdeferredframes;
 336         u32     txcollisionframes;
 337         u32     txsinglecollframes;
 338         u32     txmultcollframes;
 339         u32     txexcessivecollisions;
 340         u32     txlatecollisions;
 341         u32     txunderrun;
 342         u32     txcarriersenseerrors;
 343         u32     txoctets;
 344         u32     octetframes64;
 345         u32     octetframes65t127;
 346         u32     octetframes128t255;
 347         u32     octetframes256t511;
 348         u32     octetframes512t1023;
 349         u32     octetframes1024tup;
 350         u32     netoctets;
 351         u32     rxsofoverruns;
 352         u32     rxmofoverruns;
 353         u32     rxdmaoverruns;
 354 };
 355
 356 struct cpsw_slave_data {
 357         struct device_node *phy_node;
 358         char            phy_id[MII_BUS_ID_SIZE];
 359         int             phy_if;
 360         u8              mac_addr[ETH_ALEN];
 361         u16             dual_emac_res_vlan;     /* Reserved VLAN for DualEMAC */
 362 };
 363
 364 struct cpsw_platform_data {
 365         struct cpsw_slave_data  *slave_data;
 366         u32     ss_reg_ofs;     /* Subsystem control register offset */
 367         u32     channels;       /* number of cpdma channels (symmetric) */
 368         u32     slaves;         /* number of slave cpgmac ports */
 369         u32     active_slave; /* time stamping, ethtool and SIOCGMIIPHY slave */
 370         u32     ale_entries;    /* ale table size */
 371         u32     bd_ram_size;  /*buffer descriptor ram size */
 372         u32     mac_control;    /* Mac control register */
 373         u16     default_vlan;   /* Def VLAN for ALE lookup in VLAN aware mode*/
 374         bool    dual_emac;      /* Enable Dual EMAC mode */
 375 };
 376
 377 struct cpsw_slave {
 378         void __iomem                    *regs;
 379         struct cpsw_sliver_regs __iomem *sliver;
 380         int                             slave_num;
 381         u32                             mac_control;
 382         struct cpsw_slave_data          *data;
 383         struct phy_device               *phy;
 384         struct net_device               *ndev;
 385         u32                             port_vlan;
 386 };
 387
 388 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 389 {
 390         return readl_relaxed(slave->regs + offset);
 391 }
 392
 393 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 394 {
 395         writel_relaxed(val, slave->regs + offset);
 396 }
 397
 398 struct cpsw_vector {
 399         struct cpdma_chan *ch;
 400         int budget;
 401 };
 402
 403 struct cpsw_common {
 404         struct device                   *dev;
 405         struct cpsw_platform_data       data;
 406         struct napi_struct              napi_rx;
 407         struct napi_struct              napi_tx;
 408         struct cpsw_ss_regs __iomem     *regs;
 409         struct cpsw_wr_regs __iomem     *wr_regs;
 410         u8 __iomem                      *hw_stats;
 411         struct cpsw_host_regs __iomem   *host_port_regs;
 412         u32                             version;
 413         u32                             coal_intvl;
 414         u32                             bus_freq_mhz;
 415         int                             rx_packet_max;
 416         struct cpsw_slave               *slaves;
 417         struct cpdma_ctlr               *dma;
 418         struct cpsw_vector              txv[CPSW_MAX_QUEUES];
 419         struct cpsw_vector              rxv[CPSW_MAX_QUEUES];
 420         struct cpsw_ale                 *ale;
 421         bool                            quirk_irq;
 422         bool                            rx_irq_disabled;
 423         bool                            tx_irq_disabled;
 424         u32 irqs_table[IRQ_NUM];
 425         struct cpts                     *cpts;
 426         int                             rx_ch_num, tx_ch_num;
 427         int                             speed;
 428         int                             usage_count;
 429 };
 430
 431 struct cpsw_priv {
 432         struct net_device               *ndev;
 433         struct device                   *dev;
 434         u32                             msg_enable;
 435         u8                              mac_addr[ETH_ALEN];
 436         bool                            rx_pause;
 437         bool                            tx_pause;
 438         u32 emac_port;
 439         struct cpsw_common *cpsw;
 440 };
 441
 442 struct cpsw_stats {
 443         char stat_string[ETH_GSTRING_LEN];
 444         int type;
 445         int sizeof_stat;
 446         int stat_offset;
 447 };
 448
 449 enum {
 450         CPSW_STATS,
 451         CPDMA_RX_STATS,
 452         CPDMA_TX_STATS,
 453 };
 454
 455 #define CPSW_STAT(m)            CPSW_STATS,                             \
 456                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 457                                 offsetof(struct cpsw_hw_stats, m)
 458 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 459                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 460                                 offsetof(struct cpdma_chan_stats, m)
 461 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 462                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 463                                 offsetof(struct cpdma_chan_stats, m)
 464
 465 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 466         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 467         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 468         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 469         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 470         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 471         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 472         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 473         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 474         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 475         { "Rx Fragments", CPSW_STAT(rxfragments) },
 476         { "Rx Octets", CPSW_STAT(rxoctets) },
 477         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 478         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 479         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 480         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 481         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 482         { "Collisions", CPSW_STAT(txcollisionframes) },
 483         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 484         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 485         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 486         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 487         { "Tx Underrun", CPSW_STAT(txunderrun) },
 488         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 489         { "Tx Octets", CPSW_STAT(txoctets) },
 490         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 491         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 492         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 493         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 494         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 495         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 496         { "Net Octets", CPSW_STAT(netoctets) },
 497         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 498         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 499         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 500 };
 501
 502 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
 503         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 504         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 505         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 506         { "misqueued", CPDMA_RX_STAT(misqueued) },
 507         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 508         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 509         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 510         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 511         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 512         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 513         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 514         { "requeue", CPDMA_RX_STAT(requeue) },
 515         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 516 };
 517
 518 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
 519 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
 520
 521 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
 522 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
 523 #define for_each_slave(priv, func, arg...)                              \
 524         do {                                                            \
 525                 struct cpsw_slave *slave;                               \
 526                 struct cpsw_common *cpsw = (priv)->cpsw;                \
 527                 int n;                                                  \
 528                 if (cpsw->data.dual_emac)                               \
 529                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
 530                 else                                                    \
 531                         for (n = cpsw->data.slaves,                     \
 532                                         slave = cpsw->slaves;           \
 533                                         n; n--)                         \
 534                                 (func)(slave++, ##arg);                 \
 535         } while (0)
 536
 537 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb)         \
 538         do {                                                            \
 539                 if (!cpsw->data.dual_emac)                              \
 540                         break;                                          \
 541                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 542                         ndev = cpsw->slaves[0].ndev;                    \
 543                         skb->dev = ndev;                                \
 544                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 545                         ndev = cpsw->slaves[1].ndev;                    \
 546                         skb->dev = ndev;                                \
 547                 }                                                       \
 548         } while (0)
 549 #define cpsw_add_mcast(cpsw, priv, addr)                                \
 550         do {                                                            \
 551                 if (cpsw->data.dual_emac) {                             \
 552                         struct cpsw_slave *slave = cpsw->slaves +       \
 553                                                 priv->emac_port;        \
 554                         int slave_port = cpsw_get_slave_port(           \
 555                                                 slave->slave_num);      \
 556                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 557                                 1 << slave_port | ALE_PORT_HOST,        \
 558                                 ALE_VLAN, slave->port_vlan, 0);         \
 559                 } else {                                                \
 560                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 561                                 ALE_ALL_PORTS,                          \
 562                                 0, 0, 0);                               \
 563                 }                                                       \
 564         } while (0)
 565
 566 static inline int cpsw_get_slave_port(u32 slave_num)
 567 {
 568         return slave_num + 1;
 569 }
 570
 571 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 572 {
 573         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
 574         struct cpsw_ale *ale = cpsw->ale;
 575         int i;
 576
 577         if (cpsw->data.dual_emac) {
 578                 bool flag = false;
 579
 580                 /* Enabling promiscuous mode for one interface will be
 581                  * common for both the interface as the interface shares
 582                  * the same hardware resource.
 583                  */
 584                 for (i = 0; i < cpsw->data.slaves; i++)
 585                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
 586                                 flag = true;
 587
 588                 if (!enable && flag) {
 589                         enable = true;
 590                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 591                 }
 592
 593                 if (enable) {
 594                         /* Enable Bypass */
 595                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 596
 597                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 598                 } else {
 599                         /* Disable Bypass */
 600                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 601                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 602                 }
 603         } else {
 604                 if (enable) {
 605                         unsigned long timeout = jiffies + HZ;
 606
 607                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 608                         for (i = 0; i <= cpsw->data.slaves; i++) {
 609                                 cpsw_ale_control_set(ale, i,
 610                                                      ALE_PORT_NOLEARN, 1);
 611                                 cpsw_ale_control_set(ale, i,
 612                                                      ALE_PORT_NO_SA_UPDATE, 1);
 613                         }
 614
 615                         /* Clear All Untouched entries */
 616                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 617                         do {
 618                                 cpu_relax();
 619                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 620                                         break;
 621                         } while (time_after(timeout, jiffies));
 622                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 623
 624                         /* Clear all mcast from ALE */
 625                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
 626
 627                         /* Flood All Unicast Packets to Host port */
 628                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 629                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 630                 } else {
 631                         /* Don't Flood All Unicast Packets to Host port */
 632                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 633
 634                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 635                         for (i = 0; i <= cpsw->data.slaves; i++) {
 636                                 cpsw_ale_control_set(ale, i,
 637                                                      ALE_PORT_NOLEARN, 0);
 638                                 cpsw_ale_control_set(ale, i,
 639                                                      ALE_PORT_NO_SA_UPDATE, 0);
 640                         }
 641                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 642                 }
 643         }
 644 }
 645
 646 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 647 {
 648         struct cpsw_priv *priv = netdev_priv(ndev);
 649         struct cpsw_common *cpsw = priv->cpsw;
 650         int vid;
 651
 652         if (cpsw->data.dual_emac)
 653                 vid = cpsw->slaves[priv->emac_port].port_vlan;
 654         else
 655                 vid = cpsw->data.default_vlan;
 656
 657         if (ndev->flags & IFF_PROMISC) {
 658                 /* Enable promiscuous mode */
 659                 cpsw_set_promiscious(ndev, true);
 660                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
 661                 return;
 662         } else {
 663                 /* Disable promiscuous mode */
 664                 cpsw_set_promiscious(ndev, false);
 665         }
 666
 667         /* Restore allmulti on vlans if necessary */
 668         cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
 669
 670         /* Clear all mcast from ALE */
 671         cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
 672
 673         if (!netdev_mc_empty(ndev)) {
 674                 struct netdev_hw_addr *ha;
 675
 676                 /* program multicast address list into ALE register */
 677                 netdev_for_each_mc_addr(ha, ndev) {
 678                         cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
 679                 }
 680         }
 681 }
 682
 683 static void cpsw_intr_enable(struct cpsw_common *cpsw)
 684 {
 685         writel_relaxed(0xFF, &cpsw->wr_regs->tx_en);
 686         writel_relaxed(0xFF, &cpsw->wr_regs->rx_en);
 687
 688         cpdma_ctlr_int_ctrl(cpsw->dma, true);
 689         return;
 690 }
 691
 692 static void cpsw_intr_disable(struct cpsw_common *cpsw)
 693 {
 694         writel_relaxed(0, &cpsw->wr_regs->tx_en);
 695         writel_relaxed(0, &cpsw->wr_regs->rx_en);
 696
 697         cpdma_ctlr_int_ctrl(cpsw->dma, false);
 698         return;
 699 }
 700
 701 static void cpsw_tx_handler(void *token, int len, int status)
 702 {
 703         struct netdev_queue     *txq;
 704         struct sk_buff          *skb = token;
 705         struct net_device       *ndev = skb->dev;
 706         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 707
 708         /* Check whether the queue is stopped due to stalled tx dma, if the
 709          * queue is stopped then start the queue as we have free desc for tx
 710          */
 711         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
 712         if (unlikely(netif_tx_queue_stopped(txq)))
 713                 netif_tx_wake_queue(txq);
 714
 715         cpts_tx_timestamp(cpsw->cpts, skb);
 716         ndev->stats.tx_packets++;
 717         ndev->stats.tx_bytes += len;
 718         dev_kfree_skb_any(skb);
 719 }
 720
 721 static void cpsw_rx_handler(void *token, int len, int status)
 722 {
 723         struct cpdma_chan       *ch;
 724         struct sk_buff          *skb = token;
 725         struct sk_buff          *new_skb;
 726         struct net_device       *ndev = skb->dev;
 727         int                     ret = 0;
 728         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 729
 730         cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
 731
 732         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 733                 /* In dual emac mode check for all interfaces */
 734                 if (cpsw->data.dual_emac && cpsw->usage_count &&
 735                     (status >= 0)) {
 736                         /* The packet received is for the interface which
 737                          * is already down and the other interface is up
 738                          * and running, instead of freeing which results
 739                          * in reducing of the number of rx descriptor in
 740                          * DMA engine, requeue skb back to cpdma.
 741                          */
 742                         new_skb = skb;
 743                         goto requeue;
 744                 }
 745
 746                 /* the interface is going down, skbs are purged */
 747                 dev_kfree_skb_any(skb);
 748                 return;
 749         }
 750
 751         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
 752         if (new_skb) {
 753                 skb_copy_queue_mapping(new_skb, skb);
 754                 skb_put(skb, len);
 755                 cpts_rx_timestamp(cpsw->cpts, skb);
 756                 skb->protocol = eth_type_trans(skb, ndev);
 757                 netif_receive_skb(skb);
 758                 ndev->stats.rx_bytes += len;
 759                 ndev->stats.rx_packets++;
 760                 kmemleak_not_leak(new_skb);
 761         } else {
 762                 ndev->stats.rx_dropped++;
 763                 new_skb = skb;
 764         }
 765
 766 requeue:
 767         if (netif_dormant(ndev)) {
 768                 dev_kfree_skb_any(new_skb);
 769                 return;
 770         }
 771
 772         ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
 773         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
 774                                 skb_tailroom(new_skb), 0);
 775         if (WARN_ON(ret < 0))
 776                 dev_kfree_skb_any(new_skb);
 777 }
 778
 779 static void cpsw_split_res(struct net_device *ndev)
 780 {
 781         struct cpsw_priv *priv = netdev_priv(ndev);
 782         u32 consumed_rate = 0, bigest_rate = 0;
 783         struct cpsw_common *cpsw = priv->cpsw;
 784         struct cpsw_vector *txv = cpsw->txv;
 785         int i, ch_weight, rlim_ch_num = 0;
 786         int budget, bigest_rate_ch = 0;
 787         u32 ch_rate, max_rate;
 788         int ch_budget = 0;
 789
 790         for (i = 0; i < cpsw->tx_ch_num; i++) {
 791                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 792                 if (!ch_rate)
 793                         continue;
 794
 795                 rlim_ch_num++;
 796                 consumed_rate += ch_rate;
 797         }
 798
 799         if (cpsw->tx_ch_num == rlim_ch_num) {
 800                 max_rate = consumed_rate;
 801         } else if (!rlim_ch_num) {
 802                 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
 803                 bigest_rate = 0;
 804                 max_rate = consumed_rate;
 805         } else {
 806                 max_rate = cpsw->speed * 1000;
 807
 808                 /* if max_rate is less then expected due to reduced link speed,
 809                  * split proportionally according next potential max speed
 810                  */
 811                 if (max_rate < consumed_rate)
 812                         max_rate *= 10;
 813
 814                 if (max_rate < consumed_rate)
 815                         max_rate *= 10;
 816
 817                 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
 818                 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
 819                             (cpsw->tx_ch_num - rlim_ch_num);
 820                 bigest_rate = (max_rate - consumed_rate) /
 821                               (cpsw->tx_ch_num - rlim_ch_num);
 822         }
 823
 824         /* split tx weight/budget */
 825         budget = CPSW_POLL_WEIGHT;
 826         for (i = 0; i < cpsw->tx_ch_num; i++) {
 827                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 828                 if (ch_rate) {
 829                         txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
 830                         if (!txv[i].budget)
 831                                 txv[i].budget++;
 832                         if (ch_rate > bigest_rate) {
 833                                 bigest_rate_ch = i;
 834                                 bigest_rate = ch_rate;
 835                         }
 836
 837                         ch_weight = (ch_rate * 100) / max_rate;
 838                         if (!ch_weight)
 839                                 ch_weight++;
 840                         cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
 841                 } else {
 842                         txv[i].budget = ch_budget;
 843                         if (!bigest_rate_ch)
 844                                 bigest_rate_ch = i;
 845                         cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
 846                 }
 847
 848                 budget -= txv[i].budget;
 849         }
 850
 851         if (budget)
 852                 txv[bigest_rate_ch].budget += budget;
 853
 854         /* split rx budget */
 855         budget = CPSW_POLL_WEIGHT;
 856         ch_budget = budget / cpsw->rx_ch_num;
 857         for (i = 0; i < cpsw->rx_ch_num; i++) {
 858                 cpsw->rxv[i].budget = ch_budget;
 859                 budget -= ch_budget;
 860         }
 861
 862         if (budget)
 863                 cpsw->rxv[0].budget += budget;
 864 }
 865
 866 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 867 {
 868         struct cpsw_common *cpsw = dev_id;
 869
 870         writel(0, &cpsw->wr_regs->tx_en);
 871         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
 872
 873         if (cpsw->quirk_irq) {
 874                 disable_irq_nosync(cpsw->irqs_table[1]);
 875                 cpsw->tx_irq_disabled = true;
 876         }
 877
 878         napi_schedule(&cpsw->napi_tx);
 879         return IRQ_HANDLED;
 880 }
 881
 882 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 883 {
 884         struct cpsw_common *cpsw = dev_id;
 885
 886         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
 887         writel(0, &cpsw->wr_regs->rx_en);
 888
 889         if (cpsw->quirk_irq) {
 890                 disable_irq_nosync(cpsw->irqs_table[0]);
 891                 cpsw->rx_irq_disabled = true;
 892         }
 893
 894         napi_schedule(&cpsw->napi_rx);
 895         return IRQ_HANDLED;
 896 }
 897
 898 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 899 {
 900         u32                     ch_map;
 901         int                     num_tx, cur_budget, ch;
 902         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
 903         struct cpsw_vector      *txv;
 904
 905         /* process every unprocessed channel */
 906         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
 907         for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
 908                 if (!(ch_map & 0x01))
 909                         continue;
 910
 911                 txv = &cpsw->txv[ch];
 912                 if (unlikely(txv->budget > budget - num_tx))
 913                         cur_budget = budget - num_tx;
 914                 else
 915                         cur_budget = txv->budget;
 916
 917                 num_tx += cpdma_chan_process(txv->ch, cur_budget);
 918                 if (num_tx >= budget)
 919                         break;
 920         }
 921
 922         if (num_tx < budget) {
 923                 napi_complete(napi_tx);
 924                 writel(0xff, &cpsw->wr_regs->tx_en);
 925                 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
 926                         cpsw->tx_irq_disabled = false;
 927                         enable_irq(cpsw->irqs_table[1]);
 928                 }
 929         }
 930
 931         return num_tx;
 932 }
 933
 934 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 935 {
 936         u32                     ch_map;
 937         int                     num_rx, cur_budget, ch;
 938         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
 939         struct cpsw_vector      *rxv;
 940
 941         /* process every unprocessed channel */
 942         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
 943         for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
 944                 if (!(ch_map & 0x01))
 945                         continue;
 946
 947                 rxv = &cpsw->rxv[ch];
 948                 if (unlikely(rxv->budget > budget - num_rx))
 949                         cur_budget = budget - num_rx;
 950                 else
 951                         cur_budget = rxv->budget;
 952
 953                 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
 954                 if (num_rx >= budget)
 955                         break;
 956         }
 957
 958         if (num_rx < budget) {
 959                 napi_complete_done(napi_rx, num_rx);
 960                 writel(0xff, &cpsw->wr_regs->rx_en);
 961                 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
 962                         cpsw->rx_irq_disabled = false;
 963                         enable_irq(cpsw->irqs_table[0]);
 964                 }
 965         }
 966
 967         return num_rx;
 968 }
 969
 970 static inline void soft_reset(const char *module, void __iomem *reg)
 971 {
 972         unsigned long timeout = jiffies + HZ;
 973
 974         writel_relaxed(1, reg);
 975         do {
 976                 cpu_relax();
 977         } while ((readl_relaxed(reg) & 1) && time_after(timeout, jiffies));
 978
 979         WARN(readl_relaxed(reg) & 1, "failed to soft-reset %s\n", module);
 980 }
 981
 982 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 983                                struct cpsw_priv *priv)
 984 {
 985         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 986         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 987 }
 988
 989 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 990                               struct cpsw_priv *priv, bool *link)
 991 {
 992         struct phy_device       *phy = slave->phy;
 993         u32                     mac_control = 0;
 994         u32                     slave_port;
 995         struct cpsw_common *cpsw = priv->cpsw;
 996
 997         if (!phy)
 998                 return;
 999
1000         slave_port = cpsw_get_slave_port(slave->slave_num);
1001
1002         if (phy->link) {
1003                 mac_control = cpsw->data.mac_control;
1004
1005                 /* enable forwarding */
1006                 cpsw_ale_control_set(cpsw->ale, slave_port,
1007                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1008
1009                 if (phy->speed == 1000)
1010                         mac_control |= BIT(7);  /* GIGABITEN    */
1011                 if (phy->duplex)
1012                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
1013
1014                 /* set speed_in input in case RMII mode is used in 100Mbps */
1015                 if (phy->speed == 100)
1016                         mac_control |= BIT(15);
1017                 /* in band mode only works in 10Mbps RGMII mode */
1018                 else if ((phy->speed == 10) && phy_interface_is_rgmii(phy))
1019                         mac_control |= BIT(18); /* In Band mode */
1020
1021                 if (priv->rx_pause)
1022                         mac_control |= BIT(3);
1023
1024                 if (priv->tx_pause)
1025                         mac_control |= BIT(4);
1026
1027                 *link = true;
1028         } else {
1029                 mac_control = 0;
1030                 /* disable forwarding */
1031                 cpsw_ale_control_set(cpsw->ale, slave_port,
1032                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1033         }
1034
1035         if (mac_control != slave->mac_control) {
1036                 phy_print_status(phy);
1037                 writel_relaxed(mac_control, &slave->sliver->mac_control);
1038         }
1039
1040         slave->mac_control = mac_control;
1041 }
1042
1043 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1044 {
1045         int i, speed;
1046
1047         for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1048                 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1049                         speed += cpsw->slaves[i].phy->speed;
1050
1051         return speed;
1052 }
1053
1054 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1055 {
1056         int i, rlim_ch_num;
1057         int speed, ch_rate;
1058
1059         /* re-split resources only in case speed was changed */
1060         speed = cpsw_get_common_speed(cpsw);
1061         if (speed == cpsw->speed || !speed)
1062                 return 0;
1063
1064         cpsw->speed = speed;
1065
1066         for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1067                 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1068                 if (!ch_rate)
1069                         break;
1070
1071                 rlim_ch_num++;
1072         }
1073
1074         /* cases not dependent on speed */
1075         if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1076                 return 0;
1077
1078         return 1;
1079 }
1080
1081 static void cpsw_adjust_link(struct net_device *ndev)
1082 {
1083         struct cpsw_priv        *priv = netdev_priv(ndev);
1084         struct cpsw_common      *cpsw = priv->cpsw;
1085         bool                    link = false;
1086
1087         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1088
1089         if (link) {
1090                 if (cpsw_need_resplit(cpsw))
1091                         cpsw_split_res(ndev);
1092
1093                 netif_carrier_on(ndev);
1094                 if (netif_running(ndev))
1095                         netif_tx_wake_all_queues(ndev);
1096         } else {
1097                 netif_carrier_off(ndev);
1098                 netif_tx_stop_all_queues(ndev);
1099         }
1100 }
1101
1102 static int cpsw_get_coalesce(struct net_device *ndev,
1103                                 struct ethtool_coalesce *coal)
1104 {
1105         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1106
1107         coal->rx_coalesce_usecs = cpsw->coal_intvl;
1108         return 0;
1109 }
1110
1111 static int cpsw_set_coalesce(struct net_device *ndev,
1112                                 struct ethtool_coalesce *coal)
1113 {
1114         struct cpsw_priv *priv = netdev_priv(ndev);
1115         u32 int_ctrl;
1116         u32 num_interrupts = 0;
1117         u32 prescale = 0;
1118         u32 addnl_dvdr = 1;
1119         u32 coal_intvl = 0;
1120         struct cpsw_common *cpsw = priv->cpsw;
1121
1122         coal_intvl = coal->rx_coalesce_usecs;
1123
1124         int_ctrl =  readl(&cpsw->wr_regs->int_control);
1125         prescale = cpsw->bus_freq_mhz * 4;
1126
1127         if (!coal->rx_coalesce_usecs) {
1128                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1129                 goto update_return;
1130         }
1131
1132         if (coal_intvl < CPSW_CMINTMIN_INTVL)
1133                 coal_intvl = CPSW_CMINTMIN_INTVL;
1134
1135         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1136                 /* Interrupt pacer works with 4us Pulse, we can
1137                  * throttle further by dilating the 4us pulse.
1138                  */
1139                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1140
1141                 if (addnl_dvdr > 1) {
1142                         prescale *= addnl_dvdr;
1143                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1144                                 coal_intvl = (CPSW_CMINTMAX_INTVL
1145                                                 * addnl_dvdr);
1146                 } else {
1147                         addnl_dvdr = 1;
1148                         coal_intvl = CPSW_CMINTMAX_INTVL;
1149                 }
1150         }
1151
1152         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1153         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1154         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1155
1156         int_ctrl |= CPSW_INTPACEEN;
1157         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1158         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1159
1160 update_return:
1161         writel(int_ctrl, &cpsw->wr_regs->int_control);
1162
1163         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1164         cpsw->coal_intvl = coal_intvl;
1165
1166         return 0;
1167 }
1168
1169 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1170 {
1171         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1172
1173         switch (sset) {
1174         case ETH_SS_STATS:
1175                 return (CPSW_STATS_COMMON_LEN +
1176                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1177                        CPSW_STATS_CH_LEN);
1178         default:
1179                 return -EOPNOTSUPP;
1180         }
1181 }
1182
1183 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1184 {
1185         int ch_stats_len;
1186         int line;
1187         int i;
1188
1189         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1190         for (i = 0; i < ch_stats_len; i++) {
1191                 line = i % CPSW_STATS_CH_LEN;
1192                 snprintf(*p, ETH_GSTRING_LEN,
1193                          "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1194                          i / CPSW_STATS_CH_LEN,
1195                          cpsw_gstrings_ch_stats[line].stat_string);
1196                 *p += ETH_GSTRING_LEN;
1197         }
1198 }
1199
1200 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1201 {
1202         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1203         u8 *p = data;
1204         int i;
1205
1206         switch (stringset) {
1207         case ETH_SS_STATS:
1208                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1209                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1210                                ETH_GSTRING_LEN);
1211                         p += ETH_GSTRING_LEN;
1212                 }
1213
1214                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1215                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1216                 break;
1217         }
1218 }
1219
1220 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1221                                     struct ethtool_stats *stats, u64 *data)
1222 {
1223         u8 *p;
1224         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1225         struct cpdma_chan_stats ch_stats;
1226         int i, l, ch;
1227
1228         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1229         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1230                 data[l] = readl(cpsw->hw_stats +
1231                                 cpsw_gstrings_stats[l].stat_offset);
1232
1233         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1234                 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1235                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1236                         p = (u8 *)&ch_stats +
1237                                 cpsw_gstrings_ch_stats[i].stat_offset;
1238                         data[l] = *(u32 *)p;
1239                 }
1240         }
1241
1242         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1243                 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1244                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1245                         p = (u8 *)&ch_stats +
1246                                 cpsw_gstrings_ch_stats[i].stat_offset;
1247                         data[l] = *(u32 *)p;
1248                 }
1249         }
1250 }
1251
1252 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1253                                         struct sk_buff *skb,
1254                                         struct cpdma_chan *txch)
1255 {
1256         struct cpsw_common *cpsw = priv->cpsw;
1257
1258         skb_tx_timestamp(skb);
1259         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1260                                  priv->emac_port + cpsw->data.dual_emac);
1261 }
1262
1263 static inline void cpsw_add_dual_emac_def_ale_entries(
1264                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1265                 u32 slave_port)
1266 {
1267         struct cpsw_common *cpsw = priv->cpsw;
1268         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1269
1270         if (cpsw->version == CPSW_VERSION_1)
1271                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1272         else
1273                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1274         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1275                           port_mask, port_mask, 0);
1276         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1277                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1278         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1279                            HOST_PORT_NUM, ALE_VLAN |
1280                            ALE_SECURE, slave->port_vlan);
1281 }
1282
1283 static void soft_reset_slave(struct cpsw_slave *slave)
1284 {
1285         char name[32];
1286
1287         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1288         soft_reset(name, &slave->sliver->soft_reset);
1289 }
1290
1291 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1292 {
1293         u32 slave_port;
1294         struct phy_device *phy;
1295         struct cpsw_common *cpsw = priv->cpsw;
1296
1297         soft_reset_slave(slave);
1298
1299         /* setup priority mapping */
1300         writel_relaxed(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1301
1302         switch (cpsw->version) {
1303         case CPSW_VERSION_1:
1304                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1305                 /* Increase RX FIFO size to 5 for supporting fullduplex
1306                  * flow control mode
1307                  */
1308                 slave_write(slave,
1309                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1310                             CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1311                 break;
1312         case CPSW_VERSION_2:
1313         case CPSW_VERSION_3:
1314         case CPSW_VERSION_4:
1315                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1316                 /* Increase RX FIFO size to 5 for supporting fullduplex
1317                  * flow control mode
1318                  */
1319                 slave_write(slave,
1320                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1321                             CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1322                 break;
1323         }
1324
1325         /* setup max packet size, and mac address */
1326         writel_relaxed(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1327         cpsw_set_slave_mac(slave, priv);
1328
1329         slave->mac_control = 0; /* no link yet */
1330
1331         slave_port = cpsw_get_slave_port(slave->slave_num);
1332
1333         if (cpsw->data.dual_emac)
1334                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1335         else
1336                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1337                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1338
1339         if (slave->data->phy_node) {
1340                 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1341                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1342                 if (!phy) {
1343                         dev_err(priv->dev, "phy \"%pOF\" not found on slave %d\n",
1344                                 slave->data->phy_node,
1345                                 slave->slave_num);
1346                         return;
1347                 }
1348         } else {
1349                 phy = phy_connect(priv->ndev, slave->data->phy_id,
1350                                  &cpsw_adjust_link, slave->data->phy_if);
1351                 if (IS_ERR(phy)) {
1352                         dev_err(priv->dev,
1353                                 "phy \"%s\" not found on slave %d, err %ld\n",
1354                                 slave->data->phy_id, slave->slave_num,
1355                                 PTR_ERR(phy));
1356                         return;
1357                 }
1358         }
1359
1360         slave->phy = phy;
1361
1362         phy_attached_info(slave->phy);
1363
1364         phy_start(slave->phy);
1365
1366         /* Configure GMII_SEL register */
1367         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1368 }
1369
1370 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1371 {
1372         struct cpsw_common *cpsw = priv->cpsw;
1373         const int vlan = cpsw->data.default_vlan;
1374         u32 reg;
1375         int i;
1376         int unreg_mcast_mask;
1377
1378         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1379                CPSW2_PORT_VLAN;
1380
1381         writel(vlan, &cpsw->host_port_regs->port_vlan);
1382
1383         for (i = 0; i < cpsw->data.slaves; i++)
1384                 slave_write(cpsw->slaves + i, vlan, reg);
1385
1386         if (priv->ndev->flags & IFF_ALLMULTI)
1387                 unreg_mcast_mask = ALE_ALL_PORTS;
1388         else
1389                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1390
1391         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1392                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1393                           unreg_mcast_mask);
1394 }
1395
1396 static void cpsw_init_host_port(struct cpsw_priv *priv)
1397 {
1398         u32 fifo_mode;
1399         u32 control_reg;
1400         struct cpsw_common *cpsw = priv->cpsw;
1401
1402         /* soft reset the controller and initialize ale */
1403         soft_reset("cpsw", &cpsw->regs->soft_reset);
1404         cpsw_ale_start(cpsw->ale);
1405
1406         /* switch to vlan unaware mode */
1407         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1408                              CPSW_ALE_VLAN_AWARE);
1409         control_reg = readl(&cpsw->regs->control);
1410         control_reg |= CPSW_VLAN_AWARE;
1411         writel(control_reg, &cpsw->regs->control);
1412         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1413                      CPSW_FIFO_NORMAL_MODE;
1414         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1415
1416         /* setup host port priority mapping */
1417         writel_relaxed(CPDMA_TX_PRIORITY_MAP,
1418                        &cpsw->host_port_regs->cpdma_tx_pri_map);
1419         writel_relaxed(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1420
1421         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1422                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1423
1424         if (!cpsw->data.dual_emac) {
1425                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1426                                    0, 0);
1427                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1428                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1429         }
1430 }
1431
1432 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1433 {
1434         struct cpsw_common *cpsw = priv->cpsw;
1435         struct sk_buff *skb;
1436         int ch_buf_num;
1437         int ch, i, ret;
1438
1439         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1440                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1441                 for (i = 0; i < ch_buf_num; i++) {
1442                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1443                                                           cpsw->rx_packet_max,
1444                                                           GFP_KERNEL);
1445                         if (!skb) {
1446                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1447                                 return -ENOMEM;
1448                         }
1449
1450                         skb_set_queue_mapping(skb, ch);
1451                         ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1452                                                 skb->data, skb_tailroom(skb),
1453                                                 0);
1454                         if (ret < 0) {
1455                                 cpsw_err(priv, ifup,
1456                                          "cannot submit skb to channel %d rx, error %d\n",
1457                                          ch, ret);
1458                                 kfree_skb(skb);
1459                                 return ret;
1460                         }
1461                         kmemleak_not_leak(skb);
1462                 }
1463
1464                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1465                           ch, ch_buf_num);
1466         }
1467
1468         return 0;
1469 }
1470
1471 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1472 {
1473         u32 slave_port;
1474
1475         slave_port = cpsw_get_slave_port(slave->slave_num);
1476
1477         if (!slave->phy)
1478                 return;
1479         phy_stop(slave->phy);
1480         phy_disconnect(slave->phy);
1481         slave->phy = NULL;
1482         cpsw_ale_control_set(cpsw->ale, slave_port,
1483                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1484         soft_reset_slave(slave);
1485 }
1486
1487 static int cpsw_ndo_open(struct net_device *ndev)
1488 {
1489         struct cpsw_priv *priv = netdev_priv(ndev);
1490         struct cpsw_common *cpsw = priv->cpsw;
1491         int ret;
1492         u32 reg;
1493
1494         ret = pm_runtime_get_sync(cpsw->dev);
1495         if (ret < 0) {
1496                 pm_runtime_put_noidle(cpsw->dev);
1497                 return ret;
1498         }
1499
1500         netif_carrier_off(ndev);
1501
1502         /* Notify the stack of the actual queue counts. */
1503         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1504         if (ret) {
1505                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1506                 goto err_cleanup;
1507         }
1508
1509         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1510         if (ret) {
1511                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1512                 goto err_cleanup;
1513         }
1514
1515         reg = cpsw->version;
1516
1517         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1518                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1519                  CPSW_RTL_VERSION(reg));
1520
1521         /* Initialize host and slave ports */
1522         if (!cpsw->usage_count)
1523                 cpsw_init_host_port(priv);
1524         for_each_slave(priv, cpsw_slave_open, priv);
1525
1526         /* Add default VLAN */
1527         if (!cpsw->data.dual_emac)
1528                 cpsw_add_default_vlan(priv);
1529         else
1530                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1531                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1532
1533         /* initialize shared resources for every ndev */
1534         if (!cpsw->usage_count) {
1535                 /* disable priority elevation */
1536                 writel_relaxed(0, &cpsw->regs->ptype);
1537
1538                 /* enable statistics collection only on all ports */
1539                 writel_relaxed(0x7, &cpsw->regs->stat_port_en);
1540
1541                 /* Enable internal fifo flow control */
1542                 writel(0x7, &cpsw->regs->flow_control);
1543
1544                 napi_enable(&cpsw->napi_rx);
1545                 napi_enable(&cpsw->napi_tx);
1546
1547                 if (cpsw->tx_irq_disabled) {
1548                         cpsw->tx_irq_disabled = false;
1549                         enable_irq(cpsw->irqs_table[1]);
1550                 }
1551
1552                 if (cpsw->rx_irq_disabled) {
1553                         cpsw->rx_irq_disabled = false;
1554                         enable_irq(cpsw->irqs_table[0]);
1555                 }
1556
1557                 ret = cpsw_fill_rx_channels(priv);
1558                 if (ret < 0)
1559                         goto err_cleanup;
1560
1561                 if (cpts_register(cpsw->cpts))
1562                         dev_err(priv->dev, "error registering cpts device\n");
1563
1564         }
1565
1566         /* Enable Interrupt pacing if configured */
1567         if (cpsw->coal_intvl != 0) {
1568                 struct ethtool_coalesce coal;
1569
1570                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1571                 cpsw_set_coalesce(ndev, &coal);
1572         }
1573
1574         cpdma_ctlr_start(cpsw->dma);
1575         cpsw_intr_enable(cpsw);
1576         cpsw->usage_count++;
1577
1578         return 0;
1579
1580 err_cleanup:
1581         cpdma_ctlr_stop(cpsw->dma);
1582         for_each_slave(priv, cpsw_slave_stop, cpsw);
1583         pm_runtime_put_sync(cpsw->dev);
1584         netif_carrier_off(priv->ndev);
1585         return ret;
1586 }
1587
1588 static int cpsw_ndo_stop(struct net_device *ndev)
1589 {
1590         struct cpsw_priv *priv = netdev_priv(ndev);
1591         struct cpsw_common *cpsw = priv->cpsw;
1592
1593         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1594         netif_tx_stop_all_queues(priv->ndev);
1595         netif_carrier_off(priv->ndev);
1596
1597         if (cpsw->usage_count <= 1) {
1598                 napi_disable(&cpsw->napi_rx);
1599                 napi_disable(&cpsw->napi_tx);
1600                 cpts_unregister(cpsw->cpts);
1601                 cpsw_intr_disable(cpsw);
1602                 cpdma_ctlr_stop(cpsw->dma);
1603                 cpsw_ale_stop(cpsw->ale);
1604         }
1605         for_each_slave(priv, cpsw_slave_stop, cpsw);
1606
1607         if (cpsw_need_resplit(cpsw))
1608                 cpsw_split_res(ndev);
1609
1610         cpsw->usage_count--;
1611         pm_runtime_put_sync(cpsw->dev);
1612         return 0;
1613 }
1614
1615 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1616                                        struct net_device *ndev)
1617 {
1618         struct cpsw_priv *priv = netdev_priv(ndev);
1619         struct cpsw_common *cpsw = priv->cpsw;
1620         struct cpts *cpts = cpsw->cpts;
1621         struct netdev_queue *txq;
1622         struct cpdma_chan *txch;
1623         int ret, q_idx;
1624
1625         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1626                 cpsw_err(priv, tx_err, "packet pad failed\n");
1627                 ndev->stats.tx_dropped++;
1628                 return NET_XMIT_DROP;
1629         }
1630
1631         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1632             cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
1633                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1634
1635         q_idx = skb_get_queue_mapping(skb);
1636         if (q_idx >= cpsw->tx_ch_num)
1637                 q_idx = q_idx % cpsw->tx_ch_num;
1638
1639         txch = cpsw->txv[q_idx].ch;
1640         txq = netdev_get_tx_queue(ndev, q_idx);
1641         ret = cpsw_tx_packet_submit(priv, skb, txch);
1642         if (unlikely(ret != 0)) {
1643                 cpsw_err(priv, tx_err, "desc submit failed\n");
1644                 goto fail;
1645         }
1646
1647         /* If there is no more tx desc left free then we need to
1648          * tell the kernel to stop sending us tx frames.
1649          */
1650         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1651                 netif_tx_stop_queue(txq);
1652
1653                 /* Barrier, so that stop_queue visible to other cpus */
1654                 smp_mb__after_atomic();
1655
1656                 if (cpdma_check_free_tx_desc(txch))
1657                         netif_tx_wake_queue(txq);
1658         }
1659
1660         return NETDEV_TX_OK;
1661 fail:
1662         ndev->stats.tx_dropped++;
1663         netif_tx_stop_queue(txq);
1664
1665         /* Barrier, so that stop_queue visible to other cpus */
1666         smp_mb__after_atomic();
1667
1668         if (cpdma_check_free_tx_desc(txch))
1669                 netif_tx_wake_queue(txq);
1670
1671         return NETDEV_TX_BUSY;
1672 }
1673
1674 #if IS_ENABLED(CONFIG_TI_CPTS)
1675
1676 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1677 {
1678         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1679         u32 ts_en, seq_id;
1680
1681         if (!cpts_is_tx_enabled(cpsw->cpts) &&
1682             !cpts_is_rx_enabled(cpsw->cpts)) {
1683                 slave_write(slave, 0, CPSW1_TS_CTL);
1684                 return;
1685         }
1686
1687         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1688         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1689
1690         if (cpts_is_tx_enabled(cpsw->cpts))
1691                 ts_en |= CPSW_V1_TS_TX_EN;
1692
1693         if (cpts_is_rx_enabled(cpsw->cpts))
1694                 ts_en |= CPSW_V1_TS_RX_EN;
1695
1696         slave_write(slave, ts_en, CPSW1_TS_CTL);
1697         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1698 }
1699
1700 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1701 {
1702         struct cpsw_slave *slave;
1703         struct cpsw_common *cpsw = priv->cpsw;
1704         u32 ctrl, mtype;
1705
1706         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1707
1708         ctrl = slave_read(slave, CPSW2_CONTROL);
1709         switch (cpsw->version) {
1710         case CPSW_VERSION_2:
1711                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1712
1713                 if (cpts_is_tx_enabled(cpsw->cpts))
1714                         ctrl |= CTRL_V2_TX_TS_BITS;
1715
1716                 if (cpts_is_rx_enabled(cpsw->cpts))
1717                         ctrl |= CTRL_V2_RX_TS_BITS;
1718                 break;
1719         case CPSW_VERSION_3:
1720         default:
1721                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1722
1723                 if (cpts_is_tx_enabled(cpsw->cpts))
1724                         ctrl |= CTRL_V3_TX_TS_BITS;
1725
1726                 if (cpts_is_rx_enabled(cpsw->cpts))
1727                         ctrl |= CTRL_V3_RX_TS_BITS;
1728                 break;
1729         }
1730
1731         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1732
1733         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1734         slave_write(slave, ctrl, CPSW2_CONTROL);
1735         writel_relaxed(ETH_P_1588, &cpsw->regs->ts_ltype);
1736 }
1737
1738 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1739 {
1740         struct cpsw_priv *priv = netdev_priv(dev);
1741         struct hwtstamp_config cfg;
1742         struct cpsw_common *cpsw = priv->cpsw;
1743         struct cpts *cpts = cpsw->cpts;
1744
1745         if (cpsw->version != CPSW_VERSION_1 &&
1746             cpsw->version != CPSW_VERSION_2 &&
1747             cpsw->version != CPSW_VERSION_3)
1748                 return -EOPNOTSUPP;
1749
1750         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1751                 return -EFAULT;
1752
1753         /* reserved for future extensions */
1754         if (cfg.flags)
1755                 return -EINVAL;
1756
1757         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1758                 return -ERANGE;
1759
1760         switch (cfg.rx_filter) {
1761         case HWTSTAMP_FILTER_NONE:
1762                 cpts_rx_enable(cpts, 0);
1763                 break;
1764         case HWTSTAMP_FILTER_ALL:
1765         case HWTSTAMP_FILTER_NTP_ALL:
1766                 return -ERANGE;
1767         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1768         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1769         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1770                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
1771                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1772                 break;
1773         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1774         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1775         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1776         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1777         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1778         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1779         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1780         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1781         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1782                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
1783                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1784                 break;
1785         default:
1786                 return -ERANGE;
1787         }
1788
1789         cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
1790
1791         switch (cpsw->version) {
1792         case CPSW_VERSION_1:
1793                 cpsw_hwtstamp_v1(cpsw);
1794                 break;
1795         case CPSW_VERSION_2:
1796         case CPSW_VERSION_3:
1797                 cpsw_hwtstamp_v2(priv);
1798                 break;
1799         default:
1800                 WARN_ON(1);
1801         }
1802
1803         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1804 }
1805
1806 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1807 {
1808         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1809         struct cpts *cpts = cpsw->cpts;
1810         struct hwtstamp_config cfg;
1811
1812         if (cpsw->version != CPSW_VERSION_1 &&
1813             cpsw->version != CPSW_VERSION_2 &&
1814             cpsw->version != CPSW_VERSION_3)
1815                 return -EOPNOTSUPP;
1816
1817         cfg.flags = 0;
1818         cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1819                       HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1820         cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
1821                          cpts->rx_enable : HWTSTAMP_FILTER_NONE);
1822
1823         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1824 }
1825 #else
1826 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1827 {
1828         return -EOPNOTSUPP;
1829 }
1830
1831 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1832 {
1833         return -EOPNOTSUPP;
1834 }
1835 #endif /*CONFIG_TI_CPTS*/
1836
1837 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1838 {
1839         struct cpsw_priv *priv = netdev_priv(dev);
1840         struct cpsw_common *cpsw = priv->cpsw;
1841         int slave_no = cpsw_slave_index(cpsw, priv);
1842
1843         if (!netif_running(dev))
1844                 return -EINVAL;
1845
1846         switch (cmd) {
1847         case SIOCSHWTSTAMP:
1848                 return cpsw_hwtstamp_set(dev, req);
1849         case SIOCGHWTSTAMP:
1850                 return cpsw_hwtstamp_get(dev, req);
1851         }
1852
1853         if (!cpsw->slaves[slave_no].phy)
1854                 return -EOPNOTSUPP;
1855         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1856 }
1857
1858 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1859 {
1860         struct cpsw_priv *priv = netdev_priv(ndev);
1861         struct cpsw_common *cpsw = priv->cpsw;
1862         int ch;
1863
1864         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1865         ndev->stats.tx_errors++;
1866         cpsw_intr_disable(cpsw);
1867         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1868                 cpdma_chan_stop(cpsw->txv[ch].ch);
1869                 cpdma_chan_start(cpsw->txv[ch].ch);
1870         }
1871
1872         cpsw_intr_enable(cpsw);
1873         netif_trans_update(ndev);
1874         netif_tx_wake_all_queues(ndev);
1875 }
1876
1877 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1878 {
1879         struct cpsw_priv *priv = netdev_priv(ndev);
1880         struct sockaddr *addr = (struct sockaddr *)p;
1881         struct cpsw_common *cpsw = priv->cpsw;
1882         int flags = 0;
1883         u16 vid = 0;
1884         int ret;
1885
1886         if (!is_valid_ether_addr(addr->sa_data))
1887                 return -EADDRNOTAVAIL;
1888
1889         ret = pm_runtime_get_sync(cpsw->dev);
1890         if (ret < 0) {
1891                 pm_runtime_put_noidle(cpsw->dev);
1892                 return ret;
1893         }
1894
1895         if (cpsw->data.dual_emac) {
1896                 vid = cpsw->slaves[priv->emac_port].port_vlan;
1897                 flags = ALE_VLAN;
1898         }
1899
1900         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1901                            flags, vid);
1902         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1903                            flags, vid);
1904
1905         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1906         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1907         for_each_slave(priv, cpsw_set_slave_mac, priv);
1908
1909         pm_runtime_put(cpsw->dev);
1910
1911         return 0;
1912 }
1913
1914 #ifdef CONFIG_NET_POLL_CONTROLLER
1915 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1916 {
1917         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1918
1919         cpsw_intr_disable(cpsw);
1920         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1921         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1922         cpsw_intr_enable(cpsw);
1923 }
1924 #endif
1925
1926 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1927                                 unsigned short vid)
1928 {
1929         int ret;
1930         int unreg_mcast_mask = 0;
1931         u32 port_mask;
1932         struct cpsw_common *cpsw = priv->cpsw;
1933
1934         if (cpsw->data.dual_emac) {
1935                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1936
1937                 if (priv->ndev->flags & IFF_ALLMULTI)
1938                         unreg_mcast_mask = port_mask;
1939         } else {
1940                 port_mask = ALE_ALL_PORTS;
1941
1942                 if (priv->ndev->flags & IFF_ALLMULTI)
1943                         unreg_mcast_mask = ALE_ALL_PORTS;
1944                 else
1945                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1946         }
1947
1948         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1949                                 unreg_mcast_mask);
1950         if (ret != 0)
1951                 return ret;
1952
1953         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1954                                  HOST_PORT_NUM, ALE_VLAN, vid);
1955         if (ret != 0)
1956                 goto clean_vid;
1957
1958         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1959                                  port_mask, ALE_VLAN, vid, 0);
1960         if (ret != 0)
1961                 goto clean_vlan_ucast;
1962         return 0;
1963
1964 clean_vlan_ucast:
1965         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1966                            HOST_PORT_NUM, ALE_VLAN, vid);
1967 clean_vid:
1968         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1969         return ret;
1970 }
1971
1972 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1973                                     __be16 proto, u16 vid)
1974 {
1975         struct cpsw_priv *priv = netdev_priv(ndev);
1976         struct cpsw_common *cpsw = priv->cpsw;
1977         int ret;
1978
1979         if (vid == cpsw->data.default_vlan)
1980                 return 0;
1981
1982         ret = pm_runtime_get_sync(cpsw->dev);
1983         if (ret < 0) {
1984                 pm_runtime_put_noidle(cpsw->dev);
1985                 return ret;
1986         }
1987
1988         if (cpsw->data.dual_emac) {
1989                 /* In dual EMAC, reserved VLAN id should not be used for
1990                  * creating VLAN interfaces as this can break the dual
1991                  * EMAC port separation
1992                  */
1993                 int i;
1994
1995                 for (i = 0; i < cpsw->data.slaves; i++) {
1996                         if (vid == cpsw->slaves[i].port_vlan)
1997                                 return -EINVAL;
1998                 }
1999         }
2000
2001         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
2002         ret = cpsw_add_vlan_ale_entry(priv, vid);
2003
2004         pm_runtime_put(cpsw->dev);
2005         return ret;
2006 }
2007
2008 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
2009                                      __be16 proto, u16 vid)
2010 {
2011         struct cpsw_priv *priv = netdev_priv(ndev);
2012         struct cpsw_common *cpsw = priv->cpsw;
2013         int ret;
2014
2015         if (vid == cpsw->data.default_vlan)
2016                 return 0;
2017
2018         ret = pm_runtime_get_sync(cpsw->dev);
2019         if (ret < 0) {
2020                 pm_runtime_put_noidle(cpsw->dev);
2021                 return ret;
2022         }
2023
2024         if (cpsw->data.dual_emac) {
2025                 int i;
2026
2027                 for (i = 0; i < cpsw->data.slaves; i++) {
2028                         if (vid == cpsw->slaves[i].port_vlan)
2029                                 return -EINVAL;
2030                 }
2031         }
2032
2033         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2034         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2035         if (ret != 0)
2036                 return ret;
2037
2038         ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2039                                  HOST_PORT_NUM, ALE_VLAN, vid);
2040         if (ret != 0)
2041                 return ret;
2042
2043         ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2044                                  0, ALE_VLAN, vid);
2045         pm_runtime_put(cpsw->dev);
2046         return ret;
2047 }
2048
2049 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2050 {
2051         struct cpsw_priv *priv = netdev_priv(ndev);
2052         struct cpsw_common *cpsw = priv->cpsw;
2053         struct cpsw_slave *slave;
2054         u32 min_rate;
2055         u32 ch_rate;
2056         int i, ret;
2057
2058         ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2059         if (ch_rate == rate)
2060                 return 0;
2061
2062         ch_rate = rate * 1000;
2063         min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2064         if ((ch_rate < min_rate && ch_rate)) {
2065                 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2066                         min_rate);
2067                 return -EINVAL;
2068         }
2069
2070         if (rate > cpsw->speed) {
2071                 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2072                 return -EINVAL;
2073         }
2074
2075         ret = pm_runtime_get_sync(cpsw->dev);
2076         if (ret < 0) {
2077                 pm_runtime_put_noidle(cpsw->dev);
2078                 return ret;
2079         }
2080
2081         ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2082         pm_runtime_put(cpsw->dev);
2083
2084         if (ret)
2085                 return ret;
2086
2087         /* update rates for slaves tx queues */
2088         for (i = 0; i < cpsw->data.slaves; i++) {
2089                 slave = &cpsw->slaves[i];
2090                 if (!slave->ndev)
2091                         continue;
2092
2093                 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2094         }
2095
2096         cpsw_split_res(ndev);
2097         return ret;
2098 }
2099
2100 static const struct net_device_ops cpsw_netdev_ops = {
2101         .ndo_open               = cpsw_ndo_open,
2102         .ndo_stop               = cpsw_ndo_stop,
2103         .ndo_start_xmit         = cpsw_ndo_start_xmit,
2104         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
2105         .ndo_do_ioctl           = cpsw_ndo_ioctl,
2106         .ndo_validate_addr      = eth_validate_addr,
2107         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
2108         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
2109         .ndo_set_tx_maxrate     = cpsw_ndo_set_tx_maxrate,
2110 #ifdef CONFIG_NET_POLL_CONTROLLER
2111         .ndo_poll_controller    = cpsw_ndo_poll_controller,
2112 #endif
2113         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
2114         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
2115 };
2116
2117 static int cpsw_get_regs_len(struct net_device *ndev)
2118 {
2119         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2120
2121         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2122 }
2123
2124 static void cpsw_get_regs(struct net_device *ndev,
2125                           struct ethtool_regs *regs, void *p)
2126 {
2127         u32 *reg = p;
2128         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2129
2130         /* update CPSW IP version */
2131         regs->version = cpsw->version;
2132
2133         cpsw_ale_dump(cpsw->ale, reg);
2134 }
2135
2136 static void cpsw_get_drvinfo(struct net_device *ndev,
2137                              struct ethtool_drvinfo *info)
2138 {
2139         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2140         struct platform_device  *pdev = to_platform_device(cpsw->dev);
2141
2142         strlcpy(info->driver, "cpsw", sizeof(info->driver));
2143         strlcpy(info->version, "1.0", sizeof(info->version));
2144         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2145 }
2146
2147 static u32 cpsw_get_msglevel(struct net_device *ndev)
2148 {
2149         struct cpsw_priv *priv = netdev_priv(ndev);
2150         return priv->msg_enable;
2151 }
2152
2153 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2154 {
2155         struct cpsw_priv *priv = netdev_priv(ndev);
2156         priv->msg_enable = value;
2157 }
2158
2159 #if IS_ENABLED(CONFIG_TI_CPTS)
2160 static int cpsw_get_ts_info(struct net_device *ndev,
2161                             struct ethtool_ts_info *info)
2162 {
2163         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2164
2165         info->so_timestamping =
2166                 SOF_TIMESTAMPING_TX_HARDWARE |
2167                 SOF_TIMESTAMPING_TX_SOFTWARE |
2168                 SOF_TIMESTAMPING_RX_HARDWARE |
2169                 SOF_TIMESTAMPING_RX_SOFTWARE |
2170                 SOF_TIMESTAMPING_SOFTWARE |
2171                 SOF_TIMESTAMPING_RAW_HARDWARE;
2172         info->phc_index = cpsw->cpts->phc_index;
2173         info->tx_types =
2174                 (1 << HWTSTAMP_TX_OFF) |
2175                 (1 << HWTSTAMP_TX_ON);
2176         info->rx_filters =
2177                 (1 << HWTSTAMP_FILTER_NONE) |
2178                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2179                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2180         return 0;
2181 }
2182 #else
2183 static int cpsw_get_ts_info(struct net_device *ndev,
2184                             struct ethtool_ts_info *info)
2185 {
2186         info->so_timestamping =
2187                 SOF_TIMESTAMPING_TX_SOFTWARE |
2188                 SOF_TIMESTAMPING_RX_SOFTWARE |
2189                 SOF_TIMESTAMPING_SOFTWARE;
2190         info->phc_index = -1;
2191         info->tx_types = 0;
2192         info->rx_filters = 0;
2193         return 0;
2194 }
2195 #endif
2196
2197 static int cpsw_get_link_ksettings(struct net_device *ndev,
2198                                    struct ethtool_link_ksettings *ecmd)
2199 {
2200         struct cpsw_priv *priv = netdev_priv(ndev);
2201         struct cpsw_common *cpsw = priv->cpsw;
2202         int slave_no = cpsw_slave_index(cpsw, priv);
2203
2204         if (!cpsw->slaves[slave_no].phy)
2205                 return -EOPNOTSUPP;
2206
2207         phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2208         return 0;
2209 }
2210
2211 static int cpsw_set_link_ksettings(struct net_device *ndev,
2212                                    const struct ethtool_link_ksettings *ecmd)
2213 {
2214         struct cpsw_priv *priv = netdev_priv(ndev);
2215         struct cpsw_common *cpsw = priv->cpsw;
2216         int slave_no = cpsw_slave_index(cpsw, priv);
2217
2218         if (cpsw->slaves[slave_no].phy)
2219                 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2220                                                  ecmd);
2221         else
2222                 return -EOPNOTSUPP;
2223 }
2224
2225 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2226 {
2227         struct cpsw_priv *priv = netdev_priv(ndev);
2228         struct cpsw_common *cpsw = priv->cpsw;
2229         int slave_no = cpsw_slave_index(cpsw, priv);
2230
2231         wol->supported = 0;
2232         wol->wolopts = 0;
2233
2234         if (cpsw->slaves[slave_no].phy)
2235                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2236 }
2237
2238 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2239 {
2240         struct cpsw_priv *priv = netdev_priv(ndev);
2241         struct cpsw_common *cpsw = priv->cpsw;
2242         int slave_no = cpsw_slave_index(cpsw, priv);
2243
2244         if (cpsw->slaves[slave_no].phy)
2245                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2246         else
2247                 return -EOPNOTSUPP;
2248 }
2249
2250 static void cpsw_get_pauseparam(struct net_device *ndev,
2251                                 struct ethtool_pauseparam *pause)
2252 {
2253         struct cpsw_priv *priv = netdev_priv(ndev);
2254
2255         pause->autoneg = AUTONEG_DISABLE;
2256         pause->rx_pause = priv->rx_pause ? true : false;
2257         pause->tx_pause = priv->tx_pause ? true : false;
2258 }
2259
2260 static int cpsw_set_pauseparam(struct net_device *ndev,
2261                                struct ethtool_pauseparam *pause)
2262 {
2263         struct cpsw_priv *priv = netdev_priv(ndev);
2264         bool link;
2265
2266         priv->rx_pause = pause->rx_pause ? true : false;
2267         priv->tx_pause = pause->tx_pause ? true : false;
2268
2269         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2270         return 0;
2271 }
2272
2273 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2274 {
2275         struct cpsw_priv *priv = netdev_priv(ndev);
2276         struct cpsw_common *cpsw = priv->cpsw;
2277         int ret;
2278
2279         ret = pm_runtime_get_sync(cpsw->dev);
2280         if (ret < 0) {
2281                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2282                 pm_runtime_put_noidle(cpsw->dev);
2283         }
2284
2285         return ret;
2286 }
2287
2288 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2289 {
2290         struct cpsw_priv *priv = netdev_priv(ndev);
2291         int ret;
2292
2293         ret = pm_runtime_put(priv->cpsw->dev);
2294         if (ret < 0)
2295                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2296 }
2297
2298 static void cpsw_get_channels(struct net_device *ndev,
2299                               struct ethtool_channels *ch)
2300 {
2301         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2302
2303         ch->max_combined = 0;
2304         ch->max_rx = CPSW_MAX_QUEUES;
2305         ch->max_tx = CPSW_MAX_QUEUES;
2306         ch->max_other = 0;
2307         ch->other_count = 0;
2308         ch->rx_count = cpsw->rx_ch_num;
2309         ch->tx_count = cpsw->tx_ch_num;
2310         ch->combined_count = 0;
2311 }
2312
2313 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2314                                   struct ethtool_channels *ch)
2315 {
2316         if (ch->combined_count)
2317                 return -EINVAL;
2318
2319         /* verify we have at least one channel in each direction */
2320         if (!ch->rx_count || !ch->tx_count)
2321                 return -EINVAL;
2322
2323         if (ch->rx_count > cpsw->data.channels ||
2324             ch->tx_count > cpsw->data.channels)
2325                 return -EINVAL;
2326
2327         return 0;
2328 }
2329
2330 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2331 {
2332         struct cpsw_common *cpsw = priv->cpsw;
2333         void (*handler)(void *, int, int);
2334         struct netdev_queue *queue;
2335         struct cpsw_vector *vec;
2336         int ret, *ch;
2337
2338         if (rx) {
2339                 ch = &cpsw->rx_ch_num;
2340                 vec = cpsw->rxv;
2341                 handler = cpsw_rx_handler;
2342         } else {
2343                 ch = &cpsw->tx_ch_num;
2344                 vec = cpsw->txv;
2345                 handler = cpsw_tx_handler;
2346         }
2347
2348         while (*ch < ch_num) {
2349                 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2350                 queue = netdev_get_tx_queue(priv->ndev, *ch);
2351                 queue->tx_maxrate = 0;
2352
2353                 if (IS_ERR(vec[*ch].ch))
2354                         return PTR_ERR(vec[*ch].ch);
2355
2356                 if (!vec[*ch].ch)
2357                         return -EINVAL;
2358
2359                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2360                           (rx ? "rx" : "tx"));
2361                 (*ch)++;
2362         }
2363
2364         while (*ch > ch_num) {
2365                 (*ch)--;
2366
2367                 ret = cpdma_chan_destroy(vec[*ch].ch);
2368                 if (ret)
2369                         return ret;
2370
2371                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2372                           (rx ? "rx" : "tx"));
2373         }
2374
2375         return 0;
2376 }
2377
2378 static int cpsw_update_channels(struct cpsw_priv *priv,
2379                                 struct ethtool_channels *ch)
2380 {
2381         int ret;
2382
2383         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2384         if (ret)
2385                 return ret;
2386
2387         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2388         if (ret)
2389                 return ret;
2390
2391         return 0;
2392 }
2393
2394 static void cpsw_suspend_data_pass(struct net_device *ndev)
2395 {
2396         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2397         struct cpsw_slave *slave;
2398         int i;
2399
2400         /* Disable NAPI scheduling */
2401         cpsw_intr_disable(cpsw);
2402
2403         /* Stop all transmit queues for every network device.
2404          * Disable re-using rx descriptors with dormant_on.
2405          */
2406         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2407                 if (!(slave->ndev && netif_running(slave->ndev)))
2408                         continue;
2409
2410                 netif_tx_stop_all_queues(slave->ndev);
2411                 netif_dormant_on(slave->ndev);
2412         }
2413
2414         /* Handle rest of tx packets and stop cpdma channels */
2415         cpdma_ctlr_stop(cpsw->dma);
2416 }
2417
2418 static int cpsw_resume_data_pass(struct net_device *ndev)
2419 {
2420         struct cpsw_priv *priv = netdev_priv(ndev);
2421         struct cpsw_common *cpsw = priv->cpsw;
2422         struct cpsw_slave *slave;
2423         int i, ret;
2424
2425         /* Allow rx packets handling */
2426         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2427                 if (slave->ndev && netif_running(slave->ndev))
2428                         netif_dormant_off(slave->ndev);
2429
2430         /* After this receive is started */
2431         if (cpsw->usage_count) {
2432                 ret = cpsw_fill_rx_channels(priv);
2433                 if (ret)
2434                         return ret;
2435
2436                 cpdma_ctlr_start(cpsw->dma);
2437                 cpsw_intr_enable(cpsw);
2438         }
2439
2440         /* Resume transmit for every affected interface */
2441         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2442                 if (slave->ndev && netif_running(slave->ndev))
2443                         netif_tx_start_all_queues(slave->ndev);
2444
2445         return 0;
2446 }
2447
2448 static int cpsw_set_channels(struct net_device *ndev,
2449                              struct ethtool_channels *chs)
2450 {
2451         struct cpsw_priv *priv = netdev_priv(ndev);
2452         struct cpsw_common *cpsw = priv->cpsw;
2453         struct cpsw_slave *slave;
2454         int i, ret;
2455
2456         ret = cpsw_check_ch_settings(cpsw, chs);
2457         if (ret < 0)
2458                 return ret;
2459
2460         cpsw_suspend_data_pass(ndev);
2461         ret = cpsw_update_channels(priv, chs);
2462         if (ret)
2463                 goto err;
2464
2465         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2466                 if (!(slave->ndev && netif_running(slave->ndev)))
2467                         continue;
2468
2469                 /* Inform stack about new count of queues */
2470                 ret = netif_set_real_num_tx_queues(slave->ndev,
2471                                                    cpsw->tx_ch_num);
2472                 if (ret) {
2473                         dev_err(priv->dev, "cannot set real number of tx queues\n");
2474                         goto err;
2475                 }
2476
2477                 ret = netif_set_real_num_rx_queues(slave->ndev,
2478                                                    cpsw->rx_ch_num);
2479                 if (ret) {
2480                         dev_err(priv->dev, "cannot set real number of rx queues\n");
2481                         goto err;
2482                 }
2483         }
2484
2485         if (cpsw->usage_count)
2486                 cpsw_split_res(ndev);
2487
2488         ret = cpsw_resume_data_pass(ndev);
2489         if (!ret)
2490                 return 0;
2491 err:
2492         dev_err(priv->dev, "cannot update channels number, closing device\n");
2493         dev_close(ndev);
2494         return ret;
2495 }
2496
2497 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2498 {
2499         struct cpsw_priv *priv = netdev_priv(ndev);
2500         struct cpsw_common *cpsw = priv->cpsw;
2501         int slave_no = cpsw_slave_index(cpsw, priv);
2502
2503         if (cpsw->slaves[slave_no].phy)
2504                 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2505         else
2506                 return -EOPNOTSUPP;
2507 }
2508
2509 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2510 {
2511         struct cpsw_priv *priv = netdev_priv(ndev);
2512         struct cpsw_common *cpsw = priv->cpsw;
2513         int slave_no = cpsw_slave_index(cpsw, priv);
2514
2515         if (cpsw->slaves[slave_no].phy)
2516                 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2517         else
2518                 return -EOPNOTSUPP;
2519 }
2520
2521 static int cpsw_nway_reset(struct net_device *ndev)
2522 {
2523         struct cpsw_priv *priv = netdev_priv(ndev);
2524         struct cpsw_common *cpsw = priv->cpsw;
2525         int slave_no = cpsw_slave_index(cpsw, priv);
2526
2527         if (cpsw->slaves[slave_no].phy)
2528                 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2529         else
2530                 return -EOPNOTSUPP;
2531 }
2532
2533 static void cpsw_get_ringparam(struct net_device *ndev,
2534                                struct ethtool_ringparam *ering)
2535 {
2536         struct cpsw_priv *priv = netdev_priv(ndev);
2537         struct cpsw_common *cpsw = priv->cpsw;
2538
2539         /* not supported */
2540         ering->tx_max_pending = 0;
2541         ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2542         ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2543         ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2544 }
2545
2546 static int cpsw_set_ringparam(struct net_device *ndev,
2547                               struct ethtool_ringparam *ering)
2548 {
2549         struct cpsw_priv *priv = netdev_priv(ndev);
2550         struct cpsw_common *cpsw = priv->cpsw;
2551         int ret;
2552
2553         /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2554
2555         if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
2556             ering->rx_pending < CPSW_MAX_QUEUES ||
2557             ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
2558                 return -EINVAL;
2559
2560         if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
2561                 return 0;
2562
2563         cpsw_suspend_data_pass(ndev);
2564
2565         cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
2566
2567         if (cpsw->usage_count)
2568                 cpdma_chan_split_pool(cpsw->dma);
2569
2570         ret = cpsw_resume_data_pass(ndev);
2571         if (!ret)
2572                 return 0;
2573
2574         dev_err(&ndev->dev, "cannot set ring params, closing device\n");
2575         dev_close(ndev);
2576         return ret;
2577 }
2578
2579 static const struct ethtool_ops cpsw_ethtool_ops = {
2580         .get_drvinfo    = cpsw_get_drvinfo,
2581         .get_msglevel   = cpsw_get_msglevel,
2582         .set_msglevel   = cpsw_set_msglevel,
2583         .get_link       = ethtool_op_get_link,
2584         .get_ts_info    = cpsw_get_ts_info,
2585         .get_coalesce   = cpsw_get_coalesce,
2586         .set_coalesce   = cpsw_set_coalesce,
2587         .get_sset_count         = cpsw_get_sset_count,
2588         .get_strings            = cpsw_get_strings,
2589         .get_ethtool_stats      = cpsw_get_ethtool_stats,
2590         .get_pauseparam         = cpsw_get_pauseparam,
2591         .set_pauseparam         = cpsw_set_pauseparam,
2592         .get_wol        = cpsw_get_wol,
2593         .set_wol        = cpsw_set_wol,
2594         .get_regs_len   = cpsw_get_regs_len,
2595         .get_regs       = cpsw_get_regs,
2596         .begin          = cpsw_ethtool_op_begin,
2597         .complete       = cpsw_ethtool_op_complete,
2598         .get_channels   = cpsw_get_channels,
2599         .set_channels   = cpsw_set_channels,
2600         .get_link_ksettings     = cpsw_get_link_ksettings,
2601         .set_link_ksettings     = cpsw_set_link_ksettings,
2602         .get_eee        = cpsw_get_eee,
2603         .set_eee        = cpsw_set_eee,
2604         .nway_reset     = cpsw_nway_reset,
2605         .get_ringparam = cpsw_get_ringparam,
2606         .set_ringparam = cpsw_set_ringparam,
2607 };
2608
2609 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2610                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
2611 {
2612         void __iomem            *regs = cpsw->regs;
2613         int                     slave_num = slave->slave_num;
2614         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
2615
2616         slave->data     = data;
2617         slave->regs     = regs + slave_reg_ofs;
2618         slave->sliver   = regs + sliver_reg_ofs;
2619         slave->port_vlan = data->dual_emac_res_vlan;
2620 }
2621
2622 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2623                          struct platform_device *pdev)
2624 {
2625         struct device_node *node = pdev->dev.of_node;
2626         struct device_node *slave_node;
2627         int i = 0, ret;
2628         u32 prop;
2629
2630         if (!node)
2631                 return -EINVAL;
2632
2633         if (of_property_read_u32(node, "slaves", &prop)) {
2634                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2635                 return -EINVAL;
2636         }
2637         data->slaves = prop;
2638
2639         if (of_property_read_u32(node, "active_slave", &prop)) {
2640                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2641                 return -EINVAL;
2642         }
2643         data->active_slave = prop;
2644
2645         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2646                                         * sizeof(struct cpsw_slave_data),
2647                                         GFP_KERNEL);
2648         if (!data->slave_data)
2649                 return -ENOMEM;
2650
2651         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2652                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2653                 return -EINVAL;
2654         }
2655         data->channels = prop;
2656
2657         if (of_property_read_u32(node, "ale_entries", &prop)) {
2658                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2659                 return -EINVAL;
2660         }
2661         data->ale_entries = prop;
2662
2663         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2664                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2665                 return -EINVAL;
2666         }
2667         data->bd_ram_size = prop;
2668
2669         if (of_property_read_u32(node, "mac_control", &prop)) {
2670                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2671                 return -EINVAL;
2672         }
2673         data->mac_control = prop;
2674
2675         if (of_property_read_bool(node, "dual_emac"))
2676                 data->dual_emac = 1;
2677
2678         /*
2679          * Populate all the child nodes here...
2680          */
2681         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2682         /* We do not want to force this, as in some cases may not have child */
2683         if (ret)
2684                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2685
2686         for_each_available_child_of_node(node, slave_node) {
2687                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2688                 const void *mac_addr = NULL;
2689                 int lenp;
2690                 const __be32 *parp;
2691
2692                 /* This is no slave child node, continue */
2693                 if (strcmp(slave_node->name, "slave"))
2694                         continue;
2695
2696                 slave_data->phy_node = of_parse_phandle(slave_node,
2697                                                         "phy-handle", 0);
2698                 parp = of_get_property(slave_node, "phy_id", &lenp);
2699                 if (slave_data->phy_node) {
2700                         dev_dbg(&pdev->dev,
2701                                 "slave[%d] using phy-handle=\"%pOF\"\n",
2702                                 i, slave_data->phy_node);
2703                 } else if (of_phy_is_fixed_link(slave_node)) {
2704                         /* In the case of a fixed PHY, the DT node associated
2705                          * to the PHY is the Ethernet MAC DT node.
2706                          */
2707                         ret = of_phy_register_fixed_link(slave_node);
2708                         if (ret) {
2709                                 if (ret != -EPROBE_DEFER)
2710                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2711                                 return ret;
2712                         }
2713                         slave_data->phy_node = of_node_get(slave_node);
2714                 } else if (parp) {
2715                         u32 phyid;
2716                         struct device_node *mdio_node;
2717                         struct platform_device *mdio;
2718
2719                         if (lenp != (sizeof(__be32) * 2)) {
2720                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2721                                 goto no_phy_slave;
2722                         }
2723                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2724                         phyid = be32_to_cpup(parp+1);
2725                         mdio = of_find_device_by_node(mdio_node);
2726                         of_node_put(mdio_node);
2727                         if (!mdio) {
2728                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
2729                                 return -EINVAL;
2730                         }
2731                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2732                                  PHY_ID_FMT, mdio->name, phyid);
2733                         put_device(&mdio->dev);
2734                 } else {
2735                         dev_err(&pdev->dev,
2736                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2737                                 i);
2738                         goto no_phy_slave;
2739                 }
2740                 slave_data->phy_if = of_get_phy_mode(slave_node);
2741                 if (slave_data->phy_if < 0) {
2742                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2743                                 i);
2744                         return slave_data->phy_if;
2745                 }
2746
2747 no_phy_slave:
2748                 mac_addr = of_get_mac_address(slave_node);
2749                 if (mac_addr) {
2750                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2751                 } else {
2752                         ret = ti_cm_get_macid(&pdev->dev, i,
2753                                               slave_data->mac_addr);
2754                         if (ret)
2755                                 return ret;
2756                 }
2757                 if (data->dual_emac) {
2758                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2759                                                  &prop)) {
2760                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2761                                 slave_data->dual_emac_res_vlan = i+1;
2762                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2763                                         slave_data->dual_emac_res_vlan, i);
2764                         } else {
2765                                 slave_data->dual_emac_res_vlan = prop;
2766                         }
2767                 }
2768
2769                 i++;
2770                 if (i == data->slaves)
2771                         break;
2772         }
2773
2774         return 0;
2775 }
2776
2777 static void cpsw_remove_dt(struct platform_device *pdev)
2778 {
2779         struct net_device *ndev = platform_get_drvdata(pdev);
2780         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2781         struct cpsw_platform_data *data = &cpsw->data;
2782         struct device_node *node = pdev->dev.of_node;
2783         struct device_node *slave_node;
2784         int i = 0;
2785
2786         for_each_available_child_of_node(node, slave_node) {
2787                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2788
2789                 if (strcmp(slave_node->name, "slave"))
2790                         continue;
2791
2792                 if (of_phy_is_fixed_link(slave_node))
2793                         of_phy_deregister_fixed_link(slave_node);
2794
2795                 of_node_put(slave_data->phy_node);
2796
2797                 i++;
2798                 if (i == data->slaves)
2799                         break;
2800         }
2801
2802         of_platform_depopulate(&pdev->dev);
2803 }
2804
2805 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2806 {
2807         struct cpsw_common              *cpsw = priv->cpsw;
2808         struct cpsw_platform_data       *data = &cpsw->data;
2809         struct net_device               *ndev;
2810         struct cpsw_priv                *priv_sl2;
2811         int ret = 0;
2812
2813         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2814         if (!ndev) {
2815                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2816                 return -ENOMEM;
2817         }
2818
2819         priv_sl2 = netdev_priv(ndev);
2820         priv_sl2->cpsw = cpsw;
2821         priv_sl2->ndev = ndev;
2822         priv_sl2->dev  = &ndev->dev;
2823         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2824
2825         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2826                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2827                         ETH_ALEN);
2828                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2829                          priv_sl2->mac_addr);
2830         } else {
2831                 random_ether_addr(priv_sl2->mac_addr);
2832                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2833                          priv_sl2->mac_addr);
2834         }
2835         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2836
2837         priv_sl2->emac_port = 1;
2838         cpsw->slaves[1].ndev = ndev;
2839         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2840
2841         ndev->netdev_ops = &cpsw_netdev_ops;
2842         ndev->ethtool_ops = &cpsw_ethtool_ops;
2843
2844         /* register the network device */
2845         SET_NETDEV_DEV(ndev, cpsw->dev);
2846         ret = register_netdev(ndev);
2847         if (ret) {
2848                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2849                 free_netdev(ndev);
2850                 ret = -ENODEV;
2851         }
2852
2853         return ret;
2854 }
2855
2856 #define CPSW_QUIRK_IRQ          BIT(0)
2857
2858 static const struct platform_device_id cpsw_devtype[] = {
2859         {
2860                 /* keep it for existing comaptibles */
2861                 .name = "cpsw",
2862                 .driver_data = CPSW_QUIRK_IRQ,
2863         }, {
2864                 .name = "am335x-cpsw",
2865                 .driver_data = CPSW_QUIRK_IRQ,
2866         }, {
2867                 .name = "am4372-cpsw",
2868                 .driver_data = 0,
2869         }, {
2870                 .name = "dra7-cpsw",
2871                 .driver_data = 0,
2872         }, {
2873                 /* sentinel */
2874         }
2875 };
2876 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2877
2878 enum ti_cpsw_type {
2879         CPSW = 0,
2880         AM335X_CPSW,
2881         AM4372_CPSW,
2882         DRA7_CPSW,
2883 };
2884
2885 static const struct of_device_id cpsw_of_mtable[] = {
2886         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2887         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2888         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2889         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2890         { /* sentinel */ },
2891 };
2892 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2893
2894 static int cpsw_probe(struct platform_device *pdev)
2895 {
2896         struct clk                      *clk;
2897         struct cpsw_platform_data       *data;
2898         struct net_device               *ndev;
2899         struct cpsw_priv                *priv;
2900         struct cpdma_params             dma_params;
2901         struct cpsw_ale_params          ale_params;
2902         void __iomem                    *ss_regs;
2903         void __iomem                    *cpts_regs;
2904         struct resource                 *res, *ss_res;
2905         const struct of_device_id       *of_id;
2906         struct gpio_descs               *mode;
2907         u32 slave_offset, sliver_offset, slave_size;
2908         struct cpsw_common              *cpsw;
2909         int ret = 0, i;
2910         int irq;
2911
2912         cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2913         if (!cpsw)
2914                 return -ENOMEM;
2915
2916         cpsw->dev = &pdev->dev;
2917
2918         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2919         if (!ndev) {
2920                 dev_err(&pdev->dev, "error allocating net_device\n");
2921                 return -ENOMEM;
2922         }
2923
2924         platform_set_drvdata(pdev, ndev);
2925         priv = netdev_priv(ndev);
2926         priv->cpsw = cpsw;
2927         priv->ndev = ndev;
2928         priv->dev  = &ndev->dev;
2929         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2930         cpsw->rx_packet_max = max(rx_packet_max, 128);
2931
2932         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2933         if (IS_ERR(mode)) {
2934                 ret = PTR_ERR(mode);
2935                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2936                 goto clean_ndev_ret;
2937         }
2938
2939         /*
2940          * This may be required here for child devices.
2941          */
2942         pm_runtime_enable(&pdev->dev);
2943
2944         /* Select default pin state */
2945         pinctrl_pm_select_default_state(&pdev->dev);
2946
2947         /* Need to enable clocks with runtime PM api to access module
2948          * registers
2949          */
2950         ret = pm_runtime_get_sync(&pdev->dev);
2951         if (ret < 0) {
2952                 pm_runtime_put_noidle(&pdev->dev);
2953                 goto clean_runtime_disable_ret;
2954         }
2955
2956         ret = cpsw_probe_dt(&cpsw->data, pdev);
2957         if (ret)
2958                 goto clean_dt_ret;
2959
2960         data = &cpsw->data;
2961         cpsw->rx_ch_num = 1;
2962         cpsw->tx_ch_num = 1;
2963
2964         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2965                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2966                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2967         } else {
2968                 eth_random_addr(priv->mac_addr);
2969                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2970         }
2971
2972         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2973
2974         cpsw->slaves = devm_kzalloc(&pdev->dev,
2975                                     sizeof(struct cpsw_slave) * data->slaves,
2976                                     GFP_KERNEL);
2977         if (!cpsw->slaves) {
2978                 ret = -ENOMEM;
2979                 goto clean_dt_ret;
2980         }
2981         for (i = 0; i < data->slaves; i++)
2982                 cpsw->slaves[i].slave_num = i;
2983
2984         cpsw->slaves[0].ndev = ndev;
2985         priv->emac_port = 0;
2986
2987         clk = devm_clk_get(&pdev->dev, "fck");
2988         if (IS_ERR(clk)) {
2989                 dev_err(priv->dev, "fck is not found\n");
2990                 ret = -ENODEV;
2991                 goto clean_dt_ret;
2992         }
2993         cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2994
2995         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2996         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2997         if (IS_ERR(ss_regs)) {
2998                 ret = PTR_ERR(ss_regs);
2999                 goto clean_dt_ret;
3000         }
3001         cpsw->regs = ss_regs;
3002
3003         cpsw->version = readl(&cpsw->regs->id_ver);
3004
3005         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3006         cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
3007         if (IS_ERR(cpsw->wr_regs)) {
3008                 ret = PTR_ERR(cpsw->wr_regs);
3009                 goto clean_dt_ret;
3010         }
3011
3012         memset(&dma_params, 0, sizeof(dma_params));
3013         memset(&ale_params, 0, sizeof(ale_params));
3014
3015         switch (cpsw->version) {
3016         case CPSW_VERSION_1:
3017                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
3018                 cpts_regs               = ss_regs + CPSW1_CPTS_OFFSET;
3019                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
3020                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
3021                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
3022                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
3023                 slave_offset         = CPSW1_SLAVE_OFFSET;
3024                 slave_size           = CPSW1_SLAVE_SIZE;
3025                 sliver_offset        = CPSW1_SLIVER_OFFSET;
3026                 dma_params.desc_mem_phys = 0;
3027                 break;
3028         case CPSW_VERSION_2:
3029         case CPSW_VERSION_3:
3030         case CPSW_VERSION_4:
3031                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3032                 cpts_regs               = ss_regs + CPSW2_CPTS_OFFSET;
3033                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
3034                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
3035                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
3036                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
3037                 slave_offset         = CPSW2_SLAVE_OFFSET;
3038                 slave_size           = CPSW2_SLAVE_SIZE;
3039                 sliver_offset        = CPSW2_SLIVER_OFFSET;
3040                 dma_params.desc_mem_phys =
3041                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3042                 break;
3043         default:
3044                 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
3045                 ret = -ENODEV;
3046                 goto clean_dt_ret;
3047         }
3048         for (i = 0; i < cpsw->data.slaves; i++) {
3049                 struct cpsw_slave *slave = &cpsw->slaves[i];
3050
3051                 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3052                 slave_offset  += slave_size;
3053                 sliver_offset += SLIVER_SIZE;
3054         }
3055
3056         dma_params.dev          = &pdev->dev;
3057         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
3058         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
3059         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
3060         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
3061         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
3062
3063         dma_params.num_chan             = data->channels;
3064         dma_params.has_soft_reset       = true;
3065         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
3066         dma_params.desc_mem_size        = data->bd_ram_size;
3067         dma_params.desc_align           = 16;
3068         dma_params.has_ext_regs         = true;
3069         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
3070         dma_params.bus_freq_mhz         = cpsw->bus_freq_mhz;
3071         dma_params.descs_pool_size      = descs_pool_size;
3072
3073         cpsw->dma = cpdma_ctlr_create(&dma_params);
3074         if (!cpsw->dma) {
3075                 dev_err(priv->dev, "error initializing dma\n");
3076                 ret = -ENOMEM;
3077                 goto clean_dt_ret;
3078         }
3079
3080         cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
3081         if (IS_ERR(cpsw->txv[0].ch)) {
3082                 dev_err(priv->dev, "error initializing tx dma channel\n");
3083                 ret = PTR_ERR(cpsw->txv[0].ch);
3084                 goto clean_dma_ret;
3085         }
3086
3087         cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3088         if (IS_ERR(cpsw->rxv[0].ch)) {
3089                 dev_err(priv->dev, "error initializing rx dma channel\n");
3090                 ret = PTR_ERR(cpsw->rxv[0].ch);
3091                 goto clean_dma_ret;
3092         }
3093
3094         ale_params.dev                  = &pdev->dev;
3095         ale_params.ale_ageout           = ale_ageout;
3096         ale_params.ale_entries          = data->ale_entries;
3097         ale_params.ale_ports            = CPSW_ALE_PORTS_NUM;
3098
3099         cpsw->ale = cpsw_ale_create(&ale_params);
3100         if (!cpsw->ale) {
3101                 dev_err(priv->dev, "error initializing ale engine\n");
3102                 ret = -ENODEV;
3103                 goto clean_dma_ret;
3104         }
3105
3106         cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3107         if (IS_ERR(cpsw->cpts)) {
3108                 ret = PTR_ERR(cpsw->cpts);
3109                 goto clean_dma_ret;
3110         }
3111
3112         ndev->irq = platform_get_irq(pdev, 1);
3113         if (ndev->irq < 0) {
3114                 dev_err(priv->dev, "error getting irq resource\n");
3115                 ret = ndev->irq;
3116                 goto clean_dma_ret;
3117         }
3118
3119         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
3120         if (of_id) {
3121                 pdev->id_entry = of_id->data;
3122                 if (pdev->id_entry->driver_data)
3123                         cpsw->quirk_irq = true;
3124         }
3125
3126         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3127
3128         ndev->netdev_ops = &cpsw_netdev_ops;
3129         ndev->ethtool_ops = &cpsw_ethtool_ops;
3130         netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
3131         netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
3132         cpsw_split_res(ndev);
3133
3134         /* register the network device */
3135         SET_NETDEV_DEV(ndev, &pdev->dev);
3136         ret = register_netdev(ndev);
3137         if (ret) {
3138                 dev_err(priv->dev, "error registering net device\n");
3139                 ret = -ENODEV;
3140                 goto clean_dma_ret;
3141         }
3142
3143         if (cpsw->data.dual_emac) {
3144                 ret = cpsw_probe_dual_emac(priv);
3145                 if (ret) {
3146                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3147                         goto clean_unregister_netdev_ret;
3148                 }
3149         }
3150
3151         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3152          * MISC IRQs which are always kept disabled with this driver so
3153          * we will not request them.
3154          *
3155          * If anyone wants to implement support for those, make sure to
3156          * first request and append them to irqs_table array.
3157          */
3158
3159         /* RX IRQ */
3160         irq = platform_get_irq(pdev, 1);
3161         if (irq < 0) {
3162                 ret = irq;
3163                 goto clean_dma_ret;
3164         }
3165
3166         cpsw->irqs_table[0] = irq;
3167         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3168                                0, dev_name(&pdev->dev), cpsw);
3169         if (ret < 0) {
3170                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3171                 goto clean_dma_ret;
3172         }
3173
3174         /* TX IRQ */
3175         irq = platform_get_irq(pdev, 2);
3176         if (irq < 0) {
3177                 ret = irq;
3178                 goto clean_dma_ret;
3179         }
3180
3181         cpsw->irqs_table[1] = irq;
3182         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3183                                0, dev_name(&pdev->dev), cpsw);
3184         if (ret < 0) {
3185                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3186                 goto clean_dma_ret;
3187         }
3188
3189         cpsw_notice(priv, probe,
3190                     "initialized device (regs %pa, irq %d, pool size %d)\n",
3191                     &ss_res->start, ndev->irq, dma_params.descs_pool_size);
3192
3193         pm_runtime_put(&pdev->dev);
3194
3195         return 0;
3196
3197 clean_unregister_netdev_ret:
3198         unregister_netdev(ndev);
3199 clean_dma_ret:
3200         cpdma_ctlr_destroy(cpsw->dma);
3201 clean_dt_ret:
3202         cpsw_remove_dt(pdev);
3203         pm_runtime_put_sync(&pdev->dev);
3204 clean_runtime_disable_ret:
3205         pm_runtime_disable(&pdev->dev);
3206 clean_ndev_ret:
3207         free_netdev(priv->ndev);
3208         return ret;
3209 }
3210
3211 static int cpsw_remove(struct platform_device *pdev)
3212 {
3213         struct net_device *ndev = platform_get_drvdata(pdev);
3214         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3215         int ret;
3216
3217         ret = pm_runtime_get_sync(&pdev->dev);
3218         if (ret < 0) {
3219                 pm_runtime_put_noidle(&pdev->dev);
3220                 return ret;
3221         }
3222
3223         if (cpsw->data.dual_emac)
3224                 unregister_netdev(cpsw->slaves[1].ndev);
3225         unregister_netdev(ndev);
3226
3227         cpts_release(cpsw->cpts);
3228         cpdma_ctlr_destroy(cpsw->dma);
3229         cpsw_remove_dt(pdev);
3230         pm_runtime_put_sync(&pdev->dev);
3231         pm_runtime_disable(&pdev->dev);
3232         if (cpsw->data.dual_emac)
3233                 free_netdev(cpsw->slaves[1].ndev);
3234         free_netdev(ndev);
3235         return 0;
3236 }
3237
3238 #ifdef CONFIG_PM_SLEEP
3239 static int cpsw_suspend(struct device *dev)
3240 {
3241         struct platform_device  *pdev = to_platform_device(dev);
3242         struct net_device       *ndev = platform_get_drvdata(pdev);
3243         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3244
3245         if (cpsw->data.dual_emac) {
3246                 int i;
3247
3248                 for (i = 0; i < cpsw->data.slaves; i++) {
3249                         if (netif_running(cpsw->slaves[i].ndev))
3250                                 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3251                 }
3252         } else {
3253                 if (netif_running(ndev))
3254                         cpsw_ndo_stop(ndev);
3255         }
3256
3257         /* Select sleep pin state */
3258         pinctrl_pm_select_sleep_state(dev);
3259
3260         return 0;
3261 }
3262
3263 static int cpsw_resume(struct device *dev)
3264 {
3265         struct platform_device  *pdev = to_platform_device(dev);
3266         struct net_device       *ndev = platform_get_drvdata(pdev);
3267         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3268
3269         /* Select default pin state */
3270         pinctrl_pm_select_default_state(dev);
3271
3272         /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3273         rtnl_lock();
3274         if (cpsw->data.dual_emac) {
3275                 int i;
3276
3277                 for (i = 0; i < cpsw->data.slaves; i++) {
3278                         if (netif_running(cpsw->slaves[i].ndev))
3279                                 cpsw_ndo_open(cpsw->slaves[i].ndev);
3280                 }
3281         } else {
3282                 if (netif_running(ndev))
3283                         cpsw_ndo_open(ndev);
3284         }
3285         rtnl_unlock();
3286
3287         return 0;
3288 }
3289 #endif
3290
3291 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3292
3293 static struct platform_driver cpsw_driver = {
3294         .driver = {
3295                 .name    = "cpsw",
3296                 .pm      = &cpsw_pm_ops,
3297                 .of_match_table = cpsw_of_mtable,
3298         },
3299         .probe = cpsw_probe,
3300         .remove = cpsw_remove,
3301 };
3302
3303 module_platform_driver(cpsw_driver);
3304
3305 MODULE_LICENSE("GPL");
3306 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3307 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3308 MODULE_DESCRIPTION("TI CPSW Ethernet driver");