drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/of.h>
  33 #include <linux/of_net.h>
  34 #include <linux/of_device.h>
  35 #include <linux/if_vlan.h>
  36
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include "cpsw.h"
  40 #include "cpsw_ale.h"
  41 #include "cpts.h"
  42 #include "davinci_cpdma.h"
  43
  44 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  45                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  46                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  47                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  48                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  49                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  50                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  51                          NETIF_MSG_RX_STATUS)
  52
  53 #define cpsw_info(priv, type, format, ...)              \
  54 do {                                                            \
  55         if (netif_msg_##type(priv) && net_ratelimit())          \
  56                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  57 } while (0)
  58
  59 #define cpsw_err(priv, type, format, ...)               \
  60 do {                                                            \
  61         if (netif_msg_##type(priv) && net_ratelimit())          \
  62                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  63 } while (0)
  64
  65 #define cpsw_dbg(priv, type, format, ...)               \
  66 do {                                                            \
  67         if (netif_msg_##type(priv) && net_ratelimit())          \
  68                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  69 } while (0)
  70
  71 #define cpsw_notice(priv, type, format, ...)            \
  72 do {                                                            \
  73         if (netif_msg_##type(priv) && net_ratelimit())          \
  74                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  75 } while (0)
  76
  77 #define ALE_ALL_PORTS           0x7
  78
  79 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  80 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  81 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  82
  83 #define CPSW_VERSION_1          0x19010a
  84 #define CPSW_VERSION_2          0x19010c
  85 #define CPSW_VERSION_3          0x19010f
  86 #define CPSW_VERSION_4          0x190112
  87
  88 #define HOST_PORT_NUM           0
  89 #define SLIVER_SIZE             0x40
  90
  91 #define CPSW1_HOST_PORT_OFFSET  0x028
  92 #define CPSW1_SLAVE_OFFSET      0x050
  93 #define CPSW1_SLAVE_SIZE        0x040
  94 #define CPSW1_CPDMA_OFFSET      0x100
  95 #define CPSW1_STATERAM_OFFSET   0x200
  96 #define CPSW1_HW_STATS          0x400
  97 #define CPSW1_CPTS_OFFSET       0x500
  98 #define CPSW1_ALE_OFFSET        0x600
  99 #define CPSW1_SLIVER_OFFSET     0x700
 100
 101 #define CPSW2_HOST_PORT_OFFSET  0x108
 102 #define CPSW2_SLAVE_OFFSET      0x200
 103 #define CPSW2_SLAVE_SIZE        0x100
 104 #define CPSW2_CPDMA_OFFSET      0x800
 105 #define CPSW2_HW_STATS          0x900
 106 #define CPSW2_STATERAM_OFFSET   0xa00
 107 #define CPSW2_CPTS_OFFSET       0xc00
 108 #define CPSW2_ALE_OFFSET        0xd00
 109 #define CPSW2_SLIVER_OFFSET     0xd80
 110 #define CPSW2_BD_OFFSET         0x2000
 111
 112 #define CPDMA_RXTHRESH          0x0c0
 113 #define CPDMA_RXFREE            0x0e0
 114 #define CPDMA_TXHDP             0x00
 115 #define CPDMA_RXHDP             0x20
 116 #define CPDMA_TXCP              0x40
 117 #define CPDMA_RXCP              0x60
 118
 119 #define CPSW_POLL_WEIGHT        64
 120 #define CPSW_MIN_PACKET_SIZE    60
 121 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 122
 123 #define RX_PRIORITY_MAPPING     0x76543210
 124 #define TX_PRIORITY_MAPPING     0x33221100
 125 #define CPDMA_TX_PRIORITY_MAP   0x76543210
 126
 127 #define CPSW_VLAN_AWARE         BIT(1)
 128 #define CPSW_ALE_VLAN_AWARE     1
 129
 130 #define CPSW_FIFO_NORMAL_MODE           (0 << 15)
 131 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 15)
 132 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 15)
 133
 134 #define CPSW_INTPACEEN          (0x3f << 16)
 135 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 136 #define CPSW_CMINTMAX_CNT       63
 137 #define CPSW_CMINTMIN_CNT       2
 138 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 139 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 140
 141 #define cpsw_enable_irq(priv)   \
 142         do {                    \
 143                 u32 i;          \
 144                 for (i = 0; i < priv->num_irqs; i++) \
 145                         enable_irq(priv->irqs_table[i]); \
 146         } while (0)
 147 #define cpsw_disable_irq(priv)  \
 148         do {                    \
 149                 u32 i;          \
 150                 for (i = 0; i < priv->num_irqs; i++) \
 151                         disable_irq_nosync(priv->irqs_table[i]); \
 152         } while (0)
 153
 154 #define cpsw_slave_index(priv)                          \
 155                 ((priv->data.dual_emac) ? priv->emac_port :     \
 156                 priv->data.active_slave)
 157
 158 static int debug_level;
 159 module_param(debug_level, int, 0);
 160 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 161
 162 static int ale_ageout = 10;
 163 module_param(ale_ageout, int, 0);
 164 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 165
 166 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 167 module_param(rx_packet_max, int, 0);
 168 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 169
 170 struct cpsw_wr_regs {
 171         u32     id_ver;
 172         u32     soft_reset;
 173         u32     control;
 174         u32     int_control;
 175         u32     rx_thresh_en;
 176         u32     rx_en;
 177         u32     tx_en;
 178         u32     misc_en;
 179         u32     mem_allign1[8];
 180         u32     rx_thresh_stat;
 181         u32     rx_stat;
 182         u32     tx_stat;
 183         u32     misc_stat;
 184         u32     mem_allign2[8];
 185         u32     rx_imax;
 186         u32     tx_imax;
 187
 188 };
 189
 190 struct cpsw_ss_regs {
 191         u32     id_ver;
 192         u32     control;
 193         u32     soft_reset;
 194         u32     stat_port_en;
 195         u32     ptype;
 196         u32     soft_idle;
 197         u32     thru_rate;
 198         u32     gap_thresh;
 199         u32     tx_start_wds;
 200         u32     flow_control;
 201         u32     vlan_ltype;
 202         u32     ts_ltype;
 203         u32     dlr_ltype;
 204 };
 205
 206 /* CPSW_PORT_V1 */
 207 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 208 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 209 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 210 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 211 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 212 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 213 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 214 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 215
 216 /* CPSW_PORT_V2 */
 217 #define CPSW2_CONTROL       0x00 /* Control Register */
 218 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 219 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 220 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 221 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 222 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 223 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 224
 225 /* CPSW_PORT_V1 and V2 */
 226 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 227 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 228 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 229
 230 /* CPSW_PORT_V2 only */
 231 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 234 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 235 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 236 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 237 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 238 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 239
 240 /* Bit definitions for the CPSW2_CONTROL register */
 241 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 242 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 243 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 244 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 245 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 246 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 247 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 248 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 249 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 250 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 251 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 252 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 253 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 254 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 255 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 256 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 257 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 258
 259 #define CTRL_V2_TS_BITS \
 260         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 261          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 262
 263 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 264 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 265 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 266
 267
 268 #define CTRL_V3_TS_BITS \
 269         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 270          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 271          TS_LTYPE1_EN)
 272
 273 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 274 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 275 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 276
 277 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 278 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 279 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 280 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 281 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 282
 283 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 284 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 285
 286 /* Bit definitions for the CPSW1_TS_CTL register */
 287 #define CPSW_V1_TS_RX_EN                BIT(0)
 288 #define CPSW_V1_TS_TX_EN                BIT(4)
 289 #define CPSW_V1_MSG_TYPE_OFS            16
 290
 291 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 292 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 293
 294 struct cpsw_host_regs {
 295         u32     max_blks;
 296         u32     blk_cnt;
 297         u32     tx_in_ctl;
 298         u32     port_vlan;
 299         u32     tx_pri_map;
 300         u32     cpdma_tx_pri_map;
 301         u32     cpdma_rx_chan_map;
 302 };
 303
 304 struct cpsw_sliver_regs {
 305         u32     id_ver;
 306         u32     mac_control;
 307         u32     mac_status;
 308         u32     soft_reset;
 309         u32     rx_maxlen;
 310         u32     __reserved_0;
 311         u32     rx_pause;
 312         u32     tx_pause;
 313         u32     __reserved_1;
 314         u32     rx_pri_map;
 315 };
 316
 317 struct cpsw_hw_stats {
 318         u32     rxgoodframes;
 319         u32     rxbroadcastframes;
 320         u32     rxmulticastframes;
 321         u32     rxpauseframes;
 322         u32     rxcrcerrors;
 323         u32     rxaligncodeerrors;
 324         u32     rxoversizedframes;
 325         u32     rxjabberframes;
 326         u32     rxundersizedframes;
 327         u32     rxfragments;
 328         u32     __pad_0[2];
 329         u32     rxoctets;
 330         u32     txgoodframes;
 331         u32     txbroadcastframes;
 332         u32     txmulticastframes;
 333         u32     txpauseframes;
 334         u32     txdeferredframes;
 335         u32     txcollisionframes;
 336         u32     txsinglecollframes;
 337         u32     txmultcollframes;
 338         u32     txexcessivecollisions;
 339         u32     txlatecollisions;
 340         u32     txunderrun;
 341         u32     txcarriersenseerrors;
 342         u32     txoctets;
 343         u32     octetframes64;
 344         u32     octetframes65t127;
 345         u32     octetframes128t255;
 346         u32     octetframes256t511;
 347         u32     octetframes512t1023;
 348         u32     octetframes1024tup;
 349         u32     netoctets;
 350         u32     rxsofoverruns;
 351         u32     rxmofoverruns;
 352         u32     rxdmaoverruns;
 353 };
 354
 355 struct cpsw_slave {
 356         void __iomem                    *regs;
 357         struct cpsw_sliver_regs __iomem *sliver;
 358         int                             slave_num;
 359         u32                             mac_control;
 360         struct cpsw_slave_data          *data;
 361         struct phy_device               *phy;
 362         struct net_device               *ndev;
 363         u32                             port_vlan;
 364         u32                             open_stat;
 365 };
 366
 367 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 368 {
 369         return __raw_readl(slave->regs + offset);
 370 }
 371
 372 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 373 {
 374         __raw_writel(val, slave->regs + offset);
 375 }
 376
 377 struct cpsw_priv {
 378         spinlock_t                      lock;
 379         struct platform_device          *pdev;
 380         struct net_device               *ndev;
 381         struct napi_struct              napi;
 382         struct device                   *dev;
 383         struct cpsw_platform_data       data;
 384         struct cpsw_ss_regs __iomem     *regs;
 385         struct cpsw_wr_regs __iomem     *wr_regs;
 386         u8 __iomem                      *hw_stats;
 387         struct cpsw_host_regs __iomem   *host_port_regs;
 388         u32                             msg_enable;
 389         u32                             version;
 390         u32                             coal_intvl;
 391         u32                             bus_freq_mhz;
 392         int                             rx_packet_max;
 393         int                             host_port;
 394         struct clk                      *clk;
 395         u8                              mac_addr[ETH_ALEN];
 396         struct cpsw_slave               *slaves;
 397         struct cpdma_ctlr               *dma;
 398         struct cpdma_chan               *txch, *rxch;
 399         struct cpsw_ale                 *ale;
 400         bool                            rx_pause;
 401         bool                            tx_pause;
 402         /* snapshot of IRQ numbers */
 403         u32 irqs_table[4];
 404         u32 num_irqs;
 405         bool irq_enabled;
 406         struct cpts *cpts;
 407         u32 emac_port;
 408 };
 409
 410 struct cpsw_stats {
 411         char stat_string[ETH_GSTRING_LEN];
 412         int type;
 413         int sizeof_stat;
 414         int stat_offset;
 415 };
 416
 417 enum {
 418         CPSW_STATS,
 419         CPDMA_RX_STATS,
 420         CPDMA_TX_STATS,
 421 };
 422
 423 #define CPSW_STAT(m)            CPSW_STATS,                             \
 424                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 425                                 offsetof(struct cpsw_hw_stats, m)
 426 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 427                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 428                                 offsetof(struct cpdma_chan_stats, m)
 429 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 430                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 431                                 offsetof(struct cpdma_chan_stats, m)
 432
 433 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 434         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 435         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 436         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 437         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 438         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 439         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 440         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 441         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 442         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 443         { "Rx Fragments", CPSW_STAT(rxfragments) },
 444         { "Rx Octets", CPSW_STAT(rxoctets) },
 445         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 446         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 447         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 448         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 449         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 450         { "Collisions", CPSW_STAT(txcollisionframes) },
 451         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 452         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 453         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 454         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 455         { "Tx Underrun", CPSW_STAT(txunderrun) },
 456         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 457         { "Tx Octets", CPSW_STAT(txoctets) },
 458         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 459         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 460         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 461         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 462         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 463         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 464         { "Net Octets", CPSW_STAT(netoctets) },
 465         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 466         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 467         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 468         { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 469         { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 470         { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 471         { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) },
 472         { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 473         { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 474         { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 475         { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 476         { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 477         { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 478         { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 479         { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) },
 480         { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 481         { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) },
 482         { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) },
 483         { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) },
 484         { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) },
 485         { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) },
 486         { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) },
 487         { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) },
 488         { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) },
 489         { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) },
 490         { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) },
 491         { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) },
 492         { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) },
 493         { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) },
 494 };
 495
 496 #define CPSW_STATS_LEN  ARRAY_SIZE(cpsw_gstrings_stats)
 497
 498 #define napi_to_priv(napi)      container_of(napi, struct cpsw_priv, napi)
 499 #define for_each_slave(priv, func, arg...)                              \
 500         do {                                                            \
 501                 struct cpsw_slave *slave;                               \
 502                 int n;                                                  \
 503                 if (priv->data.dual_emac)                               \
 504                         (func)((priv)->slaves + priv->emac_port, ##arg);\
 505                 else                                                    \
 506                         for (n = (priv)->data.slaves,                   \
 507                                         slave = (priv)->slaves;         \
 508                                         n; n--)                         \
 509                                 (func)(slave++, ##arg);                 \
 510         } while (0)
 511 #define cpsw_get_slave_ndev(priv, __slave_no__)                         \
 512         (priv->slaves[__slave_no__].ndev)
 513 #define cpsw_get_slave_priv(priv, __slave_no__)                         \
 514         ((priv->slaves[__slave_no__].ndev) ?                            \
 515                 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL)    \
 516
 517 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb)         \
 518         do {                                                            \
 519                 if (!priv->data.dual_emac)                              \
 520                         break;                                          \
 521                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 522                         ndev = cpsw_get_slave_ndev(priv, 0);            \
 523                         priv = netdev_priv(ndev);                       \
 524                         skb->dev = ndev;                                \
 525                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 526                         ndev = cpsw_get_slave_ndev(priv, 1);            \
 527                         priv = netdev_priv(ndev);                       \
 528                         skb->dev = ndev;                                \
 529                 }                                                       \
 530         } while (0)
 531 #define cpsw_add_mcast(priv, addr)                                      \
 532         do {                                                            \
 533                 if (priv->data.dual_emac) {                             \
 534                         struct cpsw_slave *slave = priv->slaves +       \
 535                                                 priv->emac_port;        \
 536                         int slave_port = cpsw_get_slave_port(priv,      \
 537                                                 slave->slave_num);      \
 538                         cpsw_ale_add_mcast(priv->ale, addr,             \
 539                                 1 << slave_port | 1 << priv->host_port, \
 540                                 ALE_VLAN, slave->port_vlan, 0);         \
 541                 } else {                                                \
 542                         cpsw_ale_add_mcast(priv->ale, addr,             \
 543                                 ALE_ALL_PORTS << priv->host_port,       \
 544                                 0, 0, 0);                               \
 545                 }                                                       \
 546         } while (0)
 547
 548 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num)
 549 {
 550         if (priv->host_port == 0)
 551                 return slave_num + 1;
 552         else
 553                 return slave_num;
 554 }
 555
 556 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 557 {
 558         struct cpsw_priv *priv = netdev_priv(ndev);
 559         struct cpsw_ale *ale = priv->ale;
 560         int i;
 561
 562         if (priv->data.dual_emac) {
 563                 bool flag = false;
 564
 565                 /* Enabling promiscuous mode for one interface will be
 566                  * common for both the interface as the interface shares
 567                  * the same hardware resource.
 568                  */
 569                 for (i = 0; i < priv->data.slaves; i++)
 570                         if (priv->slaves[i].ndev->flags & IFF_PROMISC)
 571                                 flag = true;
 572
 573                 if (!enable && flag) {
 574                         enable = true;
 575                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 576                 }
 577
 578                 if (enable) {
 579                         /* Enable Bypass */
 580                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 581
 582                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 583                 } else {
 584                         /* Disable Bypass */
 585                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 586                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 587                 }
 588         } else {
 589                 if (enable) {
 590                         unsigned long timeout = jiffies + HZ;
 591
 592                         /* Disable Learn for all ports */
 593                         for (i = 0; i < priv->data.slaves; i++) {
 594                                 cpsw_ale_control_set(ale, i,
 595                                                      ALE_PORT_NOLEARN, 1);
 596                                 cpsw_ale_control_set(ale, i,
 597                                                      ALE_PORT_NO_SA_UPDATE, 1);
 598                         }
 599
 600                         /* Clear All Untouched entries */
 601                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 602                         do {
 603                                 cpu_relax();
 604                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 605                                         break;
 606                         } while (time_after(timeout, jiffies));
 607                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 608
 609                         /* Clear all mcast from ALE */
 610                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS <<
 611                                                  priv->host_port);
 612
 613                         /* Flood All Unicast Packets to Host port */
 614                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 615                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 616                 } else {
 617                         /* Flood All Unicast Packets to Host port */
 618                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 619
 620                         /* Enable Learn for all ports */
 621                         for (i = 0; i < priv->data.slaves; i++) {
 622                                 cpsw_ale_control_set(ale, i,
 623                                                      ALE_PORT_NOLEARN, 0);
 624                                 cpsw_ale_control_set(ale, i,
 625                                                      ALE_PORT_NO_SA_UPDATE, 0);
 626                         }
 627                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 628                 }
 629         }
 630 }
 631
 632 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 633 {
 634         struct cpsw_priv *priv = netdev_priv(ndev);
 635
 636         if (ndev->flags & IFF_PROMISC) {
 637                 /* Enable promiscuous mode */
 638                 cpsw_set_promiscious(ndev, true);
 639                 return;
 640         } else {
 641                 /* Disable promiscuous mode */
 642                 cpsw_set_promiscious(ndev, false);
 643         }
 644
 645         /* Clear all mcast from ALE */
 646         cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port);
 647
 648         if (!netdev_mc_empty(ndev)) {
 649                 struct netdev_hw_addr *ha;
 650
 651                 /* program multicast address list into ALE register */
 652                 netdev_for_each_mc_addr(ha, ndev) {
 653                         cpsw_add_mcast(priv, (u8 *)ha->addr);
 654                 }
 655         }
 656 }
 657
 658 static void cpsw_intr_enable(struct cpsw_priv *priv)
 659 {
 660         __raw_writel(0xFF, &priv->wr_regs->tx_en);
 661         __raw_writel(0xFF, &priv->wr_regs->rx_en);
 662
 663         cpdma_ctlr_int_ctrl(priv->dma, true);
 664         return;
 665 }
 666
 667 static void cpsw_intr_disable(struct cpsw_priv *priv)
 668 {
 669         __raw_writel(0, &priv->wr_regs->tx_en);
 670         __raw_writel(0, &priv->wr_regs->rx_en);
 671
 672         cpdma_ctlr_int_ctrl(priv->dma, false);
 673         return;
 674 }
 675
 676 static void cpsw_tx_handler(void *token, int len, int status)
 677 {
 678         struct sk_buff          *skb = token;
 679         struct net_device       *ndev = skb->dev;
 680         struct cpsw_priv        *priv = netdev_priv(ndev);
 681
 682         /* Check whether the queue is stopped due to stalled tx dma, if the
 683          * queue is stopped then start the queue as we have free desc for tx
 684          */
 685         if (unlikely(netif_queue_stopped(ndev)))
 686                 netif_wake_queue(ndev);
 687         cpts_tx_timestamp(priv->cpts, skb);
 688         ndev->stats.tx_packets++;
 689         ndev->stats.tx_bytes += len;
 690         dev_kfree_skb_any(skb);
 691 }
 692
 693 static void cpsw_rx_handler(void *token, int len, int status)
 694 {
 695         struct sk_buff          *skb = token;
 696         struct sk_buff          *new_skb;
 697         struct net_device       *ndev = skb->dev;
 698         struct cpsw_priv        *priv = netdev_priv(ndev);
 699         int                     ret = 0;
 700
 701         cpsw_dual_emac_src_port_detect(status, priv, ndev, skb);
 702
 703         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 704                 bool ndev_status = false;
 705                 struct cpsw_slave *slave = priv->slaves;
 706                 int n;
 707
 708                 if (priv->data.dual_emac) {
 709                         /* In dual emac mode check for all interfaces */
 710                         for (n = priv->data.slaves; n; n--, slave++)
 711                                 if (netif_running(slave->ndev))
 712                                         ndev_status = true;
 713                 }
 714
 715                 if (ndev_status && (status >= 0)) {
 716                         /* The packet received is for the interface which
 717                          * is already down and the other interface is up
 718                          * and running, intead of freeing which results
 719                          * in reducing of the number of rx descriptor in
 720                          * DMA engine, requeue skb back to cpdma.
 721                          */
 722                         new_skb = skb;
 723                         goto requeue;
 724                 }
 725
 726                 /* the interface is going down, skbs are purged */
 727                 dev_kfree_skb_any(skb);
 728                 return;
 729         }
 730
 731         new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max);
 732         if (new_skb) {
 733                 skb_put(skb, len);
 734                 cpts_rx_timestamp(priv->cpts, skb);
 735                 skb->protocol = eth_type_trans(skb, ndev);
 736                 netif_receive_skb(skb);
 737                 ndev->stats.rx_bytes += len;
 738                 ndev->stats.rx_packets++;
 739         } else {
 740                 ndev->stats.rx_dropped++;
 741                 new_skb = skb;
 742         }
 743
 744 requeue:
 745         ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data,
 746                         skb_tailroom(new_skb), 0);
 747         if (WARN_ON(ret < 0))
 748                 dev_kfree_skb_any(new_skb);
 749 }
 750
 751 static irqreturn_t cpsw_interrupt(int irq, void *dev_id)
 752 {
 753         struct cpsw_priv *priv = dev_id;
 754
 755         cpsw_intr_disable(priv);
 756         if (priv->irq_enabled == true) {
 757                 cpsw_disable_irq(priv);
 758                 priv->irq_enabled = false;
 759         }
 760
 761         if (netif_running(priv->ndev)) {
 762                 napi_schedule(&priv->napi);
 763                 return IRQ_HANDLED;
 764         }
 765
 766         priv = cpsw_get_slave_priv(priv, 1);
 767         if (!priv)
 768                 return IRQ_NONE;
 769
 770         if (netif_running(priv->ndev)) {
 771                 napi_schedule(&priv->napi);
 772                 return IRQ_HANDLED;
 773         }
 774         return IRQ_NONE;
 775 }
 776
 777 static int cpsw_poll(struct napi_struct *napi, int budget)
 778 {
 779         struct cpsw_priv        *priv = napi_to_priv(napi);
 780         int                     num_tx, num_rx;
 781
 782         num_tx = cpdma_chan_process(priv->txch, 128);
 783         if (num_tx)
 784                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
 785
 786         num_rx = cpdma_chan_process(priv->rxch, budget);
 787         if (num_rx < budget) {
 788                 struct cpsw_priv *prim_cpsw;
 789
 790                 napi_complete(napi);
 791                 cpsw_intr_enable(priv);
 792                 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
 793                 prim_cpsw = cpsw_get_slave_priv(priv, 0);
 794                 if (prim_cpsw->irq_enabled == false) {
 795                         prim_cpsw->irq_enabled = true;
 796                         cpsw_enable_irq(priv);
 797                 }
 798         }
 799
 800         if (num_rx || num_tx)
 801                 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n",
 802                          num_rx, num_tx);
 803
 804         return num_rx;
 805 }
 806
 807 static inline void soft_reset(const char *module, void __iomem *reg)
 808 {
 809         unsigned long timeout = jiffies + HZ;
 810
 811         __raw_writel(1, reg);
 812         do {
 813                 cpu_relax();
 814         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 815
 816         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 817 }
 818
 819 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 820                          ((mac)[2] << 16) | ((mac)[3] << 24))
 821 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 822
 823 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 824                                struct cpsw_priv *priv)
 825 {
 826         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 827         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 828 }
 829
 830 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 831                               struct cpsw_priv *priv, bool *link)
 832 {
 833         struct phy_device       *phy = slave->phy;
 834         u32                     mac_control = 0;
 835         u32                     slave_port;
 836
 837         if (!phy)
 838                 return;
 839
 840         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
 841
 842         if (phy->link) {
 843                 mac_control = priv->data.mac_control;
 844
 845                 /* enable forwarding */
 846                 cpsw_ale_control_set(priv->ale, slave_port,
 847                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 848
 849                 if (phy->speed == 1000)
 850                         mac_control |= BIT(7);  /* GIGABITEN    */
 851                 if (phy->duplex)
 852                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 853
 854                 /* set speed_in input in case RMII mode is used in 100Mbps */
 855                 if (phy->speed == 100)
 856                         mac_control |= BIT(15);
 857                 else if (phy->speed == 10)
 858                         mac_control |= BIT(18); /* In Band mode */
 859
 860                 if (priv->rx_pause)
 861                         mac_control |= BIT(3);
 862
 863                 if (priv->tx_pause)
 864                         mac_control |= BIT(4);
 865
 866                 *link = true;
 867         } else {
 868                 mac_control = 0;
 869                 /* disable forwarding */
 870                 cpsw_ale_control_set(priv->ale, slave_port,
 871                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
 872         }
 873
 874         if (mac_control != slave->mac_control) {
 875                 phy_print_status(phy);
 876                 __raw_writel(mac_control, &slave->sliver->mac_control);
 877         }
 878
 879         slave->mac_control = mac_control;
 880 }
 881
 882 static void cpsw_adjust_link(struct net_device *ndev)
 883 {
 884         struct cpsw_priv        *priv = netdev_priv(ndev);
 885         bool                    link = false;
 886
 887         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
 888
 889         if (link) {
 890                 netif_carrier_on(ndev);
 891                 if (netif_running(ndev))
 892                         netif_wake_queue(ndev);
 893         } else {
 894                 netif_carrier_off(ndev);
 895                 netif_stop_queue(ndev);
 896         }
 897 }
 898
 899 static int cpsw_get_coalesce(struct net_device *ndev,
 900                                 struct ethtool_coalesce *coal)
 901 {
 902         struct cpsw_priv *priv = netdev_priv(ndev);
 903
 904         coal->rx_coalesce_usecs = priv->coal_intvl;
 905         return 0;
 906 }
 907
 908 static int cpsw_set_coalesce(struct net_device *ndev,
 909                                 struct ethtool_coalesce *coal)
 910 {
 911         struct cpsw_priv *priv = netdev_priv(ndev);
 912         u32 int_ctrl;
 913         u32 num_interrupts = 0;
 914         u32 prescale = 0;
 915         u32 addnl_dvdr = 1;
 916         u32 coal_intvl = 0;
 917
 918         coal_intvl = coal->rx_coalesce_usecs;
 919
 920         int_ctrl =  readl(&priv->wr_regs->int_control);
 921         prescale = priv->bus_freq_mhz * 4;
 922
 923         if (!coal->rx_coalesce_usecs) {
 924                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
 925                 goto update_return;
 926         }
 927
 928         if (coal_intvl < CPSW_CMINTMIN_INTVL)
 929                 coal_intvl = CPSW_CMINTMIN_INTVL;
 930
 931         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
 932                 /* Interrupt pacer works with 4us Pulse, we can
 933                  * throttle further by dilating the 4us pulse.
 934                  */
 935                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
 936
 937                 if (addnl_dvdr > 1) {
 938                         prescale *= addnl_dvdr;
 939                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
 940                                 coal_intvl = (CPSW_CMINTMAX_INTVL
 941                                                 * addnl_dvdr);
 942                 } else {
 943                         addnl_dvdr = 1;
 944                         coal_intvl = CPSW_CMINTMAX_INTVL;
 945                 }
 946         }
 947
 948         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
 949         writel(num_interrupts, &priv->wr_regs->rx_imax);
 950         writel(num_interrupts, &priv->wr_regs->tx_imax);
 951
 952         int_ctrl |= CPSW_INTPACEEN;
 953         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
 954         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
 955
 956 update_return:
 957         writel(int_ctrl, &priv->wr_regs->int_control);
 958
 959         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
 960         if (priv->data.dual_emac) {
 961                 int i;
 962
 963                 for (i = 0; i < priv->data.slaves; i++) {
 964                         priv = netdev_priv(priv->slaves[i].ndev);
 965                         priv->coal_intvl = coal_intvl;
 966                 }
 967         } else {
 968                 priv->coal_intvl = coal_intvl;
 969         }
 970
 971         return 0;
 972 }
 973
 974 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
 975 {
 976         switch (sset) {
 977         case ETH_SS_STATS:
 978                 return CPSW_STATS_LEN;
 979         default:
 980                 return -EOPNOTSUPP;
 981         }
 982 }
 983
 984 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
 985 {
 986         u8 *p = data;
 987         int i;
 988
 989         switch (stringset) {
 990         case ETH_SS_STATS:
 991                 for (i = 0; i < CPSW_STATS_LEN; i++) {
 992                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
 993                                ETH_GSTRING_LEN);
 994                         p += ETH_GSTRING_LEN;
 995                 }
 996                 break;
 997         }
 998 }
 999
1000 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1001                                     struct ethtool_stats *stats, u64 *data)
1002 {
1003         struct cpsw_priv *priv = netdev_priv(ndev);
1004         struct cpdma_chan_stats rx_stats;
1005         struct cpdma_chan_stats tx_stats;
1006         u32 val;
1007         u8 *p;
1008         int i;
1009
1010         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1011         cpdma_chan_get_stats(priv->rxch, &rx_stats);
1012         cpdma_chan_get_stats(priv->txch, &tx_stats);
1013
1014         for (i = 0; i < CPSW_STATS_LEN; i++) {
1015                 switch (cpsw_gstrings_stats[i].type) {
1016                 case CPSW_STATS:
1017                         val = readl(priv->hw_stats +
1018                                     cpsw_gstrings_stats[i].stat_offset);
1019                         data[i] = val;
1020                         break;
1021
1022                 case CPDMA_RX_STATS:
1023                         p = (u8 *)&rx_stats +
1024                                 cpsw_gstrings_stats[i].stat_offset;
1025                         data[i] = *(u32 *)p;
1026                         break;
1027
1028                 case CPDMA_TX_STATS:
1029                         p = (u8 *)&tx_stats +
1030                                 cpsw_gstrings_stats[i].stat_offset;
1031                         data[i] = *(u32 *)p;
1032                         break;
1033                 }
1034         }
1035 }
1036
1037 static int cpsw_common_res_usage_state(struct cpsw_priv *priv)
1038 {
1039         u32 i;
1040         u32 usage_count = 0;
1041
1042         if (!priv->data.dual_emac)
1043                 return 0;
1044
1045         for (i = 0; i < priv->data.slaves; i++)
1046                 if (priv->slaves[i].open_stat)
1047                         usage_count++;
1048
1049         return usage_count;
1050 }
1051
1052 static inline int cpsw_tx_packet_submit(struct net_device *ndev,
1053                         struct cpsw_priv *priv, struct sk_buff *skb)
1054 {
1055         if (!priv->data.dual_emac)
1056                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1057                                   skb->len, 0);
1058
1059         if (ndev == cpsw_get_slave_ndev(priv, 0))
1060                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1061                                   skb->len, 1);
1062         else
1063                 return cpdma_chan_submit(priv->txch, skb, skb->data,
1064                                   skb->len, 2);
1065 }
1066
1067 static inline void cpsw_add_dual_emac_def_ale_entries(
1068                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1069                 u32 slave_port)
1070 {
1071         u32 port_mask = 1 << slave_port | 1 << priv->host_port;
1072
1073         if (priv->version == CPSW_VERSION_1)
1074                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1075         else
1076                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1077         cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask,
1078                           port_mask, port_mask, 0);
1079         cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1080                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1081         cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1082                 priv->host_port, ALE_VLAN, slave->port_vlan);
1083 }
1084
1085 static void soft_reset_slave(struct cpsw_slave *slave)
1086 {
1087         char name[32];
1088
1089         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1090         soft_reset(name, &slave->sliver->soft_reset);
1091 }
1092
1093 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1094 {
1095         u32 slave_port;
1096
1097         soft_reset_slave(slave);
1098
1099         /* setup priority mapping */
1100         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1101
1102         switch (priv->version) {
1103         case CPSW_VERSION_1:
1104                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1105                 break;
1106         case CPSW_VERSION_2:
1107         case CPSW_VERSION_3:
1108         case CPSW_VERSION_4:
1109                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1110                 break;
1111         }
1112
1113         /* setup max packet size, and mac address */
1114         __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen);
1115         cpsw_set_slave_mac(slave, priv);
1116
1117         slave->mac_control = 0; /* no link yet */
1118
1119         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1120
1121         if (priv->data.dual_emac)
1122                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1123         else
1124                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1125                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1126
1127         slave->phy = phy_connect(priv->ndev, slave->data->phy_id,
1128                                  &cpsw_adjust_link, slave->data->phy_if);
1129         if (IS_ERR(slave->phy)) {
1130                 dev_err(priv->dev, "phy %s not found on slave %d\n",
1131                         slave->data->phy_id, slave->slave_num);
1132                 slave->phy = NULL;
1133         } else {
1134                 dev_info(priv->dev, "phy found : id is : 0x%x\n",
1135                          slave->phy->phy_id);
1136                 phy_start(slave->phy);
1137
1138                 /* Configure GMII_SEL register */
1139                 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface,
1140                              slave->slave_num);
1141         }
1142 }
1143
1144 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1145 {
1146         const int vlan = priv->data.default_vlan;
1147         const int port = priv->host_port;
1148         u32 reg;
1149         int i;
1150
1151         reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1152                CPSW2_PORT_VLAN;
1153
1154         writel(vlan, &priv->host_port_regs->port_vlan);
1155
1156         for (i = 0; i < priv->data.slaves; i++)
1157                 slave_write(priv->slaves + i, vlan, reg);
1158
1159         cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port,
1160                           ALE_ALL_PORTS << port, ALE_ALL_PORTS << port,
1161                           (ALE_PORT_1 | ALE_PORT_2) << port);
1162 }
1163
1164 static void cpsw_init_host_port(struct cpsw_priv *priv)
1165 {
1166         u32 control_reg;
1167         u32 fifo_mode;
1168
1169         /* soft reset the controller and initialize ale */
1170         soft_reset("cpsw", &priv->regs->soft_reset);
1171         cpsw_ale_start(priv->ale);
1172
1173         /* switch to vlan unaware mode */
1174         cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE,
1175                              CPSW_ALE_VLAN_AWARE);
1176         control_reg = readl(&priv->regs->control);
1177         control_reg |= CPSW_VLAN_AWARE;
1178         writel(control_reg, &priv->regs->control);
1179         fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1180                      CPSW_FIFO_NORMAL_MODE;
1181         writel(fifo_mode, &priv->host_port_regs->tx_in_ctl);
1182
1183         /* setup host port priority mapping */
1184         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1185                      &priv->host_port_regs->cpdma_tx_pri_map);
1186         __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map);
1187
1188         cpsw_ale_control_set(priv->ale, priv->host_port,
1189                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1190
1191         if (!priv->data.dual_emac) {
1192                 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port,
1193                                    0, 0);
1194                 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1195                                    1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2);
1196         }
1197 }
1198
1199 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv)
1200 {
1201         u32 slave_port;
1202
1203         slave_port = cpsw_get_slave_port(priv, slave->slave_num);
1204
1205         if (!slave->phy)
1206                 return;
1207         phy_stop(slave->phy);
1208         phy_disconnect(slave->phy);
1209         slave->phy = NULL;
1210         cpsw_ale_control_set(priv->ale, slave_port,
1211                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1212 }
1213
1214 static int cpsw_ndo_open(struct net_device *ndev)
1215 {
1216         struct cpsw_priv *priv = netdev_priv(ndev);
1217         struct cpsw_priv *prim_cpsw;
1218         int i, ret;
1219         u32 reg;
1220
1221         if (!cpsw_common_res_usage_state(priv))
1222                 cpsw_intr_disable(priv);
1223         netif_carrier_off(ndev);
1224
1225         pm_runtime_get_sync(&priv->pdev->dev);
1226
1227         reg = priv->version;
1228
1229         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1230                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1231                  CPSW_RTL_VERSION(reg));
1232
1233         /* initialize host and slave ports */
1234         if (!cpsw_common_res_usage_state(priv))
1235                 cpsw_init_host_port(priv);
1236         for_each_slave(priv, cpsw_slave_open, priv);
1237
1238         /* Add default VLAN */
1239         if (!priv->data.dual_emac)
1240                 cpsw_add_default_vlan(priv);
1241         else
1242                 cpsw_ale_add_vlan(priv->ale, priv->data.default_vlan,
1243                                   ALE_ALL_PORTS << priv->host_port,
1244                                   ALE_ALL_PORTS << priv->host_port, 0, 0);
1245
1246         if (!cpsw_common_res_usage_state(priv)) {
1247                 /* setup tx dma to fixed prio and zero offset */
1248                 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1);
1249                 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0);
1250
1251                 /* disable priority elevation */
1252                 __raw_writel(0, &priv->regs->ptype);
1253
1254                 /* enable statistics collection only on all ports */
1255                 __raw_writel(0x7, &priv->regs->stat_port_en);
1256
1257                 /* Enable internal fifo flow control */
1258                 writel(0x7, &priv->regs->flow_control);
1259
1260                 if (WARN_ON(!priv->data.rx_descs))
1261                         priv->data.rx_descs = 128;
1262
1263                 for (i = 0; i < priv->data.rx_descs; i++) {
1264                         struct sk_buff *skb;
1265
1266                         ret = -ENOMEM;
1267                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1268                                         priv->rx_packet_max, GFP_KERNEL);
1269                         if (!skb)
1270                                 goto err_cleanup;
1271                         ret = cpdma_chan_submit(priv->rxch, skb, skb->data,
1272                                         skb_tailroom(skb), 0);
1273                         if (ret < 0) {
1274                                 kfree_skb(skb);
1275                                 goto err_cleanup;
1276                         }
1277                 }
1278                 /* continue even if we didn't manage to submit all
1279                  * receive descs
1280                  */
1281                 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i);
1282
1283                 if (cpts_register(&priv->pdev->dev, priv->cpts,
1284                                   priv->data.cpts_clock_mult,
1285                                   priv->data.cpts_clock_shift))
1286                         dev_err(priv->dev, "error registering cpts device\n");
1287
1288         }
1289
1290         /* Enable Interrupt pacing if configured */
1291         if (priv->coal_intvl != 0) {
1292                 struct ethtool_coalesce coal;
1293
1294                 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1295                 cpsw_set_coalesce(ndev, &coal);
1296         }
1297
1298         napi_enable(&priv->napi);
1299         cpdma_ctlr_start(priv->dma);
1300         cpsw_intr_enable(priv);
1301         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1302         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1303
1304         prim_cpsw = cpsw_get_slave_priv(priv, 0);
1305         if (prim_cpsw->irq_enabled == false) {
1306                 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) {
1307                         prim_cpsw->irq_enabled = true;
1308                         cpsw_enable_irq(prim_cpsw);
1309                 }
1310         }
1311
1312         if (priv->data.dual_emac)
1313                 priv->slaves[priv->emac_port].open_stat = true;
1314         return 0;
1315
1316 err_cleanup:
1317         cpdma_ctlr_stop(priv->dma);
1318         for_each_slave(priv, cpsw_slave_stop, priv);
1319         pm_runtime_put_sync(&priv->pdev->dev);
1320         netif_carrier_off(priv->ndev);
1321         return ret;
1322 }
1323
1324 static int cpsw_ndo_stop(struct net_device *ndev)
1325 {
1326         struct cpsw_priv *priv = netdev_priv(ndev);
1327
1328         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1329         netif_stop_queue(priv->ndev);
1330         napi_disable(&priv->napi);
1331         netif_carrier_off(priv->ndev);
1332
1333         if (cpsw_common_res_usage_state(priv) <= 1) {
1334                 cpts_unregister(priv->cpts);
1335                 cpsw_intr_disable(priv);
1336                 cpdma_ctlr_int_ctrl(priv->dma, false);
1337                 cpdma_ctlr_stop(priv->dma);
1338                 cpsw_ale_stop(priv->ale);
1339         }
1340         for_each_slave(priv, cpsw_slave_stop, priv);
1341         pm_runtime_put_sync(&priv->pdev->dev);
1342         if (priv->data.dual_emac)
1343                 priv->slaves[priv->emac_port].open_stat = false;
1344         return 0;
1345 }
1346
1347 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1348                                        struct net_device *ndev)
1349 {
1350         struct cpsw_priv *priv = netdev_priv(ndev);
1351         int ret;
1352
1353         ndev->trans_start = jiffies;
1354
1355         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1356                 cpsw_err(priv, tx_err, "packet pad failed\n");
1357                 ndev->stats.tx_dropped++;
1358                 return NETDEV_TX_OK;
1359         }
1360
1361         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1362                                 priv->cpts->tx_enable)
1363                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1364
1365         skb_tx_timestamp(skb);
1366
1367         ret = cpsw_tx_packet_submit(ndev, priv, skb);
1368         if (unlikely(ret != 0)) {
1369                 cpsw_err(priv, tx_err, "desc submit failed\n");
1370                 goto fail;
1371         }
1372
1373         /* If there is no more tx desc left free then we need to
1374          * tell the kernel to stop sending us tx frames.
1375          */
1376         if (unlikely(!cpdma_check_free_tx_desc(priv->txch)))
1377                 netif_stop_queue(ndev);
1378
1379         return NETDEV_TX_OK;
1380 fail:
1381         ndev->stats.tx_dropped++;
1382         netif_stop_queue(ndev);
1383         return NETDEV_TX_BUSY;
1384 }
1385
1386 #ifdef CONFIG_TI_CPTS
1387
1388 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv)
1389 {
1390         struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave];
1391         u32 ts_en, seq_id;
1392
1393         if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) {
1394                 slave_write(slave, 0, CPSW1_TS_CTL);
1395                 return;
1396         }
1397
1398         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1399         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1400
1401         if (priv->cpts->tx_enable)
1402                 ts_en |= CPSW_V1_TS_TX_EN;
1403
1404         if (priv->cpts->rx_enable)
1405                 ts_en |= CPSW_V1_TS_RX_EN;
1406
1407         slave_write(slave, ts_en, CPSW1_TS_CTL);
1408         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1409 }
1410
1411 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1412 {
1413         struct cpsw_slave *slave;
1414         u32 ctrl, mtype;
1415
1416         if (priv->data.dual_emac)
1417                 slave = &priv->slaves[priv->emac_port];
1418         else
1419                 slave = &priv->slaves[priv->data.active_slave];
1420
1421         ctrl = slave_read(slave, CPSW2_CONTROL);
1422         switch (priv->version) {
1423         case CPSW_VERSION_2:
1424                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1425
1426                 if (priv->cpts->tx_enable)
1427                         ctrl |= CTRL_V2_TX_TS_BITS;
1428
1429                 if (priv->cpts->rx_enable)
1430                         ctrl |= CTRL_V2_RX_TS_BITS;
1431         break;
1432         case CPSW_VERSION_3:
1433         default:
1434                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1435
1436                 if (priv->cpts->tx_enable)
1437                         ctrl |= CTRL_V3_TX_TS_BITS;
1438
1439                 if (priv->cpts->rx_enable)
1440                         ctrl |= CTRL_V3_RX_TS_BITS;
1441         break;
1442         }
1443
1444         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1445
1446         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1447         slave_write(slave, ctrl, CPSW2_CONTROL);
1448         __raw_writel(ETH_P_1588, &priv->regs->ts_ltype);
1449 }
1450
1451 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1452 {
1453         struct cpsw_priv *priv = netdev_priv(dev);
1454         struct cpts *cpts = priv->cpts;
1455         struct hwtstamp_config cfg;
1456
1457         if (priv->version != CPSW_VERSION_1 &&
1458             priv->version != CPSW_VERSION_2 &&
1459             priv->version != CPSW_VERSION_3)
1460                 return -EOPNOTSUPP;
1461
1462         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1463                 return -EFAULT;
1464
1465         /* reserved for future extensions */
1466         if (cfg.flags)
1467                 return -EINVAL;
1468
1469         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1470                 return -ERANGE;
1471
1472         switch (cfg.rx_filter) {
1473         case HWTSTAMP_FILTER_NONE:
1474                 cpts->rx_enable = 0;
1475                 break;
1476         case HWTSTAMP_FILTER_ALL:
1477         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1478         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1479         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1480                 return -ERANGE;
1481         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1482         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1483         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1484         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1485         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1486         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1487         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1488         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1489         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1490                 cpts->rx_enable = 1;
1491                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1492                 break;
1493         default:
1494                 return -ERANGE;
1495         }
1496
1497         cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON;
1498
1499         switch (priv->version) {
1500         case CPSW_VERSION_1:
1501                 cpsw_hwtstamp_v1(priv);
1502                 break;
1503         case CPSW_VERSION_2:
1504         case CPSW_VERSION_3:
1505                 cpsw_hwtstamp_v2(priv);
1506                 break;
1507         default:
1508                 WARN_ON(1);
1509         }
1510
1511         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1512 }
1513
1514 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1515 {
1516         struct cpsw_priv *priv = netdev_priv(dev);
1517         struct cpts *cpts = priv->cpts;
1518         struct hwtstamp_config cfg;
1519
1520         if (priv->version != CPSW_VERSION_1 &&
1521             priv->version != CPSW_VERSION_2 &&
1522             priv->version != CPSW_VERSION_3)
1523                 return -EOPNOTSUPP;
1524
1525         cfg.flags = 0;
1526         cfg.tx_type = cpts->tx_enable ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1527         cfg.rx_filter = (cpts->rx_enable ?
1528                          HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE);
1529
1530         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1531 }
1532
1533 #endif /*CONFIG_TI_CPTS*/
1534
1535 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1536 {
1537         struct cpsw_priv *priv = netdev_priv(dev);
1538         int slave_no = cpsw_slave_index(priv);
1539
1540         if (!netif_running(dev))
1541                 return -EINVAL;
1542
1543         switch (cmd) {
1544 #ifdef CONFIG_TI_CPTS
1545         case SIOCSHWTSTAMP:
1546                 return cpsw_hwtstamp_set(dev, req);
1547         case SIOCGHWTSTAMP:
1548                 return cpsw_hwtstamp_get(dev, req);
1549 #endif
1550         }
1551
1552         if (!priv->slaves[slave_no].phy)
1553                 return -EOPNOTSUPP;
1554         return phy_mii_ioctl(priv->slaves[slave_no].phy, req, cmd);
1555 }
1556
1557 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1558 {
1559         struct cpsw_priv *priv = netdev_priv(ndev);
1560
1561         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1562         ndev->stats.tx_errors++;
1563         cpsw_intr_disable(priv);
1564         cpdma_ctlr_int_ctrl(priv->dma, false);
1565         cpdma_chan_stop(priv->txch);
1566         cpdma_chan_start(priv->txch);
1567         cpdma_ctlr_int_ctrl(priv->dma, true);
1568         cpsw_intr_enable(priv);
1569         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1570         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1571
1572 }
1573
1574 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1575 {
1576         struct cpsw_priv *priv = netdev_priv(ndev);
1577         struct sockaddr *addr = (struct sockaddr *)p;
1578         int flags = 0;
1579         u16 vid = 0;
1580
1581         if (!is_valid_ether_addr(addr->sa_data))
1582                 return -EADDRNOTAVAIL;
1583
1584         if (priv->data.dual_emac) {
1585                 vid = priv->slaves[priv->emac_port].port_vlan;
1586                 flags = ALE_VLAN;
1587         }
1588
1589         cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port,
1590                            flags, vid);
1591         cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port,
1592                            flags, vid);
1593
1594         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1595         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1596         for_each_slave(priv, cpsw_set_slave_mac, priv);
1597
1598         return 0;
1599 }
1600
1601 #ifdef CONFIG_NET_POLL_CONTROLLER
1602 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1603 {
1604         struct cpsw_priv *priv = netdev_priv(ndev);
1605
1606         cpsw_intr_disable(priv);
1607         cpdma_ctlr_int_ctrl(priv->dma, false);
1608         cpsw_interrupt(ndev->irq, priv);
1609         cpdma_ctlr_int_ctrl(priv->dma, true);
1610         cpsw_intr_enable(priv);
1611         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX);
1612         cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX);
1613
1614 }
1615 #endif
1616
1617 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1618                                 unsigned short vid)
1619 {
1620         int ret;
1621
1622         ret = cpsw_ale_add_vlan(priv->ale, vid,
1623                                 ALE_ALL_PORTS << priv->host_port,
1624                                 0, ALE_ALL_PORTS << priv->host_port,
1625                                 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port);
1626         if (ret != 0)
1627                 return ret;
1628
1629         ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr,
1630                                  priv->host_port, ALE_VLAN, vid);
1631         if (ret != 0)
1632                 goto clean_vid;
1633
1634         ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast,
1635                                  ALE_ALL_PORTS << priv->host_port,
1636                                  ALE_VLAN, vid, 0);
1637         if (ret != 0)
1638                 goto clean_vlan_ucast;
1639         return 0;
1640
1641 clean_vlan_ucast:
1642         cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1643                             priv->host_port, ALE_VLAN, vid);
1644 clean_vid:
1645         cpsw_ale_del_vlan(priv->ale, vid, 0);
1646         return ret;
1647 }
1648
1649 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1650                                     __be16 proto, u16 vid)
1651 {
1652         struct cpsw_priv *priv = netdev_priv(ndev);
1653
1654         if (vid == priv->data.default_vlan)
1655                 return 0;
1656
1657         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1658         return cpsw_add_vlan_ale_entry(priv, vid);
1659 }
1660
1661 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1662                                      __be16 proto, u16 vid)
1663 {
1664         struct cpsw_priv *priv = netdev_priv(ndev);
1665         int ret;
1666
1667         if (vid == priv->data.default_vlan)
1668                 return 0;
1669
1670         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
1671         ret = cpsw_ale_del_vlan(priv->ale, vid, 0);
1672         if (ret != 0)
1673                 return ret;
1674
1675         ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr,
1676                                  priv->host_port, ALE_VLAN, vid);
1677         if (ret != 0)
1678                 return ret;
1679
1680         return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast,
1681                                   0, ALE_VLAN, vid);
1682 }
1683
1684 static const struct net_device_ops cpsw_netdev_ops = {
1685         .ndo_open               = cpsw_ndo_open,
1686         .ndo_stop               = cpsw_ndo_stop,
1687         .ndo_start_xmit         = cpsw_ndo_start_xmit,
1688         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
1689         .ndo_do_ioctl           = cpsw_ndo_ioctl,
1690         .ndo_validate_addr      = eth_validate_addr,
1691         .ndo_change_mtu         = eth_change_mtu,
1692         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
1693         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
1694 #ifdef CONFIG_NET_POLL_CONTROLLER
1695         .ndo_poll_controller    = cpsw_ndo_poll_controller,
1696 #endif
1697         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
1698         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
1699 };
1700
1701 static int cpsw_get_regs_len(struct net_device *ndev)
1702 {
1703         struct cpsw_priv *priv = netdev_priv(ndev);
1704
1705         return priv->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
1706 }
1707
1708 static void cpsw_get_regs(struct net_device *ndev,
1709                           struct ethtool_regs *regs, void *p)
1710 {
1711         struct cpsw_priv *priv = netdev_priv(ndev);
1712         u32 *reg = p;
1713
1714         /* update CPSW IP version */
1715         regs->version = priv->version;
1716
1717         cpsw_ale_dump(priv->ale, reg);
1718 }
1719
1720 static void cpsw_get_drvinfo(struct net_device *ndev,
1721                              struct ethtool_drvinfo *info)
1722 {
1723         struct cpsw_priv *priv = netdev_priv(ndev);
1724
1725         strlcpy(info->driver, "cpsw", sizeof(info->driver));
1726         strlcpy(info->version, "1.0", sizeof(info->version));
1727         strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info));
1728         info->regdump_len = cpsw_get_regs_len(ndev);
1729 }
1730
1731 static u32 cpsw_get_msglevel(struct net_device *ndev)
1732 {
1733         struct cpsw_priv *priv = netdev_priv(ndev);
1734         return priv->msg_enable;
1735 }
1736
1737 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
1738 {
1739         struct cpsw_priv *priv = netdev_priv(ndev);
1740         priv->msg_enable = value;
1741 }
1742
1743 static int cpsw_get_ts_info(struct net_device *ndev,
1744                             struct ethtool_ts_info *info)
1745 {
1746 #ifdef CONFIG_TI_CPTS
1747         struct cpsw_priv *priv = netdev_priv(ndev);
1748
1749         info->so_timestamping =
1750                 SOF_TIMESTAMPING_TX_HARDWARE |
1751                 SOF_TIMESTAMPING_TX_SOFTWARE |
1752                 SOF_TIMESTAMPING_RX_HARDWARE |
1753                 SOF_TIMESTAMPING_RX_SOFTWARE |
1754                 SOF_TIMESTAMPING_SOFTWARE |
1755                 SOF_TIMESTAMPING_RAW_HARDWARE;
1756         info->phc_index = priv->cpts->phc_index;
1757         info->tx_types =
1758                 (1 << HWTSTAMP_TX_OFF) |
1759                 (1 << HWTSTAMP_TX_ON);
1760         info->rx_filters =
1761                 (1 << HWTSTAMP_FILTER_NONE) |
1762                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1763 #else
1764         info->so_timestamping =
1765                 SOF_TIMESTAMPING_TX_SOFTWARE |
1766                 SOF_TIMESTAMPING_RX_SOFTWARE |
1767                 SOF_TIMESTAMPING_SOFTWARE;
1768         info->phc_index = -1;
1769         info->tx_types = 0;
1770         info->rx_filters = 0;
1771 #endif
1772         return 0;
1773 }
1774
1775 static int cpsw_get_settings(struct net_device *ndev,
1776                              struct ethtool_cmd *ecmd)
1777 {
1778         struct cpsw_priv *priv = netdev_priv(ndev);
1779         int slave_no = cpsw_slave_index(priv);
1780
1781         if (priv->slaves[slave_no].phy)
1782                 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd);
1783         else
1784                 return -EOPNOTSUPP;
1785 }
1786
1787 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1788 {
1789         struct cpsw_priv *priv = netdev_priv(ndev);
1790         int slave_no = cpsw_slave_index(priv);
1791
1792         if (priv->slaves[slave_no].phy)
1793                 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd);
1794         else
1795                 return -EOPNOTSUPP;
1796 }
1797
1798 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1799 {
1800         struct cpsw_priv *priv = netdev_priv(ndev);
1801         int slave_no = cpsw_slave_index(priv);
1802
1803         wol->supported = 0;
1804         wol->wolopts = 0;
1805
1806         if (priv->slaves[slave_no].phy)
1807                 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol);
1808 }
1809
1810 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1811 {
1812         struct cpsw_priv *priv = netdev_priv(ndev);
1813         int slave_no = cpsw_slave_index(priv);
1814
1815         if (priv->slaves[slave_no].phy)
1816                 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol);
1817         else
1818                 return -EOPNOTSUPP;
1819 }
1820
1821 static void cpsw_get_pauseparam(struct net_device *ndev,
1822                                 struct ethtool_pauseparam *pause)
1823 {
1824         struct cpsw_priv *priv = netdev_priv(ndev);
1825
1826         pause->autoneg = AUTONEG_DISABLE;
1827         pause->rx_pause = priv->rx_pause ? true : false;
1828         pause->tx_pause = priv->tx_pause ? true : false;
1829 }
1830
1831 static int cpsw_set_pauseparam(struct net_device *ndev,
1832                                struct ethtool_pauseparam *pause)
1833 {
1834         struct cpsw_priv *priv = netdev_priv(ndev);
1835         bool link;
1836
1837         priv->rx_pause = pause->rx_pause ? true : false;
1838         priv->tx_pause = pause->tx_pause ? true : false;
1839
1840         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1841
1842         return 0;
1843 }
1844
1845 static const struct ethtool_ops cpsw_ethtool_ops = {
1846         .get_drvinfo    = cpsw_get_drvinfo,
1847         .get_msglevel   = cpsw_get_msglevel,
1848         .set_msglevel   = cpsw_set_msglevel,
1849         .get_link       = ethtool_op_get_link,
1850         .get_ts_info    = cpsw_get_ts_info,
1851         .get_settings   = cpsw_get_settings,
1852         .set_settings   = cpsw_set_settings,
1853         .get_coalesce   = cpsw_get_coalesce,
1854         .set_coalesce   = cpsw_set_coalesce,
1855         .get_sset_count         = cpsw_get_sset_count,
1856         .get_strings            = cpsw_get_strings,
1857         .get_ethtool_stats      = cpsw_get_ethtool_stats,
1858         .get_pauseparam         = cpsw_get_pauseparam,
1859         .set_pauseparam         = cpsw_set_pauseparam,
1860         .get_wol        = cpsw_get_wol,
1861         .set_wol        = cpsw_set_wol,
1862         .get_regs_len   = cpsw_get_regs_len,
1863         .get_regs       = cpsw_get_regs,
1864 };
1865
1866 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv,
1867                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
1868 {
1869         void __iomem            *regs = priv->regs;
1870         int                     slave_num = slave->slave_num;
1871         struct cpsw_slave_data  *data = priv->data.slave_data + slave_num;
1872
1873         slave->data     = data;
1874         slave->regs     = regs + slave_reg_ofs;
1875         slave->sliver   = regs + sliver_reg_ofs;
1876         slave->port_vlan = data->dual_emac_res_vlan;
1877 }
1878
1879 static int cpsw_probe_dt(struct cpsw_platform_data *data,
1880                          struct platform_device *pdev)
1881 {
1882         struct device_node *node = pdev->dev.of_node;
1883         struct device_node *slave_node;
1884         int i = 0, ret;
1885         u32 prop;
1886
1887         if (!node)
1888                 return -EINVAL;
1889
1890         if (of_property_read_u32(node, "slaves", &prop)) {
1891                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
1892                 return -EINVAL;
1893         }
1894         data->slaves = prop;
1895
1896         if (of_property_read_u32(node, "active_slave", &prop)) {
1897                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
1898                 return -EINVAL;
1899         }
1900         data->active_slave = prop;
1901
1902         if (of_property_read_u32(node, "cpts_clock_mult", &prop)) {
1903                 dev_err(&pdev->dev, "Missing cpts_clock_mult property in the DT.\n");
1904                 return -EINVAL;
1905         }
1906         data->cpts_clock_mult = prop;
1907
1908         if (of_property_read_u32(node, "cpts_clock_shift", &prop)) {
1909                 dev_err(&pdev->dev, "Missing cpts_clock_shift property in the DT.\n");
1910                 return -EINVAL;
1911         }
1912         data->cpts_clock_shift = prop;
1913
1914         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
1915                                         * sizeof(struct cpsw_slave_data),
1916                                         GFP_KERNEL);
1917         if (!data->slave_data)
1918                 return -ENOMEM;
1919
1920         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
1921                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
1922                 return -EINVAL;
1923         }
1924         data->channels = prop;
1925
1926         if (of_property_read_u32(node, "ale_entries", &prop)) {
1927                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
1928                 return -EINVAL;
1929         }
1930         data->ale_entries = prop;
1931
1932         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
1933                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
1934                 return -EINVAL;
1935         }
1936         data->bd_ram_size = prop;
1937
1938         if (of_property_read_u32(node, "rx_descs", &prop)) {
1939                 dev_err(&pdev->dev, "Missing rx_descs property in the DT.\n");
1940                 return -EINVAL;
1941         }
1942         data->rx_descs = prop;
1943
1944         if (of_property_read_u32(node, "mac_control", &prop)) {
1945                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
1946                 return -EINVAL;
1947         }
1948         data->mac_control = prop;
1949
1950         if (of_property_read_bool(node, "dual_emac"))
1951                 data->dual_emac = 1;
1952
1953         /*
1954          * Populate all the child nodes here...
1955          */
1956         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
1957         /* We do not want to force this, as in some cases may not have child */
1958         if (ret)
1959                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
1960
1961         for_each_child_of_node(node, slave_node) {
1962                 struct cpsw_slave_data *slave_data = data->slave_data + i;
1963                 const void *mac_addr = NULL;
1964                 u32 phyid;
1965                 int lenp;
1966                 const __be32 *parp;
1967                 struct device_node *mdio_node;
1968                 struct platform_device *mdio;
1969
1970                 /* This is no slave child node, continue */
1971                 if (strcmp(slave_node->name, "slave"))
1972                         continue;
1973
1974                 parp = of_get_property(slave_node, "phy_id", &lenp);
1975                 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) {
1976                         dev_err(&pdev->dev, "Missing slave[%d] phy_id property\n", i);
1977                         return -EINVAL;
1978                 }
1979                 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
1980                 phyid = be32_to_cpup(parp+1);
1981                 mdio = of_find_device_by_node(mdio_node);
1982                 of_node_put(mdio_node);
1983                 if (!mdio) {
1984                         pr_err("Missing mdio platform device\n");
1985                         return -EINVAL;
1986                 }
1987                 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
1988                          PHY_ID_FMT, mdio->name, phyid);
1989
1990                 mac_addr = of_get_mac_address(slave_node);
1991                 if (mac_addr)
1992                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
1993
1994                 slave_data->phy_if = of_get_phy_mode(slave_node);
1995                 if (slave_data->phy_if < 0) {
1996                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
1997                                 i);
1998                         return slave_data->phy_if;
1999                 }
2000
2001                 if (data->dual_emac) {
2002                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2003                                                  &prop)) {
2004                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2005                                 slave_data->dual_emac_res_vlan = i+1;
2006                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2007                                         slave_data->dual_emac_res_vlan, i);
2008                         } else {
2009                                 slave_data->dual_emac_res_vlan = prop;
2010                         }
2011                 }
2012
2013                 i++;
2014                 if (i == data->slaves)
2015                         break;
2016         }
2017
2018         return 0;
2019 }
2020
2021 static int cpsw_probe_dual_emac(struct platform_device *pdev,
2022                                 struct cpsw_priv *priv)
2023 {
2024         struct cpsw_platform_data       *data = &priv->data;
2025         struct net_device               *ndev;
2026         struct cpsw_priv                *priv_sl2;
2027         int ret = 0, i;
2028
2029         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2030         if (!ndev) {
2031                 dev_err(&pdev->dev, "cpsw: error allocating net_device\n");
2032                 return -ENOMEM;
2033         }
2034
2035         priv_sl2 = netdev_priv(ndev);
2036         spin_lock_init(&priv_sl2->lock);
2037         priv_sl2->data = *data;
2038         priv_sl2->pdev = pdev;
2039         priv_sl2->ndev = ndev;
2040         priv_sl2->dev  = &ndev->dev;
2041         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2042         priv_sl2->rx_packet_max = max(rx_packet_max, 128);
2043
2044         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2045                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2046                         ETH_ALEN);
2047                 dev_info(&pdev->dev, "cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr);
2048         } else {
2049                 random_ether_addr(priv_sl2->mac_addr);
2050                 dev_info(&pdev->dev, "cpsw: Random MACID = %pM\n", priv_sl2->mac_addr);
2051         }
2052         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2053
2054         priv_sl2->slaves = priv->slaves;
2055         priv_sl2->clk = priv->clk;
2056
2057         priv_sl2->coal_intvl = 0;
2058         priv_sl2->bus_freq_mhz = priv->bus_freq_mhz;
2059
2060         priv_sl2->regs = priv->regs;
2061         priv_sl2->host_port = priv->host_port;
2062         priv_sl2->host_port_regs = priv->host_port_regs;
2063         priv_sl2->wr_regs = priv->wr_regs;
2064         priv_sl2->hw_stats = priv->hw_stats;
2065         priv_sl2->dma = priv->dma;
2066         priv_sl2->txch = priv->txch;
2067         priv_sl2->rxch = priv->rxch;
2068         priv_sl2->ale = priv->ale;
2069         priv_sl2->emac_port = 1;
2070         priv->slaves[1].ndev = ndev;
2071         priv_sl2->cpts = priv->cpts;
2072         priv_sl2->version = priv->version;
2073
2074         for (i = 0; i < priv->num_irqs; i++) {
2075                 priv_sl2->irqs_table[i] = priv->irqs_table[i];
2076                 priv_sl2->num_irqs = priv->num_irqs;
2077         }
2078         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2079
2080         ndev->netdev_ops = &cpsw_netdev_ops;
2081         ndev->ethtool_ops = &cpsw_ethtool_ops;
2082         netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2083
2084         /* register the network device */
2085         SET_NETDEV_DEV(ndev, &pdev->dev);
2086         ret = register_netdev(ndev);
2087         if (ret) {
2088                 dev_err(&pdev->dev, "cpsw: error registering net device\n");
2089                 free_netdev(ndev);
2090                 ret = -ENODEV;
2091         }
2092
2093         return ret;
2094 }
2095
2096 static int cpsw_probe(struct platform_device *pdev)
2097 {
2098         struct cpsw_platform_data       *data;
2099         struct net_device               *ndev;
2100         struct cpsw_priv                *priv;
2101         struct cpdma_params             dma_params;
2102         struct cpsw_ale_params          ale_params;
2103         void __iomem                    *ss_regs;
2104         struct resource                 *res, *ss_res;
2105         u32 slave_offset, sliver_offset, slave_size;
2106         int ret = 0, i, k = 0;
2107
2108         ndev = alloc_etherdev(sizeof(struct cpsw_priv));
2109         if (!ndev) {
2110                 dev_err(&pdev->dev, "error allocating net_device\n");
2111                 return -ENOMEM;
2112         }
2113
2114         platform_set_drvdata(pdev, ndev);
2115         priv = netdev_priv(ndev);
2116         spin_lock_init(&priv->lock);
2117         priv->pdev = pdev;
2118         priv->ndev = ndev;
2119         priv->dev  = &ndev->dev;
2120         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2121         priv->rx_packet_max = max(rx_packet_max, 128);
2122         priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL);
2123         priv->irq_enabled = true;
2124         if (!priv->cpts) {
2125                 dev_err(&pdev->dev, "error allocating cpts\n");
2126                 goto clean_ndev_ret;
2127         }
2128
2129         /*
2130          * This may be required here for child devices.
2131          */
2132         pm_runtime_enable(&pdev->dev);
2133
2134         /* Select default pin state */
2135         pinctrl_pm_select_default_state(&pdev->dev);
2136
2137         if (cpsw_probe_dt(&priv->data, pdev)) {
2138                 dev_err(&pdev->dev, "cpsw: platform data missing\n");
2139                 ret = -ENODEV;
2140                 goto clean_runtime_disable_ret;
2141         }
2142         data = &priv->data;
2143
2144         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2145                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2146                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2147         } else {
2148                 eth_random_addr(priv->mac_addr);
2149                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2150         }
2151
2152         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2153
2154         priv->slaves = devm_kzalloc(&pdev->dev,
2155                                     sizeof(struct cpsw_slave) * data->slaves,
2156                                     GFP_KERNEL);
2157         if (!priv->slaves) {
2158                 ret = -ENOMEM;
2159                 goto clean_runtime_disable_ret;
2160         }
2161         for (i = 0; i < data->slaves; i++)
2162                 priv->slaves[i].slave_num = i;
2163
2164         priv->slaves[0].ndev = ndev;
2165         priv->emac_port = 0;
2166
2167         priv->clk = devm_clk_get(&pdev->dev, "fck");
2168         if (IS_ERR(priv->clk)) {
2169                 dev_err(priv->dev, "fck is not found\n");
2170                 ret = -ENODEV;
2171                 goto clean_runtime_disable_ret;
2172         }
2173         priv->coal_intvl = 0;
2174         priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000;
2175
2176         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2177         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2178         if (IS_ERR(ss_regs)) {
2179                 ret = PTR_ERR(ss_regs);
2180                 goto clean_runtime_disable_ret;
2181         }
2182         priv->regs = ss_regs;
2183         priv->host_port = HOST_PORT_NUM;
2184
2185         /* Need to enable clocks with runtime PM api to access module
2186          * registers
2187          */
2188         pm_runtime_get_sync(&pdev->dev);
2189         priv->version = readl(&priv->regs->id_ver);
2190         pm_runtime_put_sync(&pdev->dev);
2191
2192         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2193         priv->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2194         if (IS_ERR(priv->wr_regs)) {
2195                 ret = PTR_ERR(priv->wr_regs);
2196                 goto clean_runtime_disable_ret;
2197         }
2198
2199         memset(&dma_params, 0, sizeof(dma_params));
2200         memset(&ale_params, 0, sizeof(ale_params));
2201
2202         switch (priv->version) {
2203         case CPSW_VERSION_1:
2204                 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2205                 priv->cpts->reg      = ss_regs + CPSW1_CPTS_OFFSET;
2206                 priv->hw_stats       = ss_regs + CPSW1_HW_STATS;
2207                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2208                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2209                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2210                 slave_offset         = CPSW1_SLAVE_OFFSET;
2211                 slave_size           = CPSW1_SLAVE_SIZE;
2212                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2213                 dma_params.desc_mem_phys = 0;
2214                 break;
2215         case CPSW_VERSION_2:
2216         case CPSW_VERSION_3:
2217         case CPSW_VERSION_4:
2218                 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
2219                 priv->cpts->reg      = ss_regs + CPSW2_CPTS_OFFSET;
2220                 priv->hw_stats       = ss_regs + CPSW2_HW_STATS;
2221                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
2222                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
2223                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
2224                 slave_offset         = CPSW2_SLAVE_OFFSET;
2225                 slave_size           = CPSW2_SLAVE_SIZE;
2226                 sliver_offset        = CPSW2_SLIVER_OFFSET;
2227                 dma_params.desc_mem_phys =
2228                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
2229                 break;
2230         default:
2231                 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version);
2232                 ret = -ENODEV;
2233                 goto clean_runtime_disable_ret;
2234         }
2235         for (i = 0; i < priv->data.slaves; i++) {
2236                 struct cpsw_slave *slave = &priv->slaves[i];
2237                 cpsw_slave_init(slave, priv, slave_offset, sliver_offset);
2238                 slave_offset  += slave_size;
2239                 sliver_offset += SLIVER_SIZE;
2240         }
2241
2242         dma_params.dev          = &pdev->dev;
2243         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
2244         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
2245         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
2246         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
2247         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
2248
2249         dma_params.num_chan             = data->channels;
2250         dma_params.has_soft_reset       = true;
2251         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
2252         dma_params.desc_mem_size        = data->bd_ram_size;
2253         dma_params.desc_align           = 16;
2254         dma_params.has_ext_regs         = true;
2255         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
2256
2257         priv->dma = cpdma_ctlr_create(&dma_params);
2258         if (!priv->dma) {
2259                 dev_err(priv->dev, "error initializing dma\n");
2260                 ret = -ENOMEM;
2261                 goto clean_runtime_disable_ret;
2262         }
2263
2264         priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0),
2265                                        cpsw_tx_handler);
2266         priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0),
2267                                        cpsw_rx_handler);
2268
2269         if (WARN_ON(!priv->txch || !priv->rxch)) {
2270                 dev_err(priv->dev, "error initializing dma channels\n");
2271                 ret = -ENOMEM;
2272                 goto clean_dma_ret;
2273         }
2274
2275         ale_params.dev                  = &ndev->dev;
2276         ale_params.ale_ageout           = ale_ageout;
2277         ale_params.ale_entries          = data->ale_entries;
2278         ale_params.ale_ports            = data->slaves;
2279
2280         priv->ale = cpsw_ale_create(&ale_params);
2281         if (!priv->ale) {
2282                 dev_err(priv->dev, "error initializing ale engine\n");
2283                 ret = -ENODEV;
2284                 goto clean_dma_ret;
2285         }
2286
2287         ndev->irq = platform_get_irq(pdev, 0);
2288         if (ndev->irq < 0) {
2289                 dev_err(priv->dev, "error getting irq resource\n");
2290                 ret = -ENOENT;
2291                 goto clean_ale_ret;
2292         }
2293
2294         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
2295                 if (k >= ARRAY_SIZE(priv->irqs_table)) {
2296                         ret = -EINVAL;
2297                         goto clean_ale_ret;
2298                 }
2299
2300                 ret = devm_request_irq(&pdev->dev, res->start, cpsw_interrupt,
2301                                        0, dev_name(&pdev->dev), priv);
2302                 if (ret < 0) {
2303                         dev_err(priv->dev, "error attaching irq (%d)\n", ret);
2304                         goto clean_ale_ret;
2305                 }
2306
2307                 priv->irqs_table[k] = res->start;
2308                 k++;
2309         }
2310
2311         priv->num_irqs = k;
2312
2313         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2314
2315         ndev->netdev_ops = &cpsw_netdev_ops;
2316         ndev->ethtool_ops = &cpsw_ethtool_ops;
2317         netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT);
2318
2319         /* register the network device */
2320         SET_NETDEV_DEV(ndev, &pdev->dev);
2321         ret = register_netdev(ndev);
2322         if (ret) {
2323                 dev_err(priv->dev, "error registering net device\n");
2324                 ret = -ENODEV;
2325                 goto clean_ale_ret;
2326         }
2327
2328         cpsw_notice(priv, probe, "initialized device (regs %pa, irq %d)\n",
2329                     &ss_res->start, ndev->irq);
2330
2331         if (priv->data.dual_emac) {
2332                 ret = cpsw_probe_dual_emac(pdev, priv);
2333                 if (ret) {
2334                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
2335                         goto clean_ale_ret;
2336                 }
2337         }
2338
2339         return 0;
2340
2341 clean_ale_ret:
2342         cpsw_ale_destroy(priv->ale);
2343 clean_dma_ret:
2344         cpdma_chan_destroy(priv->txch);
2345         cpdma_chan_destroy(priv->rxch);
2346         cpdma_ctlr_destroy(priv->dma);
2347 clean_runtime_disable_ret:
2348         pm_runtime_disable(&pdev->dev);
2349 clean_ndev_ret:
2350         free_netdev(priv->ndev);
2351         return ret;
2352 }
2353
2354 static int cpsw_remove(struct platform_device *pdev)
2355 {
2356         struct net_device *ndev = platform_get_drvdata(pdev);
2357         struct cpsw_priv *priv = netdev_priv(ndev);
2358
2359         if (priv->data.dual_emac)
2360                 unregister_netdev(cpsw_get_slave_ndev(priv, 1));
2361         unregister_netdev(ndev);
2362
2363         cpsw_ale_destroy(priv->ale);
2364         cpdma_chan_destroy(priv->txch);
2365         cpdma_chan_destroy(priv->rxch);
2366         cpdma_ctlr_destroy(priv->dma);
2367         pm_runtime_disable(&pdev->dev);
2368         if (priv->data.dual_emac)
2369                 free_netdev(cpsw_get_slave_ndev(priv, 1));
2370         free_netdev(ndev);
2371         return 0;
2372 }
2373
2374 static int cpsw_suspend(struct device *dev)
2375 {
2376         struct platform_device  *pdev = to_platform_device(dev);
2377         struct net_device       *ndev = platform_get_drvdata(pdev);
2378         struct cpsw_priv        *priv = netdev_priv(ndev);
2379
2380         if (priv->data.dual_emac) {
2381                 int i;
2382
2383                 for (i = 0; i < priv->data.slaves; i++) {
2384                         if (netif_running(priv->slaves[i].ndev))
2385                                 cpsw_ndo_stop(priv->slaves[i].ndev);
2386                         soft_reset_slave(priv->slaves + i);
2387                 }
2388         } else {
2389                 if (netif_running(ndev))
2390                         cpsw_ndo_stop(ndev);
2391                 for_each_slave(priv, soft_reset_slave);
2392         }
2393
2394         pm_runtime_put_sync(&pdev->dev);
2395
2396         /* Select sleep pin state */
2397         pinctrl_pm_select_sleep_state(&pdev->dev);
2398
2399         return 0;
2400 }
2401
2402 static int cpsw_resume(struct device *dev)
2403 {
2404         struct platform_device  *pdev = to_platform_device(dev);
2405         struct net_device       *ndev = platform_get_drvdata(pdev);
2406         struct cpsw_priv        *priv = netdev_priv(ndev);
2407
2408         pm_runtime_get_sync(&pdev->dev);
2409
2410         /* Select default pin state */
2411         pinctrl_pm_select_default_state(&pdev->dev);
2412
2413         if (priv->data.dual_emac) {
2414                 int i;
2415
2416                 for (i = 0; i < priv->data.slaves; i++) {
2417                         if (netif_running(priv->slaves[i].ndev))
2418                                 cpsw_ndo_open(priv->slaves[i].ndev);
2419                 }
2420         } else {
2421                 if (netif_running(ndev))
2422                         cpsw_ndo_open(ndev);
2423         }
2424         return 0;
2425 }
2426
2427 static const struct dev_pm_ops cpsw_pm_ops = {
2428         .suspend        = cpsw_suspend,
2429         .resume         = cpsw_resume,
2430 };
2431
2432 static const struct of_device_id cpsw_of_mtable[] = {
2433         { .compatible = "ti,cpsw", },
2434         { /* sentinel */ },
2435 };
2436 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2437
2438 static struct platform_driver cpsw_driver = {
2439         .driver = {
2440                 .name    = "cpsw",
2441                 .pm      = &cpsw_pm_ops,
2442                 .of_match_table = cpsw_of_mtable,
2443         },
2444         .probe = cpsw_probe,
2445         .remove = cpsw_remove,
2446 };
2447
2448 static int __init cpsw_init(void)
2449 {
2450         return platform_driver_register(&cpsw_driver);
2451 }
2452 late_initcall(cpsw_init);
2453
2454 static void __exit cpsw_exit(void)
2455 {
2456         platform_driver_unregister(&cpsw_driver);
2457 }
2458 module_exit(cpsw_exit);
2459
2460 MODULE_LICENSE("GPL");
2461 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
2462 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
2463 MODULE_DESCRIPTION("TI CPSW Ethernet driver");