1 /*******************************************************************************
2 STMMAC Ethernet Driver -- MDIO bus implementation
3 Provides Bus interface for MII registers
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 The full GNU General Public License is included in this distribution in
17 the file called "COPYING".
19 Author: Carl Shaw <carl.shaw@st.com>
20 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21 *******************************************************************************/
24 #include <linux/iopoll.h>
25 #include <linux/mii.h>
27 #include <linux/of_gpio.h>
28 #include <linux/of_mdio.h>
29 #include <linux/phy.h>
30 #include <linux/slab.h>
35 #define MII_BUSY 0x00000001
36 #define MII_WRITE 0x00000002
39 #define MII_GMAC4_GOC_SHIFT 2
40 #define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT)
41 #define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT)
44 #define MII_XGMAC_SADDR BIT(18)
45 #define MII_XGMAC_CMD_SHIFT 16
46 #define MII_XGMAC_WRITE (1 << MII_XGMAC_CMD_SHIFT)
47 #define MII_XGMAC_READ (3 << MII_XGMAC_CMD_SHIFT)
48 #define MII_XGMAC_BUSY BIT(22)
49 #define MII_XGMAC_MAX_C22ADDR 3
50 #define MII_XGMAC_C22P_MASK GENMASK(MII_XGMAC_MAX_C22ADDR, 0)
52 static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr,
53 int phyreg, u32 *hw_addr)
55 unsigned int mii_data = priv->hw->mii.data;
58 /* HW does not support C22 addr >= 4 */
59 if (phyaddr > MII_XGMAC_MAX_C22ADDR)
61 /* Wait until any existing MII operation is complete */
62 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
63 !(tmp & MII_XGMAC_BUSY), 100, 10000))
66 /* Set port as Clause 22 */
67 tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P);
68 tmp &= ~MII_XGMAC_C22P_MASK;
70 writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P);
72 *hw_addr = (phyaddr << 16) | (phyreg & 0x1f);
76 static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
78 struct net_device *ndev = bus->priv;
79 struct stmmac_priv *priv = netdev_priv(ndev);
80 unsigned int mii_address = priv->hw->mii.addr;
81 unsigned int mii_data = priv->hw->mii.data;
82 u32 tmp, addr, value = MII_XGMAC_BUSY;
85 if (phyreg & MII_ADDR_C45) {
88 ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
93 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
94 & priv->hw->mii.clk_csr_mask;
95 value |= MII_XGMAC_SADDR | MII_XGMAC_READ;
97 /* Wait until any existing MII operation is complete */
98 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
99 !(tmp & MII_XGMAC_BUSY), 100, 10000))
102 /* Set the MII address register to read */
103 writel(addr, priv->ioaddr + mii_address);
104 writel(value, priv->ioaddr + mii_data);
106 /* Wait until any existing MII operation is complete */
107 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
108 !(tmp & MII_XGMAC_BUSY), 100, 10000))
111 /* Read the data from the MII data register */
112 return readl(priv->ioaddr + mii_data) & GENMASK(15, 0);
115 static int stmmac_xgmac2_mdio_write(struct mii_bus *bus, int phyaddr,
116 int phyreg, u16 phydata)
118 struct net_device *ndev = bus->priv;
119 struct stmmac_priv *priv = netdev_priv(ndev);
120 unsigned int mii_address = priv->hw->mii.addr;
121 unsigned int mii_data = priv->hw->mii.data;
122 u32 addr, tmp, value = MII_XGMAC_BUSY;
125 if (phyreg & MII_ADDR_C45) {
128 ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr);
133 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
134 & priv->hw->mii.clk_csr_mask;
135 value |= phydata | MII_XGMAC_SADDR;
136 value |= MII_XGMAC_WRITE;
138 /* Wait until any existing MII operation is complete */
139 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
140 !(tmp & MII_XGMAC_BUSY), 100, 10000))
143 /* Set the MII address register to write */
144 writel(addr, priv->ioaddr + mii_address);
145 writel(value, priv->ioaddr + mii_data);
147 /* Wait until any existing MII operation is complete */
148 return readl_poll_timeout(priv->ioaddr + mii_data, tmp,
149 !(tmp & MII_XGMAC_BUSY), 100, 10000);
154 * @bus: points to the mii_bus structure
157 * Description: it reads data from the MII register from within the phy device.
158 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
159 * accessing the PHY registers.
160 * Fortunately, it seems this has no drawback for the 7109 MAC.
162 static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
164 struct net_device *ndev = bus->priv;
165 struct stmmac_priv *priv = netdev_priv(ndev);
166 unsigned int mii_address = priv->hw->mii.addr;
167 unsigned int mii_data = priv->hw->mii.data;
170 u32 value = MII_BUSY;
172 value |= (phyaddr << priv->hw->mii.addr_shift)
173 & priv->hw->mii.addr_mask;
174 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
175 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
176 & priv->hw->mii.clk_csr_mask;
177 if (priv->plat->has_gmac4)
178 value |= MII_GMAC4_READ;
180 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
184 writel(value, priv->ioaddr + mii_address);
186 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
190 /* Read the data from the MII data register */
191 data = (int)readl(priv->ioaddr + mii_data);
198 * @bus: points to the mii_bus structure
202 * Description: it writes the data into the MII register from within the device.
204 static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
207 struct net_device *ndev = bus->priv;
208 struct stmmac_priv *priv = netdev_priv(ndev);
209 unsigned int mii_address = priv->hw->mii.addr;
210 unsigned int mii_data = priv->hw->mii.data;
212 u32 value = MII_BUSY;
214 value |= (phyaddr << priv->hw->mii.addr_shift)
215 & priv->hw->mii.addr_mask;
216 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
218 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
219 & priv->hw->mii.clk_csr_mask;
220 if (priv->plat->has_gmac4)
221 value |= MII_GMAC4_WRITE;
225 /* Wait until any existing MII operation is complete */
226 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
230 /* Set the MII address register to write */
231 writel(phydata, priv->ioaddr + mii_data);
232 writel(value, priv->ioaddr + mii_address);
234 /* Wait until any existing MII operation is complete */
235 return readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
241 * @bus: points to the mii_bus structure
242 * Description: reset the MII bus
244 int stmmac_mdio_reset(struct mii_bus *bus)
246 #if IS_ENABLED(CONFIG_STMMAC_PLATFORM)
247 struct net_device *ndev = bus->priv;
248 struct stmmac_priv *priv = netdev_priv(ndev);
249 unsigned int mii_address = priv->hw->mii.addr;
250 struct stmmac_mdio_bus_data *data = priv->plat->mdio_bus_data;
253 if (priv->device->of_node) {
254 if (data->reset_gpio < 0) {
255 struct device_node *np = priv->device->of_node;
260 data->reset_gpio = of_get_named_gpio(np,
261 "snps,reset-gpio", 0);
262 if (data->reset_gpio < 0)
265 data->active_low = of_property_read_bool(np,
266 "snps,reset-active-low");
267 of_property_read_u32_array(np,
268 "snps,reset-delays-us", data->delays, 3);
270 if (devm_gpio_request(priv->device, data->reset_gpio,
275 gpio_direction_output(data->reset_gpio,
276 data->active_low ? 1 : 0);
278 msleep(DIV_ROUND_UP(data->delays[0], 1000));
280 gpio_set_value(data->reset_gpio, data->active_low ? 0 : 1);
282 msleep(DIV_ROUND_UP(data->delays[1], 1000));
284 gpio_set_value(data->reset_gpio, data->active_low ? 1 : 0);
286 msleep(DIV_ROUND_UP(data->delays[2], 1000));
290 if (data->phy_reset) {
291 netdev_dbg(ndev, "stmmac_mdio_reset: calling phy_reset\n");
292 data->phy_reset(priv->plat->bsp_priv);
295 /* This is a workaround for problems with the STE101P PHY.
296 * It doesn't complete its reset until at least one clock cycle
297 * on MDC, so perform a dummy mdio read. To be updated for GMAC4
300 if (!priv->plat->has_gmac4)
301 writel(0, priv->ioaddr + mii_address);
307 * stmmac_mdio_register
308 * @ndev: net device structure
309 * Description: it registers the MII bus
311 int stmmac_mdio_register(struct net_device *ndev)
314 struct mii_bus *new_bus;
315 struct stmmac_priv *priv = netdev_priv(ndev);
316 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
317 struct device_node *mdio_node = priv->plat->mdio_node;
318 struct device *dev = ndev->dev.parent;
319 int addr, found, max_addr;
324 new_bus = mdiobus_alloc();
328 if (mdio_bus_data->irqs)
329 memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq));
332 if (priv->device->of_node)
333 mdio_bus_data->reset_gpio = -1;
336 new_bus->name = "stmmac";
338 if (priv->plat->has_xgmac) {
339 new_bus->read = &stmmac_xgmac2_mdio_read;
340 new_bus->write = &stmmac_xgmac2_mdio_write;
342 /* Right now only C22 phys are supported */
343 max_addr = MII_XGMAC_MAX_C22ADDR + 1;
345 /* Check if DT specified an unsupported phy addr */
346 if (priv->plat->phy_addr > MII_XGMAC_MAX_C22ADDR)
347 dev_err(dev, "Unsupported phy_addr (max=%d)\n",
348 MII_XGMAC_MAX_C22ADDR);
350 new_bus->read = &stmmac_mdio_read;
351 new_bus->write = &stmmac_mdio_write;
352 max_addr = PHY_MAX_ADDR;
355 new_bus->reset = &stmmac_mdio_reset;
356 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
357 new_bus->name, priv->plat->bus_id);
358 new_bus->priv = ndev;
359 new_bus->phy_mask = mdio_bus_data->phy_mask;
360 new_bus->parent = priv->device;
362 err = of_mdiobus_register(new_bus, mdio_node);
364 dev_err(dev, "Cannot register the MDIO bus\n");
365 goto bus_register_fail;
368 if (priv->plat->phy_node || mdio_node)
369 goto bus_register_done;
372 for (addr = 0; addr < max_addr; addr++) {
373 struct phy_device *phydev = mdiobus_get_phy(new_bus, addr);
379 * If an IRQ was provided to be assigned after
380 * the bus probe, do it here.
382 if (!mdio_bus_data->irqs &&
383 (mdio_bus_data->probed_phy_irq > 0)) {
384 new_bus->irq[addr] = mdio_bus_data->probed_phy_irq;
385 phydev->irq = mdio_bus_data->probed_phy_irq;
389 * If we're going to bind the MAC to this PHY bus,
390 * and no PHY number was provided to the MAC,
391 * use the one probed here.
393 if (priv->plat->phy_addr == -1)
394 priv->plat->phy_addr = addr;
396 phy_attached_info(phydev);
400 if (!found && !mdio_node) {
401 dev_warn(dev, "No PHY found\n");
402 mdiobus_unregister(new_bus);
403 mdiobus_free(new_bus);
413 mdiobus_free(new_bus);
418 * stmmac_mdio_unregister
419 * @ndev: net device structure
420 * Description: it unregisters the MII bus
422 int stmmac_mdio_unregister(struct net_device *ndev)
424 struct stmmac_priv *priv = netdev_priv(ndev);
429 mdiobus_unregister(priv->mii);
430 priv->mii->priv = NULL;
431 mdiobus_free(priv->mii);