1 /*******************************************************************************
2 STMMAC Ethernet Driver -- MDIO bus implementation
3 Provides Bus interface for MII registers
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
23 Author: Carl Shaw <carl.shaw@st.com>
24 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25 *******************************************************************************/
27 #include <linux/mii.h>
28 #include <linux/phy.h>
29 #include <linux/slab.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_mdio.h>
37 #define MII_BUSY 0x00000001
38 #define MII_WRITE 0x00000002
41 #define MII_GMAC4_GOC_SHIFT 2
42 #define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT)
43 #define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT)
45 static int stmmac_mdio_busy_wait(void __iomem *ioaddr, unsigned int mii_addr)
48 unsigned long finish = jiffies + 3 * HZ;
52 if (readl(ioaddr + mii_addr) & MII_BUSY)
56 } while (!time_after_eq(curr, finish));
63 * @bus: points to the mii_bus structure
66 * Description: it reads data from the MII register from within the phy device.
67 * For the 7111 GMAC, we must set the bit 0 in the MII address register while
68 * accessing the PHY registers.
69 * Fortunately, it seems this has no drawback for the 7109 MAC.
71 static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
73 struct net_device *ndev = bus->priv;
74 struct stmmac_priv *priv = netdev_priv(ndev);
75 unsigned int mii_address = priv->hw->mii.addr;
76 unsigned int mii_data = priv->hw->mii.data;
81 value |= (phyaddr << priv->hw->mii.addr_shift)
82 & priv->hw->mii.addr_mask;
83 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
84 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
85 & priv->hw->mii.clk_csr_mask;
86 if (priv->plat->has_gmac4)
87 value |= MII_GMAC4_READ;
89 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
92 writel(value, priv->ioaddr + mii_address);
94 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
97 /* Read the data from the MII data register */
98 data = (int)readl(priv->ioaddr + mii_data);
105 * @bus: points to the mii_bus structure
109 * Description: it writes the data into the MII register from within the device.
111 static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
114 struct net_device *ndev = bus->priv;
115 struct stmmac_priv *priv = netdev_priv(ndev);
116 unsigned int mii_address = priv->hw->mii.addr;
117 unsigned int mii_data = priv->hw->mii.data;
119 u32 value = MII_WRITE | MII_BUSY;
121 value |= (phyaddr << priv->hw->mii.addr_shift)
122 & priv->hw->mii.addr_mask;
123 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
125 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
126 & priv->hw->mii.clk_csr_mask;
127 if (priv->plat->has_gmac4)
128 value |= MII_GMAC4_WRITE;
130 /* Wait until any existing MII operation is complete */
131 if (stmmac_mdio_busy_wait(priv->ioaddr, mii_address))
134 /* Set the MII address register to write */
135 writel(phydata, priv->ioaddr + mii_data);
136 writel(value, priv->ioaddr + mii_address);
138 /* Wait until any existing MII operation is complete */
139 return stmmac_mdio_busy_wait(priv->ioaddr, mii_address);
144 * @bus: points to the mii_bus structure
145 * Description: reset the MII bus
147 int stmmac_mdio_reset(struct mii_bus *bus)
149 #if defined(CONFIG_STMMAC_PLATFORM)
150 struct net_device *ndev = bus->priv;
151 struct stmmac_priv *priv = netdev_priv(ndev);
152 unsigned int mii_address = priv->hw->mii.addr;
153 struct stmmac_mdio_bus_data *data = priv->plat->mdio_bus_data;
156 if (priv->device->of_node) {
158 if (data->reset_gpio < 0) {
159 struct device_node *np = priv->device->of_node;
163 data->reset_gpio = of_get_named_gpio(np,
164 "snps,reset-gpio", 0);
165 if (data->reset_gpio < 0)
168 data->active_low = of_property_read_bool(np,
169 "snps,reset-active-low");
170 of_property_read_u32_array(np,
171 "snps,reset-delays-us", data->delays, 3);
173 if (gpio_request(data->reset_gpio, "mdio-reset"))
177 gpio_direction_output(data->reset_gpio,
178 data->active_low ? 1 : 0);
180 msleep(DIV_ROUND_UP(data->delays[0], 1000));
182 gpio_set_value(data->reset_gpio, data->active_low ? 0 : 1);
184 msleep(DIV_ROUND_UP(data->delays[1], 1000));
186 gpio_set_value(data->reset_gpio, data->active_low ? 1 : 0);
188 msleep(DIV_ROUND_UP(data->delays[2], 1000));
192 if (data->phy_reset) {
193 netdev_dbg(ndev, "stmmac_mdio_reset: calling phy_reset\n");
194 data->phy_reset(priv->plat->bsp_priv);
197 /* This is a workaround for problems with the STE101P PHY.
198 * It doesn't complete its reset until at least one clock cycle
199 * on MDC, so perform a dummy mdio read. To be upadted for GMAC4
202 if (!priv->plat->has_gmac4)
203 writel(0, priv->ioaddr + mii_address);
209 * stmmac_mdio_register
210 * @ndev: net device structure
211 * Description: it registers the MII bus
213 int stmmac_mdio_register(struct net_device *ndev)
216 struct mii_bus *new_bus;
217 struct stmmac_priv *priv = netdev_priv(ndev);
218 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data;
219 struct device_node *mdio_node = priv->plat->mdio_node;
225 new_bus = mdiobus_alloc();
229 if (mdio_bus_data->irqs)
230 memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq));
233 if (priv->device->of_node)
234 mdio_bus_data->reset_gpio = -1;
237 new_bus->name = "stmmac";
238 new_bus->read = &stmmac_mdio_read;
239 new_bus->write = &stmmac_mdio_write;
241 new_bus->reset = &stmmac_mdio_reset;
242 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x",
243 new_bus->name, priv->plat->bus_id);
244 new_bus->priv = ndev;
245 new_bus->phy_mask = mdio_bus_data->phy_mask;
246 new_bus->parent = priv->device;
249 err = of_mdiobus_register(new_bus, mdio_node);
251 err = mdiobus_register(new_bus);
253 netdev_err(ndev, "Cannot register the MDIO bus\n");
254 goto bus_register_fail;
257 if (priv->plat->phy_node || mdio_node)
258 goto bus_register_done;
261 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
262 struct phy_device *phydev = mdiobus_get_phy(new_bus, addr);
269 * If an IRQ was provided to be assigned after
270 * the bus probe, do it here.
272 if ((mdio_bus_data->irqs == NULL) &&
273 (mdio_bus_data->probed_phy_irq > 0)) {
275 mdio_bus_data->probed_phy_irq;
276 phydev->irq = mdio_bus_data->probed_phy_irq;
280 * If we're going to bind the MAC to this PHY bus,
281 * and no PHY number was provided to the MAC,
282 * use the one probed here.
284 if (priv->plat->phy_addr == -1)
285 priv->plat->phy_addr = addr;
287 act = (priv->plat->phy_addr == addr);
288 switch (phydev->irq) {
292 case PHY_IGNORE_INTERRUPT:
296 sprintf(irq_num, "%d", phydev->irq);
300 netdev_info(ndev, "PHY ID %08x at %d IRQ %s (%s)%s\n",
301 phydev->phy_id, addr,
302 irq_str, phydev_name(phydev),
303 act ? " active" : "");
308 if (!found && !mdio_node) {
309 netdev_warn(ndev, "No PHY found\n");
310 mdiobus_unregister(new_bus);
311 mdiobus_free(new_bus);
321 mdiobus_free(new_bus);
326 * stmmac_mdio_unregister
327 * @ndev: net device structure
328 * Description: it unregisters the MII bus
330 int stmmac_mdio_unregister(struct net_device *ndev)
332 struct stmmac_priv *priv = netdev_priv(ndev);
337 mdiobus_unregister(priv->mii);
338 priv->mii->priv = NULL;
339 mdiobus_free(priv->mii);