drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   4   ST Ethernet IPs are built around a Synopsys IP Core.
   5
   6         Copyright(C) 2007-2011 STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10
  11   Documentation available at:
  12         http://www.stlinux.com
  13   Support available at:
  14         https://bugzilla.stlinux.com/
  15 *******************************************************************************/
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ip.h>
  21 #include <linux/tcp.h>
  22 #include <linux/skbuff.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mii.h>
  27 #include <linux/if.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #ifdef CONFIG_DEBUG_FS
  34 #include <linux/debugfs.h>
  35 #include <linux/seq_file.h>
  36 #endif /* CONFIG_DEBUG_FS */
  37 #include <linux/net_tstamp.h>
  38 #include <linux/phylink.h>
  39 #include <net/pkt_cls.h>
  40 #include "stmmac_ptp.h"
  41 #include "stmmac.h"
  42 #include <linux/reset.h>
  43 #include <linux/of_mdio.h>
  44 #include "dwmac1000.h"
  45 #include "dwxgmac2.h"
  46 #include "hwif.h"
  47
  48 #define STMMAC_ALIGN(x)         __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
  49 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  50
  51 /* Module parameters */
  52 #define TX_TIMEO        5000
  53 static int watchdog = TX_TIMEO;
  54 module_param(watchdog, int, 0644);
  55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  56
  57 static int debug = -1;
  58 module_param(debug, int, 0644);
  59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  60
  61 static int phyaddr = -1;
  62 module_param(phyaddr, int, 0444);
  63 MODULE_PARM_DESC(phyaddr, "Physical device address");
  64
  65 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  66 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
  67
  68 static int flow_ctrl = FLOW_AUTO;
  69 module_param(flow_ctrl, int, 0644);
  70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  71
  72 static int pause = PAUSE_TIME;
  73 module_param(pause, int, 0644);
  74 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  75
  76 #define TC_DEFAULT 64
  77 static int tc = TC_DEFAULT;
  78 module_param(tc, int, 0644);
  79 MODULE_PARM_DESC(tc, "DMA threshold control value");
  80
  81 #define DEFAULT_BUFSIZE 1536
  82 static int buf_sz = DEFAULT_BUFSIZE;
  83 module_param(buf_sz, int, 0644);
  84 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  85
  86 #define STMMAC_RX_COPYBREAK     256
  87
  88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  89                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
  90                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
  91
  92 #define STMMAC_DEFAULT_LPI_TIMER        1000
  93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
  94 module_param(eee_timer, int, 0644);
  95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
  96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
  97
  98 /* By default the driver will use the ring mode to manage tx and rx descriptors,
  99  * but allow user to force to use the chain instead of the ring
 100  */
 101 static unsigned int chain_mode;
 102 module_param(chain_mode, int, 0444);
 103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 104
 105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 106
 107 #ifdef CONFIG_DEBUG_FS
 108 static int stmmac_init_fs(struct net_device *dev);
 109 static void stmmac_exit_fs(struct net_device *dev);
 110 #endif
 111
 112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 113
 114 /**
 115  * stmmac_verify_args - verify the driver parameters.
 116  * Description: it checks the driver parameters and set a default in case of
 117  * errors.
 118  */
 119 static void stmmac_verify_args(void)
 120 {
 121         if (unlikely(watchdog < 0))
 122                 watchdog = TX_TIMEO;
 123         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 124                 buf_sz = DEFAULT_BUFSIZE;
 125         if (unlikely(flow_ctrl > 1))
 126                 flow_ctrl = FLOW_AUTO;
 127         else if (likely(flow_ctrl < 0))
 128                 flow_ctrl = FLOW_OFF;
 129         if (unlikely((pause < 0) || (pause > 0xffff)))
 130                 pause = PAUSE_TIME;
 131         if (eee_timer < 0)
 132                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 133 }
 134
 135 /**
 136  * stmmac_disable_all_queues - Disable all queues
 137  * @priv: driver private structure
 138  */
 139 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
 140 {
 141         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 142         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 143         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 144         u32 queue;
 145
 146         for (queue = 0; queue < maxq; queue++) {
 147                 struct stmmac_channel *ch = &priv->channel[queue];
 148
 149                 if (queue < rx_queues_cnt)
 150                         napi_disable(&ch->rx_napi);
 151                 if (queue < tx_queues_cnt)
 152                         napi_disable(&ch->tx_napi);
 153         }
 154 }
 155
 156 /**
 157  * stmmac_enable_all_queues - Enable all queues
 158  * @priv: driver private structure
 159  */
 160 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
 161 {
 162         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 163         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 164         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 165         u32 queue;
 166
 167         for (queue = 0; queue < maxq; queue++) {
 168                 struct stmmac_channel *ch = &priv->channel[queue];
 169
 170                 if (queue < rx_queues_cnt)
 171                         napi_enable(&ch->rx_napi);
 172                 if (queue < tx_queues_cnt)
 173                         napi_enable(&ch->tx_napi);
 174         }
 175 }
 176
 177 /**
 178  * stmmac_stop_all_queues - Stop all queues
 179  * @priv: driver private structure
 180  */
 181 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
 182 {
 183         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 184         u32 queue;
 185
 186         for (queue = 0; queue < tx_queues_cnt; queue++)
 187                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
 188 }
 189
 190 /**
 191  * stmmac_start_all_queues - Start all queues
 192  * @priv: driver private structure
 193  */
 194 static void stmmac_start_all_queues(struct stmmac_priv *priv)
 195 {
 196         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 197         u32 queue;
 198
 199         for (queue = 0; queue < tx_queues_cnt; queue++)
 200                 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
 201 }
 202
 203 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 204 {
 205         if (!test_bit(STMMAC_DOWN, &priv->state) &&
 206             !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
 207                 queue_work(priv->wq, &priv->service_task);
 208 }
 209
 210 static void stmmac_global_err(struct stmmac_priv *priv)
 211 {
 212         netif_carrier_off(priv->dev);
 213         set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 214         stmmac_service_event_schedule(priv);
 215 }
 216
 217 /**
 218  * stmmac_clk_csr_set - dynamically set the MDC clock
 219  * @priv: driver private structure
 220  * Description: this is to dynamically set the MDC clock according to the csr
 221  * clock input.
 222  * Note:
 223  *      If a specific clk_csr value is passed from the platform
 224  *      this means that the CSR Clock Range selection cannot be
 225  *      changed at run-time and it is fixed (as reported in the driver
 226  *      documentation). Viceversa the driver will try to set the MDC
 227  *      clock dynamically according to the actual clock input.
 228  */
 229 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 230 {
 231         u32 clk_rate;
 232
 233         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 234
 235         /* Platform provided default clk_csr would be assumed valid
 236          * for all other cases except for the below mentioned ones.
 237          * For values higher than the IEEE 802.3 specified frequency
 238          * we can not estimate the proper divider as it is not known
 239          * the frequency of clk_csr_i. So we do not change the default
 240          * divider.
 241          */
 242         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 243                 if (clk_rate < CSR_F_35M)
 244                         priv->clk_csr = STMMAC_CSR_20_35M;
 245                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 246                         priv->clk_csr = STMMAC_CSR_35_60M;
 247                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 248                         priv->clk_csr = STMMAC_CSR_60_100M;
 249                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 250                         priv->clk_csr = STMMAC_CSR_100_150M;
 251                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 252                         priv->clk_csr = STMMAC_CSR_150_250M;
 253                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 254                         priv->clk_csr = STMMAC_CSR_250_300M;
 255         }
 256
 257         if (priv->plat->has_sun8i) {
 258                 if (clk_rate > 160000000)
 259                         priv->clk_csr = 0x03;
 260                 else if (clk_rate > 80000000)
 261                         priv->clk_csr = 0x02;
 262                 else if (clk_rate > 40000000)
 263                         priv->clk_csr = 0x01;
 264                 else
 265                         priv->clk_csr = 0;
 266         }
 267
 268         if (priv->plat->has_xgmac) {
 269                 if (clk_rate > 400000000)
 270                         priv->clk_csr = 0x5;
 271                 else if (clk_rate > 350000000)
 272                         priv->clk_csr = 0x4;
 273                 else if (clk_rate > 300000000)
 274                         priv->clk_csr = 0x3;
 275                 else if (clk_rate > 250000000)
 276                         priv->clk_csr = 0x2;
 277                 else if (clk_rate > 150000000)
 278                         priv->clk_csr = 0x1;
 279                 else
 280                         priv->clk_csr = 0x0;
 281         }
 282 }
 283
 284 static void print_pkt(unsigned char *buf, int len)
 285 {
 286         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 287         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 288 }
 289
 290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
 291 {
 292         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 293         u32 avail;
 294
 295         if (tx_q->dirty_tx > tx_q->cur_tx)
 296                 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
 297         else
 298                 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
 299
 300         return avail;
 301 }
 302
 303 /**
 304  * stmmac_rx_dirty - Get RX queue dirty
 305  * @priv: driver private structure
 306  * @queue: RX queue index
 307  */
 308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
 309 {
 310         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 311         u32 dirty;
 312
 313         if (rx_q->dirty_rx <= rx_q->cur_rx)
 314                 dirty = rx_q->cur_rx - rx_q->dirty_rx;
 315         else
 316                 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
 317
 318         return dirty;
 319 }
 320
 321 /**
 322  * stmmac_enable_eee_mode - check and enter in LPI mode
 323  * @priv: driver private structure
 324  * Description: this function is to verify and enter in LPI mode in case of
 325  * EEE.
 326  */
 327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 328 {
 329         u32 tx_cnt = priv->plat->tx_queues_to_use;
 330         u32 queue;
 331
 332         /* check if all TX queues have the work finished */
 333         for (queue = 0; queue < tx_cnt; queue++) {
 334                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 335
 336                 if (tx_q->dirty_tx != tx_q->cur_tx)
 337                         return; /* still unfinished work */
 338         }
 339
 340         /* Check and enter in LPI mode */
 341         if (!priv->tx_path_in_lpi_mode)
 342                 stmmac_set_eee_mode(priv, priv->hw,
 343                                 priv->plat->en_tx_lpi_clockgating);
 344 }
 345
 346 /**
 347  * stmmac_disable_eee_mode - disable and exit from LPI mode
 348  * @priv: driver private structure
 349  * Description: this function is to exit and disable EEE in case of
 350  * LPI state is true. This is called by the xmit.
 351  */
 352 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 353 {
 354         stmmac_reset_eee_mode(priv, priv->hw);
 355         del_timer_sync(&priv->eee_ctrl_timer);
 356         priv->tx_path_in_lpi_mode = false;
 357 }
 358
 359 /**
 360  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 361  * @arg : data hook
 362  * Description:
 363  *  if there is no data transfer and if we are not in LPI state,
 364  *  then MAC Transmitter can be moved to LPI state.
 365  */
 366 static void stmmac_eee_ctrl_timer(struct timer_list *t)
 367 {
 368         struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
 369
 370         stmmac_enable_eee_mode(priv);
 371         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 372 }
 373
 374 /**
 375  * stmmac_eee_init - init EEE
 376  * @priv: driver private structure
 377  * Description:
 378  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 379  *  can also manage EEE, this function enable the LPI state and start related
 380  *  timer.
 381  */
 382 bool stmmac_eee_init(struct stmmac_priv *priv)
 383 {
 384         int tx_lpi_timer = priv->tx_lpi_timer;
 385
 386         /* Using PCS we cannot dial with the phy registers at this stage
 387          * so we do not support extra feature like EEE.
 388          */
 389         if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
 390             (priv->hw->pcs == STMMAC_PCS_TBI) ||
 391             (priv->hw->pcs == STMMAC_PCS_RTBI))
 392                 return false;
 393
 394         /* Check if MAC core supports the EEE feature. */
 395         if (!priv->dma_cap.eee)
 396                 return false;
 397
 398         mutex_lock(&priv->lock);
 399
 400         /* Check if it needs to be deactivated */
 401         if (!priv->eee_active) {
 402                 if (priv->eee_enabled) {
 403                         netdev_dbg(priv->dev, "disable EEE\n");
 404                         del_timer_sync(&priv->eee_ctrl_timer);
 405                         stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
 406                 }
 407                 mutex_unlock(&priv->lock);
 408                 return false;
 409         }
 410
 411         if (priv->eee_active && !priv->eee_enabled) {
 412                 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
 413                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 414                 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
 415                                      tx_lpi_timer);
 416         }
 417
 418         mutex_unlock(&priv->lock);
 419         netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 420         return true;
 421 }
 422
 423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 424  * @priv: driver private structure
 425  * @p : descriptor pointer
 426  * @skb : the socket buffer
 427  * Description :
 428  * This function will read timestamp from the descriptor & pass it to stack.
 429  * and also perform some sanity checks.
 430  */
 431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 432                                    struct dma_desc *p, struct sk_buff *skb)
 433 {
 434         struct skb_shared_hwtstamps shhwtstamp;
 435         u64 ns = 0;
 436
 437         if (!priv->hwts_tx_en)
 438                 return;
 439
 440         /* exit if skb doesn't support hw tstamp */
 441         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 442                 return;
 443
 444         /* check tx tstamp status */
 445         if (stmmac_get_tx_timestamp_status(priv, p)) {
 446                 /* get the valid tstamp */
 447                 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
 448
 449                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 450                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 451
 452                 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 453                 /* pass tstamp to stack */
 454                 skb_tstamp_tx(skb, &shhwtstamp);
 455         }
 456
 457         return;
 458 }
 459
 460 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 461  * @priv: driver private structure
 462  * @p : descriptor pointer
 463  * @np : next descriptor pointer
 464  * @skb : the socket buffer
 465  * Description :
 466  * This function will read received packet's timestamp from the descriptor
 467  * and pass it to stack. It also perform some sanity checks.
 468  */
 469 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 470                                    struct dma_desc *np, struct sk_buff *skb)
 471 {
 472         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 473         struct dma_desc *desc = p;
 474         u64 ns = 0;
 475
 476         if (!priv->hwts_rx_en)
 477                 return;
 478         /* For GMAC4, the valid timestamp is from CTX next desc. */
 479         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
 480                 desc = np;
 481
 482         /* Check if timestamp is available */
 483         if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
 484                 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
 485                 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 486                 shhwtstamp = skb_hwtstamps(skb);
 487                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 488                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 489         } else  {
 490                 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 491         }
 492 }
 493
 494 /**
 495  *  stmmac_hwtstamp_set - control hardware timestamping.
 496  *  @dev: device pointer.
 497  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 498  *  a proprietary structure used to pass information to the driver.
 499  *  Description:
 500  *  This function configures the MAC to enable/disable both outgoing(TX)
 501  *  and incoming(RX) packets time stamping based on user input.
 502  *  Return Value:
 503  *  0 on success and an appropriate -ve integer on failure.
 504  */
 505 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 506 {
 507         struct stmmac_priv *priv = netdev_priv(dev);
 508         struct hwtstamp_config config;
 509         struct timespec64 now;
 510         u64 temp = 0;
 511         u32 ptp_v2 = 0;
 512         u32 tstamp_all = 0;
 513         u32 ptp_over_ipv4_udp = 0;
 514         u32 ptp_over_ipv6_udp = 0;
 515         u32 ptp_over_ethernet = 0;
 516         u32 snap_type_sel = 0;
 517         u32 ts_master_en = 0;
 518         u32 ts_event_en = 0;
 519         u32 sec_inc = 0;
 520         u32 value = 0;
 521         bool xmac;
 522
 523         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 524
 525         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 526                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 527                 priv->hwts_tx_en = 0;
 528                 priv->hwts_rx_en = 0;
 529
 530                 return -EOPNOTSUPP;
 531         }
 532
 533         if (copy_from_user(&config, ifr->ifr_data,
 534                            sizeof(config)))
 535                 return -EFAULT;
 536
 537         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 538                    __func__, config.flags, config.tx_type, config.rx_filter);
 539
 540         /* reserved for future extensions */
 541         if (config.flags)
 542                 return -EINVAL;
 543
 544         if (config.tx_type != HWTSTAMP_TX_OFF &&
 545             config.tx_type != HWTSTAMP_TX_ON)
 546                 return -ERANGE;
 547
 548         if (priv->adv_ts) {
 549                 switch (config.rx_filter) {
 550                 case HWTSTAMP_FILTER_NONE:
 551                         /* time stamp no incoming packet at all */
 552                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 553                         break;
 554
 555                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 556                         /* PTP v1, UDP, any kind of event packet */
 557                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 558                         /* 'xmac' hardware can support Sync, Pdelay_Req and
 559                          * Pdelay_resp by setting bit14 and bits17/16 to 01
 560                          * This leaves Delay_Req timestamps out.
 561                          * Enable all events *and* general purpose message
 562                          * timestamping
 563                          */
 564                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 565                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 566                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 567                         break;
 568
 569                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 570                         /* PTP v1, UDP, Sync packet */
 571                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 572                         /* take time stamp for SYNC messages only */
 573                         ts_event_en = PTP_TCR_TSEVNTENA;
 574
 575                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 576                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 577                         break;
 578
 579                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 580                         /* PTP v1, UDP, Delay_req packet */
 581                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 582                         /* take time stamp for Delay_Req messages only */
 583                         ts_master_en = PTP_TCR_TSMSTRENA;
 584                         ts_event_en = PTP_TCR_TSEVNTENA;
 585
 586                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 587                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 588                         break;
 589
 590                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 591                         /* PTP v2, UDP, any kind of event packet */
 592                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 593                         ptp_v2 = PTP_TCR_TSVER2ENA;
 594                         /* take time stamp for all event messages */
 595                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 596
 597                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 598                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 599                         break;
 600
 601                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 602                         /* PTP v2, UDP, Sync packet */
 603                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 604                         ptp_v2 = PTP_TCR_TSVER2ENA;
 605                         /* take time stamp for SYNC messages only */
 606                         ts_event_en = PTP_TCR_TSEVNTENA;
 607
 608                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 609                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 610                         break;
 611
 612                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 613                         /* PTP v2, UDP, Delay_req packet */
 614                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 615                         ptp_v2 = PTP_TCR_TSVER2ENA;
 616                         /* take time stamp for Delay_Req messages only */
 617                         ts_master_en = PTP_TCR_TSMSTRENA;
 618                         ts_event_en = PTP_TCR_TSEVNTENA;
 619
 620                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 621                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 622                         break;
 623
 624                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 625                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 626                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 627                         ptp_v2 = PTP_TCR_TSVER2ENA;
 628                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 629                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 630                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 631                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 632                         break;
 633
 634                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 635                         /* PTP v2/802.AS1, any layer, Sync packet */
 636                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 637                         ptp_v2 = PTP_TCR_TSVER2ENA;
 638                         /* take time stamp for SYNC messages only */
 639                         ts_event_en = PTP_TCR_TSEVNTENA;
 640
 641                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 642                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 643                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 644                         break;
 645
 646                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 647                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 648                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 649                         ptp_v2 = PTP_TCR_TSVER2ENA;
 650                         /* take time stamp for Delay_Req messages only */
 651                         ts_master_en = PTP_TCR_TSMSTRENA;
 652                         ts_event_en = PTP_TCR_TSEVNTENA;
 653
 654                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 655                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 656                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 657                         break;
 658
 659                 case HWTSTAMP_FILTER_NTP_ALL:
 660                 case HWTSTAMP_FILTER_ALL:
 661                         /* time stamp any incoming packet */
 662                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 663                         tstamp_all = PTP_TCR_TSENALL;
 664                         break;
 665
 666                 default:
 667                         return -ERANGE;
 668                 }
 669         } else {
 670                 switch (config.rx_filter) {
 671                 case HWTSTAMP_FILTER_NONE:
 672                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 673                         break;
 674                 default:
 675                         /* PTP v1, UDP, any kind of event packet */
 676                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 677                         break;
 678                 }
 679         }
 680         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 681         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 682
 683         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 684                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
 685         else {
 686                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 687                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 688                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 689                          ts_master_en | snap_type_sel);
 690                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
 691
 692                 /* program Sub Second Increment reg */
 693                 stmmac_config_sub_second_increment(priv,
 694                                 priv->ptpaddr, priv->plat->clk_ptp_rate,
 695                                 xmac, &sec_inc);
 696                 temp = div_u64(1000000000ULL, sec_inc);
 697
 698                 /* Store sub second increment and flags for later use */
 699                 priv->sub_second_inc = sec_inc;
 700                 priv->systime_flags = value;
 701
 702                 /* calculate default added value:
 703                  * formula is :
 704                  * addend = (2^32)/freq_div_ratio;
 705                  * where, freq_div_ratio = 1e9ns/sec_inc
 706                  */
 707                 temp = (u64)(temp << 32);
 708                 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 709                 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
 710
 711                 /* initialize system time */
 712                 ktime_get_real_ts64(&now);
 713
 714                 /* lower 32 bits of tv_sec are safe until y2106 */
 715                 stmmac_init_systime(priv, priv->ptpaddr,
 716                                 (u32)now.tv_sec, now.tv_nsec);
 717         }
 718
 719         memcpy(&priv->tstamp_config, &config, sizeof(config));
 720
 721         return copy_to_user(ifr->ifr_data, &config,
 722                             sizeof(config)) ? -EFAULT : 0;
 723 }
 724
 725 /**
 726  *  stmmac_hwtstamp_get - read hardware timestamping.
 727  *  @dev: device pointer.
 728  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 729  *  a proprietary structure used to pass information to the driver.
 730  *  Description:
 731  *  This function obtain the current hardware timestamping settings
 732     as requested.
 733  */
 734 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 735 {
 736         struct stmmac_priv *priv = netdev_priv(dev);
 737         struct hwtstamp_config *config = &priv->tstamp_config;
 738
 739         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 740                 return -EOPNOTSUPP;
 741
 742         return copy_to_user(ifr->ifr_data, config,
 743                             sizeof(*config)) ? -EFAULT : 0;
 744 }
 745
 746 /**
 747  * stmmac_init_ptp - init PTP
 748  * @priv: driver private structure
 749  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 750  * This is done by looking at the HW cap. register.
 751  * This function also registers the ptp driver.
 752  */
 753 static int stmmac_init_ptp(struct stmmac_priv *priv)
 754 {
 755         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 756
 757         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 758                 return -EOPNOTSUPP;
 759
 760         priv->adv_ts = 0;
 761         /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
 762         if (xmac && priv->dma_cap.atime_stamp)
 763                 priv->adv_ts = 1;
 764         /* Dwmac 3.x core with extend_desc can support adv_ts */
 765         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 766                 priv->adv_ts = 1;
 767
 768         if (priv->dma_cap.time_stamp)
 769                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 770
 771         if (priv->adv_ts)
 772                 netdev_info(priv->dev,
 773                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 774
 775         priv->hwts_tx_en = 0;
 776         priv->hwts_rx_en = 0;
 777
 778         stmmac_ptp_register(priv);
 779
 780         return 0;
 781 }
 782
 783 static void stmmac_release_ptp(struct stmmac_priv *priv)
 784 {
 785         if (priv->plat->clk_ptp_ref)
 786                 clk_disable_unprepare(priv->plat->clk_ptp_ref);
 787         stmmac_ptp_unregister(priv);
 788 }
 789
 790 /**
 791  *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 792  *  @priv: driver private structure
 793  *  Description: It is used for configuring the flow control in all queues
 794  */
 795 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
 796 {
 797         u32 tx_cnt = priv->plat->tx_queues_to_use;
 798
 799         stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
 800                         priv->pause, tx_cnt);
 801 }
 802
 803 static void stmmac_validate(struct phylink_config *config,
 804                             unsigned long *supported,
 805                             struct phylink_link_state *state)
 806 {
 807         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 808         __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
 809         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 810         int tx_cnt = priv->plat->tx_queues_to_use;
 811         int max_speed = priv->plat->max_speed;
 812
 813         phylink_set(mac_supported, 10baseT_Half);
 814         phylink_set(mac_supported, 10baseT_Full);
 815         phylink_set(mac_supported, 100baseT_Half);
 816         phylink_set(mac_supported, 100baseT_Full);
 817         phylink_set(mac_supported, 1000baseT_Half);
 818         phylink_set(mac_supported, 1000baseT_Full);
 819         phylink_set(mac_supported, 1000baseKX_Full);
 820
 821         phylink_set(mac_supported, Autoneg);
 822         phylink_set(mac_supported, Pause);
 823         phylink_set(mac_supported, Asym_Pause);
 824         phylink_set_port_modes(mac_supported);
 825
 826         /* Cut down 1G if asked to */
 827         if ((max_speed > 0) && (max_speed < 1000)) {
 828                 phylink_set(mask, 1000baseT_Full);
 829                 phylink_set(mask, 1000baseX_Full);
 830         } else if (priv->plat->has_xgmac) {
 831                 phylink_set(mac_supported, 2500baseT_Full);
 832                 phylink_set(mac_supported, 5000baseT_Full);
 833                 phylink_set(mac_supported, 10000baseSR_Full);
 834                 phylink_set(mac_supported, 10000baseLR_Full);
 835                 phylink_set(mac_supported, 10000baseER_Full);
 836                 phylink_set(mac_supported, 10000baseLRM_Full);
 837                 phylink_set(mac_supported, 10000baseT_Full);
 838                 phylink_set(mac_supported, 10000baseKX4_Full);
 839                 phylink_set(mac_supported, 10000baseKR_Full);
 840         }
 841
 842         /* Half-Duplex can only work with single queue */
 843         if (tx_cnt > 1) {
 844                 phylink_set(mask, 10baseT_Half);
 845                 phylink_set(mask, 100baseT_Half);
 846                 phylink_set(mask, 1000baseT_Half);
 847         }
 848
 849         bitmap_and(supported, supported, mac_supported,
 850                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 851         bitmap_andnot(supported, supported, mask,
 852                       __ETHTOOL_LINK_MODE_MASK_NBITS);
 853         bitmap_and(state->advertising, state->advertising, mac_supported,
 854                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 855         bitmap_andnot(state->advertising, state->advertising, mask,
 856                       __ETHTOOL_LINK_MODE_MASK_NBITS);
 857 }
 858
 859 static int stmmac_mac_link_state(struct phylink_config *config,
 860                                  struct phylink_link_state *state)
 861 {
 862         return -EOPNOTSUPP;
 863 }
 864
 865 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
 866                               const struct phylink_link_state *state)
 867 {
 868         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 869         u32 ctrl;
 870
 871         ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 872         ctrl &= ~priv->hw->link.speed_mask;
 873
 874         if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
 875                 switch (state->speed) {
 876                 case SPEED_10000:
 877                         ctrl |= priv->hw->link.xgmii.speed10000;
 878                         break;
 879                 case SPEED_5000:
 880                         ctrl |= priv->hw->link.xgmii.speed5000;
 881                         break;
 882                 case SPEED_2500:
 883                         ctrl |= priv->hw->link.xgmii.speed2500;
 884                         break;
 885                 default:
 886                         return;
 887                 }
 888         } else {
 889                 switch (state->speed) {
 890                 case SPEED_2500:
 891                         ctrl |= priv->hw->link.speed2500;
 892                         break;
 893                 case SPEED_1000:
 894                         ctrl |= priv->hw->link.speed1000;
 895                         break;
 896                 case SPEED_100:
 897                         ctrl |= priv->hw->link.speed100;
 898                         break;
 899                 case SPEED_10:
 900                         ctrl |= priv->hw->link.speed10;
 901                         break;
 902                 default:
 903                         return;
 904                 }
 905         }
 906
 907         priv->speed = state->speed;
 908
 909         if (priv->plat->fix_mac_speed)
 910                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed);
 911
 912         if (!state->duplex)
 913                 ctrl &= ~priv->hw->link.duplex;
 914         else
 915                 ctrl |= priv->hw->link.duplex;
 916
 917         /* Flow Control operation */
 918         if (state->pause)
 919                 stmmac_mac_flow_ctrl(priv, state->duplex);
 920
 921         writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 922 }
 923
 924 static void stmmac_mac_an_restart(struct phylink_config *config)
 925 {
 926         /* Not Supported */
 927 }
 928
 929 static void stmmac_mac_link_down(struct phylink_config *config,
 930                                  unsigned int mode, phy_interface_t interface)
 931 {
 932         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 933
 934         stmmac_mac_set(priv, priv->ioaddr, false);
 935         priv->eee_active = false;
 936         stmmac_eee_init(priv);
 937         stmmac_set_eee_pls(priv, priv->hw, false);
 938 }
 939
 940 static void stmmac_mac_link_up(struct phylink_config *config,
 941                                unsigned int mode, phy_interface_t interface,
 942                                struct phy_device *phy)
 943 {
 944         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 945
 946         stmmac_mac_set(priv, priv->ioaddr, true);
 947         if (phy && priv->dma_cap.eee) {
 948                 priv->eee_active = phy_init_eee(phy, 1) >= 0;
 949                 priv->eee_enabled = stmmac_eee_init(priv);
 950                 stmmac_set_eee_pls(priv, priv->hw, true);
 951         }
 952 }
 953
 954 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
 955         .validate = stmmac_validate,
 956         .mac_link_state = stmmac_mac_link_state,
 957         .mac_config = stmmac_mac_config,
 958         .mac_an_restart = stmmac_mac_an_restart,
 959         .mac_link_down = stmmac_mac_link_down,
 960         .mac_link_up = stmmac_mac_link_up,
 961 };
 962
 963 /**
 964  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 965  * @priv: driver private structure
 966  * Description: this is to verify if the HW supports the PCS.
 967  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 968  * configured for the TBI, RTBI, or SGMII PHY interface.
 969  */
 970 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 971 {
 972         int interface = priv->plat->interface;
 973
 974         if (priv->dma_cap.pcs) {
 975                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 976                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 977                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 978                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 979                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
 980                         priv->hw->pcs = STMMAC_PCS_RGMII;
 981                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 982                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
 983                         priv->hw->pcs = STMMAC_PCS_SGMII;
 984                 }
 985         }
 986 }
 987
 988 /**
 989  * stmmac_init_phy - PHY initialization
 990  * @dev: net device structure
 991  * Description: it initializes the driver's PHY state, and attaches the PHY
 992  * to the mac driver.
 993  *  Return value:
 994  *  0 on success
 995  */
 996 static int stmmac_init_phy(struct net_device *dev)
 997 {
 998         struct stmmac_priv *priv = netdev_priv(dev);
 999         struct device_node *node;
1000         int ret;
1001
1002         node = priv->plat->phylink_node;
1003
1004         if (node)
1005                 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1006
1007         /* Some DT bindings do not set-up the PHY handle. Let's try to
1008          * manually parse it
1009          */
1010         if (!node || ret) {
1011                 int addr = priv->plat->phy_addr;
1012                 struct phy_device *phydev;
1013
1014                 phydev = mdiobus_get_phy(priv->mii, addr);
1015                 if (!phydev) {
1016                         netdev_err(priv->dev, "no phy at addr %d\n", addr);
1017                         return -ENODEV;
1018                 }
1019
1020                 ret = phylink_connect_phy(priv->phylink, phydev);
1021         }
1022
1023         return ret;
1024 }
1025
1026 static int stmmac_phy_setup(struct stmmac_priv *priv)
1027 {
1028         struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1029         int mode = priv->plat->interface;
1030         struct phylink *phylink;
1031
1032         priv->phylink_config.dev = &priv->dev->dev;
1033         priv->phylink_config.type = PHYLINK_NETDEV;
1034
1035         phylink = phylink_create(&priv->phylink_config, fwnode,
1036                                  mode, &stmmac_phylink_mac_ops);
1037         if (IS_ERR(phylink))
1038                 return PTR_ERR(phylink);
1039
1040         priv->phylink = phylink;
1041         return 0;
1042 }
1043
1044 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1045 {
1046         u32 rx_cnt = priv->plat->rx_queues_to_use;
1047         void *head_rx;
1048         u32 queue;
1049
1050         /* Display RX rings */
1051         for (queue = 0; queue < rx_cnt; queue++) {
1052                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1053
1054                 pr_info("\tRX Queue %u rings\n", queue);
1055
1056                 if (priv->extend_desc)
1057                         head_rx = (void *)rx_q->dma_erx;
1058                 else
1059                         head_rx = (void *)rx_q->dma_rx;
1060
1061                 /* Display RX ring */
1062                 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1063         }
1064 }
1065
1066 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1067 {
1068         u32 tx_cnt = priv->plat->tx_queues_to_use;
1069         void *head_tx;
1070         u32 queue;
1071
1072         /* Display TX rings */
1073         for (queue = 0; queue < tx_cnt; queue++) {
1074                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1075
1076                 pr_info("\tTX Queue %d rings\n", queue);
1077
1078                 if (priv->extend_desc)
1079                         head_tx = (void *)tx_q->dma_etx;
1080                 else
1081                         head_tx = (void *)tx_q->dma_tx;
1082
1083                 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1084         }
1085 }
1086
1087 static void stmmac_display_rings(struct stmmac_priv *priv)
1088 {
1089         /* Display RX ring */
1090         stmmac_display_rx_rings(priv);
1091
1092         /* Display TX ring */
1093         stmmac_display_tx_rings(priv);
1094 }
1095
1096 static int stmmac_set_bfsize(int mtu, int bufsize)
1097 {
1098         int ret = bufsize;
1099
1100         if (mtu >= BUF_SIZE_4KiB)
1101                 ret = BUF_SIZE_8KiB;
1102         else if (mtu >= BUF_SIZE_2KiB)
1103                 ret = BUF_SIZE_4KiB;
1104         else if (mtu > DEFAULT_BUFSIZE)
1105                 ret = BUF_SIZE_2KiB;
1106         else
1107                 ret = DEFAULT_BUFSIZE;
1108
1109         return ret;
1110 }
1111
1112 /**
1113  * stmmac_clear_rx_descriptors - clear RX descriptors
1114  * @priv: driver private structure
1115  * @queue: RX queue index
1116  * Description: this function is called to clear the RX descriptors
1117  * in case of both basic and extended descriptors are used.
1118  */
1119 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1120 {
1121         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1122         int i;
1123
1124         /* Clear the RX descriptors */
1125         for (i = 0; i < DMA_RX_SIZE; i++)
1126                 if (priv->extend_desc)
1127                         stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1128                                         priv->use_riwt, priv->mode,
1129                                         (i == DMA_RX_SIZE - 1),
1130                                         priv->dma_buf_sz);
1131                 else
1132                         stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1133                                         priv->use_riwt, priv->mode,
1134                                         (i == DMA_RX_SIZE - 1),
1135                                         priv->dma_buf_sz);
1136 }
1137
1138 /**
1139  * stmmac_clear_tx_descriptors - clear tx descriptors
1140  * @priv: driver private structure
1141  * @queue: TX queue index.
1142  * Description: this function is called to clear the TX descriptors
1143  * in case of both basic and extended descriptors are used.
1144  */
1145 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1146 {
1147         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1148         int i;
1149
1150         /* Clear the TX descriptors */
1151         for (i = 0; i < DMA_TX_SIZE; i++)
1152                 if (priv->extend_desc)
1153                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1154                                         priv->mode, (i == DMA_TX_SIZE - 1));
1155                 else
1156                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1157                                         priv->mode, (i == DMA_TX_SIZE - 1));
1158 }
1159
1160 /**
1161  * stmmac_clear_descriptors - clear descriptors
1162  * @priv: driver private structure
1163  * Description: this function is called to clear the TX and RX descriptors
1164  * in case of both basic and extended descriptors are used.
1165  */
1166 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1167 {
1168         u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1169         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1170         u32 queue;
1171
1172         /* Clear the RX descriptors */
1173         for (queue = 0; queue < rx_queue_cnt; queue++)
1174                 stmmac_clear_rx_descriptors(priv, queue);
1175
1176         /* Clear the TX descriptors */
1177         for (queue = 0; queue < tx_queue_cnt; queue++)
1178                 stmmac_clear_tx_descriptors(priv, queue);
1179 }
1180
1181 /**
1182  * stmmac_init_rx_buffers - init the RX descriptor buffer.
1183  * @priv: driver private structure
1184  * @p: descriptor pointer
1185  * @i: descriptor index
1186  * @flags: gfp flag
1187  * @queue: RX queue index
1188  * Description: this function is called to allocate a receive buffer, perform
1189  * the DMA mapping and init the descriptor.
1190  */
1191 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1192                                   int i, gfp_t flags, u32 queue)
1193 {
1194         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1195         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1196
1197         buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
1198         if (!buf->page)
1199                 return -ENOMEM;
1200
1201         buf->addr = page_pool_get_dma_addr(buf->page);
1202         stmmac_set_desc_addr(priv, p, buf->addr);
1203         if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1204                 stmmac_init_desc3(priv, p);
1205
1206         return 0;
1207 }
1208
1209 /**
1210  * stmmac_free_rx_buffer - free RX dma buffers
1211  * @priv: private structure
1212  * @queue: RX queue index
1213  * @i: buffer index.
1214  */
1215 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1216 {
1217         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1218         struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1219
1220         if (buf->page)
1221                 page_pool_put_page(rx_q->page_pool, buf->page, false);
1222         buf->page = NULL;
1223 }
1224
1225 /**
1226  * stmmac_free_tx_buffer - free RX dma buffers
1227  * @priv: private structure
1228  * @queue: RX queue index
1229  * @i: buffer index.
1230  */
1231 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1232 {
1233         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1234
1235         if (tx_q->tx_skbuff_dma[i].buf) {
1236                 if (tx_q->tx_skbuff_dma[i].map_as_page)
1237                         dma_unmap_page(priv->device,
1238                                        tx_q->tx_skbuff_dma[i].buf,
1239                                        tx_q->tx_skbuff_dma[i].len,
1240                                        DMA_TO_DEVICE);
1241                 else
1242                         dma_unmap_single(priv->device,
1243                                          tx_q->tx_skbuff_dma[i].buf,
1244                                          tx_q->tx_skbuff_dma[i].len,
1245                                          DMA_TO_DEVICE);
1246         }
1247
1248         if (tx_q->tx_skbuff[i]) {
1249                 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1250                 tx_q->tx_skbuff[i] = NULL;
1251                 tx_q->tx_skbuff_dma[i].buf = 0;
1252                 tx_q->tx_skbuff_dma[i].map_as_page = false;
1253         }
1254 }
1255
1256 /**
1257  * init_dma_rx_desc_rings - init the RX descriptor rings
1258  * @dev: net device structure
1259  * @flags: gfp flag.
1260  * Description: this function initializes the DMA RX descriptors
1261  * and allocates the socket buffers. It supports the chained and ring
1262  * modes.
1263  */
1264 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1265 {
1266         struct stmmac_priv *priv = netdev_priv(dev);
1267         u32 rx_count = priv->plat->rx_queues_to_use;
1268         int ret = -ENOMEM;
1269         int bfsize = 0;
1270         int queue;
1271         int i;
1272
1273         bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1274         if (bfsize < 0)
1275                 bfsize = 0;
1276
1277         if (bfsize < BUF_SIZE_16KiB)
1278                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1279
1280         priv->dma_buf_sz = bfsize;
1281
1282         /* RX INITIALIZATION */
1283         netif_dbg(priv, probe, priv->dev,
1284                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1285
1286         for (queue = 0; queue < rx_count; queue++) {
1287                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1288
1289                 netif_dbg(priv, probe, priv->dev,
1290                           "(%s) dma_rx_phy=0x%08x\n", __func__,
1291                           (u32)rx_q->dma_rx_phy);
1292
1293                 stmmac_clear_rx_descriptors(priv, queue);
1294
1295                 for (i = 0; i < DMA_RX_SIZE; i++) {
1296                         struct dma_desc *p;
1297
1298                         if (priv->extend_desc)
1299                                 p = &((rx_q->dma_erx + i)->basic);
1300                         else
1301                                 p = rx_q->dma_rx + i;
1302
1303                         ret = stmmac_init_rx_buffers(priv, p, i, flags,
1304                                                      queue);
1305                         if (ret)
1306                                 goto err_init_rx_buffers;
1307                 }
1308
1309                 rx_q->cur_rx = 0;
1310                 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1311
1312                 /* Setup the chained descriptor addresses */
1313                 if (priv->mode == STMMAC_CHAIN_MODE) {
1314                         if (priv->extend_desc)
1315                                 stmmac_mode_init(priv, rx_q->dma_erx,
1316                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1317                         else
1318                                 stmmac_mode_init(priv, rx_q->dma_rx,
1319                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1320                 }
1321         }
1322
1323         buf_sz = bfsize;
1324
1325         return 0;
1326
1327 err_init_rx_buffers:
1328         while (queue >= 0) {
1329                 while (--i >= 0)
1330                         stmmac_free_rx_buffer(priv, queue, i);
1331
1332                 if (queue == 0)
1333                         break;
1334
1335                 i = DMA_RX_SIZE;
1336                 queue--;
1337         }
1338
1339         return ret;
1340 }
1341
1342 /**
1343  * init_dma_tx_desc_rings - init the TX descriptor rings
1344  * @dev: net device structure.
1345  * Description: this function initializes the DMA TX descriptors
1346  * and allocates the socket buffers. It supports the chained and ring
1347  * modes.
1348  */
1349 static int init_dma_tx_desc_rings(struct net_device *dev)
1350 {
1351         struct stmmac_priv *priv = netdev_priv(dev);
1352         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1353         u32 queue;
1354         int i;
1355
1356         for (queue = 0; queue < tx_queue_cnt; queue++) {
1357                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1358
1359                 netif_dbg(priv, probe, priv->dev,
1360                           "(%s) dma_tx_phy=0x%08x\n", __func__,
1361                          (u32)tx_q->dma_tx_phy);
1362
1363                 /* Setup the chained descriptor addresses */
1364                 if (priv->mode == STMMAC_CHAIN_MODE) {
1365                         if (priv->extend_desc)
1366                                 stmmac_mode_init(priv, tx_q->dma_etx,
1367                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1368                         else
1369                                 stmmac_mode_init(priv, tx_q->dma_tx,
1370                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1371                 }
1372
1373                 for (i = 0; i < DMA_TX_SIZE; i++) {
1374                         struct dma_desc *p;
1375                         if (priv->extend_desc)
1376                                 p = &((tx_q->dma_etx + i)->basic);
1377                         else
1378                                 p = tx_q->dma_tx + i;
1379
1380                         stmmac_clear_desc(priv, p);
1381
1382                         tx_q->tx_skbuff_dma[i].buf = 0;
1383                         tx_q->tx_skbuff_dma[i].map_as_page = false;
1384                         tx_q->tx_skbuff_dma[i].len = 0;
1385                         tx_q->tx_skbuff_dma[i].last_segment = false;
1386                         tx_q->tx_skbuff[i] = NULL;
1387                 }
1388
1389                 tx_q->dirty_tx = 0;
1390                 tx_q->cur_tx = 0;
1391                 tx_q->mss = 0;
1392
1393                 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1394         }
1395
1396         return 0;
1397 }
1398
1399 /**
1400  * init_dma_desc_rings - init the RX/TX descriptor rings
1401  * @dev: net device structure
1402  * @flags: gfp flag.
1403  * Description: this function initializes the DMA RX/TX descriptors
1404  * and allocates the socket buffers. It supports the chained and ring
1405  * modes.
1406  */
1407 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1408 {
1409         struct stmmac_priv *priv = netdev_priv(dev);
1410         int ret;
1411
1412         ret = init_dma_rx_desc_rings(dev, flags);
1413         if (ret)
1414                 return ret;
1415
1416         ret = init_dma_tx_desc_rings(dev);
1417
1418         stmmac_clear_descriptors(priv);
1419
1420         if (netif_msg_hw(priv))
1421                 stmmac_display_rings(priv);
1422
1423         return ret;
1424 }
1425
1426 /**
1427  * dma_free_rx_skbufs - free RX dma buffers
1428  * @priv: private structure
1429  * @queue: RX queue index
1430  */
1431 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1432 {
1433         int i;
1434
1435         for (i = 0; i < DMA_RX_SIZE; i++)
1436                 stmmac_free_rx_buffer(priv, queue, i);
1437 }
1438
1439 /**
1440  * dma_free_tx_skbufs - free TX dma buffers
1441  * @priv: private structure
1442  * @queue: TX queue index
1443  */
1444 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1445 {
1446         int i;
1447
1448         for (i = 0; i < DMA_TX_SIZE; i++)
1449                 stmmac_free_tx_buffer(priv, queue, i);
1450 }
1451
1452 /**
1453  * free_dma_rx_desc_resources - free RX dma desc resources
1454  * @priv: private structure
1455  */
1456 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1457 {
1458         u32 rx_count = priv->plat->rx_queues_to_use;
1459         u32 queue;
1460
1461         /* Free RX queue resources */
1462         for (queue = 0; queue < rx_count; queue++) {
1463                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1464
1465                 /* Release the DMA RX socket buffers */
1466                 dma_free_rx_skbufs(priv, queue);
1467
1468                 /* Free DMA regions of consistent memory previously allocated */
1469                 if (!priv->extend_desc)
1470                         dma_free_coherent(priv->device,
1471                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1472                                           rx_q->dma_rx, rx_q->dma_rx_phy);
1473                 else
1474                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1475                                           sizeof(struct dma_extended_desc),
1476                                           rx_q->dma_erx, rx_q->dma_rx_phy);
1477
1478                 kfree(rx_q->buf_pool);
1479                 if (rx_q->page_pool) {
1480                         page_pool_request_shutdown(rx_q->page_pool);
1481                         page_pool_destroy(rx_q->page_pool);
1482                 }
1483         }
1484 }
1485
1486 /**
1487  * free_dma_tx_desc_resources - free TX dma desc resources
1488  * @priv: private structure
1489  */
1490 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1491 {
1492         u32 tx_count = priv->plat->tx_queues_to_use;
1493         u32 queue;
1494
1495         /* Free TX queue resources */
1496         for (queue = 0; queue < tx_count; queue++) {
1497                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1498
1499                 /* Release the DMA TX socket buffers */
1500                 dma_free_tx_skbufs(priv, queue);
1501
1502                 /* Free DMA regions of consistent memory previously allocated */
1503                 if (!priv->extend_desc)
1504                         dma_free_coherent(priv->device,
1505                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1506                                           tx_q->dma_tx, tx_q->dma_tx_phy);
1507                 else
1508                         dma_free_coherent(priv->device, DMA_TX_SIZE *
1509                                           sizeof(struct dma_extended_desc),
1510                                           tx_q->dma_etx, tx_q->dma_tx_phy);
1511
1512                 kfree(tx_q->tx_skbuff_dma);
1513                 kfree(tx_q->tx_skbuff);
1514         }
1515 }
1516
1517 /**
1518  * alloc_dma_rx_desc_resources - alloc RX resources.
1519  * @priv: private structure
1520  * Description: according to which descriptor can be used (extend or basic)
1521  * this function allocates the resources for TX and RX paths. In case of
1522  * reception, for example, it pre-allocated the RX socket buffer in order to
1523  * allow zero-copy mechanism.
1524  */
1525 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1526 {
1527         u32 rx_count = priv->plat->rx_queues_to_use;
1528         int ret = -ENOMEM;
1529         u32 queue;
1530
1531         /* RX queues buffers and DMA */
1532         for (queue = 0; queue < rx_count; queue++) {
1533                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1534                 struct page_pool_params pp_params = { 0 };
1535
1536                 rx_q->queue_index = queue;
1537                 rx_q->priv_data = priv;
1538
1539                 pp_params.flags = PP_FLAG_DMA_MAP;
1540                 pp_params.pool_size = DMA_RX_SIZE;
1541                 pp_params.order = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
1542                 pp_params.nid = dev_to_node(priv->device);
1543                 pp_params.dev = priv->device;
1544                 pp_params.dma_dir = DMA_FROM_DEVICE;
1545
1546                 rx_q->page_pool = page_pool_create(&pp_params);
1547                 if (IS_ERR(rx_q->page_pool)) {
1548                         ret = PTR_ERR(rx_q->page_pool);
1549                         rx_q->page_pool = NULL;
1550                         goto err_dma;
1551                 }
1552
1553                 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool),
1554                                          GFP_KERNEL);
1555                 if (!rx_q->buf_pool)
1556                         goto err_dma;
1557
1558                 if (priv->extend_desc) {
1559                         rx_q->dma_erx = dma_alloc_coherent(priv->device,
1560                                                            DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1561                                                            &rx_q->dma_rx_phy,
1562                                                            GFP_KERNEL);
1563                         if (!rx_q->dma_erx)
1564                                 goto err_dma;
1565
1566                 } else {
1567                         rx_q->dma_rx = dma_alloc_coherent(priv->device,
1568                                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1569                                                           &rx_q->dma_rx_phy,
1570                                                           GFP_KERNEL);
1571                         if (!rx_q->dma_rx)
1572                                 goto err_dma;
1573                 }
1574         }
1575
1576         return 0;
1577
1578 err_dma:
1579         free_dma_rx_desc_resources(priv);
1580
1581         return ret;
1582 }
1583
1584 /**
1585  * alloc_dma_tx_desc_resources - alloc TX resources.
1586  * @priv: private structure
1587  * Description: according to which descriptor can be used (extend or basic)
1588  * this function allocates the resources for TX and RX paths. In case of
1589  * reception, for example, it pre-allocated the RX socket buffer in order to
1590  * allow zero-copy mechanism.
1591  */
1592 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1593 {
1594         u32 tx_count = priv->plat->tx_queues_to_use;
1595         int ret = -ENOMEM;
1596         u32 queue;
1597
1598         /* TX queues buffers and DMA */
1599         for (queue = 0; queue < tx_count; queue++) {
1600                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1601
1602                 tx_q->queue_index = queue;
1603                 tx_q->priv_data = priv;
1604
1605                 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE,
1606                                               sizeof(*tx_q->tx_skbuff_dma),
1607                                               GFP_KERNEL);
1608                 if (!tx_q->tx_skbuff_dma)
1609                         goto err_dma;
1610
1611                 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE,
1612                                           sizeof(struct sk_buff *),
1613                                           GFP_KERNEL);
1614                 if (!tx_q->tx_skbuff)
1615                         goto err_dma;
1616
1617                 if (priv->extend_desc) {
1618                         tx_q->dma_etx = dma_alloc_coherent(priv->device,
1619                                                            DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1620                                                            &tx_q->dma_tx_phy,
1621                                                            GFP_KERNEL);
1622                         if (!tx_q->dma_etx)
1623                                 goto err_dma;
1624                 } else {
1625                         tx_q->dma_tx = dma_alloc_coherent(priv->device,
1626                                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1627                                                           &tx_q->dma_tx_phy,
1628                                                           GFP_KERNEL);
1629                         if (!tx_q->dma_tx)
1630                                 goto err_dma;
1631                 }
1632         }
1633
1634         return 0;
1635
1636 err_dma:
1637         free_dma_tx_desc_resources(priv);
1638
1639         return ret;
1640 }
1641
1642 /**
1643  * alloc_dma_desc_resources - alloc TX/RX resources.
1644  * @priv: private structure
1645  * Description: according to which descriptor can be used (extend or basic)
1646  * this function allocates the resources for TX and RX paths. In case of
1647  * reception, for example, it pre-allocated the RX socket buffer in order to
1648  * allow zero-copy mechanism.
1649  */
1650 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1651 {
1652         /* RX Allocation */
1653         int ret = alloc_dma_rx_desc_resources(priv);
1654
1655         if (ret)
1656                 return ret;
1657
1658         ret = alloc_dma_tx_desc_resources(priv);
1659
1660         return ret;
1661 }
1662
1663 /**
1664  * free_dma_desc_resources - free dma desc resources
1665  * @priv: private structure
1666  */
1667 static void free_dma_desc_resources(struct stmmac_priv *priv)
1668 {
1669         /* Release the DMA RX socket buffers */
1670         free_dma_rx_desc_resources(priv);
1671
1672         /* Release the DMA TX socket buffers */
1673         free_dma_tx_desc_resources(priv);
1674 }
1675
1676 /**
1677  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
1678  *  @priv: driver private structure
1679  *  Description: It is used for enabling the rx queues in the MAC
1680  */
1681 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1682 {
1683         u32 rx_queues_count = priv->plat->rx_queues_to_use;
1684         int queue;
1685         u8 mode;
1686
1687         for (queue = 0; queue < rx_queues_count; queue++) {
1688                 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1689                 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1690         }
1691 }
1692
1693 /**
1694  * stmmac_start_rx_dma - start RX DMA channel
1695  * @priv: driver private structure
1696  * @chan: RX channel index
1697  * Description:
1698  * This starts a RX DMA channel
1699  */
1700 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1701 {
1702         netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1703         stmmac_start_rx(priv, priv->ioaddr, chan);
1704 }
1705
1706 /**
1707  * stmmac_start_tx_dma - start TX DMA channel
1708  * @priv: driver private structure
1709  * @chan: TX channel index
1710  * Description:
1711  * This starts a TX DMA channel
1712  */
1713 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1714 {
1715         netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1716         stmmac_start_tx(priv, priv->ioaddr, chan);
1717 }
1718
1719 /**
1720  * stmmac_stop_rx_dma - stop RX DMA channel
1721  * @priv: driver private structure
1722  * @chan: RX channel index
1723  * Description:
1724  * This stops a RX DMA channel
1725  */
1726 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1727 {
1728         netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1729         stmmac_stop_rx(priv, priv->ioaddr, chan);
1730 }
1731
1732 /**
1733  * stmmac_stop_tx_dma - stop TX DMA channel
1734  * @priv: driver private structure
1735  * @chan: TX channel index
1736  * Description:
1737  * This stops a TX DMA channel
1738  */
1739 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1740 {
1741         netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1742         stmmac_stop_tx(priv, priv->ioaddr, chan);
1743 }
1744
1745 /**
1746  * stmmac_start_all_dma - start all RX and TX DMA channels
1747  * @priv: driver private structure
1748  * Description:
1749  * This starts all the RX and TX DMA channels
1750  */
1751 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1752 {
1753         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1754         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1755         u32 chan = 0;
1756
1757         for (chan = 0; chan < rx_channels_count; chan++)
1758                 stmmac_start_rx_dma(priv, chan);
1759
1760         for (chan = 0; chan < tx_channels_count; chan++)
1761                 stmmac_start_tx_dma(priv, chan);
1762 }
1763
1764 /**
1765  * stmmac_stop_all_dma - stop all RX and TX DMA channels
1766  * @priv: driver private structure
1767  * Description:
1768  * This stops the RX and TX DMA channels
1769  */
1770 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1771 {
1772         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1773         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1774         u32 chan = 0;
1775
1776         for (chan = 0; chan < rx_channels_count; chan++)
1777                 stmmac_stop_rx_dma(priv, chan);
1778
1779         for (chan = 0; chan < tx_channels_count; chan++)
1780                 stmmac_stop_tx_dma(priv, chan);
1781 }
1782
1783 /**
1784  *  stmmac_dma_operation_mode - HW DMA operation mode
1785  *  @priv: driver private structure
1786  *  Description: it is used for configuring the DMA operation mode register in
1787  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1788  */
1789 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1790 {
1791         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1792         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1793         int rxfifosz = priv->plat->rx_fifo_size;
1794         int txfifosz = priv->plat->tx_fifo_size;
1795         u32 txmode = 0;
1796         u32 rxmode = 0;
1797         u32 chan = 0;
1798         u8 qmode = 0;
1799
1800         if (rxfifosz == 0)
1801                 rxfifosz = priv->dma_cap.rx_fifo_size;
1802         if (txfifosz == 0)
1803                 txfifosz = priv->dma_cap.tx_fifo_size;
1804
1805         /* Adjust for real per queue fifo size */
1806         rxfifosz /= rx_channels_count;
1807         txfifosz /= tx_channels_count;
1808
1809         if (priv->plat->force_thresh_dma_mode) {
1810                 txmode = tc;
1811                 rxmode = tc;
1812         } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1813                 /*
1814                  * In case of GMAC, SF mode can be enabled
1815                  * to perform the TX COE in HW. This depends on:
1816                  * 1) TX COE if actually supported
1817                  * 2) There is no bugged Jumbo frame support
1818                  *    that needs to not insert csum in the TDES.
1819                  */
1820                 txmode = SF_DMA_MODE;
1821                 rxmode = SF_DMA_MODE;
1822                 priv->xstats.threshold = SF_DMA_MODE;
1823         } else {
1824                 txmode = tc;
1825                 rxmode = SF_DMA_MODE;
1826         }
1827
1828         /* configure all channels */
1829         for (chan = 0; chan < rx_channels_count; chan++) {
1830                 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1831
1832                 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1833                                 rxfifosz, qmode);
1834                 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1835                                 chan);
1836         }
1837
1838         for (chan = 0; chan < tx_channels_count; chan++) {
1839                 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1840
1841                 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1842                                 txfifosz, qmode);
1843         }
1844 }
1845
1846 /**
1847  * stmmac_tx_clean - to manage the transmission completion
1848  * @priv: driver private structure
1849  * @queue: TX queue index
1850  * Description: it reclaims the transmit resources after transmission completes.
1851  */
1852 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1853 {
1854         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1855         unsigned int bytes_compl = 0, pkts_compl = 0;
1856         unsigned int entry, count = 0;
1857
1858         __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1859
1860         priv->xstats.tx_clean++;
1861
1862         entry = tx_q->dirty_tx;
1863         while ((entry != tx_q->cur_tx) && (count < budget)) {
1864                 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1865                 struct dma_desc *p;
1866                 int status;
1867
1868                 if (priv->extend_desc)
1869                         p = (struct dma_desc *)(tx_q->dma_etx + entry);
1870                 else
1871                         p = tx_q->dma_tx + entry;
1872
1873                 status = stmmac_tx_status(priv, &priv->dev->stats,
1874                                 &priv->xstats, p, priv->ioaddr);
1875                 /* Check if the descriptor is owned by the DMA */
1876                 if (unlikely(status & tx_dma_own))
1877                         break;
1878
1879                 count++;
1880
1881                 /* Make sure descriptor fields are read after reading
1882                  * the own bit.
1883                  */
1884                 dma_rmb();
1885
1886                 /* Just consider the last segment and ...*/
1887                 if (likely(!(status & tx_not_ls))) {
1888                         /* ... verify the status error condition */
1889                         if (unlikely(status & tx_err)) {
1890                                 priv->dev->stats.tx_errors++;
1891                         } else {
1892                                 priv->dev->stats.tx_packets++;
1893                                 priv->xstats.tx_pkt_n++;
1894                         }
1895                         stmmac_get_tx_hwtstamp(priv, p, skb);
1896                 }
1897
1898                 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1899                         if (tx_q->tx_skbuff_dma[entry].map_as_page)
1900                                 dma_unmap_page(priv->device,
1901                                                tx_q->tx_skbuff_dma[entry].buf,
1902                                                tx_q->tx_skbuff_dma[entry].len,
1903                                                DMA_TO_DEVICE);
1904                         else
1905                                 dma_unmap_single(priv->device,
1906                                                  tx_q->tx_skbuff_dma[entry].buf,
1907                                                  tx_q->tx_skbuff_dma[entry].len,
1908                                                  DMA_TO_DEVICE);
1909                         tx_q->tx_skbuff_dma[entry].buf = 0;
1910                         tx_q->tx_skbuff_dma[entry].len = 0;
1911                         tx_q->tx_skbuff_dma[entry].map_as_page = false;
1912                 }
1913
1914                 stmmac_clean_desc3(priv, tx_q, p);
1915
1916                 tx_q->tx_skbuff_dma[entry].last_segment = false;
1917                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1918
1919                 if (likely(skb != NULL)) {
1920                         pkts_compl++;
1921                         bytes_compl += skb->len;
1922                         dev_consume_skb_any(skb);
1923                         tx_q->tx_skbuff[entry] = NULL;
1924                 }
1925
1926                 stmmac_release_tx_desc(priv, p, priv->mode);
1927
1928                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1929         }
1930         tx_q->dirty_tx = entry;
1931
1932         netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1933                                   pkts_compl, bytes_compl);
1934
1935         if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1936                                                                 queue))) &&
1937             stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1938
1939                 netif_dbg(priv, tx_done, priv->dev,
1940                           "%s: restart transmit\n", __func__);
1941                 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1942         }
1943
1944         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1945                 stmmac_enable_eee_mode(priv);
1946                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1947         }
1948
1949         /* We still have pending packets, let's call for a new scheduling */
1950         if (tx_q->dirty_tx != tx_q->cur_tx)
1951                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1952
1953         __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1954
1955         return count;
1956 }
1957
1958 /**
1959  * stmmac_tx_err - to manage the tx error
1960  * @priv: driver private structure
1961  * @chan: channel index
1962  * Description: it cleans the descriptors and restarts the transmission
1963  * in case of transmission errors.
1964  */
1965 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1966 {
1967         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1968         int i;
1969
1970         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1971
1972         stmmac_stop_tx_dma(priv, chan);
1973         dma_free_tx_skbufs(priv, chan);
1974         for (i = 0; i < DMA_TX_SIZE; i++)
1975                 if (priv->extend_desc)
1976                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1977                                         priv->mode, (i == DMA_TX_SIZE - 1));
1978                 else
1979                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1980                                         priv->mode, (i == DMA_TX_SIZE - 1));
1981         tx_q->dirty_tx = 0;
1982         tx_q->cur_tx = 0;
1983         tx_q->mss = 0;
1984         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
1985         stmmac_start_tx_dma(priv, chan);
1986
1987         priv->dev->stats.tx_errors++;
1988         netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
1989 }
1990
1991 /**
1992  *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
1993  *  @priv: driver private structure
1994  *  @txmode: TX operating mode
1995  *  @rxmode: RX operating mode
1996  *  @chan: channel index
1997  *  Description: it is used for configuring of the DMA operation mode in
1998  *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
1999  *  mode.
2000  */
2001 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2002                                           u32 rxmode, u32 chan)
2003 {
2004         u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2005         u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2006         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2007         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2008         int rxfifosz = priv->plat->rx_fifo_size;
2009         int txfifosz = priv->plat->tx_fifo_size;
2010
2011         if (rxfifosz == 0)
2012                 rxfifosz = priv->dma_cap.rx_fifo_size;
2013         if (txfifosz == 0)
2014                 txfifosz = priv->dma_cap.tx_fifo_size;
2015
2016         /* Adjust for real per queue fifo size */
2017         rxfifosz /= rx_channels_count;
2018         txfifosz /= tx_channels_count;
2019
2020         stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2021         stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2022 }
2023
2024 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2025 {
2026         int ret;
2027
2028         ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2029                         priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2030         if (ret && (ret != -EINVAL)) {
2031                 stmmac_global_err(priv);
2032                 return true;
2033         }
2034
2035         return false;
2036 }
2037
2038 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
2039 {
2040         int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2041                                                  &priv->xstats, chan);
2042         struct stmmac_channel *ch = &priv->channel[chan];
2043
2044         if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2045                 if (napi_schedule_prep(&ch->rx_napi)) {
2046                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2047                         __napi_schedule_irqoff(&ch->rx_napi);
2048                         status |= handle_tx;
2049                 }
2050         }
2051
2052         if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use))
2053                 napi_schedule_irqoff(&ch->tx_napi);
2054
2055         return status;
2056 }
2057
2058 /**
2059  * stmmac_dma_interrupt - DMA ISR
2060  * @priv: driver private structure
2061  * Description: this is the DMA ISR. It is called by the main ISR.
2062  * It calls the dwmac dma routine and schedule poll method in case of some
2063  * work can be done.
2064  */
2065 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2066 {
2067         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2068         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2069         u32 channels_to_check = tx_channel_count > rx_channel_count ?
2070                                 tx_channel_count : rx_channel_count;
2071         u32 chan;
2072         int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2073
2074         /* Make sure we never check beyond our status buffer. */
2075         if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2076                 channels_to_check = ARRAY_SIZE(status);
2077
2078         for (chan = 0; chan < channels_to_check; chan++)
2079                 status[chan] = stmmac_napi_check(priv, chan);
2080
2081         for (chan = 0; chan < tx_channel_count; chan++) {
2082                 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2083                         /* Try to bump up the dma threshold on this failure */
2084                         if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2085                             (tc <= 256)) {
2086                                 tc += 64;
2087                                 if (priv->plat->force_thresh_dma_mode)
2088                                         stmmac_set_dma_operation_mode(priv,
2089                                                                       tc,
2090                                                                       tc,
2091                                                                       chan);
2092                                 else
2093                                         stmmac_set_dma_operation_mode(priv,
2094                                                                     tc,
2095                                                                     SF_DMA_MODE,
2096                                                                     chan);
2097                                 priv->xstats.threshold = tc;
2098                         }
2099                 } else if (unlikely(status[chan] == tx_hard_error)) {
2100                         stmmac_tx_err(priv, chan);
2101                 }
2102         }
2103 }
2104
2105 /**
2106  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2107  * @priv: driver private structure
2108  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2109  */
2110 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2111 {
2112         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2113                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2114
2115         stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2116
2117         if (priv->dma_cap.rmon) {
2118                 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2119                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2120         } else
2121                 netdev_info(priv->dev, "No MAC Management Counters available\n");
2122 }
2123
2124 /**
2125  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2126  * @priv: driver private structure
2127  * Description:
2128  *  new GMAC chip generations have a new register to indicate the
2129  *  presence of the optional feature/functions.
2130  *  This can be also used to override the value passed through the
2131  *  platform and necessary for old MAC10/100 and GMAC chips.
2132  */
2133 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2134 {
2135         return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2136 }
2137
2138 /**
2139  * stmmac_check_ether_addr - check if the MAC addr is valid
2140  * @priv: driver private structure
2141  * Description:
2142  * it is to verify if the MAC address is valid, in case of failures it
2143  * generates a random MAC address
2144  */
2145 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2146 {
2147         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2148                 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2149                 if (!is_valid_ether_addr(priv->dev->dev_addr))
2150                         eth_hw_addr_random(priv->dev);
2151                 dev_info(priv->device, "device MAC address %pM\n",
2152                          priv->dev->dev_addr);
2153         }
2154 }
2155
2156 /**
2157  * stmmac_init_dma_engine - DMA init.
2158  * @priv: driver private structure
2159  * Description:
2160  * It inits the DMA invoking the specific MAC/GMAC callback.
2161  * Some DMA parameters can be passed from the platform;
2162  * in case of these are not passed a default is kept for the MAC or GMAC.
2163  */
2164 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2165 {
2166         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2167         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2168         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2169         struct stmmac_rx_queue *rx_q;
2170         struct stmmac_tx_queue *tx_q;
2171         u32 chan = 0;
2172         int atds = 0;
2173         int ret = 0;
2174
2175         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2176                 dev_err(priv->device, "Invalid DMA configuration\n");
2177                 return -EINVAL;
2178         }
2179
2180         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2181                 atds = 1;
2182
2183         ret = stmmac_reset(priv, priv->ioaddr);
2184         if (ret) {
2185                 dev_err(priv->device, "Failed to reset the dma\n");
2186                 return ret;
2187         }
2188
2189         /* DMA Configuration */
2190         stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2191
2192         if (priv->plat->axi)
2193                 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2194
2195         /* DMA CSR Channel configuration */
2196         for (chan = 0; chan < dma_csr_ch; chan++)
2197                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2198
2199         /* DMA RX Channel Configuration */
2200         for (chan = 0; chan < rx_channels_count; chan++) {
2201                 rx_q = &priv->rx_queue[chan];
2202
2203                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2204                                     rx_q->dma_rx_phy, chan);
2205
2206                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2207                             (DMA_RX_SIZE * sizeof(struct dma_desc));
2208                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2209                                        rx_q->rx_tail_addr, chan);
2210         }
2211
2212         /* DMA TX Channel Configuration */
2213         for (chan = 0; chan < tx_channels_count; chan++) {
2214                 tx_q = &priv->tx_queue[chan];
2215
2216                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2217                                     tx_q->dma_tx_phy, chan);
2218
2219                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2220                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2221                                        tx_q->tx_tail_addr, chan);
2222         }
2223
2224         return ret;
2225 }
2226
2227 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2228 {
2229         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2230
2231         mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2232 }
2233
2234 /**
2235  * stmmac_tx_timer - mitigation sw timer for tx.
2236  * @data: data pointer
2237  * Description:
2238  * This is the timer handler to directly invoke the stmmac_tx_clean.
2239  */
2240 static void stmmac_tx_timer(struct timer_list *t)
2241 {
2242         struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2243         struct stmmac_priv *priv = tx_q->priv_data;
2244         struct stmmac_channel *ch;
2245
2246         ch = &priv->channel[tx_q->queue_index];
2247
2248         /*
2249          * If NAPI is already running we can miss some events. Let's rearm
2250          * the timer and try again.
2251          */
2252         if (likely(napi_schedule_prep(&ch->tx_napi)))
2253                 __napi_schedule(&ch->tx_napi);
2254         else
2255                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2256 }
2257
2258 /**
2259  * stmmac_init_coalesce - init mitigation options.
2260  * @priv: driver private structure
2261  * Description:
2262  * This inits the coalesce parameters: i.e. timer rate,
2263  * timer handler and default threshold used for enabling the
2264  * interrupt on completion bit.
2265  */
2266 static void stmmac_init_coalesce(struct stmmac_priv *priv)
2267 {
2268         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2269         u32 chan;
2270
2271         priv->tx_coal_frames = STMMAC_TX_FRAMES;
2272         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2273         priv->rx_coal_frames = STMMAC_RX_FRAMES;
2274
2275         for (chan = 0; chan < tx_channel_count; chan++) {
2276                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2277
2278                 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2279         }
2280 }
2281
2282 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2283 {
2284         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2285         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2286         u32 chan;
2287
2288         /* set TX ring length */
2289         for (chan = 0; chan < tx_channels_count; chan++)
2290                 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2291                                 (DMA_TX_SIZE - 1), chan);
2292
2293         /* set RX ring length */
2294         for (chan = 0; chan < rx_channels_count; chan++)
2295                 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2296                                 (DMA_RX_SIZE - 1), chan);
2297 }
2298
2299 /**
2300  *  stmmac_set_tx_queue_weight - Set TX queue weight
2301  *  @priv: driver private structure
2302  *  Description: It is used for setting TX queues weight
2303  */
2304 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2305 {
2306         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2307         u32 weight;
2308         u32 queue;
2309
2310         for (queue = 0; queue < tx_queues_count; queue++) {
2311                 weight = priv->plat->tx_queues_cfg[queue].weight;
2312                 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2313         }
2314 }
2315
2316 /**
2317  *  stmmac_configure_cbs - Configure CBS in TX queue
2318  *  @priv: driver private structure
2319  *  Description: It is used for configuring CBS in AVB TX queues
2320  */
2321 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2322 {
2323         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2324         u32 mode_to_use;
2325         u32 queue;
2326
2327         /* queue 0 is reserved for legacy traffic */
2328         for (queue = 1; queue < tx_queues_count; queue++) {
2329                 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2330                 if (mode_to_use == MTL_QUEUE_DCB)
2331                         continue;
2332
2333                 stmmac_config_cbs(priv, priv->hw,
2334                                 priv->plat->tx_queues_cfg[queue].send_slope,
2335                                 priv->plat->tx_queues_cfg[queue].idle_slope,
2336                                 priv->plat->tx_queues_cfg[queue].high_credit,
2337                                 priv->plat->tx_queues_cfg[queue].low_credit,
2338                                 queue);
2339         }
2340 }
2341
2342 /**
2343  *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2344  *  @priv: driver private structure
2345  *  Description: It is used for mapping RX queues to RX dma channels
2346  */
2347 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2348 {
2349         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2350         u32 queue;
2351         u32 chan;
2352
2353         for (queue = 0; queue < rx_queues_count; queue++) {
2354                 chan = priv->plat->rx_queues_cfg[queue].chan;
2355                 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2356         }
2357 }
2358
2359 /**
2360  *  stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2361  *  @priv: driver private structure
2362  *  Description: It is used for configuring the RX Queue Priority
2363  */
2364 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2365 {
2366         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2367         u32 queue;
2368         u32 prio;
2369
2370         for (queue = 0; queue < rx_queues_count; queue++) {
2371                 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2372                         continue;
2373
2374                 prio = priv->plat->rx_queues_cfg[queue].prio;
2375                 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2376         }
2377 }
2378
2379 /**
2380  *  stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2381  *  @priv: driver private structure
2382  *  Description: It is used for configuring the TX Queue Priority
2383  */
2384 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2385 {
2386         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2387         u32 queue;
2388         u32 prio;
2389
2390         for (queue = 0; queue < tx_queues_count; queue++) {
2391                 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2392                         continue;
2393
2394                 prio = priv->plat->tx_queues_cfg[queue].prio;
2395                 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2396         }
2397 }
2398
2399 /**
2400  *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2401  *  @priv: driver private structure
2402  *  Description: It is used for configuring the RX queue routing
2403  */
2404 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2405 {
2406         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2407         u32 queue;
2408         u8 packet;
2409
2410         for (queue = 0; queue < rx_queues_count; queue++) {
2411                 /* no specific packet type routing specified for the queue */
2412                 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2413                         continue;
2414
2415                 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2416                 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2417         }
2418 }
2419
2420 /**
2421  *  stmmac_mtl_configuration - Configure MTL
2422  *  @priv: driver private structure
2423  *  Description: It is used for configurring MTL
2424  */
2425 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2426 {
2427         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2428         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2429
2430         if (tx_queues_count > 1)
2431                 stmmac_set_tx_queue_weight(priv);
2432
2433         /* Configure MTL RX algorithms */
2434         if (rx_queues_count > 1)
2435                 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2436                                 priv->plat->rx_sched_algorithm);
2437
2438         /* Configure MTL TX algorithms */
2439         if (tx_queues_count > 1)
2440                 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2441                                 priv->plat->tx_sched_algorithm);
2442
2443         /* Configure CBS in AVB TX queues */
2444         if (tx_queues_count > 1)
2445                 stmmac_configure_cbs(priv);
2446
2447         /* Map RX MTL to DMA channels */
2448         stmmac_rx_queue_dma_chan_map(priv);
2449
2450         /* Enable MAC RX Queues */
2451         stmmac_mac_enable_rx_queues(priv);
2452
2453         /* Set RX priorities */
2454         if (rx_queues_count > 1)
2455                 stmmac_mac_config_rx_queues_prio(priv);
2456
2457         /* Set TX priorities */
2458         if (tx_queues_count > 1)
2459                 stmmac_mac_config_tx_queues_prio(priv);
2460
2461         /* Set RX routing */
2462         if (rx_queues_count > 1)
2463                 stmmac_mac_config_rx_queues_routing(priv);
2464 }
2465
2466 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2467 {
2468         if (priv->dma_cap.asp) {
2469                 netdev_info(priv->dev, "Enabling Safety Features\n");
2470                 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2471         } else {
2472                 netdev_info(priv->dev, "No Safety Features support found\n");
2473         }
2474 }
2475
2476 /**
2477  * stmmac_hw_setup - setup mac in a usable state.
2478  *  @dev : pointer to the device structure.
2479  *  Description:
2480  *  this is the main function to setup the HW in a usable state because the
2481  *  dma engine is reset, the core registers are configured (e.g. AXI,
2482  *  Checksum features, timers). The DMA is ready to start receiving and
2483  *  transmitting.
2484  *  Return value:
2485  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2486  *  file on failure.
2487  */
2488 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2489 {
2490         struct stmmac_priv *priv = netdev_priv(dev);
2491         u32 rx_cnt = priv->plat->rx_queues_to_use;
2492         u32 tx_cnt = priv->plat->tx_queues_to_use;
2493         u32 chan;
2494         int ret;
2495
2496         /* DMA initialization and SW reset */
2497         ret = stmmac_init_dma_engine(priv);
2498         if (ret < 0) {
2499                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2500                            __func__);
2501                 return ret;
2502         }
2503
2504         /* Copy the MAC addr into the HW  */
2505         stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2506
2507         /* PS and related bits will be programmed according to the speed */
2508         if (priv->hw->pcs) {
2509                 int speed = priv->plat->mac_port_sel_speed;
2510
2511                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2512                     (speed == SPEED_1000)) {
2513                         priv->hw->ps = speed;
2514                 } else {
2515                         dev_warn(priv->device, "invalid port speed\n");
2516                         priv->hw->ps = 0;
2517                 }
2518         }
2519
2520         /* Initialize the MAC Core */
2521         stmmac_core_init(priv, priv->hw, dev);
2522
2523         /* Initialize MTL*/
2524         stmmac_mtl_configuration(priv);
2525
2526         /* Initialize Safety Features */
2527         stmmac_safety_feat_configuration(priv);
2528
2529         ret = stmmac_rx_ipc(priv, priv->hw);
2530         if (!ret) {
2531                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2532                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2533                 priv->hw->rx_csum = 0;
2534         }
2535
2536         /* Enable the MAC Rx/Tx */
2537         stmmac_mac_set(priv, priv->ioaddr, true);
2538
2539         /* Set the HW DMA mode and the COE */
2540         stmmac_dma_operation_mode(priv);
2541
2542         stmmac_mmc_setup(priv);
2543
2544         if (init_ptp) {
2545                 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2546                 if (ret < 0)
2547                         netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2548
2549                 ret = stmmac_init_ptp(priv);
2550                 if (ret == -EOPNOTSUPP)
2551                         netdev_warn(priv->dev, "PTP not supported by HW\n");
2552                 else if (ret)
2553                         netdev_warn(priv->dev, "PTP init failed\n");
2554         }
2555
2556         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2557
2558         if (priv->use_riwt) {
2559                 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MIN_DMA_RIWT, rx_cnt);
2560                 if (!ret)
2561                         priv->rx_riwt = MIN_DMA_RIWT;
2562         }
2563
2564         if (priv->hw->pcs)
2565                 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2566
2567         /* set TX and RX rings length */
2568         stmmac_set_rings_length(priv);
2569
2570         /* Enable TSO */
2571         if (priv->tso) {
2572                 for (chan = 0; chan < tx_cnt; chan++)
2573                         stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2574         }
2575
2576         /* Start the ball rolling... */
2577         stmmac_start_all_dma(priv);
2578
2579         return 0;
2580 }
2581
2582 static void stmmac_hw_teardown(struct net_device *dev)
2583 {
2584         struct stmmac_priv *priv = netdev_priv(dev);
2585
2586         clk_disable_unprepare(priv->plat->clk_ptp_ref);
2587 }
2588
2589 /**
2590  *  stmmac_open - open entry point of the driver
2591  *  @dev : pointer to the device structure.
2592  *  Description:
2593  *  This function is the open entry point of the driver.
2594  *  Return value:
2595  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2596  *  file on failure.
2597  */
2598 static int stmmac_open(struct net_device *dev)
2599 {
2600         struct stmmac_priv *priv = netdev_priv(dev);
2601         u32 chan;
2602         int ret;
2603
2604         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2605             priv->hw->pcs != STMMAC_PCS_TBI &&
2606             priv->hw->pcs != STMMAC_PCS_RTBI) {
2607                 ret = stmmac_init_phy(dev);
2608                 if (ret) {
2609                         netdev_err(priv->dev,
2610                                    "%s: Cannot attach to PHY (error: %d)\n",
2611                                    __func__, ret);
2612                         return ret;
2613                 }
2614         }
2615
2616         /* Extra statistics */
2617         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2618         priv->xstats.threshold = tc;
2619
2620         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2621         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2622
2623         ret = alloc_dma_desc_resources(priv);
2624         if (ret < 0) {
2625                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2626                            __func__);
2627                 goto dma_desc_error;
2628         }
2629
2630         ret = init_dma_desc_rings(dev, GFP_KERNEL);
2631         if (ret < 0) {
2632                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2633                            __func__);
2634                 goto init_error;
2635         }
2636
2637         ret = stmmac_hw_setup(dev, true);
2638         if (ret < 0) {
2639                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2640                 goto init_error;
2641         }
2642
2643         stmmac_init_coalesce(priv);
2644
2645         phylink_start(priv->phylink);
2646
2647         /* Request the IRQ lines */
2648         ret = request_irq(dev->irq, stmmac_interrupt,
2649                           IRQF_SHARED, dev->name, dev);
2650         if (unlikely(ret < 0)) {
2651                 netdev_err(priv->dev,
2652                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2653                            __func__, dev->irq, ret);
2654                 goto irq_error;
2655         }
2656
2657         /* Request the Wake IRQ in case of another line is used for WoL */
2658         if (priv->wol_irq != dev->irq) {
2659                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2660                                   IRQF_SHARED, dev->name, dev);
2661                 if (unlikely(ret < 0)) {
2662                         netdev_err(priv->dev,
2663                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2664                                    __func__, priv->wol_irq, ret);
2665                         goto wolirq_error;
2666                 }
2667         }
2668
2669         /* Request the IRQ lines */
2670         if (priv->lpi_irq > 0) {
2671                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2672                                   dev->name, dev);
2673                 if (unlikely(ret < 0)) {
2674                         netdev_err(priv->dev,
2675                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2676                                    __func__, priv->lpi_irq, ret);
2677                         goto lpiirq_error;
2678                 }
2679         }
2680
2681         stmmac_enable_all_queues(priv);
2682         stmmac_start_all_queues(priv);
2683
2684         return 0;
2685
2686 lpiirq_error:
2687         if (priv->wol_irq != dev->irq)
2688                 free_irq(priv->wol_irq, dev);
2689 wolirq_error:
2690         free_irq(dev->irq, dev);
2691 irq_error:
2692         phylink_stop(priv->phylink);
2693
2694         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2695                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2696
2697         stmmac_hw_teardown(dev);
2698 init_error:
2699         free_dma_desc_resources(priv);
2700 dma_desc_error:
2701         phylink_disconnect_phy(priv->phylink);
2702         return ret;
2703 }
2704
2705 /**
2706  *  stmmac_release - close entry point of the driver
2707  *  @dev : device pointer.
2708  *  Description:
2709  *  This is the stop entry point of the driver.
2710  */
2711 static int stmmac_release(struct net_device *dev)
2712 {
2713         struct stmmac_priv *priv = netdev_priv(dev);
2714         u32 chan;
2715
2716         if (priv->eee_enabled)
2717                 del_timer_sync(&priv->eee_ctrl_timer);
2718
2719         /* Stop and disconnect the PHY */
2720         phylink_stop(priv->phylink);
2721         phylink_disconnect_phy(priv->phylink);
2722
2723         stmmac_stop_all_queues(priv);
2724
2725         stmmac_disable_all_queues(priv);
2726
2727         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2728                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2729
2730         /* Free the IRQ lines */
2731         free_irq(dev->irq, dev);
2732         if (priv->wol_irq != dev->irq)
2733                 free_irq(priv->wol_irq, dev);
2734         if (priv->lpi_irq > 0)
2735                 free_irq(priv->lpi_irq, dev);
2736
2737         /* Stop TX/RX DMA and clear the descriptors */
2738         stmmac_stop_all_dma(priv);
2739
2740         /* Release and free the Rx/Tx resources */
2741         free_dma_desc_resources(priv);
2742
2743         /* Disable the MAC Rx/Tx */
2744         stmmac_mac_set(priv, priv->ioaddr, false);
2745
2746         netif_carrier_off(dev);
2747
2748         stmmac_release_ptp(priv);
2749
2750         return 0;
2751 }
2752
2753 /**
2754  *  stmmac_tso_allocator - close entry point of the driver
2755  *  @priv: driver private structure
2756  *  @des: buffer start address
2757  *  @total_len: total length to fill in descriptors
2758  *  @last_segmant: condition for the last descriptor
2759  *  @queue: TX queue index
2760  *  Description:
2761  *  This function fills descriptor and request new descriptors according to
2762  *  buffer length to fill
2763  */
2764 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
2765                                  int total_len, bool last_segment, u32 queue)
2766 {
2767         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2768         struct dma_desc *desc;
2769         u32 buff_size;
2770         int tmp_len;
2771
2772         tmp_len = total_len;
2773
2774         while (tmp_len > 0) {
2775                 dma_addr_t curr_addr;
2776
2777                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2778                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2779                 desc = tx_q->dma_tx + tx_q->cur_tx;
2780
2781                 curr_addr = des + (total_len - tmp_len);
2782                 if (priv->dma_cap.addr64 <= 32)
2783                         desc->des0 = cpu_to_le32(curr_addr);
2784                 else
2785                         stmmac_set_desc_addr(priv, desc, curr_addr);
2786
2787                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2788                             TSO_MAX_BUFF_SIZE : tmp_len;
2789
2790                 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2791                                 0, 1,
2792                                 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2793                                 0, 0);
2794
2795                 tmp_len -= TSO_MAX_BUFF_SIZE;
2796         }
2797 }
2798
2799 /**
2800  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2801  *  @skb : the socket buffer
2802  *  @dev : device pointer
2803  *  Description: this is the transmit function that is called on TSO frames
2804  *  (support available on GMAC4 and newer chips).
2805  *  Diagram below show the ring programming in case of TSO frames:
2806  *
2807  *  First Descriptor
2808  *   --------
2809  *   | DES0 |---> buffer1 = L2/L3/L4 header
2810  *   | DES1 |---> TCP Payload (can continue on next descr...)
2811  *   | DES2 |---> buffer 1 and 2 len
2812  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2813  *   --------
2814  *      |
2815  *     ...
2816  *      |
2817  *   --------
2818  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
2819  *   | DES1 | --|
2820  *   | DES2 | --> buffer 1 and 2 len
2821  *   | DES3 |
2822  *   --------
2823  *
2824  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2825  */
2826 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2827 {
2828         struct dma_desc *desc, *first, *mss_desc = NULL;
2829         struct stmmac_priv *priv = netdev_priv(dev);
2830         int nfrags = skb_shinfo(skb)->nr_frags;
2831         u32 queue = skb_get_queue_mapping(skb);
2832         unsigned int first_entry;
2833         struct stmmac_tx_queue *tx_q;
2834         int tmp_pay_len = 0;
2835         u32 pay_len, mss;
2836         u8 proto_hdr_len;
2837         dma_addr_t des;
2838         int i;
2839
2840         tx_q = &priv->tx_queue[queue];
2841
2842         /* Compute header lengths */
2843         proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2844
2845         /* Desc availability based on threshold should be enough safe */
2846         if (unlikely(stmmac_tx_avail(priv, queue) <
2847                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2848                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2849                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2850                                                                 queue));
2851                         /* This is a hard error, log it. */
2852                         netdev_err(priv->dev,
2853                                    "%s: Tx Ring full when queue awake\n",
2854                                    __func__);
2855                 }
2856                 return NETDEV_TX_BUSY;
2857         }
2858
2859         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2860
2861         mss = skb_shinfo(skb)->gso_size;
2862
2863         /* set new MSS value if needed */
2864         if (mss != tx_q->mss) {
2865                 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2866                 stmmac_set_mss(priv, mss_desc, mss);
2867                 tx_q->mss = mss;
2868                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2869                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2870         }
2871
2872         if (netif_msg_tx_queued(priv)) {
2873                 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2874                         __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2875                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2876                         skb->data_len);
2877         }
2878
2879         first_entry = tx_q->cur_tx;
2880         WARN_ON(tx_q->tx_skbuff[first_entry]);
2881
2882         desc = tx_q->dma_tx + first_entry;
2883         first = desc;
2884
2885         /* first descriptor: fill Headers on Buf1 */
2886         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2887                              DMA_TO_DEVICE);
2888         if (dma_mapping_error(priv->device, des))
2889                 goto dma_map_err;
2890
2891         tx_q->tx_skbuff_dma[first_entry].buf = des;
2892         tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2893
2894         if (priv->dma_cap.addr64 <= 32) {
2895                 first->des0 = cpu_to_le32(des);
2896
2897                 /* Fill start of payload in buff2 of first descriptor */
2898                 if (pay_len)
2899                         first->des1 = cpu_to_le32(des + proto_hdr_len);
2900
2901                 /* If needed take extra descriptors to fill the remaining payload */
2902                 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2903         } else {
2904                 stmmac_set_desc_addr(priv, first, des);
2905                 tmp_pay_len = pay_len;
2906         }
2907
2908         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2909
2910         /* Prepare fragments */
2911         for (i = 0; i < nfrags; i++) {
2912                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2913
2914                 des = skb_frag_dma_map(priv->device, frag, 0,
2915                                        skb_frag_size(frag),
2916                                        DMA_TO_DEVICE);
2917                 if (dma_mapping_error(priv->device, des))
2918                         goto dma_map_err;
2919
2920                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2921                                      (i == nfrags - 1), queue);
2922
2923                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2924                 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2925                 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2926         }
2927
2928         tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2929
2930         /* Only the last descriptor gets to point to the skb. */
2931         tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2932
2933         /* We've used all descriptors we need for this skb, however,
2934          * advance cur_tx so that it references a fresh descriptor.
2935          * ndo_start_xmit will fill this descriptor the next time it's
2936          * called and stmmac_tx_clean may clean up to this descriptor.
2937          */
2938         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2939
2940         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2941                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2942                           __func__);
2943                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2944         }
2945
2946         dev->stats.tx_bytes += skb->len;
2947         priv->xstats.tx_tso_frames++;
2948         priv->xstats.tx_tso_nfrags += nfrags;
2949
2950         /* Manage tx mitigation */
2951         tx_q->tx_count_frames += nfrags + 1;
2952         if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
2953             !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
2954             (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2955             priv->hwts_tx_en)) {
2956                 stmmac_tx_timer_arm(priv, queue);
2957         } else {
2958                 tx_q->tx_count_frames = 0;
2959                 stmmac_set_tx_ic(priv, desc);
2960                 priv->xstats.tx_set_ic_bit++;
2961         }
2962
2963         skb_tx_timestamp(skb);
2964
2965         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2966                      priv->hwts_tx_en)) {
2967                 /* declare that device is doing timestamping */
2968                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2969                 stmmac_enable_tx_timestamp(priv, first);
2970         }
2971
2972         /* Complete the first descriptor before granting the DMA */
2973         stmmac_prepare_tso_tx_desc(priv, first, 1,
2974                         proto_hdr_len,
2975                         pay_len,
2976                         1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2977                         tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2978
2979         /* If context desc is used to change MSS */
2980         if (mss_desc) {
2981                 /* Make sure that first descriptor has been completely
2982                  * written, including its own bit. This is because MSS is
2983                  * actually before first descriptor, so we need to make
2984                  * sure that MSS's own bit is the last thing written.
2985                  */
2986                 dma_wmb();
2987                 stmmac_set_tx_owner(priv, mss_desc);
2988         }
2989
2990         /* The own bit must be the latest setting done when prepare the
2991          * descriptor and then barrier is needed to make sure that
2992          * all is coherent before granting the DMA engine.
2993          */
2994         wmb();
2995
2996         if (netif_msg_pktdata(priv)) {
2997                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
2998                         __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
2999                         tx_q->cur_tx, first, nfrags);
3000
3001                 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
3002
3003                 pr_info(">>> frame to be transmitted: ");
3004                 print_pkt(skb->data, skb_headlen(skb));
3005         }
3006
3007         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3008
3009         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3010         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3011
3012         return NETDEV_TX_OK;
3013
3014 dma_map_err:
3015         dev_err(priv->device, "Tx dma map failed\n");
3016         dev_kfree_skb(skb);
3017         priv->dev->stats.tx_dropped++;
3018         return NETDEV_TX_OK;
3019 }
3020
3021 /**
3022  *  stmmac_xmit - Tx entry point of the driver
3023  *  @skb : the socket buffer
3024  *  @dev : device pointer
3025  *  Description : this is the tx entry point of the driver.
3026  *  It programs the chain or the ring and supports oversized frames
3027  *  and SG feature.
3028  */
3029 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
3030 {
3031         struct stmmac_priv *priv = netdev_priv(dev);
3032         unsigned int nopaged_len = skb_headlen(skb);
3033         int i, csum_insertion = 0, is_jumbo = 0;
3034         u32 queue = skb_get_queue_mapping(skb);
3035         int nfrags = skb_shinfo(skb)->nr_frags;
3036         struct dma_desc *desc, *first;
3037         struct stmmac_tx_queue *tx_q;
3038         unsigned int first_entry;
3039         unsigned int enh_desc;
3040         dma_addr_t des;
3041         int entry;
3042
3043         tx_q = &priv->tx_queue[queue];
3044
3045         if (priv->tx_path_in_lpi_mode)
3046                 stmmac_disable_eee_mode(priv);
3047
3048         /* Manage oversized TCP frames for GMAC4 device */
3049         if (skb_is_gso(skb) && priv->tso) {
3050                 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
3051                         return stmmac_tso_xmit(skb, dev);
3052         }
3053
3054         if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3055                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3056                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3057                                                                 queue));
3058                         /* This is a hard error, log it. */
3059                         netdev_err(priv->dev,
3060                                    "%s: Tx Ring full when queue awake\n",
3061                                    __func__);
3062                 }
3063                 return NETDEV_TX_BUSY;
3064         }
3065
3066         entry = tx_q->cur_tx;
3067         first_entry = entry;
3068         WARN_ON(tx_q->tx_skbuff[first_entry]);
3069
3070         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3071
3072         if (likely(priv->extend_desc))
3073                 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3074         else
3075                 desc = tx_q->dma_tx + entry;
3076
3077         first = desc;
3078
3079         enh_desc = priv->plat->enh_desc;
3080         /* To program the descriptors according to the size of the frame */
3081         if (enh_desc)
3082                 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3083
3084         if (unlikely(is_jumbo)) {
3085                 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3086                 if (unlikely(entry < 0) && (entry != -EINVAL))
3087                         goto dma_map_err;
3088         }
3089
3090         for (i = 0; i < nfrags; i++) {
3091                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3092                 int len = skb_frag_size(frag);
3093                 bool last_segment = (i == (nfrags - 1));
3094
3095                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3096                 WARN_ON(tx_q->tx_skbuff[entry]);
3097
3098                 if (likely(priv->extend_desc))
3099                         desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3100                 else
3101                         desc = tx_q->dma_tx + entry;
3102
3103                 des = skb_frag_dma_map(priv->device, frag, 0, len,
3104                                        DMA_TO_DEVICE);
3105                 if (dma_mapping_error(priv->device, des))
3106                         goto dma_map_err; /* should reuse desc w/o issues */
3107
3108                 tx_q->tx_skbuff_dma[entry].buf = des;
3109
3110                 stmmac_set_desc_addr(priv, desc, des);
3111
3112                 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3113                 tx_q->tx_skbuff_dma[entry].len = len;
3114                 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3115
3116                 /* Prepare the descriptor and set the own bit too */
3117                 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3118                                 priv->mode, 1, last_segment, skb->len);
3119         }
3120
3121         /* Only the last descriptor gets to point to the skb. */
3122         tx_q->tx_skbuff[entry] = skb;
3123
3124         /* We've used all descriptors we need for this skb, however,
3125          * advance cur_tx so that it references a fresh descriptor.
3126          * ndo_start_xmit will fill this descriptor the next time it's
3127          * called and stmmac_tx_clean may clean up to this descriptor.
3128          */
3129         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3130         tx_q->cur_tx = entry;
3131
3132         if (netif_msg_pktdata(priv)) {
3133                 void *tx_head;
3134
3135                 netdev_dbg(priv->dev,
3136                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3137                            __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3138                            entry, first, nfrags);
3139
3140                 if (priv->extend_desc)
3141                         tx_head = (void *)tx_q->dma_etx;
3142                 else
3143                         tx_head = (void *)tx_q->dma_tx;
3144
3145                 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3146
3147                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3148                 print_pkt(skb->data, skb->len);
3149         }
3150
3151         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3152                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3153                           __func__);
3154                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3155         }
3156
3157         dev->stats.tx_bytes += skb->len;
3158
3159         /* According to the coalesce parameter the IC bit for the latest
3160          * segment is reset and the timer re-started to clean the tx status.
3161          * This approach takes care about the fragments: desc is the first
3162          * element in case of no SG.
3163          */
3164         tx_q->tx_count_frames += nfrags + 1;
3165         if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
3166             !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
3167             (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3168             priv->hwts_tx_en)) {
3169                 stmmac_tx_timer_arm(priv, queue);
3170         } else {
3171                 tx_q->tx_count_frames = 0;
3172                 stmmac_set_tx_ic(priv, desc);
3173                 priv->xstats.tx_set_ic_bit++;
3174         }
3175
3176         skb_tx_timestamp(skb);
3177
3178         /* Ready to fill the first descriptor and set the OWN bit w/o any
3179          * problems because all the descriptors are actually ready to be
3180          * passed to the DMA engine.
3181          */
3182         if (likely(!is_jumbo)) {
3183                 bool last_segment = (nfrags == 0);
3184
3185                 des = dma_map_single(priv->device, skb->data,
3186                                      nopaged_len, DMA_TO_DEVICE);
3187                 if (dma_mapping_error(priv->device, des))
3188                         goto dma_map_err;
3189
3190                 tx_q->tx_skbuff_dma[first_entry].buf = des;
3191
3192                 stmmac_set_desc_addr(priv, first, des);
3193
3194                 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3195                 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3196
3197                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3198                              priv->hwts_tx_en)) {
3199                         /* declare that device is doing timestamping */
3200                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3201                         stmmac_enable_tx_timestamp(priv, first);
3202                 }
3203
3204                 /* Prepare the first descriptor setting the OWN bit too */
3205                 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3206                                 csum_insertion, priv->mode, 1, last_segment,
3207                                 skb->len);
3208         } else {
3209                 stmmac_set_tx_owner(priv, first);
3210         }
3211
3212         /* The own bit must be the latest setting done when prepare the
3213          * descriptor and then barrier is needed to make sure that
3214          * all is coherent before granting the DMA engine.
3215          */
3216         wmb();
3217
3218         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3219
3220         stmmac_enable_dma_transmission(priv, priv->ioaddr);
3221
3222         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3223         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3224
3225         return NETDEV_TX_OK;
3226
3227 dma_map_err:
3228         netdev_err(priv->dev, "Tx DMA map failed\n");
3229         dev_kfree_skb(skb);
3230         priv->dev->stats.tx_dropped++;
3231         return NETDEV_TX_OK;
3232 }
3233
3234 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3235 {
3236         struct vlan_ethhdr *veth;
3237         __be16 vlan_proto;
3238         u16 vlanid;
3239
3240         veth = (struct vlan_ethhdr *)skb->data;
3241         vlan_proto = veth->h_vlan_proto;
3242
3243         if ((vlan_proto == htons(ETH_P_8021Q) &&
3244              dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3245             (vlan_proto == htons(ETH_P_8021AD) &&
3246              dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3247                 /* pop the vlan tag */
3248                 vlanid = ntohs(veth->h_vlan_TCI);
3249                 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3250                 skb_pull(skb, VLAN_HLEN);
3251                 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3252         }
3253 }
3254
3255
3256 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3257 {
3258         if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3259                 return 0;
3260
3261         return 1;
3262 }
3263
3264 /**
3265  * stmmac_rx_refill - refill used skb preallocated buffers
3266  * @priv: driver private structure
3267  * @queue: RX queue index
3268  * Description : this is to reallocate the skb for the reception process
3269  * that is based on zero-copy.
3270  */
3271 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3272 {
3273         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3274         int len, dirty = stmmac_rx_dirty(priv, queue);
3275         unsigned int entry = rx_q->dirty_rx;
3276
3277         len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
3278
3279         while (dirty-- > 0) {
3280                 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
3281                 struct dma_desc *p;
3282                 bool use_rx_wd;
3283
3284                 if (priv->extend_desc)
3285                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3286                 else
3287                         p = rx_q->dma_rx + entry;
3288
3289                 if (!buf->page) {
3290                         buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
3291                         if (!buf->page)
3292                                 break;
3293                 }
3294
3295                 buf->addr = page_pool_get_dma_addr(buf->page);
3296
3297                 /* Sync whole allocation to device. This will invalidate old
3298                  * data.
3299                  */
3300                 dma_sync_single_for_device(priv->device, buf->addr, len,
3301                                            DMA_FROM_DEVICE);
3302
3303                 stmmac_set_desc_addr(priv, p, buf->addr);
3304                 stmmac_refill_desc3(priv, rx_q, p);
3305
3306                 rx_q->rx_count_frames++;
3307                 rx_q->rx_count_frames %= priv->rx_coal_frames;
3308                 use_rx_wd = priv->use_riwt && rx_q->rx_count_frames;
3309
3310                 dma_wmb();
3311                 stmmac_set_rx_owner(priv, p, use_rx_wd);
3312
3313                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3314         }
3315         rx_q->dirty_rx = entry;
3316         rx_q->rx_tail_addr = rx_q->dma_rx_phy +
3317                             (rx_q->dirty_rx * sizeof(struct dma_desc));
3318         stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3319 }
3320
3321 /**
3322  * stmmac_rx - manage the receive process
3323  * @priv: driver private structure
3324  * @limit: napi bugget
3325  * @queue: RX queue index.
3326  * Description :  this the function called by the napi poll method.
3327  * It gets all the frames inside the ring.
3328  */
3329 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3330 {
3331         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3332         struct stmmac_channel *ch = &priv->channel[queue];
3333         unsigned int next_entry = rx_q->cur_rx;
3334         int coe = priv->hw->rx_csum;
3335         unsigned int count = 0;
3336
3337         if (netif_msg_rx_status(priv)) {
3338                 void *rx_head;
3339
3340                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3341                 if (priv->extend_desc)
3342                         rx_head = (void *)rx_q->dma_erx;
3343                 else
3344                         rx_head = (void *)rx_q->dma_rx;
3345
3346                 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3347         }
3348         while (count < limit) {
3349                 struct stmmac_rx_buffer *buf;
3350                 struct dma_desc *np, *p;
3351                 int entry, status;
3352
3353                 entry = next_entry;
3354                 buf = &rx_q->buf_pool[entry];
3355
3356                 if (priv->extend_desc)
3357                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3358                 else
3359                         p = rx_q->dma_rx + entry;
3360
3361                 /* read the status of the incoming frame */
3362                 status = stmmac_rx_status(priv, &priv->dev->stats,
3363                                 &priv->xstats, p);
3364                 /* check if managed by the DMA otherwise go ahead */
3365                 if (unlikely(status & dma_own))
3366                         break;
3367
3368                 count++;
3369
3370                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3371                 next_entry = rx_q->cur_rx;
3372
3373                 if (priv->extend_desc)
3374                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3375                 else
3376                         np = rx_q->dma_rx + next_entry;
3377
3378                 prefetch(np);
3379
3380                 if (priv->extend_desc)
3381                         stmmac_rx_extended_status(priv, &priv->dev->stats,
3382                                         &priv->xstats, rx_q->dma_erx + entry);
3383                 if (unlikely(status == discard_frame)) {
3384                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
3385                         priv->dev->stats.rx_errors++;
3386                         buf->page = NULL;
3387                 } else {
3388                         struct sk_buff *skb;
3389                         int frame_len;
3390                         unsigned int des;
3391
3392                         stmmac_get_desc_addr(priv, p, &des);
3393                         frame_len = stmmac_get_rx_frame_len(priv, p, coe);
3394
3395                         /*  If frame length is greater than skb buffer size
3396                          *  (preallocated during init) then the packet is
3397                          *  ignored
3398                          */
3399                         if (frame_len > priv->dma_buf_sz) {
3400                                 if (net_ratelimit())
3401                                         netdev_err(priv->dev,
3402                                                    "len %d larger than size (%d)\n",
3403                                                    frame_len, priv->dma_buf_sz);
3404                                 priv->dev->stats.rx_length_errors++;
3405                                 continue;
3406                         }
3407
3408                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3409                          * Type frames (LLC/LLC-SNAP)
3410                          *
3411                          * llc_snap is never checked in GMAC >= 4, so this ACS
3412                          * feature is always disabled and packets need to be
3413                          * stripped manually.
3414                          */
3415                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3416                             unlikely(status != llc_snap))
3417                                 frame_len -= ETH_FCS_LEN;
3418
3419                         if (netif_msg_rx_status(priv)) {
3420                                 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3421                                            p, entry, des);
3422                                 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3423                                            frame_len, status);
3424                         }
3425
3426                         skb = netdev_alloc_skb_ip_align(priv->dev, frame_len);
3427                         if (unlikely(!skb)) {
3428                                 priv->dev->stats.rx_dropped++;
3429                                 continue;
3430                         }
3431
3432                         dma_sync_single_for_cpu(priv->device, buf->addr,
3433                                                 frame_len, DMA_FROM_DEVICE);
3434                         skb_copy_to_linear_data(skb, page_address(buf->page),
3435                                                 frame_len);
3436                         skb_put(skb, frame_len);
3437
3438                         if (netif_msg_pktdata(priv)) {
3439                                 netdev_dbg(priv->dev, "frame received (%dbytes)",
3440                                            frame_len);
3441                                 print_pkt(skb->data, frame_len);
3442                         }
3443
3444                         stmmac_get_rx_hwtstamp(priv, p, np, skb);
3445
3446                         stmmac_rx_vlan(priv->dev, skb);
3447
3448                         skb->protocol = eth_type_trans(skb, priv->dev);
3449
3450                         if (unlikely(!coe))
3451                                 skb_checksum_none_assert(skb);
3452                         else
3453                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3454
3455                         napi_gro_receive(&ch->rx_napi, skb);
3456
3457                         /* Data payload copied into SKB, page ready for recycle */
3458                         page_pool_recycle_direct(rx_q->page_pool, buf->page);
3459                         buf->page = NULL;
3460
3461                         priv->dev->stats.rx_packets++;
3462                         priv->dev->stats.rx_bytes += frame_len;
3463                 }
3464         }
3465
3466         stmmac_rx_refill(priv, queue);
3467
3468         priv->xstats.rx_pkt_n += count;
3469
3470         return count;
3471 }
3472
3473 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3474 {
3475         struct stmmac_channel *ch =
3476                 container_of(napi, struct stmmac_channel, rx_napi);
3477         struct stmmac_priv *priv = ch->priv_data;
3478         u32 chan = ch->index;
3479         int work_done;
3480
3481         priv->xstats.napi_poll++;
3482
3483         work_done = stmmac_rx(priv, budget, chan);
3484         if (work_done < budget && napi_complete_done(napi, work_done))
3485                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3486         return work_done;
3487 }
3488
3489 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3490 {
3491         struct stmmac_channel *ch =
3492                 container_of(napi, struct stmmac_channel, tx_napi);
3493         struct stmmac_priv *priv = ch->priv_data;
3494         struct stmmac_tx_queue *tx_q;
3495         u32 chan = ch->index;
3496         int work_done;
3497
3498         priv->xstats.napi_poll++;
3499
3500         work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3501         work_done = min(work_done, budget);
3502
3503         if (work_done < budget)
3504                 napi_complete_done(napi, work_done);
3505
3506         /* Force transmission restart */
3507         tx_q = &priv->tx_queue[chan];
3508         if (tx_q->cur_tx != tx_q->dirty_tx) {
3509                 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3510                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3511                                        chan);
3512         }
3513
3514         return work_done;
3515 }
3516
3517 /**
3518  *  stmmac_tx_timeout
3519  *  @dev : Pointer to net device structure
3520  *  Description: this function is called when a packet transmission fails to
3521  *   complete within a reasonable time. The driver will mark the error in the
3522  *   netdev structure and arrange for the device to be reset to a sane state
3523  *   in order to transmit a new packet.
3524  */
3525 static void stmmac_tx_timeout(struct net_device *dev)
3526 {
3527         struct stmmac_priv *priv = netdev_priv(dev);
3528
3529         stmmac_global_err(priv);
3530 }
3531
3532 /**
3533  *  stmmac_set_rx_mode - entry point for multicast addressing
3534  *  @dev : pointer to the device structure
3535  *  Description:
3536  *  This function is a driver entry point which gets called by the kernel
3537  *  whenever multicast addresses must be enabled/disabled.
3538  *  Return value:
3539  *  void.
3540  */
3541 static void stmmac_set_rx_mode(struct net_device *dev)
3542 {
3543         struct stmmac_priv *priv = netdev_priv(dev);
3544
3545         stmmac_set_filter(priv, priv->hw, dev);
3546 }
3547
3548 /**
3549  *  stmmac_change_mtu - entry point to change MTU size for the device.
3550  *  @dev : device pointer.
3551  *  @new_mtu : the new MTU size for the device.
3552  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
3553  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
3554  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
3555  *  Return value:
3556  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3557  *  file on failure.
3558  */
3559 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3560 {
3561         struct stmmac_priv *priv = netdev_priv(dev);
3562
3563         if (netif_running(dev)) {
3564                 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3565                 return -EBUSY;
3566         }
3567
3568         dev->mtu = new_mtu;
3569
3570         netdev_update_features(dev);
3571
3572         return 0;
3573 }
3574
3575 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3576                                              netdev_features_t features)
3577 {
3578         struct stmmac_priv *priv = netdev_priv(dev);
3579
3580         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3581                 features &= ~NETIF_F_RXCSUM;
3582
3583         if (!priv->plat->tx_coe)
3584                 features &= ~NETIF_F_CSUM_MASK;
3585
3586         /* Some GMAC devices have a bugged Jumbo frame support that
3587          * needs to have the Tx COE disabled for oversized frames
3588          * (due to limited buffer sizes). In this case we disable
3589          * the TX csum insertion in the TDES and not use SF.
3590          */
3591         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3592                 features &= ~NETIF_F_CSUM_MASK;
3593
3594         /* Disable tso if asked by ethtool */
3595         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3596                 if (features & NETIF_F_TSO)
3597                         priv->tso = true;
3598                 else
3599                         priv->tso = false;
3600         }
3601
3602         return features;
3603 }
3604
3605 static int stmmac_set_features(struct net_device *netdev,
3606                                netdev_features_t features)
3607 {
3608         struct stmmac_priv *priv = netdev_priv(netdev);
3609
3610         /* Keep the COE Type in case of csum is supporting */
3611         if (features & NETIF_F_RXCSUM)
3612                 priv->hw->rx_csum = priv->plat->rx_coe;
3613         else
3614                 priv->hw->rx_csum = 0;
3615         /* No check needed because rx_coe has been set before and it will be
3616          * fixed in case of issue.
3617          */
3618         stmmac_rx_ipc(priv, priv->hw);
3619
3620         return 0;
3621 }
3622
3623 /**
3624  *  stmmac_interrupt - main ISR
3625  *  @irq: interrupt number.
3626  *  @dev_id: to pass the net device pointer.
3627  *  Description: this is the main driver interrupt service routine.
3628  *  It can call:
3629  *  o DMA service routine (to manage incoming frame reception and transmission
3630  *    status)
3631  *  o Core interrupts to manage: remote wake-up, management counter, LPI
3632  *    interrupts.
3633  */
3634 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3635 {
3636         struct net_device *dev = (struct net_device *)dev_id;
3637         struct stmmac_priv *priv = netdev_priv(dev);
3638         u32 rx_cnt = priv->plat->rx_queues_to_use;
3639         u32 tx_cnt = priv->plat->tx_queues_to_use;
3640         u32 queues_count;
3641         u32 queue;
3642         bool xmac;
3643
3644         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3645         queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3646
3647         if (priv->irq_wake)
3648                 pm_wakeup_event(priv->device, 0);
3649
3650         if (unlikely(!dev)) {
3651                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3652                 return IRQ_NONE;
3653         }
3654
3655         /* Check if adapter is up */
3656         if (test_bit(STMMAC_DOWN, &priv->state))
3657                 return IRQ_HANDLED;
3658         /* Check if a fatal error happened */
3659         if (stmmac_safety_feat_interrupt(priv))
3660                 return IRQ_HANDLED;
3661
3662         /* To handle GMAC own interrupts */
3663         if ((priv->plat->has_gmac) || xmac) {
3664                 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3665                 int mtl_status;
3666
3667                 if (unlikely(status)) {
3668                         /* For LPI we need to save the tx status */
3669                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3670                                 priv->tx_path_in_lpi_mode = true;
3671                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3672                                 priv->tx_path_in_lpi_mode = false;
3673                 }
3674
3675                 for (queue = 0; queue < queues_count; queue++) {
3676                         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3677
3678                         mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3679                                                                 queue);
3680                         if (mtl_status != -EINVAL)
3681                                 status |= mtl_status;
3682
3683                         if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3684                                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3685                                                        rx_q->rx_tail_addr,
3686                                                        queue);
3687                 }
3688
3689                 /* PCS link status */
3690                 if (priv->hw->pcs) {
3691                         if (priv->xstats.pcs_link)
3692                                 netif_carrier_on(dev);
3693                         else
3694                                 netif_carrier_off(dev);
3695                 }
3696         }
3697
3698         /* To handle DMA interrupts */
3699         stmmac_dma_interrupt(priv);
3700
3701         return IRQ_HANDLED;
3702 }
3703
3704 #ifdef CONFIG_NET_POLL_CONTROLLER
3705 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3706  * to allow network I/O with interrupts disabled.
3707  */
3708 static void stmmac_poll_controller(struct net_device *dev)
3709 {
3710         disable_irq(dev->irq);
3711         stmmac_interrupt(dev->irq, dev);
3712         enable_irq(dev->irq);
3713 }
3714 #endif
3715
3716 /**
3717  *  stmmac_ioctl - Entry point for the Ioctl
3718  *  @dev: Device pointer.
3719  *  @rq: An IOCTL specefic structure, that can contain a pointer to
3720  *  a proprietary structure used to pass information to the driver.
3721  *  @cmd: IOCTL command
3722  *  Description:
3723  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3724  */
3725 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3726 {
3727         struct stmmac_priv *priv = netdev_priv (dev);
3728         int ret = -EOPNOTSUPP;
3729
3730         if (!netif_running(dev))
3731                 return -EINVAL;
3732
3733         switch (cmd) {
3734         case SIOCGMIIPHY:
3735         case SIOCGMIIREG:
3736         case SIOCSMIIREG:
3737                 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
3738                 break;
3739         case SIOCSHWTSTAMP:
3740                 ret = stmmac_hwtstamp_set(dev, rq);
3741                 break;
3742         case SIOCGHWTSTAMP:
3743                 ret = stmmac_hwtstamp_get(dev, rq);
3744                 break;
3745         default:
3746                 break;
3747         }
3748
3749         return ret;
3750 }
3751
3752 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3753                                     void *cb_priv)
3754 {
3755         struct stmmac_priv *priv = cb_priv;
3756         int ret = -EOPNOTSUPP;
3757
3758         stmmac_disable_all_queues(priv);
3759
3760         switch (type) {
3761         case TC_SETUP_CLSU32:
3762                 if (tc_cls_can_offload_and_chain0(priv->dev, type_data))
3763                         ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3764                 break;
3765         default:
3766                 break;
3767         }
3768
3769         stmmac_enable_all_queues(priv);
3770         return ret;
3771 }
3772
3773 static LIST_HEAD(stmmac_block_cb_list);
3774
3775 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3776                            void *type_data)
3777 {
3778         struct stmmac_priv *priv = netdev_priv(ndev);
3779
3780         switch (type) {
3781         case TC_SETUP_BLOCK:
3782                 return flow_block_cb_setup_simple(type_data,
3783                                                   &stmmac_block_cb_list,
3784                                                   stmmac_setup_tc_block_cb,
3785                                                   priv, priv, true);
3786         case TC_SETUP_QDISC_CBS:
3787                 return stmmac_tc_setup_cbs(priv, priv, type_data);
3788         default:
3789                 return -EOPNOTSUPP;
3790         }
3791 }
3792
3793 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
3794                                struct net_device *sb_dev)
3795 {
3796         if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3797                 /*
3798                  * There is no way to determine the number of TSO
3799                  * capable Queues. Let's use always the Queue 0
3800                  * because if TSO is supported then at least this
3801                  * one will be capable.
3802                  */
3803                 return 0;
3804         }
3805
3806         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
3807 }
3808
3809 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
3810 {
3811         struct stmmac_priv *priv = netdev_priv(ndev);
3812         int ret = 0;
3813
3814         ret = eth_mac_addr(ndev, addr);
3815         if (ret)
3816                 return ret;
3817
3818         stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
3819
3820         return ret;
3821 }
3822
3823 #ifdef CONFIG_DEBUG_FS
3824 static struct dentry *stmmac_fs_dir;
3825
3826 static void sysfs_display_ring(void *head, int size, int extend_desc,
3827                                struct seq_file *seq)
3828 {
3829         int i;
3830         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3831         struct dma_desc *p = (struct dma_desc *)head;
3832
3833         for (i = 0; i < size; i++) {
3834                 if (extend_desc) {
3835                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3836                                    i, (unsigned int)virt_to_phys(ep),
3837                                    le32_to_cpu(ep->basic.des0),
3838                                    le32_to_cpu(ep->basic.des1),
3839                                    le32_to_cpu(ep->basic.des2),
3840                                    le32_to_cpu(ep->basic.des3));
3841                         ep++;
3842                 } else {
3843                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3844                                    i, (unsigned int)virt_to_phys(p),
3845                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3846                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3847                         p++;
3848                 }
3849                 seq_printf(seq, "\n");
3850         }
3851 }
3852
3853 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
3854 {
3855         struct net_device *dev = seq->private;
3856         struct stmmac_priv *priv = netdev_priv(dev);
3857         u32 rx_count = priv->plat->rx_queues_to_use;
3858         u32 tx_count = priv->plat->tx_queues_to_use;
3859         u32 queue;
3860
3861         if ((dev->flags & IFF_UP) == 0)
3862                 return 0;
3863
3864         for (queue = 0; queue < rx_count; queue++) {
3865                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3866
3867                 seq_printf(seq, "RX Queue %d:\n", queue);
3868
3869                 if (priv->extend_desc) {
3870                         seq_printf(seq, "Extended descriptor ring:\n");
3871                         sysfs_display_ring((void *)rx_q->dma_erx,
3872                                            DMA_RX_SIZE, 1, seq);
3873                 } else {
3874                         seq_printf(seq, "Descriptor ring:\n");
3875                         sysfs_display_ring((void *)rx_q->dma_rx,
3876                                            DMA_RX_SIZE, 0, seq);
3877                 }
3878         }
3879
3880         for (queue = 0; queue < tx_count; queue++) {
3881                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3882
3883                 seq_printf(seq, "TX Queue %d:\n", queue);
3884
3885                 if (priv->extend_desc) {
3886                         seq_printf(seq, "Extended descriptor ring:\n");
3887                         sysfs_display_ring((void *)tx_q->dma_etx,
3888                                            DMA_TX_SIZE, 1, seq);
3889                 } else {
3890                         seq_printf(seq, "Descriptor ring:\n");
3891                         sysfs_display_ring((void *)tx_q->dma_tx,
3892                                            DMA_TX_SIZE, 0, seq);
3893                 }
3894         }
3895
3896         return 0;
3897 }
3898 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
3899
3900 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
3901 {
3902         struct net_device *dev = seq->private;
3903         struct stmmac_priv *priv = netdev_priv(dev);
3904
3905         if (!priv->hw_cap_support) {
3906                 seq_printf(seq, "DMA HW features not supported\n");
3907                 return 0;
3908         }
3909
3910         seq_printf(seq, "==============================\n");
3911         seq_printf(seq, "\tDMA HW features\n");
3912         seq_printf(seq, "==============================\n");
3913
3914         seq_printf(seq, "\t10/100 Mbps: %s\n",
3915                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
3916         seq_printf(seq, "\t1000 Mbps: %s\n",
3917                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
3918         seq_printf(seq, "\tHalf duplex: %s\n",
3919                    (priv->dma_cap.half_duplex) ? "Y" : "N");
3920         seq_printf(seq, "\tHash Filter: %s\n",
3921                    (priv->dma_cap.hash_filter) ? "Y" : "N");
3922         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
3923                    (priv->dma_cap.multi_addr) ? "Y" : "N");
3924         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
3925                    (priv->dma_cap.pcs) ? "Y" : "N");
3926         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
3927                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
3928         seq_printf(seq, "\tPMT Remote wake up: %s\n",
3929                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
3930         seq_printf(seq, "\tPMT Magic Frame: %s\n",
3931                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
3932         seq_printf(seq, "\tRMON module: %s\n",
3933                    (priv->dma_cap.rmon) ? "Y" : "N");
3934         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
3935                    (priv->dma_cap.time_stamp) ? "Y" : "N");
3936         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
3937                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
3938         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
3939                    (priv->dma_cap.eee) ? "Y" : "N");
3940         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
3941         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
3942                    (priv->dma_cap.tx_coe) ? "Y" : "N");
3943         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
3944                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
3945                            (priv->dma_cap.rx_coe) ? "Y" : "N");
3946         } else {
3947                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
3948                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
3949                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
3950                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
3951         }
3952         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
3953                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
3954         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
3955                    priv->dma_cap.number_rx_channel);
3956         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
3957                    priv->dma_cap.number_tx_channel);
3958         seq_printf(seq, "\tEnhanced descriptors: %s\n",
3959                    (priv->dma_cap.enh_desc) ? "Y" : "N");
3960
3961         return 0;
3962 }
3963 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
3964
3965 static int stmmac_init_fs(struct net_device *dev)
3966 {
3967         struct stmmac_priv *priv = netdev_priv(dev);
3968
3969         /* Create per netdev entries */
3970         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
3971
3972         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
3973                 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
3974
3975                 return -ENOMEM;
3976         }
3977
3978         /* Entry to report DMA RX/TX rings */
3979         priv->dbgfs_rings_status =
3980                 debugfs_create_file("descriptors_status", 0444,
3981                                     priv->dbgfs_dir, dev,
3982                                     &stmmac_rings_status_fops);
3983
3984         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
3985                 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
3986                 debugfs_remove_recursive(priv->dbgfs_dir);
3987
3988                 return -ENOMEM;
3989         }
3990
3991         /* Entry to report the DMA HW features */
3992         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444,
3993                                                   priv->dbgfs_dir,
3994                                                   dev, &stmmac_dma_cap_fops);
3995
3996         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
3997                 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
3998                 debugfs_remove_recursive(priv->dbgfs_dir);
3999
4000                 return -ENOMEM;
4001         }
4002
4003         return 0;
4004 }
4005
4006 static void stmmac_exit_fs(struct net_device *dev)
4007 {
4008         struct stmmac_priv *priv = netdev_priv(dev);
4009
4010         debugfs_remove_recursive(priv->dbgfs_dir);
4011 }
4012 #endif /* CONFIG_DEBUG_FS */
4013
4014 static const struct net_device_ops stmmac_netdev_ops = {
4015         .ndo_open = stmmac_open,
4016         .ndo_start_xmit = stmmac_xmit,
4017         .ndo_stop = stmmac_release,
4018         .ndo_change_mtu = stmmac_change_mtu,
4019         .ndo_fix_features = stmmac_fix_features,
4020         .ndo_set_features = stmmac_set_features,
4021         .ndo_set_rx_mode = stmmac_set_rx_mode,
4022         .ndo_tx_timeout = stmmac_tx_timeout,
4023         .ndo_do_ioctl = stmmac_ioctl,
4024         .ndo_setup_tc = stmmac_setup_tc,
4025         .ndo_select_queue = stmmac_select_queue,
4026 #ifdef CONFIG_NET_POLL_CONTROLLER
4027         .ndo_poll_controller = stmmac_poll_controller,
4028 #endif
4029         .ndo_set_mac_address = stmmac_set_mac_address,
4030 };
4031
4032 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4033 {
4034         if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4035                 return;
4036         if (test_bit(STMMAC_DOWN, &priv->state))
4037                 return;
4038
4039         netdev_err(priv->dev, "Reset adapter.\n");
4040
4041         rtnl_lock();
4042         netif_trans_update(priv->dev);
4043         while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4044                 usleep_range(1000, 2000);
4045
4046         set_bit(STMMAC_DOWN, &priv->state);
4047         dev_close(priv->dev);
4048         dev_open(priv->dev, NULL);
4049         clear_bit(STMMAC_DOWN, &priv->state);
4050         clear_bit(STMMAC_RESETING, &priv->state);
4051         rtnl_unlock();
4052 }
4053
4054 static void stmmac_service_task(struct work_struct *work)
4055 {
4056         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4057                         service_task);
4058
4059         stmmac_reset_subtask(priv);
4060         clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4061 }
4062
4063 /**
4064  *  stmmac_hw_init - Init the MAC device
4065  *  @priv: driver private structure
4066  *  Description: this function is to configure the MAC device according to
4067  *  some platform parameters or the HW capability register. It prepares the
4068  *  driver to use either ring or chain modes and to setup either enhanced or
4069  *  normal descriptors.
4070  */
4071 static int stmmac_hw_init(struct stmmac_priv *priv)
4072 {
4073         int ret;
4074
4075         /* dwmac-sun8i only work in chain mode */
4076         if (priv->plat->has_sun8i)
4077                 chain_mode = 1;
4078         priv->chain_mode = chain_mode;
4079
4080         /* Initialize HW Interface */
4081         ret = stmmac_hwif_init(priv);
4082         if (ret)
4083                 return ret;
4084
4085         /* Get the HW capability (new GMAC newer than 3.50a) */
4086         priv->hw_cap_support = stmmac_get_hw_features(priv);
4087         if (priv->hw_cap_support) {
4088                 dev_info(priv->device, "DMA HW capability register supported\n");
4089
4090                 /* We can override some gmac/dma configuration fields: e.g.
4091                  * enh_desc, tx_coe (e.g. that are passed through the
4092                  * platform) with the values from the HW capability
4093                  * register (if supported).
4094                  */
4095                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4096                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4097                 priv->hw->pmt = priv->plat->pmt;
4098                 if (priv->dma_cap.hash_tb_sz) {
4099                         priv->hw->multicast_filter_bins =
4100                                         (BIT(priv->dma_cap.hash_tb_sz) << 5);
4101                         priv->hw->mcast_bits_log2 =
4102                                         ilog2(priv->hw->multicast_filter_bins);
4103                 }
4104
4105                 /* TXCOE doesn't work in thresh DMA mode */
4106                 if (priv->plat->force_thresh_dma_mode)
4107                         priv->plat->tx_coe = 0;
4108                 else
4109                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
4110
4111                 /* In case of GMAC4 rx_coe is from HW cap register. */
4112                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4113
4114                 if (priv->dma_cap.rx_coe_type2)
4115                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4116                 else if (priv->dma_cap.rx_coe_type1)
4117                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4118
4119         } else {
4120                 dev_info(priv->device, "No HW DMA feature register supported\n");
4121         }
4122
4123         if (priv->plat->rx_coe) {
4124                 priv->hw->rx_csum = priv->plat->rx_coe;
4125                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4126                 if (priv->synopsys_id < DWMAC_CORE_4_00)
4127                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4128         }
4129         if (priv->plat->tx_coe)
4130                 dev_info(priv->device, "TX Checksum insertion supported\n");
4131
4132         if (priv->plat->pmt) {
4133                 dev_info(priv->device, "Wake-Up On Lan supported\n");
4134                 device_set_wakeup_capable(priv->device, 1);
4135         }
4136
4137         if (priv->dma_cap.tsoen)
4138                 dev_info(priv->device, "TSO supported\n");
4139
4140         /* Run HW quirks, if any */
4141         if (priv->hwif_quirks) {
4142                 ret = priv->hwif_quirks(priv);
4143                 if (ret)
4144                         return ret;
4145         }
4146
4147         /* Rx Watchdog is available in the COREs newer than the 3.40.
4148          * In some case, for example on bugged HW this feature
4149          * has to be disable and this can be done by passing the
4150          * riwt_off field from the platform.
4151          */
4152         if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4153             (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4154                 priv->use_riwt = 1;
4155                 dev_info(priv->device,
4156                          "Enable RX Mitigation via HW Watchdog Timer\n");
4157         }
4158
4159         return 0;
4160 }
4161
4162 /**
4163  * stmmac_dvr_probe
4164  * @device: device pointer
4165  * @plat_dat: platform data pointer
4166  * @res: stmmac resource pointer
4167  * Description: this is the main probe function used to
4168  * call the alloc_etherdev, allocate the priv structure.
4169  * Return:
4170  * returns 0 on success, otherwise errno.
4171  */
4172 int stmmac_dvr_probe(struct device *device,
4173                      struct plat_stmmacenet_data *plat_dat,
4174                      struct stmmac_resources *res)
4175 {
4176         struct net_device *ndev = NULL;
4177         struct stmmac_priv *priv;
4178         u32 queue, maxq;
4179         int ret = 0;
4180
4181         ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4182                                        MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
4183         if (!ndev)
4184                 return -ENOMEM;
4185
4186         SET_NETDEV_DEV(ndev, device);
4187
4188         priv = netdev_priv(ndev);
4189         priv->device = device;
4190         priv->dev = ndev;
4191
4192         stmmac_set_ethtool_ops(ndev);
4193         priv->pause = pause;
4194         priv->plat = plat_dat;
4195         priv->ioaddr = res->addr;
4196         priv->dev->base_addr = (unsigned long)res->addr;
4197
4198         priv->dev->irq = res->irq;
4199         priv->wol_irq = res->wol_irq;
4200         priv->lpi_irq = res->lpi_irq;
4201
4202         if (!IS_ERR_OR_NULL(res->mac))
4203                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4204
4205         dev_set_drvdata(device, priv->dev);
4206
4207         /* Verify driver arguments */
4208         stmmac_verify_args();
4209
4210         /* Allocate workqueue */
4211         priv->wq = create_singlethread_workqueue("stmmac_wq");
4212         if (!priv->wq) {
4213                 dev_err(priv->device, "failed to create workqueue\n");
4214                 return -ENOMEM;
4215         }
4216
4217         INIT_WORK(&priv->service_task, stmmac_service_task);
4218
4219         /* Override with kernel parameters if supplied XXX CRS XXX
4220          * this needs to have multiple instances
4221          */
4222         if ((phyaddr >= 0) && (phyaddr <= 31))
4223                 priv->plat->phy_addr = phyaddr;
4224
4225         if (priv->plat->stmmac_rst) {
4226                 ret = reset_control_assert(priv->plat->stmmac_rst);
4227                 reset_control_deassert(priv->plat->stmmac_rst);
4228                 /* Some reset controllers have only reset callback instead of
4229                  * assert + deassert callbacks pair.
4230                  */
4231                 if (ret == -ENOTSUPP)
4232                         reset_control_reset(priv->plat->stmmac_rst);
4233         }
4234
4235         /* Init MAC and get the capabilities */
4236         ret = stmmac_hw_init(priv);
4237         if (ret)
4238                 goto error_hw_init;
4239
4240         stmmac_check_ether_addr(priv);
4241
4242         /* Configure real RX and TX queues */
4243         netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4244         netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4245
4246         ndev->netdev_ops = &stmmac_netdev_ops;
4247
4248         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4249                             NETIF_F_RXCSUM;
4250
4251         ret = stmmac_tc_init(priv, priv);
4252         if (!ret) {
4253                 ndev->hw_features |= NETIF_F_HW_TC;
4254         }
4255
4256         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4257                 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4258                 priv->tso = true;
4259                 dev_info(priv->device, "TSO feature enabled\n");
4260         }
4261
4262         if (priv->dma_cap.addr64) {
4263                 ret = dma_set_mask_and_coherent(device,
4264                                 DMA_BIT_MASK(priv->dma_cap.addr64));
4265                 if (!ret) {
4266                         dev_info(priv->device, "Using %d bits DMA width\n",
4267                                  priv->dma_cap.addr64);
4268                 } else {
4269                         ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
4270                         if (ret) {
4271                                 dev_err(priv->device, "Failed to set DMA Mask\n");
4272                                 goto error_hw_init;
4273                         }
4274
4275                         priv->dma_cap.addr64 = 32;
4276                 }
4277         }
4278
4279         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4280         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4281 #ifdef STMMAC_VLAN_TAG_USED
4282         /* Both mac100 and gmac support receive VLAN tag detection */
4283         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4284 #endif
4285         priv->msg_enable = netif_msg_init(debug, default_msg_level);
4286
4287         /* MTU range: 46 - hw-specific max */
4288         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4289         if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4290                 ndev->max_mtu = JUMBO_LEN;
4291         else if (priv->plat->has_xgmac)
4292                 ndev->max_mtu = XGMAC_JUMBO_LEN;
4293         else
4294                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4295         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4296          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4297          */
4298         if ((priv->plat->maxmtu < ndev->max_mtu) &&
4299             (priv->plat->maxmtu >= ndev->min_mtu))
4300                 ndev->max_mtu = priv->plat->maxmtu;
4301         else if (priv->plat->maxmtu < ndev->min_mtu)
4302                 dev_warn(priv->device,
4303                          "%s: warning: maxmtu having invalid value (%d)\n",
4304                          __func__, priv->plat->maxmtu);
4305
4306         if (flow_ctrl)
4307                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
4308
4309         /* Setup channels NAPI */
4310         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4311
4312         for (queue = 0; queue < maxq; queue++) {
4313                 struct stmmac_channel *ch = &priv->channel[queue];
4314
4315                 ch->priv_data = priv;
4316                 ch->index = queue;
4317
4318                 if (queue < priv->plat->rx_queues_to_use) {
4319                         netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4320                                        NAPI_POLL_WEIGHT);
4321                 }
4322                 if (queue < priv->plat->tx_queues_to_use) {
4323                         netif_tx_napi_add(ndev, &ch->tx_napi,
4324                                           stmmac_napi_poll_tx,
4325                                           NAPI_POLL_WEIGHT);
4326                 }
4327         }
4328
4329         mutex_init(&priv->lock);
4330
4331         /* If a specific clk_csr value is passed from the platform
4332          * this means that the CSR Clock Range selection cannot be
4333          * changed at run-time and it is fixed. Viceversa the driver'll try to
4334          * set the MDC clock dynamically according to the csr actual
4335          * clock input.
4336          */
4337         if (priv->plat->clk_csr >= 0)
4338                 priv->clk_csr = priv->plat->clk_csr;
4339         else
4340                 stmmac_clk_csr_set(priv);
4341
4342         stmmac_check_pcs_mode(priv);
4343
4344         if (priv->hw->pcs != STMMAC_PCS_RGMII  &&
4345             priv->hw->pcs != STMMAC_PCS_TBI &&
4346             priv->hw->pcs != STMMAC_PCS_RTBI) {
4347                 /* MDIO bus Registration */
4348                 ret = stmmac_mdio_register(ndev);
4349                 if (ret < 0) {
4350                         dev_err(priv->device,
4351                                 "%s: MDIO bus (id: %d) registration failed",
4352                                 __func__, priv->plat->bus_id);
4353                         goto error_mdio_register;
4354                 }
4355         }
4356
4357         ret = stmmac_phy_setup(priv);
4358         if (ret) {
4359                 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4360                 goto error_phy_setup;
4361         }
4362
4363         ret = register_netdev(ndev);
4364         if (ret) {
4365                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4366                         __func__, ret);
4367                 goto error_netdev_register;
4368         }
4369
4370 #ifdef CONFIG_DEBUG_FS
4371         ret = stmmac_init_fs(ndev);
4372         if (ret < 0)
4373                 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
4374                             __func__);
4375 #endif
4376
4377         return ret;
4378
4379 error_netdev_register:
4380         phylink_destroy(priv->phylink);
4381 error_phy_setup:
4382         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4383             priv->hw->pcs != STMMAC_PCS_TBI &&
4384             priv->hw->pcs != STMMAC_PCS_RTBI)
4385                 stmmac_mdio_unregister(ndev);
4386 error_mdio_register:
4387         for (queue = 0; queue < maxq; queue++) {
4388                 struct stmmac_channel *ch = &priv->channel[queue];
4389
4390                 if (queue < priv->plat->rx_queues_to_use)
4391                         netif_napi_del(&ch->rx_napi);
4392                 if (queue < priv->plat->tx_queues_to_use)
4393                         netif_napi_del(&ch->tx_napi);
4394         }
4395 error_hw_init:
4396         destroy_workqueue(priv->wq);
4397
4398         return ret;
4399 }
4400 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4401
4402 /**
4403  * stmmac_dvr_remove
4404  * @dev: device pointer
4405  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4406  * changes the link status, releases the DMA descriptor rings.
4407  */
4408 int stmmac_dvr_remove(struct device *dev)
4409 {
4410         struct net_device *ndev = dev_get_drvdata(dev);
4411         struct stmmac_priv *priv = netdev_priv(ndev);
4412
4413         netdev_info(priv->dev, "%s: removing driver", __func__);
4414
4415 #ifdef CONFIG_DEBUG_FS
4416         stmmac_exit_fs(ndev);
4417 #endif
4418         stmmac_stop_all_dma(priv);
4419
4420         stmmac_mac_set(priv, priv->ioaddr, false);
4421         netif_carrier_off(ndev);
4422         unregister_netdev(ndev);
4423         phylink_destroy(priv->phylink);
4424         if (priv->plat->stmmac_rst)
4425                 reset_control_assert(priv->plat->stmmac_rst);
4426         clk_disable_unprepare(priv->plat->pclk);
4427         clk_disable_unprepare(priv->plat->stmmac_clk);
4428         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4429             priv->hw->pcs != STMMAC_PCS_TBI &&
4430             priv->hw->pcs != STMMAC_PCS_RTBI)
4431                 stmmac_mdio_unregister(ndev);
4432         destroy_workqueue(priv->wq);
4433         mutex_destroy(&priv->lock);
4434
4435         return 0;
4436 }
4437 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4438
4439 /**
4440  * stmmac_suspend - suspend callback
4441  * @dev: device pointer
4442  * Description: this is the function to suspend the device and it is called
4443  * by the platform driver to stop the network queue, release the resources,
4444  * program the PMT register (for WoL), clean and release driver resources.
4445  */
4446 int stmmac_suspend(struct device *dev)
4447 {
4448         struct net_device *ndev = dev_get_drvdata(dev);
4449         struct stmmac_priv *priv = netdev_priv(ndev);
4450
4451         if (!ndev || !netif_running(ndev))
4452                 return 0;
4453
4454         phylink_stop(priv->phylink);
4455
4456         mutex_lock(&priv->lock);
4457
4458         netif_device_detach(ndev);
4459         stmmac_stop_all_queues(priv);
4460
4461         stmmac_disable_all_queues(priv);
4462
4463         /* Stop TX/RX DMA */
4464         stmmac_stop_all_dma(priv);
4465
4466         /* Enable Power down mode by programming the PMT regs */
4467         if (device_may_wakeup(priv->device)) {
4468                 stmmac_pmt(priv, priv->hw, priv->wolopts);
4469                 priv->irq_wake = 1;
4470         } else {
4471                 stmmac_mac_set(priv, priv->ioaddr, false);
4472                 pinctrl_pm_select_sleep_state(priv->device);
4473                 /* Disable clock in case of PWM is off */
4474                 clk_disable(priv->plat->pclk);
4475                 clk_disable(priv->plat->stmmac_clk);
4476         }
4477         mutex_unlock(&priv->lock);
4478
4479         priv->speed = SPEED_UNKNOWN;
4480         return 0;
4481 }
4482 EXPORT_SYMBOL_GPL(stmmac_suspend);
4483
4484 /**
4485  * stmmac_reset_queues_param - reset queue parameters
4486  * @dev: device pointer
4487  */
4488 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4489 {
4490         u32 rx_cnt = priv->plat->rx_queues_to_use;
4491         u32 tx_cnt = priv->plat->tx_queues_to_use;
4492         u32 queue;
4493
4494         for (queue = 0; queue < rx_cnt; queue++) {
4495                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4496
4497                 rx_q->cur_rx = 0;
4498                 rx_q->dirty_rx = 0;
4499         }
4500
4501         for (queue = 0; queue < tx_cnt; queue++) {
4502                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4503
4504                 tx_q->cur_tx = 0;
4505                 tx_q->dirty_tx = 0;
4506                 tx_q->mss = 0;
4507         }
4508 }
4509
4510 /**
4511  * stmmac_resume - resume callback
4512  * @dev: device pointer
4513  * Description: when resume this function is invoked to setup the DMA and CORE
4514  * in a usable state.
4515  */
4516 int stmmac_resume(struct device *dev)
4517 {
4518         struct net_device *ndev = dev_get_drvdata(dev);
4519         struct stmmac_priv *priv = netdev_priv(ndev);
4520
4521         if (!netif_running(ndev))
4522                 return 0;
4523
4524         /* Power Down bit, into the PM register, is cleared
4525          * automatically as soon as a magic packet or a Wake-up frame
4526          * is received. Anyway, it's better to manually clear
4527          * this bit because it can generate problems while resuming
4528          * from another devices (e.g. serial console).
4529          */
4530         if (device_may_wakeup(priv->device)) {
4531                 mutex_lock(&priv->lock);
4532                 stmmac_pmt(priv, priv->hw, 0);
4533                 mutex_unlock(&priv->lock);
4534                 priv->irq_wake = 0;
4535         } else {
4536                 pinctrl_pm_select_default_state(priv->device);
4537                 /* enable the clk previously disabled */
4538                 clk_enable(priv->plat->stmmac_clk);
4539                 clk_enable(priv->plat->pclk);
4540                 /* reset the phy so that it's ready */
4541                 if (priv->mii)
4542                         stmmac_mdio_reset(priv->mii);
4543         }
4544
4545         netif_device_attach(ndev);
4546
4547         mutex_lock(&priv->lock);
4548
4549         stmmac_reset_queues_param(priv);
4550
4551         stmmac_clear_descriptors(priv);
4552
4553         stmmac_hw_setup(ndev, false);
4554         stmmac_init_coalesce(priv);
4555         stmmac_set_rx_mode(ndev);
4556
4557         stmmac_enable_all_queues(priv);
4558
4559         stmmac_start_all_queues(priv);
4560
4561         mutex_unlock(&priv->lock);
4562
4563         phylink_start(priv->phylink);
4564
4565         return 0;
4566 }
4567 EXPORT_SYMBOL_GPL(stmmac_resume);
4568
4569 #ifndef MODULE
4570 static int __init stmmac_cmdline_opt(char *str)
4571 {
4572         char *opt;
4573
4574         if (!str || !*str)
4575                 return -EINVAL;
4576         while ((opt = strsep(&str, ",")) != NULL) {
4577                 if (!strncmp(opt, "debug:", 6)) {
4578                         if (kstrtoint(opt + 6, 0, &debug))
4579                                 goto err;
4580                 } else if (!strncmp(opt, "phyaddr:", 8)) {
4581                         if (kstrtoint(opt + 8, 0, &phyaddr))
4582                                 goto err;
4583                 } else if (!strncmp(opt, "buf_sz:", 7)) {
4584                         if (kstrtoint(opt + 7, 0, &buf_sz))
4585                                 goto err;
4586                 } else if (!strncmp(opt, "tc:", 3)) {
4587                         if (kstrtoint(opt + 3, 0, &tc))
4588                                 goto err;
4589                 } else if (!strncmp(opt, "watchdog:", 9)) {
4590                         if (kstrtoint(opt + 9, 0, &watchdog))
4591                                 goto err;
4592                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4593                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
4594                                 goto err;
4595                 } else if (!strncmp(opt, "pause:", 6)) {
4596                         if (kstrtoint(opt + 6, 0, &pause))
4597                                 goto err;
4598                 } else if (!strncmp(opt, "eee_timer:", 10)) {
4599                         if (kstrtoint(opt + 10, 0, &eee_timer))
4600                                 goto err;
4601                 } else if (!strncmp(opt, "chain_mode:", 11)) {
4602                         if (kstrtoint(opt + 11, 0, &chain_mode))
4603                                 goto err;
4604                 }
4605         }
4606         return 0;
4607
4608 err:
4609         pr_err("%s: ERROR broken module parameter conversion", __func__);
4610         return -EINVAL;
4611 }
4612
4613 __setup("stmmaceth=", stmmac_cmdline_opt);
4614 #endif /* MODULE */
4615
4616 static int __init stmmac_init(void)
4617 {
4618 #ifdef CONFIG_DEBUG_FS
4619         /* Create debugfs main directory if it doesn't exist yet */
4620         if (!stmmac_fs_dir) {
4621                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4622
4623                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4624                         pr_err("ERROR %s, debugfs create directory failed\n",
4625                                STMMAC_RESOURCE_NAME);
4626
4627                         return -ENOMEM;
4628                 }
4629         }
4630 #endif
4631
4632         return 0;
4633 }
4634
4635 static void __exit stmmac_exit(void)
4636 {
4637 #ifdef CONFIG_DEBUG_FS
4638         debugfs_remove_recursive(stmmac_fs_dir);
4639 #endif
4640 }
4641
4642 module_init(stmmac_init)
4643 module_exit(stmmac_exit)
4644
4645 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4646 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4647 MODULE_LICENSE("GPL");