drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #include <linux/pinctrl/consumer.h>
  47 #ifdef CONFIG_DEBUG_FS
  48 #include <linux/debugfs.h>
  49 #include <linux/seq_file.h>
  50 #endif /* CONFIG_DEBUG_FS */
  51 #include <linux/net_tstamp.h>
  52 #include "stmmac_ptp.h"
  53 #include "stmmac.h"
  54 #include <linux/reset.h>
  55
  56 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  57
  58 /* Module parameters */
  59 #define TX_TIMEO        5000
  60 static int watchdog = TX_TIMEO;
  61 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  62 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  63
  64 static int debug = -1;
  65 module_param(debug, int, S_IRUGO | S_IWUSR);
  66 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  67
  68 static int phyaddr = -1;
  69 module_param(phyaddr, int, S_IRUGO);
  70 MODULE_PARM_DESC(phyaddr, "Physical device address");
  71
  72 #define DMA_TX_SIZE 256
  73 static int dma_txsize = DMA_TX_SIZE;
  74 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  75 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  76
  77 #define DMA_RX_SIZE 256
  78 static int dma_rxsize = DMA_RX_SIZE;
  79 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
  80 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
  81
  82 static int flow_ctrl = FLOW_OFF;
  83 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
  84 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  85
  86 static int pause = PAUSE_TIME;
  87 module_param(pause, int, S_IRUGO | S_IWUSR);
  88 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  89
  90 #define TC_DEFAULT 64
  91 static int tc = TC_DEFAULT;
  92 module_param(tc, int, S_IRUGO | S_IWUSR);
  93 MODULE_PARM_DESC(tc, "DMA threshold control value");
  94
  95 #define DEFAULT_BUFSIZE 1536
  96 static int buf_sz = DEFAULT_BUFSIZE;
  97 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
  98 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  99
 100 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 101                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 102                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 103
 104 #define STMMAC_DEFAULT_LPI_TIMER        1000
 105 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 106 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 107 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 108 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
 109
 110 /* By default the driver will use the ring mode to manage tx and rx descriptors
 111  * but passing this value so user can force to use the chain instead of the ring
 112  */
 113 static unsigned int chain_mode;
 114 module_param(chain_mode, int, S_IRUGO);
 115 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 116
 117 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 118
 119 #ifdef CONFIG_DEBUG_FS
 120 static int stmmac_init_fs(struct net_device *dev);
 121 static void stmmac_exit_fs(void);
 122 #endif
 123
 124 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 125
 126 /**
 127  * stmmac_verify_args - verify the driver parameters.
 128  * Description: it checks the driver parameters and set a default in case of
 129  * errors.
 130  */
 131 static void stmmac_verify_args(void)
 132 {
 133         if (unlikely(watchdog < 0))
 134                 watchdog = TX_TIMEO;
 135         if (unlikely(dma_rxsize < 0))
 136                 dma_rxsize = DMA_RX_SIZE;
 137         if (unlikely(dma_txsize < 0))
 138                 dma_txsize = DMA_TX_SIZE;
 139         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 140                 buf_sz = DEFAULT_BUFSIZE;
 141         if (unlikely(flow_ctrl > 1))
 142                 flow_ctrl = FLOW_AUTO;
 143         else if (likely(flow_ctrl < 0))
 144                 flow_ctrl = FLOW_OFF;
 145         if (unlikely((pause < 0) || (pause > 0xffff)))
 146                 pause = PAUSE_TIME;
 147         if (eee_timer < 0)
 148                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 149 }
 150
 151 /**
 152  * stmmac_clk_csr_set - dynamically set the MDC clock
 153  * @priv: driver private structure
 154  * Description: this is to dynamically set the MDC clock according to the csr
 155  * clock input.
 156  * Note:
 157  *      If a specific clk_csr value is passed from the platform
 158  *      this means that the CSR Clock Range selection cannot be
 159  *      changed at run-time and it is fixed (as reported in the driver
 160  *      documentation). Viceversa the driver will try to set the MDC
 161  *      clock dynamically according to the actual clock input.
 162  */
 163 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 164 {
 165         u32 clk_rate;
 166
 167         clk_rate = clk_get_rate(priv->stmmac_clk);
 168
 169         /* Platform provided default clk_csr would be assumed valid
 170          * for all other cases except for the below mentioned ones.
 171          * For values higher than the IEEE 802.3 specified frequency
 172          * we can not estimate the proper divider as it is not known
 173          * the frequency of clk_csr_i. So we do not change the default
 174          * divider.
 175          */
 176         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 177                 if (clk_rate < CSR_F_35M)
 178                         priv->clk_csr = STMMAC_CSR_20_35M;
 179                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 180                         priv->clk_csr = STMMAC_CSR_35_60M;
 181                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 182                         priv->clk_csr = STMMAC_CSR_60_100M;
 183                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 184                         priv->clk_csr = STMMAC_CSR_100_150M;
 185                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 186                         priv->clk_csr = STMMAC_CSR_150_250M;
 187                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 188                         priv->clk_csr = STMMAC_CSR_250_300M;
 189         }
 190 }
 191
 192 static void print_pkt(unsigned char *buf, int len)
 193 {
 194         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 195         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 196 }
 197
 198 /* minimum number of free TX descriptors required to wake up TX process */
 199 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 200
 201 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 202 {
 203         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 204 }
 205
 206 /**
 207  * stmmac_hw_fix_mac_speed - callback for speed selection
 208  * @priv: driver private structure
 209  * Description: on some platforms (e.g. ST), some HW system configuraton
 210  * registers have to be set according to the link speed negotiated.
 211  */
 212 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 213 {
 214         struct phy_device *phydev = priv->phydev;
 215
 216         if (likely(priv->plat->fix_mac_speed))
 217                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed);
 218 }
 219
 220 /**
 221  * stmmac_enable_eee_mode - check and enter in LPI mode
 222  * @priv: driver private structure
 223  * Description: this function is to verify and enter in LPI mode in case of
 224  * EEE.
 225  */
 226 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 227 {
 228         /* Check and enter in LPI mode */
 229         if ((priv->dirty_tx == priv->cur_tx) &&
 230             (priv->tx_path_in_lpi_mode == false))
 231                 priv->hw->mac->set_eee_mode(priv->hw);
 232 }
 233
 234 /**
 235  * stmmac_disable_eee_mode - disable and exit from LPI mode
 236  * @priv: driver private structure
 237  * Description: this function is to exit and disable EEE in case of
 238  * LPI state is true. This is called by the xmit.
 239  */
 240 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 241 {
 242         priv->hw->mac->reset_eee_mode(priv->hw);
 243         del_timer_sync(&priv->eee_ctrl_timer);
 244         priv->tx_path_in_lpi_mode = false;
 245 }
 246
 247 /**
 248  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 249  * @arg : data hook
 250  * Description:
 251  *  if there is no data transfer and if we are not in LPI state,
 252  *  then MAC Transmitter can be moved to LPI state.
 253  */
 254 static void stmmac_eee_ctrl_timer(unsigned long arg)
 255 {
 256         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 257
 258         stmmac_enable_eee_mode(priv);
 259         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 260 }
 261
 262 /**
 263  * stmmac_eee_init - init EEE
 264  * @priv: driver private structure
 265  * Description:
 266  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 267  *  can also manage EEE, this function enable the LPI state and start related
 268  *  timer.
 269  */
 270 bool stmmac_eee_init(struct stmmac_priv *priv)
 271 {
 272         char *phy_bus_name = priv->plat->phy_bus_name;
 273         unsigned long flags;
 274         bool ret = false;
 275
 276         /* Using PCS we cannot dial with the phy registers at this stage
 277          * so we do not support extra feature like EEE.
 278          */
 279         if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) ||
 280             (priv->pcs == STMMAC_PCS_RTBI))
 281                 goto out;
 282
 283         /* Never init EEE in case of a switch is attached */
 284         if (phy_bus_name && (!strcmp(phy_bus_name, "fixed")))
 285                 goto out;
 286
 287         /* MAC core supports the EEE feature. */
 288         if (priv->dma_cap.eee) {
 289                 int tx_lpi_timer = priv->tx_lpi_timer;
 290
 291                 /* Check if the PHY supports EEE */
 292                 if (phy_init_eee(priv->phydev, 1)) {
 293                         /* To manage at run-time if the EEE cannot be supported
 294                          * anymore (for example because the lp caps have been
 295                          * changed).
 296                          * In that case the driver disable own timers.
 297                          */
 298                         spin_lock_irqsave(&priv->lock, flags);
 299                         if (priv->eee_active) {
 300                                 pr_debug("stmmac: disable EEE\n");
 301                                 del_timer_sync(&priv->eee_ctrl_timer);
 302                                 priv->hw->mac->set_eee_timer(priv->hw, 0,
 303                                                              tx_lpi_timer);
 304                         }
 305                         priv->eee_active = 0;
 306                         spin_unlock_irqrestore(&priv->lock, flags);
 307                         goto out;
 308                 }
 309                 /* Activate the EEE and start timers */
 310                 spin_lock_irqsave(&priv->lock, flags);
 311                 if (!priv->eee_active) {
 312                         priv->eee_active = 1;
 313                         setup_timer(&priv->eee_ctrl_timer,
 314                                     stmmac_eee_ctrl_timer,
 315                                     (unsigned long)priv);
 316                         mod_timer(&priv->eee_ctrl_timer,
 317                                   STMMAC_LPI_T(eee_timer));
 318
 319                         priv->hw->mac->set_eee_timer(priv->hw,
 320                                                      STMMAC_DEFAULT_LIT_LS,
 321                                                      tx_lpi_timer);
 322                 }
 323                 /* Set HW EEE according to the speed */
 324                 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link);
 325
 326                 ret = true;
 327                 spin_unlock_irqrestore(&priv->lock, flags);
 328
 329                 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n");
 330         }
 331 out:
 332         return ret;
 333 }
 334
 335 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 336  * @priv: driver private structure
 337  * @entry : descriptor index to be used.
 338  * @skb : the socket buffer
 339  * Description :
 340  * This function will read timestamp from the descriptor & pass it to stack.
 341  * and also perform some sanity checks.
 342  */
 343 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 344                                    unsigned int entry, struct sk_buff *skb)
 345 {
 346         struct skb_shared_hwtstamps shhwtstamp;
 347         u64 ns;
 348         void *desc = NULL;
 349
 350         if (!priv->hwts_tx_en)
 351                 return;
 352
 353         /* exit if skb doesn't support hw tstamp */
 354         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 355                 return;
 356
 357         if (priv->adv_ts)
 358                 desc = (priv->dma_etx + entry);
 359         else
 360                 desc = (priv->dma_tx + entry);
 361
 362         /* check tx tstamp status */
 363         if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc))
 364                 return;
 365
 366         /* get the valid tstamp */
 367         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 368
 369         memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 370         shhwtstamp.hwtstamp = ns_to_ktime(ns);
 371         /* pass tstamp to stack */
 372         skb_tstamp_tx(skb, &shhwtstamp);
 373
 374         return;
 375 }
 376
 377 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 378  * @priv: driver private structure
 379  * @entry : descriptor index to be used.
 380  * @skb : the socket buffer
 381  * Description :
 382  * This function will read received packet's timestamp from the descriptor
 383  * and pass it to stack. It also perform some sanity checks.
 384  */
 385 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv,
 386                                    unsigned int entry, struct sk_buff *skb)
 387 {
 388         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 389         u64 ns;
 390         void *desc = NULL;
 391
 392         if (!priv->hwts_rx_en)
 393                 return;
 394
 395         if (priv->adv_ts)
 396                 desc = (priv->dma_erx + entry);
 397         else
 398                 desc = (priv->dma_rx + entry);
 399
 400         /* exit if rx tstamp is not valid */
 401         if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts))
 402                 return;
 403
 404         /* get valid tstamp */
 405         ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts);
 406         shhwtstamp = skb_hwtstamps(skb);
 407         memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 408         shhwtstamp->hwtstamp = ns_to_ktime(ns);
 409 }
 410
 411 /**
 412  *  stmmac_hwtstamp_ioctl - control hardware timestamping.
 413  *  @dev: device pointer.
 414  *  @ifr: An IOCTL specefic structure, that can contain a pointer to
 415  *  a proprietary structure used to pass information to the driver.
 416  *  Description:
 417  *  This function configures the MAC to enable/disable both outgoing(TX)
 418  *  and incoming(RX) packets time stamping based on user input.
 419  *  Return Value:
 420  *  0 on success and an appropriate -ve integer on failure.
 421  */
 422 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr)
 423 {
 424         struct stmmac_priv *priv = netdev_priv(dev);
 425         struct hwtstamp_config config;
 426         struct timespec now;
 427         u64 temp = 0;
 428         u32 ptp_v2 = 0;
 429         u32 tstamp_all = 0;
 430         u32 ptp_over_ipv4_udp = 0;
 431         u32 ptp_over_ipv6_udp = 0;
 432         u32 ptp_over_ethernet = 0;
 433         u32 snap_type_sel = 0;
 434         u32 ts_master_en = 0;
 435         u32 ts_event_en = 0;
 436         u32 value = 0;
 437
 438         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 439                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 440                 priv->hwts_tx_en = 0;
 441                 priv->hwts_rx_en = 0;
 442
 443                 return -EOPNOTSUPP;
 444         }
 445
 446         if (copy_from_user(&config, ifr->ifr_data,
 447                            sizeof(struct hwtstamp_config)))
 448                 return -EFAULT;
 449
 450         pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 451                  __func__, config.flags, config.tx_type, config.rx_filter);
 452
 453         /* reserved for future extensions */
 454         if (config.flags)
 455                 return -EINVAL;
 456
 457         if (config.tx_type != HWTSTAMP_TX_OFF &&
 458             config.tx_type != HWTSTAMP_TX_ON)
 459                 return -ERANGE;
 460
 461         if (priv->adv_ts) {
 462                 switch (config.rx_filter) {
 463                 case HWTSTAMP_FILTER_NONE:
 464                         /* time stamp no incoming packet at all */
 465                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 466                         break;
 467
 468                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 469                         /* PTP v1, UDP, any kind of event packet */
 470                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 471                         /* take time stamp for all event messages */
 472                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 473
 474                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 475                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 476                         break;
 477
 478                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 479                         /* PTP v1, UDP, Sync packet */
 480                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 481                         /* take time stamp for SYNC messages only */
 482                         ts_event_en = PTP_TCR_TSEVNTENA;
 483
 484                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 485                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 486                         break;
 487
 488                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 489                         /* PTP v1, UDP, Delay_req packet */
 490                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 491                         /* take time stamp for Delay_Req messages only */
 492                         ts_master_en = PTP_TCR_TSMSTRENA;
 493                         ts_event_en = PTP_TCR_TSEVNTENA;
 494
 495                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 496                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 497                         break;
 498
 499                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 500                         /* PTP v2, UDP, any kind of event packet */
 501                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 502                         ptp_v2 = PTP_TCR_TSVER2ENA;
 503                         /* take time stamp for all event messages */
 504                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 505
 506                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 507                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 508                         break;
 509
 510                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 511                         /* PTP v2, UDP, Sync packet */
 512                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 513                         ptp_v2 = PTP_TCR_TSVER2ENA;
 514                         /* take time stamp for SYNC messages only */
 515                         ts_event_en = PTP_TCR_TSEVNTENA;
 516
 517                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 518                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 519                         break;
 520
 521                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 522                         /* PTP v2, UDP, Delay_req packet */
 523                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 524                         ptp_v2 = PTP_TCR_TSVER2ENA;
 525                         /* take time stamp for Delay_Req messages only */
 526                         ts_master_en = PTP_TCR_TSMSTRENA;
 527                         ts_event_en = PTP_TCR_TSEVNTENA;
 528
 529                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 530                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 531                         break;
 532
 533                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 534                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 535                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 536                         ptp_v2 = PTP_TCR_TSVER2ENA;
 537                         /* take time stamp for all event messages */
 538                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 539
 540                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 541                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 542                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 543                         break;
 544
 545                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 546                         /* PTP v2/802.AS1, any layer, Sync packet */
 547                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 548                         ptp_v2 = PTP_TCR_TSVER2ENA;
 549                         /* take time stamp for SYNC messages only */
 550                         ts_event_en = PTP_TCR_TSEVNTENA;
 551
 552                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 553                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 554                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 555                         break;
 556
 557                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 558                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 559                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 560                         ptp_v2 = PTP_TCR_TSVER2ENA;
 561                         /* take time stamp for Delay_Req messages only */
 562                         ts_master_en = PTP_TCR_TSMSTRENA;
 563                         ts_event_en = PTP_TCR_TSEVNTENA;
 564
 565                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 566                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 567                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 568                         break;
 569
 570                 case HWTSTAMP_FILTER_ALL:
 571                         /* time stamp any incoming packet */
 572                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 573                         tstamp_all = PTP_TCR_TSENALL;
 574                         break;
 575
 576                 default:
 577                         return -ERANGE;
 578                 }
 579         } else {
 580                 switch (config.rx_filter) {
 581                 case HWTSTAMP_FILTER_NONE:
 582                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 583                         break;
 584                 default:
 585                         /* PTP v1, UDP, any kind of event packet */
 586                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 587                         break;
 588                 }
 589         }
 590         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 591         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 592
 593         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 594                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0);
 595         else {
 596                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 597                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 598                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 599                          ts_master_en | snap_type_sel);
 600
 601                 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value);
 602
 603                 /* program Sub Second Increment reg */
 604                 priv->hw->ptp->config_sub_second_increment(priv->ioaddr);
 605
 606                 /* calculate default added value:
 607                  * formula is :
 608                  * addend = (2^32)/freq_div_ratio;
 609                  * where, freq_div_ratio = clk_ptp_ref_i/50MHz
 610                  * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i;
 611                  * NOTE: clk_ptp_ref_i should be >= 50MHz to
 612                  *       achieve 20ns accuracy.
 613                  *
 614                  * 2^x * y == (y << x), hence
 615                  * 2^32 * 50000000 ==> (50000000 << 32)
 616                  */
 617                 temp = (u64) (50000000ULL << 32);
 618                 priv->default_addend = div_u64(temp, priv->clk_ptp_rate);
 619                 priv->hw->ptp->config_addend(priv->ioaddr,
 620                                              priv->default_addend);
 621
 622                 /* initialize system time */
 623                 getnstimeofday(&now);
 624                 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec,
 625                                             now.tv_nsec);
 626         }
 627
 628         return copy_to_user(ifr->ifr_data, &config,
 629                             sizeof(struct hwtstamp_config)) ? -EFAULT : 0;
 630 }
 631
 632 /**
 633  * stmmac_init_ptp - init PTP
 634  * @priv: driver private structure
 635  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 636  * This is done by looking at the HW cap. register.
 637  * This function also registers the ptp driver.
 638  */
 639 static int stmmac_init_ptp(struct stmmac_priv *priv)
 640 {
 641         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 642                 return -EOPNOTSUPP;
 643
 644         /* Fall-back to main clock in case of no PTP ref is passed */
 645         priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref");
 646         if (IS_ERR(priv->clk_ptp_ref)) {
 647                 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk);
 648                 priv->clk_ptp_ref = NULL;
 649         } else {
 650                 clk_prepare_enable(priv->clk_ptp_ref);
 651                 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref);
 652         }
 653
 654         priv->adv_ts = 0;
 655         if (priv->dma_cap.atime_stamp && priv->extend_desc)
 656                 priv->adv_ts = 1;
 657
 658         if (netif_msg_hw(priv) && priv->dma_cap.time_stamp)
 659                 pr_debug("IEEE 1588-2002 Time Stamp supported\n");
 660
 661         if (netif_msg_hw(priv) && priv->adv_ts)
 662                 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n");
 663
 664         priv->hw->ptp = &stmmac_ptp;
 665         priv->hwts_tx_en = 0;
 666         priv->hwts_rx_en = 0;
 667
 668         return stmmac_ptp_register(priv);
 669 }
 670
 671 static void stmmac_release_ptp(struct stmmac_priv *priv)
 672 {
 673         if (priv->clk_ptp_ref)
 674                 clk_disable_unprepare(priv->clk_ptp_ref);
 675         stmmac_ptp_unregister(priv);
 676 }
 677
 678 /**
 679  * stmmac_adjust_link - adjusts the link parameters
 680  * @dev: net device structure
 681  * Description: this is the helper called by the physical abstraction layer
 682  * drivers to communicate the phy link status. According the speed and duplex
 683  * this driver can invoke registered glue-logic as well.
 684  * It also invoke the eee initialization because it could happen when switch
 685  * on different networks (that are eee capable).
 686  */
 687 static void stmmac_adjust_link(struct net_device *dev)
 688 {
 689         struct stmmac_priv *priv = netdev_priv(dev);
 690         struct phy_device *phydev = priv->phydev;
 691         unsigned long flags;
 692         int new_state = 0;
 693         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 694
 695         if (phydev == NULL)
 696                 return;
 697
 698         spin_lock_irqsave(&priv->lock, flags);
 699
 700         if (phydev->link) {
 701                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 702
 703                 /* Now we make sure that we can be in full duplex mode.
 704                  * If not, we operate in half-duplex mode. */
 705                 if (phydev->duplex != priv->oldduplex) {
 706                         new_state = 1;
 707                         if (!(phydev->duplex))
 708                                 ctrl &= ~priv->hw->link.duplex;
 709                         else
 710                                 ctrl |= priv->hw->link.duplex;
 711                         priv->oldduplex = phydev->duplex;
 712                 }
 713                 /* Flow Control operation */
 714                 if (phydev->pause)
 715                         priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex,
 716                                                  fc, pause_time);
 717
 718                 if (phydev->speed != priv->speed) {
 719                         new_state = 1;
 720                         switch (phydev->speed) {
 721                         case 1000:
 722                                 if (likely(priv->plat->has_gmac))
 723                                         ctrl &= ~priv->hw->link.port;
 724                                 stmmac_hw_fix_mac_speed(priv);
 725                                 break;
 726                         case 100:
 727                         case 10:
 728                                 if (priv->plat->has_gmac) {
 729                                         ctrl |= priv->hw->link.port;
 730                                         if (phydev->speed == SPEED_100) {
 731                                                 ctrl |= priv->hw->link.speed;
 732                                         } else {
 733                                                 ctrl &= ~(priv->hw->link.speed);
 734                                         }
 735                                 } else {
 736                                         ctrl &= ~priv->hw->link.port;
 737                                 }
 738                                 stmmac_hw_fix_mac_speed(priv);
 739                                 break;
 740                         default:
 741                                 if (netif_msg_link(priv))
 742                                         pr_warn("%s: Speed (%d) not 10/100\n",
 743                                                 dev->name, phydev->speed);
 744                                 break;
 745                         }
 746
 747                         priv->speed = phydev->speed;
 748                 }
 749
 750                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 751
 752                 if (!priv->oldlink) {
 753                         new_state = 1;
 754                         priv->oldlink = 1;
 755                 }
 756         } else if (priv->oldlink) {
 757                 new_state = 1;
 758                 priv->oldlink = 0;
 759                 priv->speed = 0;
 760                 priv->oldduplex = -1;
 761         }
 762
 763         if (new_state && netif_msg_link(priv))
 764                 phy_print_status(phydev);
 765
 766         spin_unlock_irqrestore(&priv->lock, flags);
 767
 768         /* At this stage, it could be needed to setup the EEE or adjust some
 769          * MAC related HW registers.
 770          */
 771         priv->eee_enabled = stmmac_eee_init(priv);
 772 }
 773
 774 /**
 775  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 776  * @priv: driver private structure
 777  * Description: this is to verify if the HW supports the PCS.
 778  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 779  * configured for the TBI, RTBI, or SGMII PHY interface.
 780  */
 781 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 782 {
 783         int interface = priv->plat->interface;
 784
 785         if (priv->dma_cap.pcs) {
 786                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 787                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 788                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 789                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 790                         pr_debug("STMMAC: PCS RGMII support enable\n");
 791                         priv->pcs = STMMAC_PCS_RGMII;
 792                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 793                         pr_debug("STMMAC: PCS SGMII support enable\n");
 794                         priv->pcs = STMMAC_PCS_SGMII;
 795                 }
 796         }
 797 }
 798
 799 /**
 800  * stmmac_init_phy - PHY initialization
 801  * @dev: net device structure
 802  * Description: it initializes the driver's PHY state, and attaches the PHY
 803  * to the mac driver.
 804  *  Return value:
 805  *  0 on success
 806  */
 807 static int stmmac_init_phy(struct net_device *dev)
 808 {
 809         struct stmmac_priv *priv = netdev_priv(dev);
 810         struct phy_device *phydev;
 811         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 812         char bus_id[MII_BUS_ID_SIZE];
 813         int interface = priv->plat->interface;
 814         int max_speed = priv->plat->max_speed;
 815         priv->oldlink = 0;
 816         priv->speed = 0;
 817         priv->oldduplex = -1;
 818
 819         if (priv->plat->phy_bus_name)
 820                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 821                          priv->plat->phy_bus_name, priv->plat->bus_id);
 822         else
 823                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 824                          priv->plat->bus_id);
 825
 826         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 827                  priv->plat->phy_addr);
 828         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 829
 830         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 831
 832         if (IS_ERR(phydev)) {
 833                 pr_err("%s: Could not attach to PHY\n", dev->name);
 834                 return PTR_ERR(phydev);
 835         }
 836
 837         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 838         if ((interface == PHY_INTERFACE_MODE_MII) ||
 839             (interface == PHY_INTERFACE_MODE_RMII) ||
 840                 (max_speed < 1000 && max_speed > 0))
 841                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 842                                          SUPPORTED_1000baseT_Full);
 843
 844         /*
 845          * Broken HW is sometimes missing the pull-up resistor on the
 846          * MDIO line, which results in reads to non-existent devices returning
 847          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 848          * device as well.
 849          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 850          */
 851         if (phydev->phy_id == 0) {
 852                 phy_disconnect(phydev);
 853                 return -ENODEV;
 854         }
 855         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 856                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 857
 858         priv->phydev = phydev;
 859
 860         return 0;
 861 }
 862
 863 /**
 864  * stmmac_display_ring - display ring
 865  * @head: pointer to the head of the ring passed.
 866  * @size: size of the ring.
 867  * @extend_desc: to verify if extended descriptors are used.
 868  * Description: display the control/status and buffer descriptors.
 869  */
 870 static void stmmac_display_ring(void *head, int size, int extend_desc)
 871 {
 872         int i;
 873         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
 874         struct dma_desc *p = (struct dma_desc *)head;
 875
 876         for (i = 0; i < size; i++) {
 877                 u64 x;
 878                 if (extend_desc) {
 879                         x = *(u64 *) ep;
 880                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
 881                                 i, (unsigned int)virt_to_phys(ep),
 882                                 (unsigned int)x, (unsigned int)(x >> 32),
 883                                 ep->basic.des2, ep->basic.des3);
 884                         ep++;
 885                 } else {
 886                         x = *(u64 *) p;
 887                         pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x",
 888                                 i, (unsigned int)virt_to_phys(p),
 889                                 (unsigned int)x, (unsigned int)(x >> 32),
 890                                 p->des2, p->des3);
 891                         p++;
 892                 }
 893                 pr_info("\n");
 894         }
 895 }
 896
 897 static void stmmac_display_rings(struct stmmac_priv *priv)
 898 {
 899         unsigned int txsize = priv->dma_tx_size;
 900         unsigned int rxsize = priv->dma_rx_size;
 901
 902         if (priv->extend_desc) {
 903                 pr_info("Extended RX descriptor ring:\n");
 904                 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
 905                 pr_info("Extended TX descriptor ring:\n");
 906                 stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
 907         } else {
 908                 pr_info("RX descriptor ring:\n");
 909                 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
 910                 pr_info("TX descriptor ring:\n");
 911                 stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
 912         }
 913 }
 914
 915 static int stmmac_set_bfsize(int mtu, int bufsize)
 916 {
 917         int ret = bufsize;
 918
 919         if (mtu >= BUF_SIZE_4KiB)
 920                 ret = BUF_SIZE_8KiB;
 921         else if (mtu >= BUF_SIZE_2KiB)
 922                 ret = BUF_SIZE_4KiB;
 923         else if (mtu > DEFAULT_BUFSIZE)
 924                 ret = BUF_SIZE_2KiB;
 925         else
 926                 ret = DEFAULT_BUFSIZE;
 927
 928         return ret;
 929 }
 930
 931 /**
 932  * stmmac_clear_descriptors - clear descriptors
 933  * @priv: driver private structure
 934  * Description: this function is called to clear the tx and rx descriptors
 935  * in case of both basic and extended descriptors are used.
 936  */
 937 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
 938 {
 939         int i;
 940         unsigned int txsize = priv->dma_tx_size;
 941         unsigned int rxsize = priv->dma_rx_size;
 942
 943         /* Clear the Rx/Tx descriptors */
 944         for (i = 0; i < rxsize; i++)
 945                 if (priv->extend_desc)
 946                         priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic,
 947                                                      priv->use_riwt, priv->mode,
 948                                                      (i == rxsize - 1));
 949                 else
 950                         priv->hw->desc->init_rx_desc(&priv->dma_rx[i],
 951                                                      priv->use_riwt, priv->mode,
 952                                                      (i == rxsize - 1));
 953         for (i = 0; i < txsize; i++)
 954                 if (priv->extend_desc)
 955                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
 956                                                      priv->mode,
 957                                                      (i == txsize - 1));
 958                 else
 959                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
 960                                                      priv->mode,
 961                                                      (i == txsize - 1));
 962 }
 963
 964 /**
 965  * stmmac_init_rx_buffers - init the RX descriptor buffer.
 966  * @priv: driver private structure
 967  * @p: descriptor pointer
 968  * @i: descriptor index
 969  * @flags: gfp flag.
 970  * Description: this function is called to allocate a receive buffer, perform
 971  * the DMA mapping and init the descriptor.
 972  */
 973 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
 974                                   int i, gfp_t flags)
 975 {
 976         struct sk_buff *skb;
 977
 978         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
 979         if (!skb) {
 980                 pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 981                 return -ENOMEM;
 982         }
 983         priv->rx_skbuff[i] = skb;
 984         priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 985                                                 priv->dma_buf_sz,
 986                                                 DMA_FROM_DEVICE);
 987         if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) {
 988                 pr_err("%s: DMA mapping error\n", __func__);
 989                 dev_kfree_skb_any(skb);
 990                 return -EINVAL;
 991         }
 992
 993         p->des2 = priv->rx_skbuff_dma[i];
 994
 995         if ((priv->hw->mode->init_desc3) &&
 996             (priv->dma_buf_sz == BUF_SIZE_16KiB))
 997                 priv->hw->mode->init_desc3(p);
 998
 999         return 0;
1000 }
1001
1002 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i)
1003 {
1004         if (priv->rx_skbuff[i]) {
1005                 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
1006                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1007                 dev_kfree_skb_any(priv->rx_skbuff[i]);
1008         }
1009         priv->rx_skbuff[i] = NULL;
1010 }
1011
1012 /**
1013  * init_dma_desc_rings - init the RX/TX descriptor rings
1014  * @dev: net device structure
1015  * @flags: gfp flag.
1016  * Description: this function initializes the DMA RX/TX descriptors
1017  * and allocates the socket buffers. It suppors the chained and ring
1018  * modes.
1019  */
1020 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1021 {
1022         int i;
1023         struct stmmac_priv *priv = netdev_priv(dev);
1024         unsigned int txsize = priv->dma_tx_size;
1025         unsigned int rxsize = priv->dma_rx_size;
1026         unsigned int bfsize = 0;
1027         int ret = -ENOMEM;
1028
1029         if (priv->hw->mode->set_16kib_bfsize)
1030                 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu);
1031
1032         if (bfsize < BUF_SIZE_16KiB)
1033                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1034
1035         priv->dma_buf_sz = bfsize;
1036
1037         if (netif_msg_probe(priv))
1038                 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__,
1039                          txsize, rxsize, bfsize);
1040
1041         if (netif_msg_probe(priv)) {
1042                 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__,
1043                          (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy);
1044
1045                 /* RX INITIALIZATION */
1046                 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n");
1047         }
1048         for (i = 0; i < rxsize; i++) {
1049                 struct dma_desc *p;
1050                 if (priv->extend_desc)
1051                         p = &((priv->dma_erx + i)->basic);
1052                 else
1053                         p = priv->dma_rx + i;
1054
1055                 ret = stmmac_init_rx_buffers(priv, p, i, flags);
1056                 if (ret)
1057                         goto err_init_rx_buffers;
1058
1059                 if (netif_msg_probe(priv))
1060                         pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
1061                                  priv->rx_skbuff[i]->data,
1062                                  (unsigned int)priv->rx_skbuff_dma[i]);
1063         }
1064         priv->cur_rx = 0;
1065         priv->dirty_rx = (unsigned int)(i - rxsize);
1066         buf_sz = bfsize;
1067
1068         /* Setup the chained descriptor addresses */
1069         if (priv->mode == STMMAC_CHAIN_MODE) {
1070                 if (priv->extend_desc) {
1071                         priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy,
1072                                              rxsize, 1);
1073                         priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy,
1074                                              txsize, 1);
1075                 } else {
1076                         priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy,
1077                                              rxsize, 0);
1078                         priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy,
1079                                              txsize, 0);
1080                 }
1081         }
1082
1083         /* TX INITIALIZATION */
1084         for (i = 0; i < txsize; i++) {
1085                 struct dma_desc *p;
1086                 if (priv->extend_desc)
1087                         p = &((priv->dma_etx + i)->basic);
1088                 else
1089                         p = priv->dma_tx + i;
1090                 p->des2 = 0;
1091                 priv->tx_skbuff_dma[i].buf = 0;
1092                 priv->tx_skbuff_dma[i].map_as_page = false;
1093                 priv->tx_skbuff[i] = NULL;
1094         }
1095
1096         priv->dirty_tx = 0;
1097         priv->cur_tx = 0;
1098         netdev_reset_queue(priv->dev);
1099
1100         stmmac_clear_descriptors(priv);
1101
1102         if (netif_msg_hw(priv))
1103                 stmmac_display_rings(priv);
1104
1105         return 0;
1106 err_init_rx_buffers:
1107         while (--i >= 0)
1108                 stmmac_free_rx_buffers(priv, i);
1109         return ret;
1110 }
1111
1112 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
1113 {
1114         int i;
1115
1116         for (i = 0; i < priv->dma_rx_size; i++)
1117                 stmmac_free_rx_buffers(priv, i);
1118 }
1119
1120 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
1121 {
1122         int i;
1123
1124         for (i = 0; i < priv->dma_tx_size; i++) {
1125                 struct dma_desc *p;
1126
1127                 if (priv->extend_desc)
1128                         p = &((priv->dma_etx + i)->basic);
1129                 else
1130                         p = priv->dma_tx + i;
1131
1132                 if (priv->tx_skbuff_dma[i].buf) {
1133                         if (priv->tx_skbuff_dma[i].map_as_page)
1134                                 dma_unmap_page(priv->device,
1135                                                priv->tx_skbuff_dma[i].buf,
1136                                                priv->hw->desc->get_tx_len(p),
1137                                                DMA_TO_DEVICE);
1138                         else
1139                                 dma_unmap_single(priv->device,
1140                                                  priv->tx_skbuff_dma[i].buf,
1141                                                  priv->hw->desc->get_tx_len(p),
1142                                                  DMA_TO_DEVICE);
1143                 }
1144
1145                 if (priv->tx_skbuff[i] != NULL) {
1146                         dev_kfree_skb_any(priv->tx_skbuff[i]);
1147                         priv->tx_skbuff[i] = NULL;
1148                         priv->tx_skbuff_dma[i].buf = 0;
1149                         priv->tx_skbuff_dma[i].map_as_page = false;
1150                 }
1151         }
1152 }
1153
1154 /**
1155  * alloc_dma_desc_resources - alloc TX/RX resources.
1156  * @priv: private structure
1157  * Description: according to which descriptor can be used (extend or basic)
1158  * this function allocates the resources for TX and RX paths. In case of
1159  * reception, for example, it pre-allocated the RX socket buffer in order to
1160  * allow zero-copy mechanism.
1161  */
1162 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1163 {
1164         unsigned int txsize = priv->dma_tx_size;
1165         unsigned int rxsize = priv->dma_rx_size;
1166         int ret = -ENOMEM;
1167
1168         priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t),
1169                                             GFP_KERNEL);
1170         if (!priv->rx_skbuff_dma)
1171                 return -ENOMEM;
1172
1173         priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *),
1174                                         GFP_KERNEL);
1175         if (!priv->rx_skbuff)
1176                 goto err_rx_skbuff;
1177
1178         priv->tx_skbuff_dma = kmalloc_array(txsize,
1179                                             sizeof(*priv->tx_skbuff_dma),
1180                                             GFP_KERNEL);
1181         if (!priv->tx_skbuff_dma)
1182                 goto err_tx_skbuff_dma;
1183
1184         priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *),
1185                                         GFP_KERNEL);
1186         if (!priv->tx_skbuff)
1187                 goto err_tx_skbuff;
1188
1189         if (priv->extend_desc) {
1190                 priv->dma_erx = dma_alloc_coherent(priv->device, rxsize *
1191                                                    sizeof(struct
1192                                                           dma_extended_desc),
1193                                                    &priv->dma_rx_phy,
1194                                                    GFP_KERNEL);
1195                 if (!priv->dma_erx)
1196                         goto err_dma;
1197
1198                 priv->dma_etx = dma_alloc_coherent(priv->device, txsize *
1199                                                    sizeof(struct
1200                                                           dma_extended_desc),
1201                                                    &priv->dma_tx_phy,
1202                                                    GFP_KERNEL);
1203                 if (!priv->dma_etx) {
1204                         dma_free_coherent(priv->device, priv->dma_rx_size *
1205                                         sizeof(struct dma_extended_desc),
1206                                         priv->dma_erx, priv->dma_rx_phy);
1207                         goto err_dma;
1208                 }
1209         } else {
1210                 priv->dma_rx = dma_alloc_coherent(priv->device, rxsize *
1211                                                   sizeof(struct dma_desc),
1212                                                   &priv->dma_rx_phy,
1213                                                   GFP_KERNEL);
1214                 if (!priv->dma_rx)
1215                         goto err_dma;
1216
1217                 priv->dma_tx = dma_alloc_coherent(priv->device, txsize *
1218                                                   sizeof(struct dma_desc),
1219                                                   &priv->dma_tx_phy,
1220                                                   GFP_KERNEL);
1221                 if (!priv->dma_tx) {
1222                         dma_free_coherent(priv->device, priv->dma_rx_size *
1223                                         sizeof(struct dma_desc),
1224                                         priv->dma_rx, priv->dma_rx_phy);
1225                         goto err_dma;
1226                 }
1227         }
1228
1229         return 0;
1230
1231 err_dma:
1232         kfree(priv->tx_skbuff);
1233 err_tx_skbuff:
1234         kfree(priv->tx_skbuff_dma);
1235 err_tx_skbuff_dma:
1236         kfree(priv->rx_skbuff);
1237 err_rx_skbuff:
1238         kfree(priv->rx_skbuff_dma);
1239         return ret;
1240 }
1241
1242 static void free_dma_desc_resources(struct stmmac_priv *priv)
1243 {
1244         /* Release the DMA TX/RX socket buffers */
1245         dma_free_rx_skbufs(priv);
1246         dma_free_tx_skbufs(priv);
1247
1248         /* Free DMA regions of consistent memory previously allocated */
1249         if (!priv->extend_desc) {
1250                 dma_free_coherent(priv->device,
1251                                   priv->dma_tx_size * sizeof(struct dma_desc),
1252                                   priv->dma_tx, priv->dma_tx_phy);
1253                 dma_free_coherent(priv->device,
1254                                   priv->dma_rx_size * sizeof(struct dma_desc),
1255                                   priv->dma_rx, priv->dma_rx_phy);
1256         } else {
1257                 dma_free_coherent(priv->device, priv->dma_tx_size *
1258                                   sizeof(struct dma_extended_desc),
1259                                   priv->dma_etx, priv->dma_tx_phy);
1260                 dma_free_coherent(priv->device, priv->dma_rx_size *
1261                                   sizeof(struct dma_extended_desc),
1262                                   priv->dma_erx, priv->dma_rx_phy);
1263         }
1264         kfree(priv->rx_skbuff_dma);
1265         kfree(priv->rx_skbuff);
1266         kfree(priv->tx_skbuff_dma);
1267         kfree(priv->tx_skbuff);
1268 }
1269
1270 /**
1271  *  stmmac_dma_operation_mode - HW DMA operation mode
1272  *  @priv: driver private structure
1273  *  Description: it is used for configuring the DMA operation mode register in
1274  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1275  */
1276 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1277 {
1278         int rxfifosz = priv->plat->rx_fifo_size;
1279
1280         if (priv->plat->force_thresh_dma_mode)
1281                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz);
1282         else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1283                 /*
1284                  * In case of GMAC, SF mode can be enabled
1285                  * to perform the TX COE in HW. This depends on:
1286                  * 1) TX COE if actually supported
1287                  * 2) There is no bugged Jumbo frame support
1288                  *    that needs to not insert csum in the TDES.
1289                  */
1290                 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE,
1291                                         rxfifosz);
1292                 priv->xstats.threshold = SF_DMA_MODE;
1293         } else
1294                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE,
1295                                         rxfifosz);
1296 }
1297
1298 /**
1299  * stmmac_tx_clean - to manage the transmission completion
1300  * @priv: driver private structure
1301  * Description: it reclaims the transmit resources after transmission completes.
1302  */
1303 static void stmmac_tx_clean(struct stmmac_priv *priv)
1304 {
1305         unsigned int txsize = priv->dma_tx_size;
1306         unsigned int bytes_compl = 0, pkts_compl = 0;
1307
1308         spin_lock(&priv->tx_lock);
1309
1310         priv->xstats.tx_clean++;
1311
1312         while (priv->dirty_tx != priv->cur_tx) {
1313                 int last;
1314                 unsigned int entry = priv->dirty_tx % txsize;
1315                 struct sk_buff *skb = priv->tx_skbuff[entry];
1316                 struct dma_desc *p;
1317
1318                 if (priv->extend_desc)
1319                         p = (struct dma_desc *)(priv->dma_etx + entry);
1320                 else
1321                         p = priv->dma_tx + entry;
1322
1323                 /* Check if the descriptor is owned by the DMA. */
1324                 if (priv->hw->desc->get_tx_owner(p))
1325                         break;
1326
1327                 /* Verify tx error by looking at the last segment. */
1328                 last = priv->hw->desc->get_tx_ls(p);
1329                 if (likely(last)) {
1330                         int tx_error =
1331                             priv->hw->desc->tx_status(&priv->dev->stats,
1332                                                       &priv->xstats, p,
1333                                                       priv->ioaddr);
1334                         if (likely(tx_error == 0)) {
1335                                 priv->dev->stats.tx_packets++;
1336                                 priv->xstats.tx_pkt_n++;
1337                         } else
1338                                 priv->dev->stats.tx_errors++;
1339
1340                         stmmac_get_tx_hwtstamp(priv, entry, skb);
1341                 }
1342                 if (netif_msg_tx_done(priv))
1343                         pr_debug("%s: curr %d, dirty %d\n", __func__,
1344                                  priv->cur_tx, priv->dirty_tx);
1345
1346                 if (likely(priv->tx_skbuff_dma[entry].buf)) {
1347                         if (priv->tx_skbuff_dma[entry].map_as_page)
1348                                 dma_unmap_page(priv->device,
1349                                                priv->tx_skbuff_dma[entry].buf,
1350                                                priv->hw->desc->get_tx_len(p),
1351                                                DMA_TO_DEVICE);
1352                         else
1353                                 dma_unmap_single(priv->device,
1354                                                  priv->tx_skbuff_dma[entry].buf,
1355                                                  priv->hw->desc->get_tx_len(p),
1356                                                  DMA_TO_DEVICE);
1357                         priv->tx_skbuff_dma[entry].buf = 0;
1358                         priv->tx_skbuff_dma[entry].map_as_page = false;
1359                 }
1360                 priv->hw->mode->clean_desc3(priv, p);
1361
1362                 if (likely(skb != NULL)) {
1363                         pkts_compl++;
1364                         bytes_compl += skb->len;
1365                         dev_consume_skb_any(skb);
1366                         priv->tx_skbuff[entry] = NULL;
1367                 }
1368
1369                 priv->hw->desc->release_tx_desc(p, priv->mode);
1370
1371                 priv->dirty_tx++;
1372         }
1373
1374         netdev_completed_queue(priv->dev, pkts_compl, bytes_compl);
1375
1376         if (unlikely(netif_queue_stopped(priv->dev) &&
1377                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
1378                 netif_tx_lock(priv->dev);
1379                 if (netif_queue_stopped(priv->dev) &&
1380                     stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
1381                         if (netif_msg_tx_done(priv))
1382                                 pr_debug("%s: restart transmit\n", __func__);
1383                         netif_wake_queue(priv->dev);
1384                 }
1385                 netif_tx_unlock(priv->dev);
1386         }
1387
1388         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1389                 stmmac_enable_eee_mode(priv);
1390                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1391         }
1392         spin_unlock(&priv->tx_lock);
1393 }
1394
1395 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
1396 {
1397         priv->hw->dma->enable_dma_irq(priv->ioaddr);
1398 }
1399
1400 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
1401 {
1402         priv->hw->dma->disable_dma_irq(priv->ioaddr);
1403 }
1404
1405 /**
1406  * stmmac_tx_err - to manage the tx error
1407  * @priv: driver private structure
1408  * Description: it cleans the descriptors and restarts the transmission
1409  * in case of transmission errors.
1410  */
1411 static void stmmac_tx_err(struct stmmac_priv *priv)
1412 {
1413         int i;
1414         int txsize = priv->dma_tx_size;
1415         netif_stop_queue(priv->dev);
1416
1417         priv->hw->dma->stop_tx(priv->ioaddr);
1418         dma_free_tx_skbufs(priv);
1419         for (i = 0; i < txsize; i++)
1420                 if (priv->extend_desc)
1421                         priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic,
1422                                                      priv->mode,
1423                                                      (i == txsize - 1));
1424                 else
1425                         priv->hw->desc->init_tx_desc(&priv->dma_tx[i],
1426                                                      priv->mode,
1427                                                      (i == txsize - 1));
1428         priv->dirty_tx = 0;
1429         priv->cur_tx = 0;
1430         netdev_reset_queue(priv->dev);
1431         priv->hw->dma->start_tx(priv->ioaddr);
1432
1433         priv->dev->stats.tx_errors++;
1434         netif_wake_queue(priv->dev);
1435 }
1436
1437 /**
1438  * stmmac_dma_interrupt - DMA ISR
1439  * @priv: driver private structure
1440  * Description: this is the DMA ISR. It is called by the main ISR.
1441  * It calls the dwmac dma routine and schedule poll method in case of some
1442  * work can be done.
1443  */
1444 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
1445 {
1446         int status;
1447         int rxfifosz = priv->plat->rx_fifo_size;
1448
1449         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
1450         if (likely((status & handle_rx)) || (status & handle_tx)) {
1451                 if (likely(napi_schedule_prep(&priv->napi))) {
1452                         stmmac_disable_dma_irq(priv);
1453                         __napi_schedule(&priv->napi);
1454                 }
1455         }
1456         if (unlikely(status & tx_hard_error_bump_tc)) {
1457                 /* Try to bump up the dma threshold on this failure */
1458                 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
1459                     (tc <= 256)) {
1460                         tc += 64;
1461                         if (priv->plat->force_thresh_dma_mode)
1462                                 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc,
1463                                                         rxfifosz);
1464                         else
1465                                 priv->hw->dma->dma_mode(priv->ioaddr, tc,
1466                                                         SF_DMA_MODE, rxfifosz);
1467                         priv->xstats.threshold = tc;
1468                 }
1469         } else if (unlikely(status == tx_hard_error))
1470                 stmmac_tx_err(priv);
1471 }
1472
1473 /**
1474  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
1475  * @priv: driver private structure
1476  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
1477  */
1478 static void stmmac_mmc_setup(struct stmmac_priv *priv)
1479 {
1480         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
1481             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
1482
1483         dwmac_mmc_intr_all_mask(priv->ioaddr);
1484
1485         if (priv->dma_cap.rmon) {
1486                 dwmac_mmc_ctrl(priv->ioaddr, mode);
1487                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
1488         } else
1489                 pr_info(" No MAC Management Counters available\n");
1490 }
1491
1492 /**
1493  * stmmac_get_synopsys_id - return the SYINID.
1494  * @priv: driver private structure
1495  * Description: this simple function is to decode and return the SYINID
1496  * starting from the HW core register.
1497  */
1498 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
1499 {
1500         u32 hwid = priv->hw->synopsys_uid;
1501
1502         /* Check Synopsys Id (not available on old chips) */
1503         if (likely(hwid)) {
1504                 u32 uid = ((hwid & 0x0000ff00) >> 8);
1505                 u32 synid = (hwid & 0x000000ff);
1506
1507                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
1508                         uid, synid);
1509
1510                 return synid;
1511         }
1512         return 0;
1513 }
1514
1515 /**
1516  * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors
1517  * @priv: driver private structure
1518  * Description: select the Enhanced/Alternate or Normal descriptors.
1519  * In case of Enhanced/Alternate, it checks if the extended descriptors are
1520  * supported by the HW capability register.
1521  */
1522 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
1523 {
1524         if (priv->plat->enh_desc) {
1525                 pr_info(" Enhanced/Alternate descriptors\n");
1526
1527                 /* GMAC older than 3.50 has no extended descriptors */
1528                 if (priv->synopsys_id >= DWMAC_CORE_3_50) {
1529                         pr_info("\tEnabled extended descriptors\n");
1530                         priv->extend_desc = 1;
1531                 } else
1532                         pr_warn("Extended descriptors not supported\n");
1533
1534                 priv->hw->desc = &enh_desc_ops;
1535         } else {
1536                 pr_info(" Normal descriptors\n");
1537                 priv->hw->desc = &ndesc_ops;
1538         }
1539 }
1540
1541 /**
1542  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
1543  * @priv: driver private structure
1544  * Description:
1545  *  new GMAC chip generations have a new register to indicate the
1546  *  presence of the optional feature/functions.
1547  *  This can be also used to override the value passed through the
1548  *  platform and necessary for old MAC10/100 and GMAC chips.
1549  */
1550 static int stmmac_get_hw_features(struct stmmac_priv *priv)
1551 {
1552         u32 hw_cap = 0;
1553
1554         if (priv->hw->dma->get_hw_feature) {
1555                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
1556
1557                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
1558                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
1559                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
1560                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
1561                 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5;
1562                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
1563                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
1564                 priv->dma_cap.pmt_remote_wake_up =
1565                     (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
1566                 priv->dma_cap.pmt_magic_frame =
1567                     (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
1568                 /* MMC */
1569                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
1570                 /* IEEE 1588-2002 */
1571                 priv->dma_cap.time_stamp =
1572                     (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
1573                 /* IEEE 1588-2008 */
1574                 priv->dma_cap.atime_stamp =
1575                     (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
1576                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
1577                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
1578                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
1579                 /* TX and RX csum */
1580                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
1581                 priv->dma_cap.rx_coe_type1 =
1582                     (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
1583                 priv->dma_cap.rx_coe_type2 =
1584                     (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
1585                 priv->dma_cap.rxfifo_over_2048 =
1586                     (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
1587                 /* TX and RX number of channels */
1588                 priv->dma_cap.number_rx_channel =
1589                     (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
1590                 priv->dma_cap.number_tx_channel =
1591                     (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
1592                 /* Alternate (enhanced) DESC mode */
1593                 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
1594         }
1595
1596         return hw_cap;
1597 }
1598
1599 /**
1600  * stmmac_check_ether_addr - check if the MAC addr is valid
1601  * @priv: driver private structure
1602  * Description:
1603  * it is to verify if the MAC address is valid, in case of failures it
1604  * generates a random MAC address
1605  */
1606 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
1607 {
1608         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
1609                 priv->hw->mac->get_umac_addr(priv->hw,
1610                                              priv->dev->dev_addr, 0);
1611                 if (!is_valid_ether_addr(priv->dev->dev_addr))
1612                         eth_hw_addr_random(priv->dev);
1613                 pr_info("%s: device MAC address %pM\n", priv->dev->name,
1614                         priv->dev->dev_addr);
1615         }
1616 }
1617
1618 /**
1619  * stmmac_init_dma_engine - DMA init.
1620  * @priv: driver private structure
1621  * Description:
1622  * It inits the DMA invoking the specific MAC/GMAC callback.
1623  * Some DMA parameters can be passed from the platform;
1624  * in case of these are not passed a default is kept for the MAC or GMAC.
1625  */
1626 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
1627 {
1628         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
1629         int mixed_burst = 0;
1630         int atds = 0;
1631
1632         if (priv->plat->dma_cfg) {
1633                 pbl = priv->plat->dma_cfg->pbl;
1634                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
1635                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
1636                 burst_len = priv->plat->dma_cfg->burst_len;
1637         }
1638
1639         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
1640                 atds = 1;
1641
1642         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
1643                                    burst_len, priv->dma_tx_phy,
1644                                    priv->dma_rx_phy, atds);
1645 }
1646
1647 /**
1648  * stmmac_tx_timer - mitigation sw timer for tx.
1649  * @data: data pointer
1650  * Description:
1651  * This is the timer handler to directly invoke the stmmac_tx_clean.
1652  */
1653 static void stmmac_tx_timer(unsigned long data)
1654 {
1655         struct stmmac_priv *priv = (struct stmmac_priv *)data;
1656
1657         stmmac_tx_clean(priv);
1658 }
1659
1660 /**
1661  * stmmac_init_tx_coalesce - init tx mitigation options.
1662  * @priv: driver private structure
1663  * Description:
1664  * This inits the transmit coalesce parameters: i.e. timer rate,
1665  * timer handler and default threshold used for enabling the
1666  * interrupt on completion bit.
1667  */
1668 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
1669 {
1670         priv->tx_coal_frames = STMMAC_TX_FRAMES;
1671         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
1672         init_timer(&priv->txtimer);
1673         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
1674         priv->txtimer.data = (unsigned long)priv;
1675         priv->txtimer.function = stmmac_tx_timer;
1676         add_timer(&priv->txtimer);
1677 }
1678
1679 /**
1680  * stmmac_hw_setup - setup mac in a usable state.
1681  *  @dev : pointer to the device structure.
1682  *  Description:
1683  *  this is the main function to setup the HW in a usable state because the
1684  *  dma engine is reset, the core registers are configured (e.g. AXI,
1685  *  Checksum features, timers). The DMA is ready to start receiving and
1686  *  transmitting.
1687  *  Return value:
1688  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1689  *  file on failure.
1690  */
1691 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
1692 {
1693         struct stmmac_priv *priv = netdev_priv(dev);
1694         int ret;
1695
1696         /* DMA initialization and SW reset */
1697         ret = stmmac_init_dma_engine(priv);
1698         if (ret < 0) {
1699                 pr_err("%s: DMA engine initialization failed\n", __func__);
1700                 return ret;
1701         }
1702
1703         /* Copy the MAC addr into the HW  */
1704         priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0);
1705
1706         /* If required, perform hw setup of the bus. */
1707         if (priv->plat->bus_setup)
1708                 priv->plat->bus_setup(priv->ioaddr);
1709
1710         /* Initialize the MAC Core */
1711         priv->hw->mac->core_init(priv->hw, dev->mtu);
1712
1713         ret = priv->hw->mac->rx_ipc(priv->hw);
1714         if (!ret) {
1715                 pr_warn(" RX IPC Checksum Offload disabled\n");
1716                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1717                 priv->hw->rx_csum = 0;
1718         }
1719
1720         /* Enable the MAC Rx/Tx */
1721         stmmac_set_mac(priv->ioaddr, true);
1722
1723         /* Set the HW DMA mode and the COE */
1724         stmmac_dma_operation_mode(priv);
1725
1726         stmmac_mmc_setup(priv);
1727
1728         if (init_ptp) {
1729                 ret = stmmac_init_ptp(priv);
1730                 if (ret && ret != -EOPNOTSUPP)
1731                         pr_warn("%s: failed PTP initialisation\n", __func__);
1732         }
1733
1734 #ifdef CONFIG_DEBUG_FS
1735         ret = stmmac_init_fs(dev);
1736         if (ret < 0)
1737                 pr_warn("%s: failed debugFS registration\n", __func__);
1738 #endif
1739         /* Start the ball rolling... */
1740         pr_debug("%s: DMA RX/TX processes started...\n", dev->name);
1741         priv->hw->dma->start_tx(priv->ioaddr);
1742         priv->hw->dma->start_rx(priv->ioaddr);
1743
1744         /* Dump DMA/MAC registers */
1745         if (netif_msg_hw(priv)) {
1746                 priv->hw->mac->dump_regs(priv->hw);
1747                 priv->hw->dma->dump_regs(priv->ioaddr);
1748         }
1749         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
1750
1751         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1752                 priv->rx_riwt = MAX_DMA_RIWT;
1753                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1754         }
1755
1756         if (priv->pcs && priv->hw->mac->ctrl_ane)
1757                 priv->hw->mac->ctrl_ane(priv->hw, 0);
1758
1759         return 0;
1760 }
1761
1762 /**
1763  *  stmmac_open - open entry point of the driver
1764  *  @dev : pointer to the device structure.
1765  *  Description:
1766  *  This function is the open entry point of the driver.
1767  *  Return value:
1768  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1769  *  file on failure.
1770  */
1771 static int stmmac_open(struct net_device *dev)
1772 {
1773         struct stmmac_priv *priv = netdev_priv(dev);
1774         int ret;
1775
1776         stmmac_check_ether_addr(priv);
1777
1778         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
1779             priv->pcs != STMMAC_PCS_RTBI) {
1780                 ret = stmmac_init_phy(dev);
1781                 if (ret) {
1782                         pr_err("%s: Cannot attach to PHY (error: %d)\n",
1783                                __func__, ret);
1784                         return ret;
1785                 }
1786         }
1787
1788         /* Extra statistics */
1789         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1790         priv->xstats.threshold = tc;
1791
1792         /* Create and initialize the TX/RX descriptors chains. */
1793         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1794         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1795         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1796
1797         ret = alloc_dma_desc_resources(priv);
1798         if (ret < 0) {
1799                 pr_err("%s: DMA descriptors allocation failed\n", __func__);
1800                 goto dma_desc_error;
1801         }
1802
1803         ret = init_dma_desc_rings(dev, GFP_KERNEL);
1804         if (ret < 0) {
1805                 pr_err("%s: DMA descriptors initialization failed\n", __func__);
1806                 goto init_error;
1807         }
1808
1809         ret = stmmac_hw_setup(dev, true);
1810         if (ret < 0) {
1811                 pr_err("%s: Hw setup failed\n", __func__);
1812                 goto init_error;
1813         }
1814
1815         stmmac_init_tx_coalesce(priv);
1816
1817         if (priv->phydev)
1818                 phy_start(priv->phydev);
1819
1820         /* Request the IRQ lines */
1821         ret = request_irq(dev->irq, stmmac_interrupt,
1822                           IRQF_SHARED, dev->name, dev);
1823         if (unlikely(ret < 0)) {
1824                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1825                        __func__, dev->irq, ret);
1826                 goto init_error;
1827         }
1828
1829         /* Request the Wake IRQ in case of another line is used for WoL */
1830         if (priv->wol_irq != dev->irq) {
1831                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1832                                   IRQF_SHARED, dev->name, dev);
1833                 if (unlikely(ret < 0)) {
1834                         pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n",
1835                                __func__, priv->wol_irq, ret);
1836                         goto wolirq_error;
1837                 }
1838         }
1839
1840         /* Request the IRQ lines */
1841         if (priv->lpi_irq > 0) {
1842                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1843                                   dev->name, dev);
1844                 if (unlikely(ret < 0)) {
1845                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1846                                __func__, priv->lpi_irq, ret);
1847                         goto lpiirq_error;
1848                 }
1849         }
1850
1851         napi_enable(&priv->napi);
1852         netif_start_queue(dev);
1853
1854         return 0;
1855
1856 lpiirq_error:
1857         if (priv->wol_irq != dev->irq)
1858                 free_irq(priv->wol_irq, dev);
1859 wolirq_error:
1860         free_irq(dev->irq, dev);
1861
1862 init_error:
1863         free_dma_desc_resources(priv);
1864 dma_desc_error:
1865         if (priv->phydev)
1866                 phy_disconnect(priv->phydev);
1867
1868         return ret;
1869 }
1870
1871 /**
1872  *  stmmac_release - close entry point of the driver
1873  *  @dev : device pointer.
1874  *  Description:
1875  *  This is the stop entry point of the driver.
1876  */
1877 static int stmmac_release(struct net_device *dev)
1878 {
1879         struct stmmac_priv *priv = netdev_priv(dev);
1880
1881         if (priv->eee_enabled)
1882                 del_timer_sync(&priv->eee_ctrl_timer);
1883
1884         /* Stop and disconnect the PHY */
1885         if (priv->phydev) {
1886                 phy_stop(priv->phydev);
1887                 phy_disconnect(priv->phydev);
1888                 priv->phydev = NULL;
1889         }
1890
1891         netif_stop_queue(dev);
1892
1893         napi_disable(&priv->napi);
1894
1895         del_timer_sync(&priv->txtimer);
1896
1897         /* Free the IRQ lines */
1898         free_irq(dev->irq, dev);
1899         if (priv->wol_irq != dev->irq)
1900                 free_irq(priv->wol_irq, dev);
1901         if (priv->lpi_irq > 0)
1902                 free_irq(priv->lpi_irq, dev);
1903
1904         /* Stop TX/RX DMA and clear the descriptors */
1905         priv->hw->dma->stop_tx(priv->ioaddr);
1906         priv->hw->dma->stop_rx(priv->ioaddr);
1907
1908         /* Release and free the Rx/Tx resources */
1909         free_dma_desc_resources(priv);
1910
1911         /* Disable the MAC Rx/Tx */
1912         stmmac_set_mac(priv->ioaddr, false);
1913
1914         netif_carrier_off(dev);
1915
1916 #ifdef CONFIG_DEBUG_FS
1917         stmmac_exit_fs();
1918 #endif
1919
1920         stmmac_release_ptp(priv);
1921
1922         return 0;
1923 }
1924
1925 /**
1926  *  stmmac_xmit - Tx entry point of the driver
1927  *  @skb : the socket buffer
1928  *  @dev : device pointer
1929  *  Description : this is the tx entry point of the driver.
1930  *  It programs the chain or the ring and supports oversized frames
1931  *  and SG feature.
1932  */
1933 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1934 {
1935         struct stmmac_priv *priv = netdev_priv(dev);
1936         unsigned int txsize = priv->dma_tx_size;
1937         unsigned int entry;
1938         int i, csum_insertion = 0, is_jumbo = 0;
1939         int nfrags = skb_shinfo(skb)->nr_frags;
1940         struct dma_desc *desc, *first;
1941         unsigned int nopaged_len = skb_headlen(skb);
1942         unsigned int enh_desc = priv->plat->enh_desc;
1943
1944         spin_lock(&priv->tx_lock);
1945
1946         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1947                 spin_unlock(&priv->tx_lock);
1948                 if (!netif_queue_stopped(dev)) {
1949                         netif_stop_queue(dev);
1950                         /* This is a hard error, log it. */
1951                         pr_err("%s: Tx Ring full when queue awake\n", __func__);
1952                 }
1953                 return NETDEV_TX_BUSY;
1954         }
1955
1956         if (priv->tx_path_in_lpi_mode)
1957                 stmmac_disable_eee_mode(priv);
1958
1959         entry = priv->cur_tx % txsize;
1960
1961         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1962
1963         if (priv->extend_desc)
1964                 desc = (struct dma_desc *)(priv->dma_etx + entry);
1965         else
1966                 desc = priv->dma_tx + entry;
1967
1968         first = desc;
1969
1970         /* To program the descriptors according to the size of the frame */
1971         if (enh_desc)
1972                 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc);
1973
1974         if (likely(!is_jumbo)) {
1975                 desc->des2 = dma_map_single(priv->device, skb->data,
1976                                             nopaged_len, DMA_TO_DEVICE);
1977                 if (dma_mapping_error(priv->device, desc->des2))
1978                         goto dma_map_err;
1979                 priv->tx_skbuff_dma[entry].buf = desc->des2;
1980                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1981                                                 csum_insertion, priv->mode);
1982         } else {
1983                 desc = first;
1984                 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion);
1985                 if (unlikely(entry < 0))
1986                         goto dma_map_err;
1987         }
1988
1989         for (i = 0; i < nfrags; i++) {
1990                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1991                 int len = skb_frag_size(frag);
1992
1993                 priv->tx_skbuff[entry] = NULL;
1994                 entry = (++priv->cur_tx) % txsize;
1995                 if (priv->extend_desc)
1996                         desc = (struct dma_desc *)(priv->dma_etx + entry);
1997                 else
1998                         desc = priv->dma_tx + entry;
1999
2000                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
2001                                               DMA_TO_DEVICE);
2002                 if (dma_mapping_error(priv->device, desc->des2))
2003                         goto dma_map_err; /* should reuse desc w/o issues */
2004
2005                 priv->tx_skbuff_dma[entry].buf = desc->des2;
2006                 priv->tx_skbuff_dma[entry].map_as_page = true;
2007                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion,
2008                                                 priv->mode);
2009                 wmb();
2010                 priv->hw->desc->set_tx_owner(desc);
2011                 wmb();
2012         }
2013
2014         priv->tx_skbuff[entry] = skb;
2015
2016         /* Finalize the latest segment. */
2017         priv->hw->desc->close_tx_desc(desc);
2018
2019         wmb();
2020         /* According to the coalesce parameter the IC bit for the latest
2021          * segment could be reset and the timer re-started to invoke the
2022          * stmmac_tx function. This approach takes care about the fragments.
2023          */
2024         priv->tx_count_frames += nfrags + 1;
2025         if (priv->tx_coal_frames > priv->tx_count_frames) {
2026                 priv->hw->desc->clear_tx_ic(desc);
2027                 priv->xstats.tx_reset_ic_bit++;
2028                 mod_timer(&priv->txtimer,
2029                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
2030         } else
2031                 priv->tx_count_frames = 0;
2032
2033         /* To avoid raise condition */
2034         priv->hw->desc->set_tx_owner(first);
2035         wmb();
2036
2037         priv->cur_tx++;
2038
2039         if (netif_msg_pktdata(priv)) {
2040                 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
2041                         __func__, (priv->cur_tx % txsize),
2042                         (priv->dirty_tx % txsize), entry, first, nfrags);
2043
2044                 if (priv->extend_desc)
2045                         stmmac_display_ring((void *)priv->dma_etx, txsize, 1);
2046                 else
2047                         stmmac_display_ring((void *)priv->dma_tx, txsize, 0);
2048
2049                 pr_debug(">>> frame to be transmitted: ");
2050                 print_pkt(skb->data, skb->len);
2051         }
2052         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
2053                 if (netif_msg_hw(priv))
2054                         pr_debug("%s: stop transmitted packets\n", __func__);
2055                 netif_stop_queue(dev);
2056         }
2057
2058         dev->stats.tx_bytes += skb->len;
2059
2060         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2061                      priv->hwts_tx_en)) {
2062                 /* declare that device is doing timestamping */
2063                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2064                 priv->hw->desc->enable_tx_timestamp(first);
2065         }
2066
2067         if (!priv->hwts_tx_en)
2068                 skb_tx_timestamp(skb);
2069
2070         netdev_sent_queue(dev, skb->len);
2071         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
2072
2073         spin_unlock(&priv->tx_lock);
2074         return NETDEV_TX_OK;
2075
2076 dma_map_err:
2077         spin_unlock(&priv->tx_lock);
2078         dev_err(priv->device, "Tx dma map failed\n");
2079         dev_kfree_skb(skb);
2080         priv->dev->stats.tx_dropped++;
2081         return NETDEV_TX_OK;
2082 }
2083
2084 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
2085 {
2086         struct ethhdr *ehdr;
2087         u16 vlanid;
2088
2089         if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) ==
2090             NETIF_F_HW_VLAN_CTAG_RX &&
2091             !__vlan_get_tag(skb, &vlanid)) {
2092                 /* pop the vlan tag */
2093                 ehdr = (struct ethhdr *)skb->data;
2094                 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
2095                 skb_pull(skb, VLAN_HLEN);
2096                 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
2097         }
2098 }
2099
2100
2101 /**
2102  * stmmac_rx_refill - refill used skb preallocated buffers
2103  * @priv: driver private structure
2104  * Description : this is to reallocate the skb for the reception process
2105  * that is based on zero-copy.
2106  */
2107 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
2108 {
2109         unsigned int rxsize = priv->dma_rx_size;
2110         int bfsize = priv->dma_buf_sz;
2111
2112         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
2113                 unsigned int entry = priv->dirty_rx % rxsize;
2114                 struct dma_desc *p;
2115
2116                 if (priv->extend_desc)
2117                         p = (struct dma_desc *)(priv->dma_erx + entry);
2118                 else
2119                         p = priv->dma_rx + entry;
2120
2121                 if (likely(priv->rx_skbuff[entry] == NULL)) {
2122                         struct sk_buff *skb;
2123
2124                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
2125
2126                         if (unlikely(skb == NULL))
2127                                 break;
2128
2129                         priv->rx_skbuff[entry] = skb;
2130                         priv->rx_skbuff_dma[entry] =
2131                             dma_map_single(priv->device, skb->data, bfsize,
2132                                            DMA_FROM_DEVICE);
2133                         if (dma_mapping_error(priv->device,
2134                                               priv->rx_skbuff_dma[entry])) {
2135                                 dev_err(priv->device, "Rx dma map failed\n");
2136                                 dev_kfree_skb(skb);
2137                                 break;
2138                         }
2139                         p->des2 = priv->rx_skbuff_dma[entry];
2140
2141                         priv->hw->mode->refill_desc3(priv, p);
2142
2143                         if (netif_msg_rx_status(priv))
2144                                 pr_debug("\trefill entry #%d\n", entry);
2145                 }
2146                 wmb();
2147                 priv->hw->desc->set_rx_owner(p);
2148                 wmb();
2149         }
2150 }
2151
2152 /**
2153  * stmmac_rx - manage the receive process
2154  * @priv: driver private structure
2155  * @limit: napi bugget.
2156  * Description :  this the function called by the napi poll method.
2157  * It gets all the frames inside the ring.
2158  */
2159 static int stmmac_rx(struct stmmac_priv *priv, int limit)
2160 {
2161         unsigned int rxsize = priv->dma_rx_size;
2162         unsigned int entry = priv->cur_rx % rxsize;
2163         unsigned int next_entry;
2164         unsigned int count = 0;
2165         int coe = priv->hw->rx_csum;
2166
2167         if (netif_msg_rx_status(priv)) {
2168                 pr_debug("%s: descriptor ring:\n", __func__);
2169                 if (priv->extend_desc)
2170                         stmmac_display_ring((void *)priv->dma_erx, rxsize, 1);
2171                 else
2172                         stmmac_display_ring((void *)priv->dma_rx, rxsize, 0);
2173         }
2174         while (count < limit) {
2175                 int status;
2176                 struct dma_desc *p;
2177
2178                 if (priv->extend_desc)
2179                         p = (struct dma_desc *)(priv->dma_erx + entry);
2180                 else
2181                         p = priv->dma_rx + entry;
2182
2183                 if (priv->hw->desc->get_rx_owner(p))
2184                         break;
2185
2186                 count++;
2187
2188                 next_entry = (++priv->cur_rx) % rxsize;
2189                 if (priv->extend_desc)
2190                         prefetch(priv->dma_erx + next_entry);
2191                 else
2192                         prefetch(priv->dma_rx + next_entry);
2193
2194                 /* read the status of the incoming frame */
2195                 status = priv->hw->desc->rx_status(&priv->dev->stats,
2196                                                    &priv->xstats, p);
2197                 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status))
2198                         priv->hw->desc->rx_extended_status(&priv->dev->stats,
2199                                                            &priv->xstats,
2200                                                            priv->dma_erx +
2201                                                            entry);
2202                 if (unlikely(status == discard_frame)) {
2203                         priv->dev->stats.rx_errors++;
2204                         if (priv->hwts_rx_en && !priv->extend_desc) {
2205                                 /* DESC2 & DESC3 will be overwitten by device
2206                                  * with timestamp value, hence reinitialize
2207                                  * them in stmmac_rx_refill() function so that
2208                                  * device can reuse it.
2209                                  */
2210                                 priv->rx_skbuff[entry] = NULL;
2211                                 dma_unmap_single(priv->device,
2212                                                  priv->rx_skbuff_dma[entry],
2213                                                  priv->dma_buf_sz,
2214                                                  DMA_FROM_DEVICE);
2215                         }
2216                 } else {
2217                         struct sk_buff *skb;
2218                         int frame_len;
2219
2220                         frame_len = priv->hw->desc->get_rx_frame_len(p, coe);
2221
2222                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
2223                          * Type frames (LLC/LLC-SNAP)
2224                          */
2225                         if (unlikely(status != llc_snap))
2226                                 frame_len -= ETH_FCS_LEN;
2227
2228                         if (netif_msg_rx_status(priv)) {
2229                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
2230                                          p, entry, p->des2);
2231                                 if (frame_len > ETH_FRAME_LEN)
2232                                         pr_debug("\tframe size %d, COE: %d\n",
2233                                                  frame_len, status);
2234                         }
2235                         skb = priv->rx_skbuff[entry];
2236                         if (unlikely(!skb)) {
2237                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
2238                                        priv->dev->name);
2239                                 priv->dev->stats.rx_dropped++;
2240                                 break;
2241                         }
2242                         prefetch(skb->data - NET_IP_ALIGN);
2243                         priv->rx_skbuff[entry] = NULL;
2244
2245                         stmmac_get_rx_hwtstamp(priv, entry, skb);
2246
2247                         skb_put(skb, frame_len);
2248                         dma_unmap_single(priv->device,
2249                                          priv->rx_skbuff_dma[entry],
2250                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
2251
2252                         if (netif_msg_pktdata(priv)) {
2253                                 pr_debug("frame received (%dbytes)", frame_len);
2254                                 print_pkt(skb->data, frame_len);
2255                         }
2256
2257                         stmmac_rx_vlan(priv->dev, skb);
2258
2259                         skb->protocol = eth_type_trans(skb, priv->dev);
2260
2261                         if (unlikely(!coe))
2262                                 skb_checksum_none_assert(skb);
2263                         else
2264                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
2265
2266                         napi_gro_receive(&priv->napi, skb);
2267
2268                         priv->dev->stats.rx_packets++;
2269                         priv->dev->stats.rx_bytes += frame_len;
2270                 }
2271                 entry = next_entry;
2272         }
2273
2274         stmmac_rx_refill(priv);
2275
2276         priv->xstats.rx_pkt_n += count;
2277
2278         return count;
2279 }
2280
2281 /**
2282  *  stmmac_poll - stmmac poll method (NAPI)
2283  *  @napi : pointer to the napi structure.
2284  *  @budget : maximum number of packets that the current CPU can receive from
2285  *            all interfaces.
2286  *  Description :
2287  *  To look at the incoming frames and clear the tx resources.
2288  */
2289 static int stmmac_poll(struct napi_struct *napi, int budget)
2290 {
2291         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
2292         int work_done = 0;
2293
2294         priv->xstats.napi_poll++;
2295         stmmac_tx_clean(priv);
2296
2297         work_done = stmmac_rx(priv, budget);
2298         if (work_done < budget) {
2299                 napi_complete(napi);
2300                 stmmac_enable_dma_irq(priv);
2301         }
2302         return work_done;
2303 }
2304
2305 /**
2306  *  stmmac_tx_timeout
2307  *  @dev : Pointer to net device structure
2308  *  Description: this function is called when a packet transmission fails to
2309  *   complete within a reasonable time. The driver will mark the error in the
2310  *   netdev structure and arrange for the device to be reset to a sane state
2311  *   in order to transmit a new packet.
2312  */
2313 static void stmmac_tx_timeout(struct net_device *dev)
2314 {
2315         struct stmmac_priv *priv = netdev_priv(dev);
2316
2317         /* Clear Tx resources and restart transmitting again */
2318         stmmac_tx_err(priv);
2319 }
2320
2321 /**
2322  *  stmmac_set_rx_mode - entry point for multicast addressing
2323  *  @dev : pointer to the device structure
2324  *  Description:
2325  *  This function is a driver entry point which gets called by the kernel
2326  *  whenever multicast addresses must be enabled/disabled.
2327  *  Return value:
2328  *  void.
2329  */
2330 static void stmmac_set_rx_mode(struct net_device *dev)
2331 {
2332         struct stmmac_priv *priv = netdev_priv(dev);
2333
2334         priv->hw->mac->set_filter(priv->hw, dev);
2335 }
2336
2337 /**
2338  *  stmmac_change_mtu - entry point to change MTU size for the device.
2339  *  @dev : device pointer.
2340  *  @new_mtu : the new MTU size for the device.
2341  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
2342  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
2343  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
2344  *  Return value:
2345  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2346  *  file on failure.
2347  */
2348 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
2349 {
2350         struct stmmac_priv *priv = netdev_priv(dev);
2351         int max_mtu;
2352
2353         if (netif_running(dev)) {
2354                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
2355                 return -EBUSY;
2356         }
2357
2358         if (priv->plat->enh_desc)
2359                 max_mtu = JUMBO_LEN;
2360         else
2361                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
2362
2363         if (priv->plat->maxmtu < max_mtu)
2364                 max_mtu = priv->plat->maxmtu;
2365
2366         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
2367                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
2368                 return -EINVAL;
2369         }
2370
2371         dev->mtu = new_mtu;
2372         netdev_update_features(dev);
2373
2374         return 0;
2375 }
2376
2377 static netdev_features_t stmmac_fix_features(struct net_device *dev,
2378                                              netdev_features_t features)
2379 {
2380         struct stmmac_priv *priv = netdev_priv(dev);
2381
2382         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
2383                 features &= ~NETIF_F_RXCSUM;
2384
2385         if (!priv->plat->tx_coe)
2386                 features &= ~NETIF_F_ALL_CSUM;
2387
2388         /* Some GMAC devices have a bugged Jumbo frame support that
2389          * needs to have the Tx COE disabled for oversized frames
2390          * (due to limited buffer sizes). In this case we disable
2391          * the TX csum insertionin the TDES and not use SF.
2392          */
2393         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
2394                 features &= ~NETIF_F_ALL_CSUM;
2395
2396         return features;
2397 }
2398
2399 static int stmmac_set_features(struct net_device *netdev,
2400                                netdev_features_t features)
2401 {
2402         struct stmmac_priv *priv = netdev_priv(netdev);
2403
2404         /* Keep the COE Type in case of csum is supporting */
2405         if (features & NETIF_F_RXCSUM)
2406                 priv->hw->rx_csum = priv->plat->rx_coe;
2407         else
2408                 priv->hw->rx_csum = 0;
2409         /* No check needed because rx_coe has been set before and it will be
2410          * fixed in case of issue.
2411          */
2412         priv->hw->mac->rx_ipc(priv->hw);
2413
2414         return 0;
2415 }
2416
2417 /**
2418  *  stmmac_interrupt - main ISR
2419  *  @irq: interrupt number.
2420  *  @dev_id: to pass the net device pointer.
2421  *  Description: this is the main driver interrupt service routine.
2422  *  It can call:
2423  *  o DMA service routine (to manage incoming frame reception and transmission
2424  *    status)
2425  *  o Core interrupts to manage: remote wake-up, management counter, LPI
2426  *    interrupts.
2427  */
2428 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
2429 {
2430         struct net_device *dev = (struct net_device *)dev_id;
2431         struct stmmac_priv *priv = netdev_priv(dev);
2432
2433         if (priv->irq_wake)
2434                 pm_wakeup_event(priv->device, 0);
2435
2436         if (unlikely(!dev)) {
2437                 pr_err("%s: invalid dev pointer\n", __func__);
2438                 return IRQ_NONE;
2439         }
2440
2441         /* To handle GMAC own interrupts */
2442         if (priv->plat->has_gmac) {
2443                 int status = priv->hw->mac->host_irq_status(priv->hw,
2444                                                             &priv->xstats);
2445                 if (unlikely(status)) {
2446                         /* For LPI we need to save the tx status */
2447                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
2448                                 priv->tx_path_in_lpi_mode = true;
2449                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
2450                                 priv->tx_path_in_lpi_mode = false;
2451                 }
2452         }
2453
2454         /* To handle DMA interrupts */
2455         stmmac_dma_interrupt(priv);
2456
2457         return IRQ_HANDLED;
2458 }
2459
2460 #ifdef CONFIG_NET_POLL_CONTROLLER
2461 /* Polling receive - used by NETCONSOLE and other diagnostic tools
2462  * to allow network I/O with interrupts disabled.
2463  */
2464 static void stmmac_poll_controller(struct net_device *dev)
2465 {
2466         disable_irq(dev->irq);
2467         stmmac_interrupt(dev->irq, dev);
2468         enable_irq(dev->irq);
2469 }
2470 #endif
2471
2472 /**
2473  *  stmmac_ioctl - Entry point for the Ioctl
2474  *  @dev: Device pointer.
2475  *  @rq: An IOCTL specefic structure, that can contain a pointer to
2476  *  a proprietary structure used to pass information to the driver.
2477  *  @cmd: IOCTL command
2478  *  Description:
2479  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
2480  */
2481 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2482 {
2483         struct stmmac_priv *priv = netdev_priv(dev);
2484         int ret = -EOPNOTSUPP;
2485
2486         if (!netif_running(dev))
2487                 return -EINVAL;
2488
2489         switch (cmd) {
2490         case SIOCGMIIPHY:
2491         case SIOCGMIIREG:
2492         case SIOCSMIIREG:
2493                 if (!priv->phydev)
2494                         return -EINVAL;
2495                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
2496                 break;
2497         case SIOCSHWTSTAMP:
2498                 ret = stmmac_hwtstamp_ioctl(dev, rq);
2499                 break;
2500         default:
2501                 break;
2502         }
2503
2504         return ret;
2505 }
2506
2507 #ifdef CONFIG_DEBUG_FS
2508 static struct dentry *stmmac_fs_dir;
2509 static struct dentry *stmmac_rings_status;
2510 static struct dentry *stmmac_dma_cap;
2511
2512 static void sysfs_display_ring(void *head, int size, int extend_desc,
2513                                struct seq_file *seq)
2514 {
2515         int i;
2516         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
2517         struct dma_desc *p = (struct dma_desc *)head;
2518
2519         for (i = 0; i < size; i++) {
2520                 u64 x;
2521                 if (extend_desc) {
2522                         x = *(u64 *) ep;
2523                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2524                                    i, (unsigned int)virt_to_phys(ep),
2525                                    (unsigned int)x, (unsigned int)(x >> 32),
2526                                    ep->basic.des2, ep->basic.des3);
2527                         ep++;
2528                 } else {
2529                         x = *(u64 *) p;
2530                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
2531                                    i, (unsigned int)virt_to_phys(ep),
2532                                    (unsigned int)x, (unsigned int)(x >> 32),
2533                                    p->des2, p->des3);
2534                         p++;
2535                 }
2536                 seq_printf(seq, "\n");
2537         }
2538 }
2539
2540 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
2541 {
2542         struct net_device *dev = seq->private;
2543         struct stmmac_priv *priv = netdev_priv(dev);
2544         unsigned int txsize = priv->dma_tx_size;
2545         unsigned int rxsize = priv->dma_rx_size;
2546
2547         if (priv->extend_desc) {
2548                 seq_printf(seq, "Extended RX descriptor ring:\n");
2549                 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq);
2550                 seq_printf(seq, "Extended TX descriptor ring:\n");
2551                 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq);
2552         } else {
2553                 seq_printf(seq, "RX descriptor ring:\n");
2554                 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq);
2555                 seq_printf(seq, "TX descriptor ring:\n");
2556                 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq);
2557         }
2558
2559         return 0;
2560 }
2561
2562 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
2563 {
2564         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
2565 }
2566
2567 static const struct file_operations stmmac_rings_status_fops = {
2568         .owner = THIS_MODULE,
2569         .open = stmmac_sysfs_ring_open,
2570         .read = seq_read,
2571         .llseek = seq_lseek,
2572         .release = single_release,
2573 };
2574
2575 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
2576 {
2577         struct net_device *dev = seq->private;
2578         struct stmmac_priv *priv = netdev_priv(dev);
2579
2580         if (!priv->hw_cap_support) {
2581                 seq_printf(seq, "DMA HW features not supported\n");
2582                 return 0;
2583         }
2584
2585         seq_printf(seq, "==============================\n");
2586         seq_printf(seq, "\tDMA HW features\n");
2587         seq_printf(seq, "==============================\n");
2588
2589         seq_printf(seq, "\t10/100 Mbps %s\n",
2590                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
2591         seq_printf(seq, "\t1000 Mbps %s\n",
2592                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
2593         seq_printf(seq, "\tHalf duple %s\n",
2594                    (priv->dma_cap.half_duplex) ? "Y" : "N");
2595         seq_printf(seq, "\tHash Filter: %s\n",
2596                    (priv->dma_cap.hash_filter) ? "Y" : "N");
2597         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
2598                    (priv->dma_cap.multi_addr) ? "Y" : "N");
2599         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
2600                    (priv->dma_cap.pcs) ? "Y" : "N");
2601         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
2602                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
2603         seq_printf(seq, "\tPMT Remote wake up: %s\n",
2604                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
2605         seq_printf(seq, "\tPMT Magic Frame: %s\n",
2606                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
2607         seq_printf(seq, "\tRMON module: %s\n",
2608                    (priv->dma_cap.rmon) ? "Y" : "N");
2609         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
2610                    (priv->dma_cap.time_stamp) ? "Y" : "N");
2611         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
2612                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
2613         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
2614                    (priv->dma_cap.eee) ? "Y" : "N");
2615         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
2616         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
2617                    (priv->dma_cap.tx_coe) ? "Y" : "N");
2618         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
2619                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
2620         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
2621                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
2622         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
2623                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
2624         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
2625                    priv->dma_cap.number_rx_channel);
2626         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
2627                    priv->dma_cap.number_tx_channel);
2628         seq_printf(seq, "\tEnhanced descriptors: %s\n",
2629                    (priv->dma_cap.enh_desc) ? "Y" : "N");
2630
2631         return 0;
2632 }
2633
2634 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
2635 {
2636         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
2637 }
2638
2639 static const struct file_operations stmmac_dma_cap_fops = {
2640         .owner = THIS_MODULE,
2641         .open = stmmac_sysfs_dma_cap_open,
2642         .read = seq_read,
2643         .llseek = seq_lseek,
2644         .release = single_release,
2645 };
2646
2647 static int stmmac_init_fs(struct net_device *dev)
2648 {
2649         /* Create debugfs entries */
2650         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
2651
2652         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
2653                 pr_err("ERROR %s, debugfs create directory failed\n",
2654                        STMMAC_RESOURCE_NAME);
2655
2656                 return -ENOMEM;
2657         }
2658
2659         /* Entry to report DMA RX/TX rings */
2660         stmmac_rings_status = debugfs_create_file("descriptors_status",
2661                                                   S_IRUGO, stmmac_fs_dir, dev,
2662                                                   &stmmac_rings_status_fops);
2663
2664         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
2665                 pr_info("ERROR creating stmmac ring debugfs file\n");
2666                 debugfs_remove(stmmac_fs_dir);
2667
2668                 return -ENOMEM;
2669         }
2670
2671         /* Entry to report the DMA HW features */
2672         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
2673                                              dev, &stmmac_dma_cap_fops);
2674
2675         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
2676                 pr_info("ERROR creating stmmac MMC debugfs file\n");
2677                 debugfs_remove(stmmac_rings_status);
2678                 debugfs_remove(stmmac_fs_dir);
2679
2680                 return -ENOMEM;
2681         }
2682
2683         return 0;
2684 }
2685
2686 static void stmmac_exit_fs(void)
2687 {
2688         debugfs_remove(stmmac_rings_status);
2689         debugfs_remove(stmmac_dma_cap);
2690         debugfs_remove(stmmac_fs_dir);
2691 }
2692 #endif /* CONFIG_DEBUG_FS */
2693
2694 static const struct net_device_ops stmmac_netdev_ops = {
2695         .ndo_open = stmmac_open,
2696         .ndo_start_xmit = stmmac_xmit,
2697         .ndo_stop = stmmac_release,
2698         .ndo_change_mtu = stmmac_change_mtu,
2699         .ndo_fix_features = stmmac_fix_features,
2700         .ndo_set_features = stmmac_set_features,
2701         .ndo_set_rx_mode = stmmac_set_rx_mode,
2702         .ndo_tx_timeout = stmmac_tx_timeout,
2703         .ndo_do_ioctl = stmmac_ioctl,
2704 #ifdef CONFIG_NET_POLL_CONTROLLER
2705         .ndo_poll_controller = stmmac_poll_controller,
2706 #endif
2707         .ndo_set_mac_address = eth_mac_addr,
2708 };
2709
2710 /**
2711  *  stmmac_hw_init - Init the MAC device
2712  *  @priv: driver private structure
2713  *  Description: this function is to configure the MAC device according to
2714  *  some platform parameters or the HW capability register. It prepares the
2715  *  driver to use either ring or chain modes and to setup either enhanced or
2716  *  normal descriptors.
2717  */
2718 static int stmmac_hw_init(struct stmmac_priv *priv)
2719 {
2720         struct mac_device_info *mac;
2721
2722         /* Identify the MAC HW device */
2723         if (priv->plat->has_gmac) {
2724                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
2725                 mac = dwmac1000_setup(priv->ioaddr,
2726                                       priv->plat->multicast_filter_bins,
2727                                       priv->plat->unicast_filter_entries);
2728         } else {
2729                 mac = dwmac100_setup(priv->ioaddr);
2730         }
2731         if (!mac)
2732                 return -ENOMEM;
2733
2734         priv->hw = mac;
2735
2736         /* Get and dump the chip ID */
2737         priv->synopsys_id = stmmac_get_synopsys_id(priv);
2738
2739         /* To use the chained or ring mode */
2740         if (chain_mode) {
2741                 priv->hw->mode = &chain_mode_ops;
2742                 pr_info(" Chain mode enabled\n");
2743                 priv->mode = STMMAC_CHAIN_MODE;
2744         } else {
2745                 priv->hw->mode = &ring_mode_ops;
2746                 pr_info(" Ring mode enabled\n");
2747                 priv->mode = STMMAC_RING_MODE;
2748         }
2749
2750         /* Get the HW capability (new GMAC newer than 3.50a) */
2751         priv->hw_cap_support = stmmac_get_hw_features(priv);
2752         if (priv->hw_cap_support) {
2753                 pr_info(" DMA HW capability register supported");
2754
2755                 /* We can override some gmac/dma configuration fields: e.g.
2756                  * enh_desc, tx_coe (e.g. that are passed through the
2757                  * platform) with the values from the HW capability
2758                  * register (if supported).
2759                  */
2760                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
2761                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
2762
2763                 /* TXCOE doesn't work in thresh DMA mode */
2764                 if (priv->plat->force_thresh_dma_mode)
2765                         priv->plat->tx_coe = 0;
2766                 else
2767                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
2768
2769                 if (priv->dma_cap.rx_coe_type2)
2770                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
2771                 else if (priv->dma_cap.rx_coe_type1)
2772                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
2773
2774         } else
2775                 pr_info(" No HW DMA feature register supported");
2776
2777         /* To use alternate (extended) or normal descriptor structures */
2778         stmmac_selec_desc_mode(priv);
2779
2780         if (priv->plat->rx_coe) {
2781                 priv->hw->rx_csum = priv->plat->rx_coe;
2782                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
2783                         priv->plat->rx_coe);
2784         }
2785         if (priv->plat->tx_coe)
2786                 pr_info(" TX Checksum insertion supported\n");
2787
2788         if (priv->plat->pmt) {
2789                 pr_info(" Wake-Up On Lan supported\n");
2790                 device_set_wakeup_capable(priv->device, 1);
2791         }
2792
2793         return 0;
2794 }
2795
2796 /**
2797  * stmmac_dvr_probe
2798  * @device: device pointer
2799  * @plat_dat: platform data pointer
2800  * @res: stmmac resource pointer
2801  * Description: this is the main probe function used to
2802  * call the alloc_etherdev, allocate the priv structure.
2803  * Return:
2804  * returns 0 on success, otherwise errno.
2805  */
2806 int stmmac_dvr_probe(struct device *device,
2807                      struct plat_stmmacenet_data *plat_dat,
2808                      struct stmmac_resources *res)
2809 {
2810         int ret = 0;
2811         struct net_device *ndev = NULL;
2812         struct stmmac_priv *priv;
2813
2814         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
2815         if (!ndev)
2816                 return -ENOMEM;
2817
2818         SET_NETDEV_DEV(ndev, device);
2819
2820         priv = netdev_priv(ndev);
2821         priv->device = device;
2822         priv->dev = ndev;
2823
2824         stmmac_set_ethtool_ops(ndev);
2825         priv->pause = pause;
2826         priv->plat = plat_dat;
2827         priv->ioaddr = res->addr;
2828         priv->dev->base_addr = (unsigned long)res->addr;
2829
2830         priv->dev->irq = res->irq;
2831         priv->wol_irq = res->wol_irq;
2832         priv->lpi_irq = res->lpi_irq;
2833
2834         if (res->mac)
2835                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
2836
2837         dev_set_drvdata(device, priv);
2838
2839         /* Verify driver arguments */
2840         stmmac_verify_args();
2841
2842         /* Override with kernel parameters if supplied XXX CRS XXX
2843          * this needs to have multiple instances
2844          */
2845         if ((phyaddr >= 0) && (phyaddr <= 31))
2846                 priv->plat->phy_addr = phyaddr;
2847
2848         priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME);
2849         if (IS_ERR(priv->stmmac_clk)) {
2850                 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n",
2851                          __func__);
2852                 /* If failed to obtain stmmac_clk and specific clk_csr value
2853                  * is NOT passed from the platform, probe fail.
2854                  */
2855                 if (!priv->plat->clk_csr) {
2856                         ret = PTR_ERR(priv->stmmac_clk);
2857                         goto error_clk_get;
2858                 } else {
2859                         priv->stmmac_clk = NULL;
2860                 }
2861         }
2862         clk_prepare_enable(priv->stmmac_clk);
2863
2864         priv->pclk = devm_clk_get(priv->device, "pclk");
2865         if (IS_ERR(priv->pclk)) {
2866                 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
2867                         ret = -EPROBE_DEFER;
2868                         goto error_pclk_get;
2869                 }
2870                 priv->pclk = NULL;
2871         }
2872         clk_prepare_enable(priv->pclk);
2873
2874         priv->stmmac_rst = devm_reset_control_get(priv->device,
2875                                                   STMMAC_RESOURCE_NAME);
2876         if (IS_ERR(priv->stmmac_rst)) {
2877                 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) {
2878                         ret = -EPROBE_DEFER;
2879                         goto error_hw_init;
2880                 }
2881                 dev_info(priv->device, "no reset control found\n");
2882                 priv->stmmac_rst = NULL;
2883         }
2884         if (priv->stmmac_rst)
2885                 reset_control_deassert(priv->stmmac_rst);
2886
2887         /* Init MAC and get the capabilities */
2888         ret = stmmac_hw_init(priv);
2889         if (ret)
2890                 goto error_hw_init;
2891
2892         ndev->netdev_ops = &stmmac_netdev_ops;
2893
2894         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2895                             NETIF_F_RXCSUM;
2896         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2897         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
2898 #ifdef STMMAC_VLAN_TAG_USED
2899         /* Both mac100 and gmac support receive VLAN tag detection */
2900         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX;
2901 #endif
2902         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2903
2904         if (flow_ctrl)
2905                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2906
2907         /* Rx Watchdog is available in the COREs newer than the 3.40.
2908          * In some case, for example on bugged HW this feature
2909          * has to be disable and this can be done by passing the
2910          * riwt_off field from the platform.
2911          */
2912         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2913                 priv->use_riwt = 1;
2914                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2915         }
2916
2917         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2918
2919         spin_lock_init(&priv->lock);
2920         spin_lock_init(&priv->tx_lock);
2921
2922         ret = register_netdev(ndev);
2923         if (ret) {
2924                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2925                 goto error_netdev_register;
2926         }
2927
2928         /* If a specific clk_csr value is passed from the platform
2929          * this means that the CSR Clock Range selection cannot be
2930          * changed at run-time and it is fixed. Viceversa the driver'll try to
2931          * set the MDC clock dynamically according to the csr actual
2932          * clock input.
2933          */
2934         if (!priv->plat->clk_csr)
2935                 stmmac_clk_csr_set(priv);
2936         else
2937                 priv->clk_csr = priv->plat->clk_csr;
2938
2939         stmmac_check_pcs_mode(priv);
2940
2941         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2942             priv->pcs != STMMAC_PCS_RTBI) {
2943                 /* MDIO bus Registration */
2944                 ret = stmmac_mdio_register(ndev);
2945                 if (ret < 0) {
2946                         pr_debug("%s: MDIO bus (id: %d) registration failed",
2947                                  __func__, priv->plat->bus_id);
2948                         goto error_mdio_register;
2949                 }
2950         }
2951
2952         return 0;
2953
2954 error_mdio_register:
2955         unregister_netdev(ndev);
2956 error_netdev_register:
2957         netif_napi_del(&priv->napi);
2958 error_hw_init:
2959         clk_disable_unprepare(priv->pclk);
2960 error_pclk_get:
2961         clk_disable_unprepare(priv->stmmac_clk);
2962 error_clk_get:
2963         free_netdev(ndev);
2964
2965         return ret;
2966 }
2967 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
2968
2969 /**
2970  * stmmac_dvr_remove
2971  * @ndev: net device pointer
2972  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2973  * changes the link status, releases the DMA descriptor rings.
2974  */
2975 int stmmac_dvr_remove(struct net_device *ndev)
2976 {
2977         struct stmmac_priv *priv = netdev_priv(ndev);
2978
2979         pr_info("%s:\n\tremoving driver", __func__);
2980
2981         priv->hw->dma->stop_rx(priv->ioaddr);
2982         priv->hw->dma->stop_tx(priv->ioaddr);
2983
2984         stmmac_set_mac(priv->ioaddr, false);
2985         netif_carrier_off(ndev);
2986         unregister_netdev(ndev);
2987         if (priv->stmmac_rst)
2988                 reset_control_assert(priv->stmmac_rst);
2989         clk_disable_unprepare(priv->pclk);
2990         clk_disable_unprepare(priv->stmmac_clk);
2991         if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI &&
2992             priv->pcs != STMMAC_PCS_RTBI)
2993                 stmmac_mdio_unregister(ndev);
2994         free_netdev(ndev);
2995
2996         return 0;
2997 }
2998 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
2999
3000 /**
3001  * stmmac_suspend - suspend callback
3002  * @ndev: net device pointer
3003  * Description: this is the function to suspend the device and it is called
3004  * by the platform driver to stop the network queue, release the resources,
3005  * program the PMT register (for WoL), clean and release driver resources.
3006  */
3007 int stmmac_suspend(struct net_device *ndev)
3008 {
3009         struct stmmac_priv *priv = netdev_priv(ndev);
3010         unsigned long flags;
3011
3012         if (!ndev || !netif_running(ndev))
3013                 return 0;
3014
3015         if (priv->phydev)
3016                 phy_stop(priv->phydev);
3017
3018         spin_lock_irqsave(&priv->lock, flags);
3019
3020         netif_device_detach(ndev);
3021         netif_stop_queue(ndev);
3022
3023         napi_disable(&priv->napi);
3024
3025         /* Stop TX/RX DMA */
3026         priv->hw->dma->stop_tx(priv->ioaddr);
3027         priv->hw->dma->stop_rx(priv->ioaddr);
3028
3029         stmmac_clear_descriptors(priv);
3030
3031         /* Enable Power down mode by programming the PMT regs */
3032         if (device_may_wakeup(priv->device)) {
3033                 priv->hw->mac->pmt(priv->hw, priv->wolopts);
3034                 priv->irq_wake = 1;
3035         } else {
3036                 stmmac_set_mac(priv->ioaddr, false);
3037                 pinctrl_pm_select_sleep_state(priv->device);
3038                 /* Disable clock in case of PWM is off */
3039                 clk_disable(priv->pclk);
3040                 clk_disable(priv->stmmac_clk);
3041         }
3042         spin_unlock_irqrestore(&priv->lock, flags);
3043
3044         priv->oldlink = 0;
3045         priv->speed = 0;
3046         priv->oldduplex = -1;
3047         return 0;
3048 }
3049 EXPORT_SYMBOL_GPL(stmmac_suspend);
3050
3051 /**
3052  * stmmac_resume - resume callback
3053  * @ndev: net device pointer
3054  * Description: when resume this function is invoked to setup the DMA and CORE
3055  * in a usable state.
3056  */
3057 int stmmac_resume(struct net_device *ndev)
3058 {
3059         struct stmmac_priv *priv = netdev_priv(ndev);
3060         unsigned long flags;
3061
3062         if (!netif_running(ndev))
3063                 return 0;
3064
3065         spin_lock_irqsave(&priv->lock, flags);
3066
3067         /* Power Down bit, into the PM register, is cleared
3068          * automatically as soon as a magic packet or a Wake-up frame
3069          * is received. Anyway, it's better to manually clear
3070          * this bit because it can generate problems while resuming
3071          * from another devices (e.g. serial console).
3072          */
3073         if (device_may_wakeup(priv->device)) {
3074                 priv->hw->mac->pmt(priv->hw, 0);
3075                 priv->irq_wake = 0;
3076         } else {
3077                 pinctrl_pm_select_default_state(priv->device);
3078                 /* enable the clk prevously disabled */
3079                 clk_enable(priv->stmmac_clk);
3080                 clk_enable(priv->pclk);
3081                 /* reset the phy so that it's ready */
3082                 if (priv->mii)
3083                         stmmac_mdio_reset(priv->mii);
3084         }
3085
3086         netif_device_attach(ndev);
3087
3088         init_dma_desc_rings(ndev, GFP_ATOMIC);
3089         stmmac_hw_setup(ndev, false);
3090         stmmac_init_tx_coalesce(priv);
3091
3092         napi_enable(&priv->napi);
3093
3094         netif_start_queue(ndev);
3095
3096         spin_unlock_irqrestore(&priv->lock, flags);
3097
3098         if (priv->phydev)
3099                 phy_start(priv->phydev);
3100
3101         return 0;
3102 }
3103 EXPORT_SYMBOL_GPL(stmmac_resume);
3104
3105 #ifndef MODULE
3106 static int __init stmmac_cmdline_opt(char *str)
3107 {
3108         char *opt;
3109
3110         if (!str || !*str)
3111                 return -EINVAL;
3112         while ((opt = strsep(&str, ",")) != NULL) {
3113                 if (!strncmp(opt, "debug:", 6)) {
3114                         if (kstrtoint(opt + 6, 0, &debug))
3115                                 goto err;
3116                 } else if (!strncmp(opt, "phyaddr:", 8)) {
3117                         if (kstrtoint(opt + 8, 0, &phyaddr))
3118                                 goto err;
3119                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
3120                         if (kstrtoint(opt + 11, 0, &dma_txsize))
3121                                 goto err;
3122                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
3123                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
3124                                 goto err;
3125                 } else if (!strncmp(opt, "buf_sz:", 7)) {
3126                         if (kstrtoint(opt + 7, 0, &buf_sz))
3127                                 goto err;
3128                 } else if (!strncmp(opt, "tc:", 3)) {
3129                         if (kstrtoint(opt + 3, 0, &tc))
3130                                 goto err;
3131                 } else if (!strncmp(opt, "watchdog:", 9)) {
3132                         if (kstrtoint(opt + 9, 0, &watchdog))
3133                                 goto err;
3134                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
3135                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
3136                                 goto err;
3137                 } else if (!strncmp(opt, "pause:", 6)) {
3138                         if (kstrtoint(opt + 6, 0, &pause))
3139                                 goto err;
3140                 } else if (!strncmp(opt, "eee_timer:", 10)) {
3141                         if (kstrtoint(opt + 10, 0, &eee_timer))
3142                                 goto err;
3143                 } else if (!strncmp(opt, "chain_mode:", 11)) {
3144                         if (kstrtoint(opt + 11, 0, &chain_mode))
3145                                 goto err;
3146                 }
3147         }
3148         return 0;
3149
3150 err:
3151         pr_err("%s: ERROR broken module parameter conversion", __func__);
3152         return -EINVAL;
3153 }
3154
3155 __setup("stmmaceth=", stmmac_cmdline_opt);
3156 #endif /* MODULE */
3157
3158 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
3159 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
3160 MODULE_LICENSE("GPL");