1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
4 ST Ethernet IPs are built around a Synopsys IP Core.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 Documentation available at:
12 http://www.stlinux.com
14 https://bugzilla.stlinux.com/
15 *******************************************************************************/
17 #include <linux/clk.h>
18 #include <linux/kernel.h>
19 #include <linux/interrupt.h>
21 #include <linux/tcp.h>
22 #include <linux/skbuff.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_ether.h>
25 #include <linux/crc32.h>
26 #include <linux/mii.h>
28 #include <linux/if_vlan.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/prefetch.h>
32 #include <linux/pinctrl/consumer.h>
33 #ifdef CONFIG_DEBUG_FS
34 #include <linux/debugfs.h>
35 #include <linux/seq_file.h>
36 #endif /* CONFIG_DEBUG_FS */
37 #include <linux/net_tstamp.h>
38 #include <linux/phylink.h>
39 #include <net/pkt_cls.h>
40 #include "stmmac_ptp.h"
42 #include <linux/reset.h>
43 #include <linux/of_mdio.h>
44 #include "dwmac1000.h"
48 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
49 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
51 /* Module parameters */
53 static int watchdog = TX_TIMEO;
54 module_param(watchdog, int, 0644);
55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
57 static int debug = -1;
58 module_param(debug, int, 0644);
59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
61 static int phyaddr = -1;
62 module_param(phyaddr, int, 0444);
63 MODULE_PARM_DESC(phyaddr, "Physical device address");
65 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
66 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
68 static int flow_ctrl = FLOW_AUTO;
69 module_param(flow_ctrl, int, 0644);
70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
72 static int pause = PAUSE_TIME;
73 module_param(pause, int, 0644);
74 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
77 static int tc = TC_DEFAULT;
78 module_param(tc, int, 0644);
79 MODULE_PARM_DESC(tc, "DMA threshold control value");
81 #define DEFAULT_BUFSIZE 1536
82 static int buf_sz = DEFAULT_BUFSIZE;
83 module_param(buf_sz, int, 0644);
84 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
86 #define STMMAC_RX_COPYBREAK 256
88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
89 NETIF_MSG_LINK | NETIF_MSG_IFUP |
90 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
92 #define STMMAC_DEFAULT_LPI_TIMER 1000
93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
94 module_param(eee_timer, int, 0644);
95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
98 /* By default the driver will use the ring mode to manage tx and rx descriptors,
99 * but allow user to force to use the chain instead of the ring
101 static unsigned int chain_mode;
102 module_param(chain_mode, int, 0444);
103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
107 #ifdef CONFIG_DEBUG_FS
108 static int stmmac_init_fs(struct net_device *dev);
109 static void stmmac_exit_fs(struct net_device *dev);
112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
115 * stmmac_verify_args - verify the driver parameters.
116 * Description: it checks the driver parameters and set a default in case of
119 static void stmmac_verify_args(void)
121 if (unlikely(watchdog < 0))
123 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
124 buf_sz = DEFAULT_BUFSIZE;
125 if (unlikely(flow_ctrl > 1))
126 flow_ctrl = FLOW_AUTO;
127 else if (likely(flow_ctrl < 0))
128 flow_ctrl = FLOW_OFF;
129 if (unlikely((pause < 0) || (pause > 0xffff)))
132 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
136 * stmmac_disable_all_queues - Disable all queues
137 * @priv: driver private structure
139 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
141 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
142 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
143 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
146 for (queue = 0; queue < maxq; queue++) {
147 struct stmmac_channel *ch = &priv->channel[queue];
149 if (queue < rx_queues_cnt)
150 napi_disable(&ch->rx_napi);
151 if (queue < tx_queues_cnt)
152 napi_disable(&ch->tx_napi);
157 * stmmac_enable_all_queues - Enable all queues
158 * @priv: driver private structure
160 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
162 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
163 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
164 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
167 for (queue = 0; queue < maxq; queue++) {
168 struct stmmac_channel *ch = &priv->channel[queue];
170 if (queue < rx_queues_cnt)
171 napi_enable(&ch->rx_napi);
172 if (queue < tx_queues_cnt)
173 napi_enable(&ch->tx_napi);
178 * stmmac_stop_all_queues - Stop all queues
179 * @priv: driver private structure
181 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
183 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
186 for (queue = 0; queue < tx_queues_cnt; queue++)
187 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
191 * stmmac_start_all_queues - Start all queues
192 * @priv: driver private structure
194 static void stmmac_start_all_queues(struct stmmac_priv *priv)
196 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
199 for (queue = 0; queue < tx_queues_cnt; queue++)
200 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
203 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
205 if (!test_bit(STMMAC_DOWN, &priv->state) &&
206 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
207 queue_work(priv->wq, &priv->service_task);
210 static void stmmac_global_err(struct stmmac_priv *priv)
212 netif_carrier_off(priv->dev);
213 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
214 stmmac_service_event_schedule(priv);
218 * stmmac_clk_csr_set - dynamically set the MDC clock
219 * @priv: driver private structure
220 * Description: this is to dynamically set the MDC clock according to the csr
223 * If a specific clk_csr value is passed from the platform
224 * this means that the CSR Clock Range selection cannot be
225 * changed at run-time and it is fixed (as reported in the driver
226 * documentation). Viceversa the driver will try to set the MDC
227 * clock dynamically according to the actual clock input.
229 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
233 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
235 /* Platform provided default clk_csr would be assumed valid
236 * for all other cases except for the below mentioned ones.
237 * For values higher than the IEEE 802.3 specified frequency
238 * we can not estimate the proper divider as it is not known
239 * the frequency of clk_csr_i. So we do not change the default
242 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
243 if (clk_rate < CSR_F_35M)
244 priv->clk_csr = STMMAC_CSR_20_35M;
245 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
246 priv->clk_csr = STMMAC_CSR_35_60M;
247 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
248 priv->clk_csr = STMMAC_CSR_60_100M;
249 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
250 priv->clk_csr = STMMAC_CSR_100_150M;
251 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
252 priv->clk_csr = STMMAC_CSR_150_250M;
253 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
254 priv->clk_csr = STMMAC_CSR_250_300M;
257 if (priv->plat->has_sun8i) {
258 if (clk_rate > 160000000)
259 priv->clk_csr = 0x03;
260 else if (clk_rate > 80000000)
261 priv->clk_csr = 0x02;
262 else if (clk_rate > 40000000)
263 priv->clk_csr = 0x01;
268 if (priv->plat->has_xgmac) {
269 if (clk_rate > 400000000)
271 else if (clk_rate > 350000000)
273 else if (clk_rate > 300000000)
275 else if (clk_rate > 250000000)
277 else if (clk_rate > 150000000)
284 static void print_pkt(unsigned char *buf, int len)
286 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
287 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
292 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
295 if (tx_q->dirty_tx > tx_q->cur_tx)
296 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
298 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
304 * stmmac_rx_dirty - Get RX queue dirty
305 * @priv: driver private structure
306 * @queue: RX queue index
308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
310 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
313 if (rx_q->dirty_rx <= rx_q->cur_rx)
314 dirty = rx_q->cur_rx - rx_q->dirty_rx;
316 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
322 * stmmac_enable_eee_mode - check and enter in LPI mode
323 * @priv: driver private structure
324 * Description: this function is to verify and enter in LPI mode in case of
327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
329 u32 tx_cnt = priv->plat->tx_queues_to_use;
332 /* check if all TX queues have the work finished */
333 for (queue = 0; queue < tx_cnt; queue++) {
334 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
336 if (tx_q->dirty_tx != tx_q->cur_tx)
337 return; /* still unfinished work */
340 /* Check and enter in LPI mode */
341 if (!priv->tx_path_in_lpi_mode)
342 stmmac_set_eee_mode(priv, priv->hw,
343 priv->plat->en_tx_lpi_clockgating);
347 * stmmac_disable_eee_mode - disable and exit from LPI mode
348 * @priv: driver private structure
349 * Description: this function is to exit and disable EEE in case of
350 * LPI state is true. This is called by the xmit.
352 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
354 stmmac_reset_eee_mode(priv, priv->hw);
355 del_timer_sync(&priv->eee_ctrl_timer);
356 priv->tx_path_in_lpi_mode = false;
360 * stmmac_eee_ctrl_timer - EEE TX SW timer.
363 * if there is no data transfer and if we are not in LPI state,
364 * then MAC Transmitter can be moved to LPI state.
366 static void stmmac_eee_ctrl_timer(struct timer_list *t)
368 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
370 stmmac_enable_eee_mode(priv);
371 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
375 * stmmac_eee_init - init EEE
376 * @priv: driver private structure
378 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
379 * can also manage EEE, this function enable the LPI state and start related
382 bool stmmac_eee_init(struct stmmac_priv *priv)
384 int tx_lpi_timer = priv->tx_lpi_timer;
386 /* Using PCS we cannot dial with the phy registers at this stage
387 * so we do not support extra feature like EEE.
389 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
390 (priv->hw->pcs == STMMAC_PCS_TBI) ||
391 (priv->hw->pcs == STMMAC_PCS_RTBI))
394 /* Check if MAC core supports the EEE feature. */
395 if (!priv->dma_cap.eee)
398 mutex_lock(&priv->lock);
400 /* Check if it needs to be deactivated */
401 if (!priv->eee_active) {
402 if (priv->eee_enabled) {
403 netdev_dbg(priv->dev, "disable EEE\n");
404 del_timer_sync(&priv->eee_ctrl_timer);
405 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
407 mutex_unlock(&priv->lock);
411 if (priv->eee_active && !priv->eee_enabled) {
412 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
413 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
414 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
418 mutex_unlock(&priv->lock);
419 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
424 * @priv: driver private structure
425 * @p : descriptor pointer
426 * @skb : the socket buffer
428 * This function will read timestamp from the descriptor & pass it to stack.
429 * and also perform some sanity checks.
431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
432 struct dma_desc *p, struct sk_buff *skb)
434 struct skb_shared_hwtstamps shhwtstamp;
437 if (!priv->hwts_tx_en)
440 /* exit if skb doesn't support hw tstamp */
441 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
444 /* check tx tstamp status */
445 if (stmmac_get_tx_timestamp_status(priv, p)) {
446 /* get the valid tstamp */
447 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
449 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
450 shhwtstamp.hwtstamp = ns_to_ktime(ns);
452 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
453 /* pass tstamp to stack */
454 skb_tstamp_tx(skb, &shhwtstamp);
460 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
461 * @priv: driver private structure
462 * @p : descriptor pointer
463 * @np : next descriptor pointer
464 * @skb : the socket buffer
466 * This function will read received packet's timestamp from the descriptor
467 * and pass it to stack. It also perform some sanity checks.
469 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
470 struct dma_desc *np, struct sk_buff *skb)
472 struct skb_shared_hwtstamps *shhwtstamp = NULL;
473 struct dma_desc *desc = p;
476 if (!priv->hwts_rx_en)
478 /* For GMAC4, the valid timestamp is from CTX next desc. */
479 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
482 /* Check if timestamp is available */
483 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
484 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
485 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
486 shhwtstamp = skb_hwtstamps(skb);
487 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
488 shhwtstamp->hwtstamp = ns_to_ktime(ns);
490 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
495 * stmmac_hwtstamp_set - control hardware timestamping.
496 * @dev: device pointer.
497 * @ifr: An IOCTL specific structure, that can contain a pointer to
498 * a proprietary structure used to pass information to the driver.
500 * This function configures the MAC to enable/disable both outgoing(TX)
501 * and incoming(RX) packets time stamping based on user input.
503 * 0 on success and an appropriate -ve integer on failure.
505 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
507 struct stmmac_priv *priv = netdev_priv(dev);
508 struct hwtstamp_config config;
509 struct timespec64 now;
513 u32 ptp_over_ipv4_udp = 0;
514 u32 ptp_over_ipv6_udp = 0;
515 u32 ptp_over_ethernet = 0;
516 u32 snap_type_sel = 0;
517 u32 ts_master_en = 0;
523 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
525 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
526 netdev_alert(priv->dev, "No support for HW time stamping\n");
527 priv->hwts_tx_en = 0;
528 priv->hwts_rx_en = 0;
533 if (copy_from_user(&config, ifr->ifr_data,
537 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
538 __func__, config.flags, config.tx_type, config.rx_filter);
540 /* reserved for future extensions */
544 if (config.tx_type != HWTSTAMP_TX_OFF &&
545 config.tx_type != HWTSTAMP_TX_ON)
549 switch (config.rx_filter) {
550 case HWTSTAMP_FILTER_NONE:
551 /* time stamp no incoming packet at all */
552 config.rx_filter = HWTSTAMP_FILTER_NONE;
555 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
556 /* PTP v1, UDP, any kind of event packet */
557 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
558 /* 'xmac' hardware can support Sync, Pdelay_Req and
559 * Pdelay_resp by setting bit14 and bits17/16 to 01
560 * This leaves Delay_Req timestamps out.
561 * Enable all events *and* general purpose message
564 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
565 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
566 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
569 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
570 /* PTP v1, UDP, Sync packet */
571 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
572 /* take time stamp for SYNC messages only */
573 ts_event_en = PTP_TCR_TSEVNTENA;
575 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
576 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
579 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
580 /* PTP v1, UDP, Delay_req packet */
581 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
582 /* take time stamp for Delay_Req messages only */
583 ts_master_en = PTP_TCR_TSMSTRENA;
584 ts_event_en = PTP_TCR_TSEVNTENA;
586 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
587 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
590 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
591 /* PTP v2, UDP, any kind of event packet */
592 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
593 ptp_v2 = PTP_TCR_TSVER2ENA;
594 /* take time stamp for all event messages */
595 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
597 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
598 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
601 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
602 /* PTP v2, UDP, Sync packet */
603 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
604 ptp_v2 = PTP_TCR_TSVER2ENA;
605 /* take time stamp for SYNC messages only */
606 ts_event_en = PTP_TCR_TSEVNTENA;
608 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
609 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
612 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
613 /* PTP v2, UDP, Delay_req packet */
614 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
615 ptp_v2 = PTP_TCR_TSVER2ENA;
616 /* take time stamp for Delay_Req messages only */
617 ts_master_en = PTP_TCR_TSMSTRENA;
618 ts_event_en = PTP_TCR_TSEVNTENA;
620 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
621 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
624 case HWTSTAMP_FILTER_PTP_V2_EVENT:
625 /* PTP v2/802.AS1 any layer, any kind of event packet */
626 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
627 ptp_v2 = PTP_TCR_TSVER2ENA;
628 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
629 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
630 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
631 ptp_over_ethernet = PTP_TCR_TSIPENA;
634 case HWTSTAMP_FILTER_PTP_V2_SYNC:
635 /* PTP v2/802.AS1, any layer, Sync packet */
636 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
637 ptp_v2 = PTP_TCR_TSVER2ENA;
638 /* take time stamp for SYNC messages only */
639 ts_event_en = PTP_TCR_TSEVNTENA;
641 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
642 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
643 ptp_over_ethernet = PTP_TCR_TSIPENA;
646 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
647 /* PTP v2/802.AS1, any layer, Delay_req packet */
648 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
649 ptp_v2 = PTP_TCR_TSVER2ENA;
650 /* take time stamp for Delay_Req messages only */
651 ts_master_en = PTP_TCR_TSMSTRENA;
652 ts_event_en = PTP_TCR_TSEVNTENA;
654 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
655 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
656 ptp_over_ethernet = PTP_TCR_TSIPENA;
659 case HWTSTAMP_FILTER_NTP_ALL:
660 case HWTSTAMP_FILTER_ALL:
661 /* time stamp any incoming packet */
662 config.rx_filter = HWTSTAMP_FILTER_ALL;
663 tstamp_all = PTP_TCR_TSENALL;
670 switch (config.rx_filter) {
671 case HWTSTAMP_FILTER_NONE:
672 config.rx_filter = HWTSTAMP_FILTER_NONE;
675 /* PTP v1, UDP, any kind of event packet */
676 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
680 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
681 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
683 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
684 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
686 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
687 tstamp_all | ptp_v2 | ptp_over_ethernet |
688 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
689 ts_master_en | snap_type_sel);
690 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
692 /* program Sub Second Increment reg */
693 stmmac_config_sub_second_increment(priv,
694 priv->ptpaddr, priv->plat->clk_ptp_rate,
696 temp = div_u64(1000000000ULL, sec_inc);
698 /* Store sub second increment and flags for later use */
699 priv->sub_second_inc = sec_inc;
700 priv->systime_flags = value;
702 /* calculate default added value:
704 * addend = (2^32)/freq_div_ratio;
705 * where, freq_div_ratio = 1e9ns/sec_inc
707 temp = (u64)(temp << 32);
708 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
709 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
711 /* initialize system time */
712 ktime_get_real_ts64(&now);
714 /* lower 32 bits of tv_sec are safe until y2106 */
715 stmmac_init_systime(priv, priv->ptpaddr,
716 (u32)now.tv_sec, now.tv_nsec);
719 memcpy(&priv->tstamp_config, &config, sizeof(config));
721 return copy_to_user(ifr->ifr_data, &config,
722 sizeof(config)) ? -EFAULT : 0;
726 * stmmac_hwtstamp_get - read hardware timestamping.
727 * @dev: device pointer.
728 * @ifr: An IOCTL specific structure, that can contain a pointer to
729 * a proprietary structure used to pass information to the driver.
731 * This function obtain the current hardware timestamping settings
734 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
736 struct stmmac_priv *priv = netdev_priv(dev);
737 struct hwtstamp_config *config = &priv->tstamp_config;
739 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
742 return copy_to_user(ifr->ifr_data, config,
743 sizeof(*config)) ? -EFAULT : 0;
747 * stmmac_init_ptp - init PTP
748 * @priv: driver private structure
749 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
750 * This is done by looking at the HW cap. register.
751 * This function also registers the ptp driver.
753 static int stmmac_init_ptp(struct stmmac_priv *priv)
755 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
757 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
761 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
762 if (xmac && priv->dma_cap.atime_stamp)
764 /* Dwmac 3.x core with extend_desc can support adv_ts */
765 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
768 if (priv->dma_cap.time_stamp)
769 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
772 netdev_info(priv->dev,
773 "IEEE 1588-2008 Advanced Timestamp supported\n");
775 priv->hwts_tx_en = 0;
776 priv->hwts_rx_en = 0;
778 stmmac_ptp_register(priv);
783 static void stmmac_release_ptp(struct stmmac_priv *priv)
785 if (priv->plat->clk_ptp_ref)
786 clk_disable_unprepare(priv->plat->clk_ptp_ref);
787 stmmac_ptp_unregister(priv);
791 * stmmac_mac_flow_ctrl - Configure flow control in all queues
792 * @priv: driver private structure
793 * Description: It is used for configuring the flow control in all queues
795 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
797 u32 tx_cnt = priv->plat->tx_queues_to_use;
799 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
800 priv->pause, tx_cnt);
803 static void stmmac_validate(struct phylink_config *config,
804 unsigned long *supported,
805 struct phylink_link_state *state)
807 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
808 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
809 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
810 int tx_cnt = priv->plat->tx_queues_to_use;
811 int max_speed = priv->plat->max_speed;
813 phylink_set(mac_supported, 10baseT_Half);
814 phylink_set(mac_supported, 10baseT_Full);
815 phylink_set(mac_supported, 100baseT_Half);
816 phylink_set(mac_supported, 100baseT_Full);
818 phylink_set(mac_supported, Autoneg);
819 phylink_set(mac_supported, Pause);
820 phylink_set(mac_supported, Asym_Pause);
821 phylink_set_port_modes(mac_supported);
823 if (priv->plat->has_gmac ||
824 priv->plat->has_gmac4 ||
825 priv->plat->has_xgmac) {
826 phylink_set(mac_supported, 1000baseT_Half);
827 phylink_set(mac_supported, 1000baseT_Full);
828 phylink_set(mac_supported, 1000baseKX_Full);
831 /* Cut down 1G if asked to */
832 if ((max_speed > 0) && (max_speed < 1000)) {
833 phylink_set(mask, 1000baseT_Full);
834 phylink_set(mask, 1000baseX_Full);
835 } else if (priv->plat->has_xgmac) {
836 phylink_set(mac_supported, 2500baseT_Full);
837 phylink_set(mac_supported, 5000baseT_Full);
838 phylink_set(mac_supported, 10000baseSR_Full);
839 phylink_set(mac_supported, 10000baseLR_Full);
840 phylink_set(mac_supported, 10000baseER_Full);
841 phylink_set(mac_supported, 10000baseLRM_Full);
842 phylink_set(mac_supported, 10000baseT_Full);
843 phylink_set(mac_supported, 10000baseKX4_Full);
844 phylink_set(mac_supported, 10000baseKR_Full);
847 /* Half-Duplex can only work with single queue */
849 phylink_set(mask, 10baseT_Half);
850 phylink_set(mask, 100baseT_Half);
851 phylink_set(mask, 1000baseT_Half);
854 bitmap_and(supported, supported, mac_supported,
855 __ETHTOOL_LINK_MODE_MASK_NBITS);
856 bitmap_andnot(supported, supported, mask,
857 __ETHTOOL_LINK_MODE_MASK_NBITS);
858 bitmap_and(state->advertising, state->advertising, mac_supported,
859 __ETHTOOL_LINK_MODE_MASK_NBITS);
860 bitmap_andnot(state->advertising, state->advertising, mask,
861 __ETHTOOL_LINK_MODE_MASK_NBITS);
864 static int stmmac_mac_link_state(struct phylink_config *config,
865 struct phylink_link_state *state)
870 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
871 const struct phylink_link_state *state)
873 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
876 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
877 ctrl &= ~priv->hw->link.speed_mask;
879 if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
880 switch (state->speed) {
882 ctrl |= priv->hw->link.xgmii.speed10000;
885 ctrl |= priv->hw->link.xgmii.speed5000;
888 ctrl |= priv->hw->link.xgmii.speed2500;
894 switch (state->speed) {
896 ctrl |= priv->hw->link.speed2500;
899 ctrl |= priv->hw->link.speed1000;
902 ctrl |= priv->hw->link.speed100;
905 ctrl |= priv->hw->link.speed10;
912 priv->speed = state->speed;
914 if (priv->plat->fix_mac_speed)
915 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed);
918 ctrl &= ~priv->hw->link.duplex;
920 ctrl |= priv->hw->link.duplex;
922 /* Flow Control operation */
924 stmmac_mac_flow_ctrl(priv, state->duplex);
926 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
929 static void stmmac_mac_an_restart(struct phylink_config *config)
934 static void stmmac_mac_link_down(struct phylink_config *config,
935 unsigned int mode, phy_interface_t interface)
937 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
939 stmmac_mac_set(priv, priv->ioaddr, false);
940 priv->eee_active = false;
941 stmmac_eee_init(priv);
942 stmmac_set_eee_pls(priv, priv->hw, false);
945 static void stmmac_mac_link_up(struct phylink_config *config,
946 unsigned int mode, phy_interface_t interface,
947 struct phy_device *phy)
949 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
951 stmmac_mac_set(priv, priv->ioaddr, true);
952 if (phy && priv->dma_cap.eee) {
953 priv->eee_active = phy_init_eee(phy, 1) >= 0;
954 priv->eee_enabled = stmmac_eee_init(priv);
955 stmmac_set_eee_pls(priv, priv->hw, true);
959 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
960 .validate = stmmac_validate,
961 .mac_link_state = stmmac_mac_link_state,
962 .mac_config = stmmac_mac_config,
963 .mac_an_restart = stmmac_mac_an_restart,
964 .mac_link_down = stmmac_mac_link_down,
965 .mac_link_up = stmmac_mac_link_up,
969 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
970 * @priv: driver private structure
971 * Description: this is to verify if the HW supports the PCS.
972 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
973 * configured for the TBI, RTBI, or SGMII PHY interface.
975 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
977 int interface = priv->plat->interface;
979 if (priv->dma_cap.pcs) {
980 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
981 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
982 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
983 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
984 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
985 priv->hw->pcs = STMMAC_PCS_RGMII;
986 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
987 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
988 priv->hw->pcs = STMMAC_PCS_SGMII;
994 * stmmac_init_phy - PHY initialization
995 * @dev: net device structure
996 * Description: it initializes the driver's PHY state, and attaches the PHY
1001 static int stmmac_init_phy(struct net_device *dev)
1003 struct stmmac_priv *priv = netdev_priv(dev);
1004 struct device_node *node;
1007 node = priv->plat->phylink_node;
1010 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1012 /* Some DT bindings do not set-up the PHY handle. Let's try to
1016 int addr = priv->plat->phy_addr;
1017 struct phy_device *phydev;
1019 phydev = mdiobus_get_phy(priv->mii, addr);
1021 netdev_err(priv->dev, "no phy at addr %d\n", addr);
1025 ret = phylink_connect_phy(priv->phylink, phydev);
1031 static int stmmac_phy_setup(struct stmmac_priv *priv)
1033 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1034 int mode = priv->plat->interface;
1035 struct phylink *phylink;
1037 priv->phylink_config.dev = &priv->dev->dev;
1038 priv->phylink_config.type = PHYLINK_NETDEV;
1040 phylink = phylink_create(&priv->phylink_config, fwnode,
1041 mode, &stmmac_phylink_mac_ops);
1042 if (IS_ERR(phylink))
1043 return PTR_ERR(phylink);
1045 priv->phylink = phylink;
1049 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1051 u32 rx_cnt = priv->plat->rx_queues_to_use;
1055 /* Display RX rings */
1056 for (queue = 0; queue < rx_cnt; queue++) {
1057 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1059 pr_info("\tRX Queue %u rings\n", queue);
1061 if (priv->extend_desc)
1062 head_rx = (void *)rx_q->dma_erx;
1064 head_rx = (void *)rx_q->dma_rx;
1066 /* Display RX ring */
1067 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1071 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1073 u32 tx_cnt = priv->plat->tx_queues_to_use;
1077 /* Display TX rings */
1078 for (queue = 0; queue < tx_cnt; queue++) {
1079 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1081 pr_info("\tTX Queue %d rings\n", queue);
1083 if (priv->extend_desc)
1084 head_tx = (void *)tx_q->dma_etx;
1086 head_tx = (void *)tx_q->dma_tx;
1088 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1092 static void stmmac_display_rings(struct stmmac_priv *priv)
1094 /* Display RX ring */
1095 stmmac_display_rx_rings(priv);
1097 /* Display TX ring */
1098 stmmac_display_tx_rings(priv);
1101 static int stmmac_set_bfsize(int mtu, int bufsize)
1105 if (mtu >= BUF_SIZE_4KiB)
1106 ret = BUF_SIZE_8KiB;
1107 else if (mtu >= BUF_SIZE_2KiB)
1108 ret = BUF_SIZE_4KiB;
1109 else if (mtu > DEFAULT_BUFSIZE)
1110 ret = BUF_SIZE_2KiB;
1112 ret = DEFAULT_BUFSIZE;
1118 * stmmac_clear_rx_descriptors - clear RX descriptors
1119 * @priv: driver private structure
1120 * @queue: RX queue index
1121 * Description: this function is called to clear the RX descriptors
1122 * in case of both basic and extended descriptors are used.
1124 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1126 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1129 /* Clear the RX descriptors */
1130 for (i = 0; i < DMA_RX_SIZE; i++)
1131 if (priv->extend_desc)
1132 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1133 priv->use_riwt, priv->mode,
1134 (i == DMA_RX_SIZE - 1),
1137 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1138 priv->use_riwt, priv->mode,
1139 (i == DMA_RX_SIZE - 1),
1144 * stmmac_clear_tx_descriptors - clear tx descriptors
1145 * @priv: driver private structure
1146 * @queue: TX queue index.
1147 * Description: this function is called to clear the TX descriptors
1148 * in case of both basic and extended descriptors are used.
1150 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1152 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1155 /* Clear the TX descriptors */
1156 for (i = 0; i < DMA_TX_SIZE; i++)
1157 if (priv->extend_desc)
1158 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1159 priv->mode, (i == DMA_TX_SIZE - 1));
1161 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1162 priv->mode, (i == DMA_TX_SIZE - 1));
1166 * stmmac_clear_descriptors - clear descriptors
1167 * @priv: driver private structure
1168 * Description: this function is called to clear the TX and RX descriptors
1169 * in case of both basic and extended descriptors are used.
1171 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1173 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1174 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1177 /* Clear the RX descriptors */
1178 for (queue = 0; queue < rx_queue_cnt; queue++)
1179 stmmac_clear_rx_descriptors(priv, queue);
1181 /* Clear the TX descriptors */
1182 for (queue = 0; queue < tx_queue_cnt; queue++)
1183 stmmac_clear_tx_descriptors(priv, queue);
1187 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1188 * @priv: driver private structure
1189 * @p: descriptor pointer
1190 * @i: descriptor index
1192 * @queue: RX queue index
1193 * Description: this function is called to allocate a receive buffer, perform
1194 * the DMA mapping and init the descriptor.
1196 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1197 int i, gfp_t flags, u32 queue)
1199 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1200 struct sk_buff *skb;
1202 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1204 netdev_err(priv->dev,
1205 "%s: Rx init fails; skb is NULL\n", __func__);
1208 rx_q->rx_skbuff[i] = skb;
1209 rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1212 if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1213 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1214 dev_kfree_skb_any(skb);
1218 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[i]);
1220 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1221 stmmac_init_desc3(priv, p);
1227 * stmmac_free_rx_buffer - free RX dma buffers
1228 * @priv: private structure
1229 * @queue: RX queue index
1232 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1234 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1236 if (rx_q->rx_skbuff[i]) {
1237 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1238 priv->dma_buf_sz, DMA_FROM_DEVICE);
1239 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1241 rx_q->rx_skbuff[i] = NULL;
1245 * stmmac_free_tx_buffer - free RX dma buffers
1246 * @priv: private structure
1247 * @queue: RX queue index
1250 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1252 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1254 if (tx_q->tx_skbuff_dma[i].buf) {
1255 if (tx_q->tx_skbuff_dma[i].map_as_page)
1256 dma_unmap_page(priv->device,
1257 tx_q->tx_skbuff_dma[i].buf,
1258 tx_q->tx_skbuff_dma[i].len,
1261 dma_unmap_single(priv->device,
1262 tx_q->tx_skbuff_dma[i].buf,
1263 tx_q->tx_skbuff_dma[i].len,
1267 if (tx_q->tx_skbuff[i]) {
1268 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1269 tx_q->tx_skbuff[i] = NULL;
1270 tx_q->tx_skbuff_dma[i].buf = 0;
1271 tx_q->tx_skbuff_dma[i].map_as_page = false;
1276 * init_dma_rx_desc_rings - init the RX descriptor rings
1277 * @dev: net device structure
1279 * Description: this function initializes the DMA RX descriptors
1280 * and allocates the socket buffers. It supports the chained and ring
1283 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1285 struct stmmac_priv *priv = netdev_priv(dev);
1286 u32 rx_count = priv->plat->rx_queues_to_use;
1292 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1296 if (bfsize < BUF_SIZE_16KiB)
1297 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1299 priv->dma_buf_sz = bfsize;
1301 /* RX INITIALIZATION */
1302 netif_dbg(priv, probe, priv->dev,
1303 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1305 for (queue = 0; queue < rx_count; queue++) {
1306 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1308 netif_dbg(priv, probe, priv->dev,
1309 "(%s) dma_rx_phy=0x%08x\n", __func__,
1310 (u32)rx_q->dma_rx_phy);
1312 for (i = 0; i < DMA_RX_SIZE; i++) {
1315 if (priv->extend_desc)
1316 p = &((rx_q->dma_erx + i)->basic);
1318 p = rx_q->dma_rx + i;
1320 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1323 goto err_init_rx_buffers;
1325 netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1326 rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1327 (unsigned int)rx_q->rx_skbuff_dma[i]);
1331 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1333 stmmac_clear_rx_descriptors(priv, queue);
1335 /* Setup the chained descriptor addresses */
1336 if (priv->mode == STMMAC_CHAIN_MODE) {
1337 if (priv->extend_desc)
1338 stmmac_mode_init(priv, rx_q->dma_erx,
1339 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1341 stmmac_mode_init(priv, rx_q->dma_rx,
1342 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1350 err_init_rx_buffers:
1351 while (queue >= 0) {
1353 stmmac_free_rx_buffer(priv, queue, i);
1366 * init_dma_tx_desc_rings - init the TX descriptor rings
1367 * @dev: net device structure.
1368 * Description: this function initializes the DMA TX descriptors
1369 * and allocates the socket buffers. It supports the chained and ring
1372 static int init_dma_tx_desc_rings(struct net_device *dev)
1374 struct stmmac_priv *priv = netdev_priv(dev);
1375 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1379 for (queue = 0; queue < tx_queue_cnt; queue++) {
1380 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1382 netif_dbg(priv, probe, priv->dev,
1383 "(%s) dma_tx_phy=0x%08x\n", __func__,
1384 (u32)tx_q->dma_tx_phy);
1386 /* Setup the chained descriptor addresses */
1387 if (priv->mode == STMMAC_CHAIN_MODE) {
1388 if (priv->extend_desc)
1389 stmmac_mode_init(priv, tx_q->dma_etx,
1390 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1392 stmmac_mode_init(priv, tx_q->dma_tx,
1393 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1396 for (i = 0; i < DMA_TX_SIZE; i++) {
1398 if (priv->extend_desc)
1399 p = &((tx_q->dma_etx + i)->basic);
1401 p = tx_q->dma_tx + i;
1403 stmmac_clear_desc(priv, p);
1405 tx_q->tx_skbuff_dma[i].buf = 0;
1406 tx_q->tx_skbuff_dma[i].map_as_page = false;
1407 tx_q->tx_skbuff_dma[i].len = 0;
1408 tx_q->tx_skbuff_dma[i].last_segment = false;
1409 tx_q->tx_skbuff[i] = NULL;
1416 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1423 * init_dma_desc_rings - init the RX/TX descriptor rings
1424 * @dev: net device structure
1426 * Description: this function initializes the DMA RX/TX descriptors
1427 * and allocates the socket buffers. It supports the chained and ring
1430 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1432 struct stmmac_priv *priv = netdev_priv(dev);
1435 ret = init_dma_rx_desc_rings(dev, flags);
1439 ret = init_dma_tx_desc_rings(dev);
1441 stmmac_clear_descriptors(priv);
1443 if (netif_msg_hw(priv))
1444 stmmac_display_rings(priv);
1450 * dma_free_rx_skbufs - free RX dma buffers
1451 * @priv: private structure
1452 * @queue: RX queue index
1454 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1458 for (i = 0; i < DMA_RX_SIZE; i++)
1459 stmmac_free_rx_buffer(priv, queue, i);
1463 * dma_free_tx_skbufs - free TX dma buffers
1464 * @priv: private structure
1465 * @queue: TX queue index
1467 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1471 for (i = 0; i < DMA_TX_SIZE; i++)
1472 stmmac_free_tx_buffer(priv, queue, i);
1476 * free_dma_rx_desc_resources - free RX dma desc resources
1477 * @priv: private structure
1479 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1481 u32 rx_count = priv->plat->rx_queues_to_use;
1484 /* Free RX queue resources */
1485 for (queue = 0; queue < rx_count; queue++) {
1486 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1488 /* Release the DMA RX socket buffers */
1489 dma_free_rx_skbufs(priv, queue);
1491 /* Free DMA regions of consistent memory previously allocated */
1492 if (!priv->extend_desc)
1493 dma_free_coherent(priv->device,
1494 DMA_RX_SIZE * sizeof(struct dma_desc),
1495 rx_q->dma_rx, rx_q->dma_rx_phy);
1497 dma_free_coherent(priv->device, DMA_RX_SIZE *
1498 sizeof(struct dma_extended_desc),
1499 rx_q->dma_erx, rx_q->dma_rx_phy);
1501 kfree(rx_q->rx_skbuff_dma);
1502 kfree(rx_q->rx_skbuff);
1507 * free_dma_tx_desc_resources - free TX dma desc resources
1508 * @priv: private structure
1510 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1512 u32 tx_count = priv->plat->tx_queues_to_use;
1515 /* Free TX queue resources */
1516 for (queue = 0; queue < tx_count; queue++) {
1517 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1519 /* Release the DMA TX socket buffers */
1520 dma_free_tx_skbufs(priv, queue);
1522 /* Free DMA regions of consistent memory previously allocated */
1523 if (!priv->extend_desc)
1524 dma_free_coherent(priv->device,
1525 DMA_TX_SIZE * sizeof(struct dma_desc),
1526 tx_q->dma_tx, tx_q->dma_tx_phy);
1528 dma_free_coherent(priv->device, DMA_TX_SIZE *
1529 sizeof(struct dma_extended_desc),
1530 tx_q->dma_etx, tx_q->dma_tx_phy);
1532 kfree(tx_q->tx_skbuff_dma);
1533 kfree(tx_q->tx_skbuff);
1538 * alloc_dma_rx_desc_resources - alloc RX resources.
1539 * @priv: private structure
1540 * Description: according to which descriptor can be used (extend or basic)
1541 * this function allocates the resources for TX and RX paths. In case of
1542 * reception, for example, it pre-allocated the RX socket buffer in order to
1543 * allow zero-copy mechanism.
1545 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1547 u32 rx_count = priv->plat->rx_queues_to_use;
1551 /* RX queues buffers and DMA */
1552 for (queue = 0; queue < rx_count; queue++) {
1553 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1555 rx_q->queue_index = queue;
1556 rx_q->priv_data = priv;
1558 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1561 if (!rx_q->rx_skbuff_dma)
1564 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1565 sizeof(struct sk_buff *),
1567 if (!rx_q->rx_skbuff)
1570 if (priv->extend_desc) {
1571 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1572 DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1579 rx_q->dma_rx = dma_alloc_coherent(priv->device,
1580 DMA_RX_SIZE * sizeof(struct dma_desc),
1591 free_dma_rx_desc_resources(priv);
1597 * alloc_dma_tx_desc_resources - alloc TX resources.
1598 * @priv: private structure
1599 * Description: according to which descriptor can be used (extend or basic)
1600 * this function allocates the resources for TX and RX paths. In case of
1601 * reception, for example, it pre-allocated the RX socket buffer in order to
1602 * allow zero-copy mechanism.
1604 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1606 u32 tx_count = priv->plat->tx_queues_to_use;
1610 /* TX queues buffers and DMA */
1611 for (queue = 0; queue < tx_count; queue++) {
1612 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1614 tx_q->queue_index = queue;
1615 tx_q->priv_data = priv;
1617 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1618 sizeof(*tx_q->tx_skbuff_dma),
1620 if (!tx_q->tx_skbuff_dma)
1623 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1624 sizeof(struct sk_buff *),
1626 if (!tx_q->tx_skbuff)
1629 if (priv->extend_desc) {
1630 tx_q->dma_etx = dma_alloc_coherent(priv->device,
1631 DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1637 tx_q->dma_tx = dma_alloc_coherent(priv->device,
1638 DMA_TX_SIZE * sizeof(struct dma_desc),
1649 free_dma_tx_desc_resources(priv);
1655 * alloc_dma_desc_resources - alloc TX/RX resources.
1656 * @priv: private structure
1657 * Description: according to which descriptor can be used (extend or basic)
1658 * this function allocates the resources for TX and RX paths. In case of
1659 * reception, for example, it pre-allocated the RX socket buffer in order to
1660 * allow zero-copy mechanism.
1662 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1665 int ret = alloc_dma_rx_desc_resources(priv);
1670 ret = alloc_dma_tx_desc_resources(priv);
1676 * free_dma_desc_resources - free dma desc resources
1677 * @priv: private structure
1679 static void free_dma_desc_resources(struct stmmac_priv *priv)
1681 /* Release the DMA RX socket buffers */
1682 free_dma_rx_desc_resources(priv);
1684 /* Release the DMA TX socket buffers */
1685 free_dma_tx_desc_resources(priv);
1689 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1690 * @priv: driver private structure
1691 * Description: It is used for enabling the rx queues in the MAC
1693 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1695 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1699 for (queue = 0; queue < rx_queues_count; queue++) {
1700 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1701 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1706 * stmmac_start_rx_dma - start RX DMA channel
1707 * @priv: driver private structure
1708 * @chan: RX channel index
1710 * This starts a RX DMA channel
1712 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1714 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1715 stmmac_start_rx(priv, priv->ioaddr, chan);
1719 * stmmac_start_tx_dma - start TX DMA channel
1720 * @priv: driver private structure
1721 * @chan: TX channel index
1723 * This starts a TX DMA channel
1725 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1727 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1728 stmmac_start_tx(priv, priv->ioaddr, chan);
1732 * stmmac_stop_rx_dma - stop RX DMA channel
1733 * @priv: driver private structure
1734 * @chan: RX channel index
1736 * This stops a RX DMA channel
1738 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1740 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1741 stmmac_stop_rx(priv, priv->ioaddr, chan);
1745 * stmmac_stop_tx_dma - stop TX DMA channel
1746 * @priv: driver private structure
1747 * @chan: TX channel index
1749 * This stops a TX DMA channel
1751 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1753 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1754 stmmac_stop_tx(priv, priv->ioaddr, chan);
1758 * stmmac_start_all_dma - start all RX and TX DMA channels
1759 * @priv: driver private structure
1761 * This starts all the RX and TX DMA channels
1763 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1765 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1766 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1769 for (chan = 0; chan < rx_channels_count; chan++)
1770 stmmac_start_rx_dma(priv, chan);
1772 for (chan = 0; chan < tx_channels_count; chan++)
1773 stmmac_start_tx_dma(priv, chan);
1777 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1778 * @priv: driver private structure
1780 * This stops the RX and TX DMA channels
1782 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1784 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1785 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1788 for (chan = 0; chan < rx_channels_count; chan++)
1789 stmmac_stop_rx_dma(priv, chan);
1791 for (chan = 0; chan < tx_channels_count; chan++)
1792 stmmac_stop_tx_dma(priv, chan);
1796 * stmmac_dma_operation_mode - HW DMA operation mode
1797 * @priv: driver private structure
1798 * Description: it is used for configuring the DMA operation mode register in
1799 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1801 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1803 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1804 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1805 int rxfifosz = priv->plat->rx_fifo_size;
1806 int txfifosz = priv->plat->tx_fifo_size;
1813 rxfifosz = priv->dma_cap.rx_fifo_size;
1815 txfifosz = priv->dma_cap.tx_fifo_size;
1817 /* Adjust for real per queue fifo size */
1818 rxfifosz /= rx_channels_count;
1819 txfifosz /= tx_channels_count;
1821 if (priv->plat->force_thresh_dma_mode) {
1824 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1826 * In case of GMAC, SF mode can be enabled
1827 * to perform the TX COE in HW. This depends on:
1828 * 1) TX COE if actually supported
1829 * 2) There is no bugged Jumbo frame support
1830 * that needs to not insert csum in the TDES.
1832 txmode = SF_DMA_MODE;
1833 rxmode = SF_DMA_MODE;
1834 priv->xstats.threshold = SF_DMA_MODE;
1837 rxmode = SF_DMA_MODE;
1840 /* configure all channels */
1841 for (chan = 0; chan < rx_channels_count; chan++) {
1842 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1844 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1846 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1850 for (chan = 0; chan < tx_channels_count; chan++) {
1851 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1853 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1859 * stmmac_tx_clean - to manage the transmission completion
1860 * @priv: driver private structure
1861 * @queue: TX queue index
1862 * Description: it reclaims the transmit resources after transmission completes.
1864 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1866 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1867 unsigned int bytes_compl = 0, pkts_compl = 0;
1868 unsigned int entry, count = 0;
1870 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1872 priv->xstats.tx_clean++;
1874 entry = tx_q->dirty_tx;
1875 while ((entry != tx_q->cur_tx) && (count < budget)) {
1876 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1880 if (priv->extend_desc)
1881 p = (struct dma_desc *)(tx_q->dma_etx + entry);
1883 p = tx_q->dma_tx + entry;
1885 status = stmmac_tx_status(priv, &priv->dev->stats,
1886 &priv->xstats, p, priv->ioaddr);
1887 /* Check if the descriptor is owned by the DMA */
1888 if (unlikely(status & tx_dma_own))
1893 /* Make sure descriptor fields are read after reading
1898 /* Just consider the last segment and ...*/
1899 if (likely(!(status & tx_not_ls))) {
1900 /* ... verify the status error condition */
1901 if (unlikely(status & tx_err)) {
1902 priv->dev->stats.tx_errors++;
1904 priv->dev->stats.tx_packets++;
1905 priv->xstats.tx_pkt_n++;
1907 stmmac_get_tx_hwtstamp(priv, p, skb);
1910 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1911 if (tx_q->tx_skbuff_dma[entry].map_as_page)
1912 dma_unmap_page(priv->device,
1913 tx_q->tx_skbuff_dma[entry].buf,
1914 tx_q->tx_skbuff_dma[entry].len,
1917 dma_unmap_single(priv->device,
1918 tx_q->tx_skbuff_dma[entry].buf,
1919 tx_q->tx_skbuff_dma[entry].len,
1921 tx_q->tx_skbuff_dma[entry].buf = 0;
1922 tx_q->tx_skbuff_dma[entry].len = 0;
1923 tx_q->tx_skbuff_dma[entry].map_as_page = false;
1926 stmmac_clean_desc3(priv, tx_q, p);
1928 tx_q->tx_skbuff_dma[entry].last_segment = false;
1929 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1931 if (likely(skb != NULL)) {
1933 bytes_compl += skb->len;
1934 dev_consume_skb_any(skb);
1935 tx_q->tx_skbuff[entry] = NULL;
1938 stmmac_release_tx_desc(priv, p, priv->mode);
1940 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1942 tx_q->dirty_tx = entry;
1944 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1945 pkts_compl, bytes_compl);
1947 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1949 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1951 netif_dbg(priv, tx_done, priv->dev,
1952 "%s: restart transmit\n", __func__);
1953 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1956 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1957 stmmac_enable_eee_mode(priv);
1958 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1961 /* We still have pending packets, let's call for a new scheduling */
1962 if (tx_q->dirty_tx != tx_q->cur_tx)
1963 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1965 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1971 * stmmac_tx_err - to manage the tx error
1972 * @priv: driver private structure
1973 * @chan: channel index
1974 * Description: it cleans the descriptors and restarts the transmission
1975 * in case of transmission errors.
1977 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1979 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1982 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1984 stmmac_stop_tx_dma(priv, chan);
1985 dma_free_tx_skbufs(priv, chan);
1986 for (i = 0; i < DMA_TX_SIZE; i++)
1987 if (priv->extend_desc)
1988 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1989 priv->mode, (i == DMA_TX_SIZE - 1));
1991 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1992 priv->mode, (i == DMA_TX_SIZE - 1));
1996 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
1997 stmmac_start_tx_dma(priv, chan);
1999 priv->dev->stats.tx_errors++;
2000 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2004 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2005 * @priv: driver private structure
2006 * @txmode: TX operating mode
2007 * @rxmode: RX operating mode
2008 * @chan: channel index
2009 * Description: it is used for configuring of the DMA operation mode in
2010 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2013 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2014 u32 rxmode, u32 chan)
2016 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2017 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2018 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2019 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2020 int rxfifosz = priv->plat->rx_fifo_size;
2021 int txfifosz = priv->plat->tx_fifo_size;
2024 rxfifosz = priv->dma_cap.rx_fifo_size;
2026 txfifosz = priv->dma_cap.tx_fifo_size;
2028 /* Adjust for real per queue fifo size */
2029 rxfifosz /= rx_channels_count;
2030 txfifosz /= tx_channels_count;
2032 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2033 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2036 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2040 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2041 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2042 if (ret && (ret != -EINVAL)) {
2043 stmmac_global_err(priv);
2050 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
2052 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2053 &priv->xstats, chan);
2054 struct stmmac_channel *ch = &priv->channel[chan];
2056 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2057 if (napi_schedule_prep(&ch->rx_napi)) {
2058 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2059 __napi_schedule_irqoff(&ch->rx_napi);
2060 status |= handle_tx;
2064 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use))
2065 napi_schedule_irqoff(&ch->tx_napi);
2071 * stmmac_dma_interrupt - DMA ISR
2072 * @priv: driver private structure
2073 * Description: this is the DMA ISR. It is called by the main ISR.
2074 * It calls the dwmac dma routine and schedule poll method in case of some
2077 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2079 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2080 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2081 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2082 tx_channel_count : rx_channel_count;
2084 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2086 /* Make sure we never check beyond our status buffer. */
2087 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2088 channels_to_check = ARRAY_SIZE(status);
2090 for (chan = 0; chan < channels_to_check; chan++)
2091 status[chan] = stmmac_napi_check(priv, chan);
2093 for (chan = 0; chan < tx_channel_count; chan++) {
2094 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2095 /* Try to bump up the dma threshold on this failure */
2096 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2099 if (priv->plat->force_thresh_dma_mode)
2100 stmmac_set_dma_operation_mode(priv,
2105 stmmac_set_dma_operation_mode(priv,
2109 priv->xstats.threshold = tc;
2111 } else if (unlikely(status[chan] == tx_hard_error)) {
2112 stmmac_tx_err(priv, chan);
2118 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2119 * @priv: driver private structure
2120 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2122 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2124 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2125 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2127 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2129 if (priv->dma_cap.rmon) {
2130 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2131 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2133 netdev_info(priv->dev, "No MAC Management Counters available\n");
2137 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2138 * @priv: driver private structure
2140 * new GMAC chip generations have a new register to indicate the
2141 * presence of the optional feature/functions.
2142 * This can be also used to override the value passed through the
2143 * platform and necessary for old MAC10/100 and GMAC chips.
2145 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2147 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2151 * stmmac_check_ether_addr - check if the MAC addr is valid
2152 * @priv: driver private structure
2154 * it is to verify if the MAC address is valid, in case of failures it
2155 * generates a random MAC address
2157 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2159 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2160 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2161 if (!is_valid_ether_addr(priv->dev->dev_addr))
2162 eth_hw_addr_random(priv->dev);
2163 dev_info(priv->device, "device MAC address %pM\n",
2164 priv->dev->dev_addr);
2169 * stmmac_init_dma_engine - DMA init.
2170 * @priv: driver private structure
2172 * It inits the DMA invoking the specific MAC/GMAC callback.
2173 * Some DMA parameters can be passed from the platform;
2174 * in case of these are not passed a default is kept for the MAC or GMAC.
2176 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2178 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2179 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2180 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2181 struct stmmac_rx_queue *rx_q;
2182 struct stmmac_tx_queue *tx_q;
2187 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2188 dev_err(priv->device, "Invalid DMA configuration\n");
2192 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2195 ret = stmmac_reset(priv, priv->ioaddr);
2197 dev_err(priv->device, "Failed to reset the dma\n");
2201 /* DMA Configuration */
2202 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2204 if (priv->plat->axi)
2205 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2207 /* DMA CSR Channel configuration */
2208 for (chan = 0; chan < dma_csr_ch; chan++)
2209 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2211 /* DMA RX Channel Configuration */
2212 for (chan = 0; chan < rx_channels_count; chan++) {
2213 rx_q = &priv->rx_queue[chan];
2215 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2216 rx_q->dma_rx_phy, chan);
2218 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2219 (DMA_RX_SIZE * sizeof(struct dma_desc));
2220 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2221 rx_q->rx_tail_addr, chan);
2224 /* DMA TX Channel Configuration */
2225 for (chan = 0; chan < tx_channels_count; chan++) {
2226 tx_q = &priv->tx_queue[chan];
2228 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2229 tx_q->dma_tx_phy, chan);
2231 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2232 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2233 tx_q->tx_tail_addr, chan);
2239 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2241 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2243 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2247 * stmmac_tx_timer - mitigation sw timer for tx.
2248 * @data: data pointer
2250 * This is the timer handler to directly invoke the stmmac_tx_clean.
2252 static void stmmac_tx_timer(struct timer_list *t)
2254 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2255 struct stmmac_priv *priv = tx_q->priv_data;
2256 struct stmmac_channel *ch;
2258 ch = &priv->channel[tx_q->queue_index];
2261 * If NAPI is already running we can miss some events. Let's rearm
2262 * the timer and try again.
2264 if (likely(napi_schedule_prep(&ch->tx_napi)))
2265 __napi_schedule(&ch->tx_napi);
2267 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2271 * stmmac_init_tx_coalesce - init tx mitigation options.
2272 * @priv: driver private structure
2274 * This inits the transmit coalesce parameters: i.e. timer rate,
2275 * timer handler and default threshold used for enabling the
2276 * interrupt on completion bit.
2278 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2280 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2283 priv->tx_coal_frames = STMMAC_TX_FRAMES;
2284 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2286 for (chan = 0; chan < tx_channel_count; chan++) {
2287 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2289 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2293 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2295 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2296 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2299 /* set TX ring length */
2300 for (chan = 0; chan < tx_channels_count; chan++)
2301 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2302 (DMA_TX_SIZE - 1), chan);
2304 /* set RX ring length */
2305 for (chan = 0; chan < rx_channels_count; chan++)
2306 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2307 (DMA_RX_SIZE - 1), chan);
2311 * stmmac_set_tx_queue_weight - Set TX queue weight
2312 * @priv: driver private structure
2313 * Description: It is used for setting TX queues weight
2315 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2317 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2321 for (queue = 0; queue < tx_queues_count; queue++) {
2322 weight = priv->plat->tx_queues_cfg[queue].weight;
2323 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2328 * stmmac_configure_cbs - Configure CBS in TX queue
2329 * @priv: driver private structure
2330 * Description: It is used for configuring CBS in AVB TX queues
2332 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2334 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2338 /* queue 0 is reserved for legacy traffic */
2339 for (queue = 1; queue < tx_queues_count; queue++) {
2340 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2341 if (mode_to_use == MTL_QUEUE_DCB)
2344 stmmac_config_cbs(priv, priv->hw,
2345 priv->plat->tx_queues_cfg[queue].send_slope,
2346 priv->plat->tx_queues_cfg[queue].idle_slope,
2347 priv->plat->tx_queues_cfg[queue].high_credit,
2348 priv->plat->tx_queues_cfg[queue].low_credit,
2354 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2355 * @priv: driver private structure
2356 * Description: It is used for mapping RX queues to RX dma channels
2358 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2360 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2364 for (queue = 0; queue < rx_queues_count; queue++) {
2365 chan = priv->plat->rx_queues_cfg[queue].chan;
2366 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2371 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2372 * @priv: driver private structure
2373 * Description: It is used for configuring the RX Queue Priority
2375 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2377 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2381 for (queue = 0; queue < rx_queues_count; queue++) {
2382 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2385 prio = priv->plat->rx_queues_cfg[queue].prio;
2386 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2391 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2392 * @priv: driver private structure
2393 * Description: It is used for configuring the TX Queue Priority
2395 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2397 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2401 for (queue = 0; queue < tx_queues_count; queue++) {
2402 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2405 prio = priv->plat->tx_queues_cfg[queue].prio;
2406 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2411 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2412 * @priv: driver private structure
2413 * Description: It is used for configuring the RX queue routing
2415 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2417 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2421 for (queue = 0; queue < rx_queues_count; queue++) {
2422 /* no specific packet type routing specified for the queue */
2423 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2426 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2427 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2432 * stmmac_mtl_configuration - Configure MTL
2433 * @priv: driver private structure
2434 * Description: It is used for configurring MTL
2436 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2438 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2439 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2441 if (tx_queues_count > 1)
2442 stmmac_set_tx_queue_weight(priv);
2444 /* Configure MTL RX algorithms */
2445 if (rx_queues_count > 1)
2446 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2447 priv->plat->rx_sched_algorithm);
2449 /* Configure MTL TX algorithms */
2450 if (tx_queues_count > 1)
2451 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2452 priv->plat->tx_sched_algorithm);
2454 /* Configure CBS in AVB TX queues */
2455 if (tx_queues_count > 1)
2456 stmmac_configure_cbs(priv);
2458 /* Map RX MTL to DMA channels */
2459 stmmac_rx_queue_dma_chan_map(priv);
2461 /* Enable MAC RX Queues */
2462 stmmac_mac_enable_rx_queues(priv);
2464 /* Set RX priorities */
2465 if (rx_queues_count > 1)
2466 stmmac_mac_config_rx_queues_prio(priv);
2468 /* Set TX priorities */
2469 if (tx_queues_count > 1)
2470 stmmac_mac_config_tx_queues_prio(priv);
2472 /* Set RX routing */
2473 if (rx_queues_count > 1)
2474 stmmac_mac_config_rx_queues_routing(priv);
2477 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2479 if (priv->dma_cap.asp) {
2480 netdev_info(priv->dev, "Enabling Safety Features\n");
2481 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2483 netdev_info(priv->dev, "No Safety Features support found\n");
2488 * stmmac_hw_setup - setup mac in a usable state.
2489 * @dev : pointer to the device structure.
2491 * this is the main function to setup the HW in a usable state because the
2492 * dma engine is reset, the core registers are configured (e.g. AXI,
2493 * Checksum features, timers). The DMA is ready to start receiving and
2496 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2499 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2501 struct stmmac_priv *priv = netdev_priv(dev);
2502 u32 rx_cnt = priv->plat->rx_queues_to_use;
2503 u32 tx_cnt = priv->plat->tx_queues_to_use;
2507 /* DMA initialization and SW reset */
2508 ret = stmmac_init_dma_engine(priv);
2510 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2515 /* Copy the MAC addr into the HW */
2516 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2518 /* PS and related bits will be programmed according to the speed */
2519 if (priv->hw->pcs) {
2520 int speed = priv->plat->mac_port_sel_speed;
2522 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2523 (speed == SPEED_1000)) {
2524 priv->hw->ps = speed;
2526 dev_warn(priv->device, "invalid port speed\n");
2531 /* Initialize the MAC Core */
2532 stmmac_core_init(priv, priv->hw, dev);
2535 stmmac_mtl_configuration(priv);
2537 /* Initialize Safety Features */
2538 stmmac_safety_feat_configuration(priv);
2540 ret = stmmac_rx_ipc(priv, priv->hw);
2542 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2543 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2544 priv->hw->rx_csum = 0;
2547 /* Enable the MAC Rx/Tx */
2548 stmmac_mac_set(priv, priv->ioaddr, true);
2550 /* Set the HW DMA mode and the COE */
2551 stmmac_dma_operation_mode(priv);
2553 stmmac_mmc_setup(priv);
2556 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2558 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2560 ret = stmmac_init_ptp(priv);
2561 if (ret == -EOPNOTSUPP)
2562 netdev_warn(priv->dev, "PTP not supported by HW\n");
2564 netdev_warn(priv->dev, "PTP init failed\n");
2567 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2569 if (priv->use_riwt) {
2570 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MIN_DMA_RIWT, rx_cnt);
2572 priv->rx_riwt = MIN_DMA_RIWT;
2576 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2578 /* set TX and RX rings length */
2579 stmmac_set_rings_length(priv);
2583 for (chan = 0; chan < tx_cnt; chan++)
2584 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2587 /* Start the ball rolling... */
2588 stmmac_start_all_dma(priv);
2593 static void stmmac_hw_teardown(struct net_device *dev)
2595 struct stmmac_priv *priv = netdev_priv(dev);
2597 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2601 * stmmac_open - open entry point of the driver
2602 * @dev : pointer to the device structure.
2604 * This function is the open entry point of the driver.
2606 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2609 static int stmmac_open(struct net_device *dev)
2611 struct stmmac_priv *priv = netdev_priv(dev);
2615 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2616 priv->hw->pcs != STMMAC_PCS_TBI &&
2617 priv->hw->pcs != STMMAC_PCS_RTBI) {
2618 ret = stmmac_init_phy(dev);
2620 netdev_err(priv->dev,
2621 "%s: Cannot attach to PHY (error: %d)\n",
2627 /* Extra statistics */
2628 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2629 priv->xstats.threshold = tc;
2631 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2632 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2634 ret = alloc_dma_desc_resources(priv);
2636 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2638 goto dma_desc_error;
2641 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2643 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2648 ret = stmmac_hw_setup(dev, true);
2650 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2654 stmmac_init_tx_coalesce(priv);
2656 phylink_start(priv->phylink);
2658 /* Request the IRQ lines */
2659 ret = request_irq(dev->irq, stmmac_interrupt,
2660 IRQF_SHARED, dev->name, dev);
2661 if (unlikely(ret < 0)) {
2662 netdev_err(priv->dev,
2663 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2664 __func__, dev->irq, ret);
2668 /* Request the Wake IRQ in case of another line is used for WoL */
2669 if (priv->wol_irq != dev->irq) {
2670 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2671 IRQF_SHARED, dev->name, dev);
2672 if (unlikely(ret < 0)) {
2673 netdev_err(priv->dev,
2674 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2675 __func__, priv->wol_irq, ret);
2680 /* Request the IRQ lines */
2681 if (priv->lpi_irq > 0) {
2682 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2684 if (unlikely(ret < 0)) {
2685 netdev_err(priv->dev,
2686 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2687 __func__, priv->lpi_irq, ret);
2692 stmmac_enable_all_queues(priv);
2693 stmmac_start_all_queues(priv);
2698 if (priv->wol_irq != dev->irq)
2699 free_irq(priv->wol_irq, dev);
2701 free_irq(dev->irq, dev);
2703 phylink_stop(priv->phylink);
2705 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2706 del_timer_sync(&priv->tx_queue[chan].txtimer);
2708 stmmac_hw_teardown(dev);
2710 free_dma_desc_resources(priv);
2712 phylink_disconnect_phy(priv->phylink);
2717 * stmmac_release - close entry point of the driver
2718 * @dev : device pointer.
2720 * This is the stop entry point of the driver.
2722 static int stmmac_release(struct net_device *dev)
2724 struct stmmac_priv *priv = netdev_priv(dev);
2727 if (priv->eee_enabled)
2728 del_timer_sync(&priv->eee_ctrl_timer);
2730 /* Stop and disconnect the PHY */
2731 phylink_stop(priv->phylink);
2732 phylink_disconnect_phy(priv->phylink);
2734 stmmac_stop_all_queues(priv);
2736 stmmac_disable_all_queues(priv);
2738 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2739 del_timer_sync(&priv->tx_queue[chan].txtimer);
2741 /* Free the IRQ lines */
2742 free_irq(dev->irq, dev);
2743 if (priv->wol_irq != dev->irq)
2744 free_irq(priv->wol_irq, dev);
2745 if (priv->lpi_irq > 0)
2746 free_irq(priv->lpi_irq, dev);
2748 /* Stop TX/RX DMA and clear the descriptors */
2749 stmmac_stop_all_dma(priv);
2751 /* Release and free the Rx/Tx resources */
2752 free_dma_desc_resources(priv);
2754 /* Disable the MAC Rx/Tx */
2755 stmmac_mac_set(priv, priv->ioaddr, false);
2757 netif_carrier_off(dev);
2759 stmmac_release_ptp(priv);
2765 * stmmac_tso_allocator - close entry point of the driver
2766 * @priv: driver private structure
2767 * @des: buffer start address
2768 * @total_len: total length to fill in descriptors
2769 * @last_segmant: condition for the last descriptor
2770 * @queue: TX queue index
2772 * This function fills descriptor and request new descriptors according to
2773 * buffer length to fill
2775 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
2776 int total_len, bool last_segment, u32 queue)
2778 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2779 struct dma_desc *desc;
2783 tmp_len = total_len;
2785 while (tmp_len > 0) {
2786 dma_addr_t curr_addr;
2788 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2789 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2790 desc = tx_q->dma_tx + tx_q->cur_tx;
2792 curr_addr = des + (total_len - tmp_len);
2793 if (priv->dma_cap.addr64 <= 32)
2794 desc->des0 = cpu_to_le32(curr_addr);
2796 stmmac_set_desc_addr(priv, desc, curr_addr);
2798 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2799 TSO_MAX_BUFF_SIZE : tmp_len;
2801 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2803 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2806 tmp_len -= TSO_MAX_BUFF_SIZE;
2811 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2812 * @skb : the socket buffer
2813 * @dev : device pointer
2814 * Description: this is the transmit function that is called on TSO frames
2815 * (support available on GMAC4 and newer chips).
2816 * Diagram below show the ring programming in case of TSO frames:
2820 * | DES0 |---> buffer1 = L2/L3/L4 header
2821 * | DES1 |---> TCP Payload (can continue on next descr...)
2822 * | DES2 |---> buffer 1 and 2 len
2823 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2829 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2831 * | DES2 | --> buffer 1 and 2 len
2835 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2837 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2839 struct dma_desc *desc, *first, *mss_desc = NULL;
2840 struct stmmac_priv *priv = netdev_priv(dev);
2841 int nfrags = skb_shinfo(skb)->nr_frags;
2842 u32 queue = skb_get_queue_mapping(skb);
2843 unsigned int first_entry;
2844 struct stmmac_tx_queue *tx_q;
2845 int tmp_pay_len = 0;
2851 tx_q = &priv->tx_queue[queue];
2853 /* Compute header lengths */
2854 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2856 /* Desc availability based on threshold should be enough safe */
2857 if (unlikely(stmmac_tx_avail(priv, queue) <
2858 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2859 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2860 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2862 /* This is a hard error, log it. */
2863 netdev_err(priv->dev,
2864 "%s: Tx Ring full when queue awake\n",
2867 return NETDEV_TX_BUSY;
2870 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2872 mss = skb_shinfo(skb)->gso_size;
2874 /* set new MSS value if needed */
2875 if (mss != tx_q->mss) {
2876 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2877 stmmac_set_mss(priv, mss_desc, mss);
2879 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2880 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2883 if (netif_msg_tx_queued(priv)) {
2884 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2885 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2886 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2890 first_entry = tx_q->cur_tx;
2891 WARN_ON(tx_q->tx_skbuff[first_entry]);
2893 desc = tx_q->dma_tx + first_entry;
2896 /* first descriptor: fill Headers on Buf1 */
2897 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2899 if (dma_mapping_error(priv->device, des))
2902 tx_q->tx_skbuff_dma[first_entry].buf = des;
2903 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2905 if (priv->dma_cap.addr64 <= 32) {
2906 first->des0 = cpu_to_le32(des);
2908 /* Fill start of payload in buff2 of first descriptor */
2910 first->des1 = cpu_to_le32(des + proto_hdr_len);
2912 /* If needed take extra descriptors to fill the remaining payload */
2913 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2915 stmmac_set_desc_addr(priv, first, des);
2916 tmp_pay_len = pay_len;
2919 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2921 /* Prepare fragments */
2922 for (i = 0; i < nfrags; i++) {
2923 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2925 des = skb_frag_dma_map(priv->device, frag, 0,
2926 skb_frag_size(frag),
2928 if (dma_mapping_error(priv->device, des))
2931 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2932 (i == nfrags - 1), queue);
2934 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2935 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2936 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2939 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2941 /* Only the last descriptor gets to point to the skb. */
2942 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2944 /* We've used all descriptors we need for this skb, however,
2945 * advance cur_tx so that it references a fresh descriptor.
2946 * ndo_start_xmit will fill this descriptor the next time it's
2947 * called and stmmac_tx_clean may clean up to this descriptor.
2949 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2951 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2952 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2954 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2957 dev->stats.tx_bytes += skb->len;
2958 priv->xstats.tx_tso_frames++;
2959 priv->xstats.tx_tso_nfrags += nfrags;
2961 /* Manage tx mitigation */
2962 tx_q->tx_count_frames += nfrags + 1;
2963 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
2964 !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
2965 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2966 priv->hwts_tx_en)) {
2967 stmmac_tx_timer_arm(priv, queue);
2969 tx_q->tx_count_frames = 0;
2970 stmmac_set_tx_ic(priv, desc);
2971 priv->xstats.tx_set_ic_bit++;
2974 skb_tx_timestamp(skb);
2976 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2977 priv->hwts_tx_en)) {
2978 /* declare that device is doing timestamping */
2979 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2980 stmmac_enable_tx_timestamp(priv, first);
2983 /* Complete the first descriptor before granting the DMA */
2984 stmmac_prepare_tso_tx_desc(priv, first, 1,
2987 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2988 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2990 /* If context desc is used to change MSS */
2992 /* Make sure that first descriptor has been completely
2993 * written, including its own bit. This is because MSS is
2994 * actually before first descriptor, so we need to make
2995 * sure that MSS's own bit is the last thing written.
2998 stmmac_set_tx_owner(priv, mss_desc);
3001 /* The own bit must be the latest setting done when prepare the
3002 * descriptor and then barrier is needed to make sure that
3003 * all is coherent before granting the DMA engine.
3007 if (netif_msg_pktdata(priv)) {
3008 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
3009 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3010 tx_q->cur_tx, first, nfrags);
3012 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
3014 pr_info(">>> frame to be transmitted: ");
3015 print_pkt(skb->data, skb_headlen(skb));
3018 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3020 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3021 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3023 return NETDEV_TX_OK;
3026 dev_err(priv->device, "Tx dma map failed\n");
3028 priv->dev->stats.tx_dropped++;
3029 return NETDEV_TX_OK;
3033 * stmmac_xmit - Tx entry point of the driver
3034 * @skb : the socket buffer
3035 * @dev : device pointer
3036 * Description : this is the tx entry point of the driver.
3037 * It programs the chain or the ring and supports oversized frames
3040 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
3042 struct stmmac_priv *priv = netdev_priv(dev);
3043 unsigned int nopaged_len = skb_headlen(skb);
3044 int i, csum_insertion = 0, is_jumbo = 0;
3045 u32 queue = skb_get_queue_mapping(skb);
3046 int nfrags = skb_shinfo(skb)->nr_frags;
3047 struct dma_desc *desc, *first;
3048 struct stmmac_tx_queue *tx_q;
3049 unsigned int first_entry;
3050 unsigned int enh_desc;
3054 tx_q = &priv->tx_queue[queue];
3056 if (priv->tx_path_in_lpi_mode)
3057 stmmac_disable_eee_mode(priv);
3059 /* Manage oversized TCP frames for GMAC4 device */
3060 if (skb_is_gso(skb) && priv->tso) {
3061 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
3062 return stmmac_tso_xmit(skb, dev);
3065 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3066 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3067 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3069 /* This is a hard error, log it. */
3070 netdev_err(priv->dev,
3071 "%s: Tx Ring full when queue awake\n",
3074 return NETDEV_TX_BUSY;
3077 entry = tx_q->cur_tx;
3078 first_entry = entry;
3079 WARN_ON(tx_q->tx_skbuff[first_entry]);
3081 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3083 if (likely(priv->extend_desc))
3084 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3086 desc = tx_q->dma_tx + entry;
3090 enh_desc = priv->plat->enh_desc;
3091 /* To program the descriptors according to the size of the frame */
3093 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3095 if (unlikely(is_jumbo)) {
3096 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3097 if (unlikely(entry < 0) && (entry != -EINVAL))
3101 for (i = 0; i < nfrags; i++) {
3102 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3103 int len = skb_frag_size(frag);
3104 bool last_segment = (i == (nfrags - 1));
3106 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3107 WARN_ON(tx_q->tx_skbuff[entry]);
3109 if (likely(priv->extend_desc))
3110 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3112 desc = tx_q->dma_tx + entry;
3114 des = skb_frag_dma_map(priv->device, frag, 0, len,
3116 if (dma_mapping_error(priv->device, des))
3117 goto dma_map_err; /* should reuse desc w/o issues */
3119 tx_q->tx_skbuff_dma[entry].buf = des;
3121 stmmac_set_desc_addr(priv, desc, des);
3123 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3124 tx_q->tx_skbuff_dma[entry].len = len;
3125 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3127 /* Prepare the descriptor and set the own bit too */
3128 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3129 priv->mode, 1, last_segment, skb->len);
3132 /* Only the last descriptor gets to point to the skb. */
3133 tx_q->tx_skbuff[entry] = skb;
3135 /* We've used all descriptors we need for this skb, however,
3136 * advance cur_tx so that it references a fresh descriptor.
3137 * ndo_start_xmit will fill this descriptor the next time it's
3138 * called and stmmac_tx_clean may clean up to this descriptor.
3140 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3141 tx_q->cur_tx = entry;
3143 if (netif_msg_pktdata(priv)) {
3146 netdev_dbg(priv->dev,
3147 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3148 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3149 entry, first, nfrags);
3151 if (priv->extend_desc)
3152 tx_head = (void *)tx_q->dma_etx;
3154 tx_head = (void *)tx_q->dma_tx;
3156 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3158 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3159 print_pkt(skb->data, skb->len);
3162 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3163 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3165 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3168 dev->stats.tx_bytes += skb->len;
3170 /* According to the coalesce parameter the IC bit for the latest
3171 * segment is reset and the timer re-started to clean the tx status.
3172 * This approach takes care about the fragments: desc is the first
3173 * element in case of no SG.
3175 tx_q->tx_count_frames += nfrags + 1;
3176 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
3177 !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
3178 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3179 priv->hwts_tx_en)) {
3180 stmmac_tx_timer_arm(priv, queue);
3182 tx_q->tx_count_frames = 0;
3183 stmmac_set_tx_ic(priv, desc);
3184 priv->xstats.tx_set_ic_bit++;
3187 skb_tx_timestamp(skb);
3189 /* Ready to fill the first descriptor and set the OWN bit w/o any
3190 * problems because all the descriptors are actually ready to be
3191 * passed to the DMA engine.
3193 if (likely(!is_jumbo)) {
3194 bool last_segment = (nfrags == 0);
3196 des = dma_map_single(priv->device, skb->data,
3197 nopaged_len, DMA_TO_DEVICE);
3198 if (dma_mapping_error(priv->device, des))
3201 tx_q->tx_skbuff_dma[first_entry].buf = des;
3203 stmmac_set_desc_addr(priv, first, des);
3205 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3206 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3208 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3209 priv->hwts_tx_en)) {
3210 /* declare that device is doing timestamping */
3211 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3212 stmmac_enable_tx_timestamp(priv, first);
3215 /* Prepare the first descriptor setting the OWN bit too */
3216 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3217 csum_insertion, priv->mode, 1, last_segment,
3220 stmmac_set_tx_owner(priv, first);
3223 /* The own bit must be the latest setting done when prepare the
3224 * descriptor and then barrier is needed to make sure that
3225 * all is coherent before granting the DMA engine.
3229 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3231 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3233 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3234 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3236 return NETDEV_TX_OK;
3239 netdev_err(priv->dev, "Tx DMA map failed\n");
3241 priv->dev->stats.tx_dropped++;
3242 return NETDEV_TX_OK;
3245 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3247 struct vlan_ethhdr *veth;
3251 veth = (struct vlan_ethhdr *)skb->data;
3252 vlan_proto = veth->h_vlan_proto;
3254 if ((vlan_proto == htons(ETH_P_8021Q) &&
3255 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3256 (vlan_proto == htons(ETH_P_8021AD) &&
3257 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3258 /* pop the vlan tag */
3259 vlanid = ntohs(veth->h_vlan_TCI);
3260 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3261 skb_pull(skb, VLAN_HLEN);
3262 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3267 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3269 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3276 * stmmac_rx_refill - refill used skb preallocated buffers
3277 * @priv: driver private structure
3278 * @queue: RX queue index
3279 * Description : this is to reallocate the skb for the reception process
3280 * that is based on zero-copy.
3282 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3284 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3285 int dirty = stmmac_rx_dirty(priv, queue);
3286 unsigned int entry = rx_q->dirty_rx;
3288 int bfsize = priv->dma_buf_sz;
3290 while (dirty-- > 0) {
3293 if (priv->extend_desc)
3294 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3296 p = rx_q->dma_rx + entry;
3298 if (likely(!rx_q->rx_skbuff[entry])) {
3299 struct sk_buff *skb;
3301 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3302 if (unlikely(!skb)) {
3303 /* so for a while no zero-copy! */
3304 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3305 if (unlikely(net_ratelimit()))
3306 dev_err(priv->device,
3307 "fail to alloc skb entry %d\n",
3312 rx_q->rx_skbuff[entry] = skb;
3313 rx_q->rx_skbuff_dma[entry] =
3314 dma_map_single(priv->device, skb->data, bfsize,
3316 if (dma_mapping_error(priv->device,
3317 rx_q->rx_skbuff_dma[entry])) {
3318 netdev_err(priv->dev, "Rx DMA map failed\n");
3323 stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[entry]);
3324 stmmac_refill_desc3(priv, rx_q, p);
3326 if (rx_q->rx_zeroc_thresh > 0)
3327 rx_q->rx_zeroc_thresh--;
3329 netif_dbg(priv, rx_status, priv->dev,
3330 "refill entry #%d\n", entry);
3334 stmmac_set_rx_owner(priv, p, priv->use_riwt);
3338 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3340 rx_q->dirty_rx = entry;
3341 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
3342 (rx_q->dirty_rx * sizeof(struct dma_desc));
3343 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3347 * stmmac_rx - manage the receive process
3348 * @priv: driver private structure
3349 * @limit: napi bugget
3350 * @queue: RX queue index.
3351 * Description : this the function called by the napi poll method.
3352 * It gets all the frames inside the ring.
3354 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3356 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3357 struct stmmac_channel *ch = &priv->channel[queue];
3358 unsigned int next_entry = rx_q->cur_rx;
3359 int coe = priv->hw->rx_csum;
3360 unsigned int count = 0;
3363 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3365 if (netif_msg_rx_status(priv)) {
3368 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3369 if (priv->extend_desc)
3370 rx_head = (void *)rx_q->dma_erx;
3372 rx_head = (void *)rx_q->dma_rx;
3374 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3376 while (count < limit) {
3379 struct dma_desc *np;
3383 if (priv->extend_desc)
3384 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3386 p = rx_q->dma_rx + entry;
3388 /* read the status of the incoming frame */
3389 status = stmmac_rx_status(priv, &priv->dev->stats,
3391 /* check if managed by the DMA otherwise go ahead */
3392 if (unlikely(status & dma_own))
3397 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3398 next_entry = rx_q->cur_rx;
3400 if (priv->extend_desc)
3401 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3403 np = rx_q->dma_rx + next_entry;
3407 if (priv->extend_desc)
3408 stmmac_rx_extended_status(priv, &priv->dev->stats,
3409 &priv->xstats, rx_q->dma_erx + entry);
3410 if (unlikely(status == discard_frame)) {
3411 priv->dev->stats.rx_errors++;
3412 if (priv->hwts_rx_en && !priv->extend_desc) {
3413 /* DESC2 & DESC3 will be overwritten by device
3414 * with timestamp value, hence reinitialize
3415 * them in stmmac_rx_refill() function so that
3416 * device can reuse it.
3418 dev_kfree_skb_any(rx_q->rx_skbuff[entry]);
3419 rx_q->rx_skbuff[entry] = NULL;
3420 dma_unmap_single(priv->device,
3421 rx_q->rx_skbuff_dma[entry],
3426 struct sk_buff *skb;
3430 stmmac_get_desc_addr(priv, p, &des);
3431 frame_len = stmmac_get_rx_frame_len(priv, p, coe);
3433 /* If frame length is greater than skb buffer size
3434 * (preallocated during init) then the packet is
3437 if (frame_len > priv->dma_buf_sz) {
3438 if (net_ratelimit())
3439 netdev_err(priv->dev,
3440 "len %d larger than size (%d)\n",
3441 frame_len, priv->dma_buf_sz);
3442 priv->dev->stats.rx_length_errors++;
3446 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3447 * Type frames (LLC/LLC-SNAP)
3449 * llc_snap is never checked in GMAC >= 4, so this ACS
3450 * feature is always disabled and packets need to be
3451 * stripped manually.
3453 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3454 unlikely(status != llc_snap))
3455 frame_len -= ETH_FCS_LEN;
3457 if (netif_msg_rx_status(priv)) {
3458 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3460 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3464 /* The zero-copy is always used for all the sizes
3465 * in case of GMAC4 because it needs
3466 * to refill the used descriptors, always.
3468 if (unlikely(!xmac &&
3469 ((frame_len < priv->rx_copybreak) ||
3470 stmmac_rx_threshold_count(rx_q)))) {
3471 skb = netdev_alloc_skb_ip_align(priv->dev,
3473 if (unlikely(!skb)) {
3474 if (net_ratelimit())
3475 dev_warn(priv->device,
3476 "packet dropped\n");
3477 priv->dev->stats.rx_dropped++;
3481 dma_sync_single_for_cpu(priv->device,
3485 skb_copy_to_linear_data(skb,
3487 rx_skbuff[entry]->data,
3490 skb_put(skb, frame_len);
3491 dma_sync_single_for_device(priv->device,
3496 skb = rx_q->rx_skbuff[entry];
3497 if (unlikely(!skb)) {
3498 if (net_ratelimit())
3499 netdev_err(priv->dev,
3500 "%s: Inconsistent Rx chain\n",
3502 priv->dev->stats.rx_dropped++;
3505 prefetch(skb->data - NET_IP_ALIGN);
3506 rx_q->rx_skbuff[entry] = NULL;
3507 rx_q->rx_zeroc_thresh++;
3509 skb_put(skb, frame_len);
3510 dma_unmap_single(priv->device,
3511 rx_q->rx_skbuff_dma[entry],
3516 if (netif_msg_pktdata(priv)) {
3517 netdev_dbg(priv->dev, "frame received (%dbytes)",
3519 print_pkt(skb->data, frame_len);
3522 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3524 stmmac_rx_vlan(priv->dev, skb);
3526 skb->protocol = eth_type_trans(skb, priv->dev);
3529 skb_checksum_none_assert(skb);
3531 skb->ip_summed = CHECKSUM_UNNECESSARY;
3533 napi_gro_receive(&ch->rx_napi, skb);
3535 priv->dev->stats.rx_packets++;
3536 priv->dev->stats.rx_bytes += frame_len;
3540 stmmac_rx_refill(priv, queue);
3542 priv->xstats.rx_pkt_n += count;
3547 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3549 struct stmmac_channel *ch =
3550 container_of(napi, struct stmmac_channel, rx_napi);
3551 struct stmmac_priv *priv = ch->priv_data;
3552 u32 chan = ch->index;
3555 priv->xstats.napi_poll++;
3557 work_done = stmmac_rx(priv, budget, chan);
3558 if (work_done < budget && napi_complete_done(napi, work_done))
3559 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3563 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3565 struct stmmac_channel *ch =
3566 container_of(napi, struct stmmac_channel, tx_napi);
3567 struct stmmac_priv *priv = ch->priv_data;
3568 struct stmmac_tx_queue *tx_q;
3569 u32 chan = ch->index;
3572 priv->xstats.napi_poll++;
3574 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3575 work_done = min(work_done, budget);
3577 if (work_done < budget)
3578 napi_complete_done(napi, work_done);
3580 /* Force transmission restart */
3581 tx_q = &priv->tx_queue[chan];
3582 if (tx_q->cur_tx != tx_q->dirty_tx) {
3583 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3584 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3593 * @dev : Pointer to net device structure
3594 * Description: this function is called when a packet transmission fails to
3595 * complete within a reasonable time. The driver will mark the error in the
3596 * netdev structure and arrange for the device to be reset to a sane state
3597 * in order to transmit a new packet.
3599 static void stmmac_tx_timeout(struct net_device *dev)
3601 struct stmmac_priv *priv = netdev_priv(dev);
3603 stmmac_global_err(priv);
3607 * stmmac_set_rx_mode - entry point for multicast addressing
3608 * @dev : pointer to the device structure
3610 * This function is a driver entry point which gets called by the kernel
3611 * whenever multicast addresses must be enabled/disabled.
3615 static void stmmac_set_rx_mode(struct net_device *dev)
3617 struct stmmac_priv *priv = netdev_priv(dev);
3619 stmmac_set_filter(priv, priv->hw, dev);
3623 * stmmac_change_mtu - entry point to change MTU size for the device.
3624 * @dev : device pointer.
3625 * @new_mtu : the new MTU size for the device.
3626 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3627 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3628 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3630 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3633 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3635 struct stmmac_priv *priv = netdev_priv(dev);
3637 if (netif_running(dev)) {
3638 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3644 netdev_update_features(dev);
3649 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3650 netdev_features_t features)
3652 struct stmmac_priv *priv = netdev_priv(dev);
3654 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3655 features &= ~NETIF_F_RXCSUM;
3657 if (!priv->plat->tx_coe)
3658 features &= ~NETIF_F_CSUM_MASK;
3660 /* Some GMAC devices have a bugged Jumbo frame support that
3661 * needs to have the Tx COE disabled for oversized frames
3662 * (due to limited buffer sizes). In this case we disable
3663 * the TX csum insertion in the TDES and not use SF.
3665 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3666 features &= ~NETIF_F_CSUM_MASK;
3668 /* Disable tso if asked by ethtool */
3669 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3670 if (features & NETIF_F_TSO)
3679 static int stmmac_set_features(struct net_device *netdev,
3680 netdev_features_t features)
3682 struct stmmac_priv *priv = netdev_priv(netdev);
3684 /* Keep the COE Type in case of csum is supporting */
3685 if (features & NETIF_F_RXCSUM)
3686 priv->hw->rx_csum = priv->plat->rx_coe;
3688 priv->hw->rx_csum = 0;
3689 /* No check needed because rx_coe has been set before and it will be
3690 * fixed in case of issue.
3692 stmmac_rx_ipc(priv, priv->hw);
3698 * stmmac_interrupt - main ISR
3699 * @irq: interrupt number.
3700 * @dev_id: to pass the net device pointer.
3701 * Description: this is the main driver interrupt service routine.
3703 * o DMA service routine (to manage incoming frame reception and transmission
3705 * o Core interrupts to manage: remote wake-up, management counter, LPI
3708 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3710 struct net_device *dev = (struct net_device *)dev_id;
3711 struct stmmac_priv *priv = netdev_priv(dev);
3712 u32 rx_cnt = priv->plat->rx_queues_to_use;
3713 u32 tx_cnt = priv->plat->tx_queues_to_use;
3718 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3719 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3722 pm_wakeup_event(priv->device, 0);
3724 if (unlikely(!dev)) {
3725 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3729 /* Check if adapter is up */
3730 if (test_bit(STMMAC_DOWN, &priv->state))
3732 /* Check if a fatal error happened */
3733 if (stmmac_safety_feat_interrupt(priv))
3736 /* To handle GMAC own interrupts */
3737 if ((priv->plat->has_gmac) || xmac) {
3738 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3741 if (unlikely(status)) {
3742 /* For LPI we need to save the tx status */
3743 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3744 priv->tx_path_in_lpi_mode = true;
3745 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3746 priv->tx_path_in_lpi_mode = false;
3749 for (queue = 0; queue < queues_count; queue++) {
3750 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3752 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3754 if (mtl_status != -EINVAL)
3755 status |= mtl_status;
3757 if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3758 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3763 /* PCS link status */
3764 if (priv->hw->pcs) {
3765 if (priv->xstats.pcs_link)
3766 netif_carrier_on(dev);
3768 netif_carrier_off(dev);
3772 /* To handle DMA interrupts */
3773 stmmac_dma_interrupt(priv);
3778 #ifdef CONFIG_NET_POLL_CONTROLLER
3779 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3780 * to allow network I/O with interrupts disabled.
3782 static void stmmac_poll_controller(struct net_device *dev)
3784 disable_irq(dev->irq);
3785 stmmac_interrupt(dev->irq, dev);
3786 enable_irq(dev->irq);
3791 * stmmac_ioctl - Entry point for the Ioctl
3792 * @dev: Device pointer.
3793 * @rq: An IOCTL specefic structure, that can contain a pointer to
3794 * a proprietary structure used to pass information to the driver.
3795 * @cmd: IOCTL command
3797 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3799 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3801 struct stmmac_priv *priv = netdev_priv (dev);
3802 int ret = -EOPNOTSUPP;
3804 if (!netif_running(dev))
3811 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
3814 ret = stmmac_hwtstamp_set(dev, rq);
3817 ret = stmmac_hwtstamp_get(dev, rq);
3826 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3829 struct stmmac_priv *priv = cb_priv;
3830 int ret = -EOPNOTSUPP;
3832 stmmac_disable_all_queues(priv);
3835 case TC_SETUP_CLSU32:
3836 if (tc_cls_can_offload_and_chain0(priv->dev, type_data))
3837 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3843 stmmac_enable_all_queues(priv);
3847 static int stmmac_setup_tc_block(struct stmmac_priv *priv,
3848 struct tc_block_offload *f)
3850 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3853 switch (f->command) {
3855 return tcf_block_cb_register(f->block, stmmac_setup_tc_block_cb,
3856 priv, priv, f->extack);
3857 case TC_BLOCK_UNBIND:
3858 tcf_block_cb_unregister(f->block, stmmac_setup_tc_block_cb, priv);
3865 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3868 struct stmmac_priv *priv = netdev_priv(ndev);
3871 case TC_SETUP_BLOCK:
3872 return stmmac_setup_tc_block(priv, type_data);
3873 case TC_SETUP_QDISC_CBS:
3874 return stmmac_tc_setup_cbs(priv, priv, type_data);
3880 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
3881 struct net_device *sb_dev)
3883 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3885 * There is no way to determine the number of TSO
3886 * capable Queues. Let's use always the Queue 0
3887 * because if TSO is supported then at least this
3888 * one will be capable.
3893 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
3896 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
3898 struct stmmac_priv *priv = netdev_priv(ndev);
3901 ret = eth_mac_addr(ndev, addr);
3905 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
3910 #ifdef CONFIG_DEBUG_FS
3911 static struct dentry *stmmac_fs_dir;
3913 static void sysfs_display_ring(void *head, int size, int extend_desc,
3914 struct seq_file *seq)
3917 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3918 struct dma_desc *p = (struct dma_desc *)head;
3920 for (i = 0; i < size; i++) {
3922 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3923 i, (unsigned int)virt_to_phys(ep),
3924 le32_to_cpu(ep->basic.des0),
3925 le32_to_cpu(ep->basic.des1),
3926 le32_to_cpu(ep->basic.des2),
3927 le32_to_cpu(ep->basic.des3));
3930 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3931 i, (unsigned int)virt_to_phys(p),
3932 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3933 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3936 seq_printf(seq, "\n");
3940 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
3942 struct net_device *dev = seq->private;
3943 struct stmmac_priv *priv = netdev_priv(dev);
3944 u32 rx_count = priv->plat->rx_queues_to_use;
3945 u32 tx_count = priv->plat->tx_queues_to_use;
3948 if ((dev->flags & IFF_UP) == 0)
3951 for (queue = 0; queue < rx_count; queue++) {
3952 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3954 seq_printf(seq, "RX Queue %d:\n", queue);
3956 if (priv->extend_desc) {
3957 seq_printf(seq, "Extended descriptor ring:\n");
3958 sysfs_display_ring((void *)rx_q->dma_erx,
3959 DMA_RX_SIZE, 1, seq);
3961 seq_printf(seq, "Descriptor ring:\n");
3962 sysfs_display_ring((void *)rx_q->dma_rx,
3963 DMA_RX_SIZE, 0, seq);
3967 for (queue = 0; queue < tx_count; queue++) {
3968 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3970 seq_printf(seq, "TX Queue %d:\n", queue);
3972 if (priv->extend_desc) {
3973 seq_printf(seq, "Extended descriptor ring:\n");
3974 sysfs_display_ring((void *)tx_q->dma_etx,
3975 DMA_TX_SIZE, 1, seq);
3977 seq_printf(seq, "Descriptor ring:\n");
3978 sysfs_display_ring((void *)tx_q->dma_tx,
3979 DMA_TX_SIZE, 0, seq);
3985 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
3987 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
3989 struct net_device *dev = seq->private;
3990 struct stmmac_priv *priv = netdev_priv(dev);
3992 if (!priv->hw_cap_support) {
3993 seq_printf(seq, "DMA HW features not supported\n");
3997 seq_printf(seq, "==============================\n");
3998 seq_printf(seq, "\tDMA HW features\n");
3999 seq_printf(seq, "==============================\n");
4001 seq_printf(seq, "\t10/100 Mbps: %s\n",
4002 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
4003 seq_printf(seq, "\t1000 Mbps: %s\n",
4004 (priv->dma_cap.mbps_1000) ? "Y" : "N");
4005 seq_printf(seq, "\tHalf duplex: %s\n",
4006 (priv->dma_cap.half_duplex) ? "Y" : "N");
4007 seq_printf(seq, "\tHash Filter: %s\n",
4008 (priv->dma_cap.hash_filter) ? "Y" : "N");
4009 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
4010 (priv->dma_cap.multi_addr) ? "Y" : "N");
4011 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
4012 (priv->dma_cap.pcs) ? "Y" : "N");
4013 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
4014 (priv->dma_cap.sma_mdio) ? "Y" : "N");
4015 seq_printf(seq, "\tPMT Remote wake up: %s\n",
4016 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
4017 seq_printf(seq, "\tPMT Magic Frame: %s\n",
4018 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
4019 seq_printf(seq, "\tRMON module: %s\n",
4020 (priv->dma_cap.rmon) ? "Y" : "N");
4021 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
4022 (priv->dma_cap.time_stamp) ? "Y" : "N");
4023 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
4024 (priv->dma_cap.atime_stamp) ? "Y" : "N");
4025 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
4026 (priv->dma_cap.eee) ? "Y" : "N");
4027 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
4028 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
4029 (priv->dma_cap.tx_coe) ? "Y" : "N");
4030 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
4031 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
4032 (priv->dma_cap.rx_coe) ? "Y" : "N");
4034 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
4035 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
4036 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
4037 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
4039 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
4040 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
4041 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
4042 priv->dma_cap.number_rx_channel);
4043 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
4044 priv->dma_cap.number_tx_channel);
4045 seq_printf(seq, "\tEnhanced descriptors: %s\n",
4046 (priv->dma_cap.enh_desc) ? "Y" : "N");
4050 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
4052 static int stmmac_init_fs(struct net_device *dev)
4054 struct stmmac_priv *priv = netdev_priv(dev);
4056 /* Create per netdev entries */
4057 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
4059 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
4060 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
4065 /* Entry to report DMA RX/TX rings */
4066 priv->dbgfs_rings_status =
4067 debugfs_create_file("descriptors_status", 0444,
4068 priv->dbgfs_dir, dev,
4069 &stmmac_rings_status_fops);
4071 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
4072 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
4073 debugfs_remove_recursive(priv->dbgfs_dir);
4078 /* Entry to report the DMA HW features */
4079 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444,
4081 dev, &stmmac_dma_cap_fops);
4083 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
4084 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
4085 debugfs_remove_recursive(priv->dbgfs_dir);
4093 static void stmmac_exit_fs(struct net_device *dev)
4095 struct stmmac_priv *priv = netdev_priv(dev);
4097 debugfs_remove_recursive(priv->dbgfs_dir);
4099 #endif /* CONFIG_DEBUG_FS */
4101 static const struct net_device_ops stmmac_netdev_ops = {
4102 .ndo_open = stmmac_open,
4103 .ndo_start_xmit = stmmac_xmit,
4104 .ndo_stop = stmmac_release,
4105 .ndo_change_mtu = stmmac_change_mtu,
4106 .ndo_fix_features = stmmac_fix_features,
4107 .ndo_set_features = stmmac_set_features,
4108 .ndo_set_rx_mode = stmmac_set_rx_mode,
4109 .ndo_tx_timeout = stmmac_tx_timeout,
4110 .ndo_do_ioctl = stmmac_ioctl,
4111 .ndo_setup_tc = stmmac_setup_tc,
4112 .ndo_select_queue = stmmac_select_queue,
4113 #ifdef CONFIG_NET_POLL_CONTROLLER
4114 .ndo_poll_controller = stmmac_poll_controller,
4116 .ndo_set_mac_address = stmmac_set_mac_address,
4119 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4121 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4123 if (test_bit(STMMAC_DOWN, &priv->state))
4126 netdev_err(priv->dev, "Reset adapter.\n");
4129 netif_trans_update(priv->dev);
4130 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4131 usleep_range(1000, 2000);
4133 set_bit(STMMAC_DOWN, &priv->state);
4134 dev_close(priv->dev);
4135 dev_open(priv->dev, NULL);
4136 clear_bit(STMMAC_DOWN, &priv->state);
4137 clear_bit(STMMAC_RESETING, &priv->state);
4141 static void stmmac_service_task(struct work_struct *work)
4143 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4146 stmmac_reset_subtask(priv);
4147 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4151 * stmmac_hw_init - Init the MAC device
4152 * @priv: driver private structure
4153 * Description: this function is to configure the MAC device according to
4154 * some platform parameters or the HW capability register. It prepares the
4155 * driver to use either ring or chain modes and to setup either enhanced or
4156 * normal descriptors.
4158 static int stmmac_hw_init(struct stmmac_priv *priv)
4162 /* dwmac-sun8i only work in chain mode */
4163 if (priv->plat->has_sun8i)
4165 priv->chain_mode = chain_mode;
4167 /* Initialize HW Interface */
4168 ret = stmmac_hwif_init(priv);
4172 /* Get the HW capability (new GMAC newer than 3.50a) */
4173 priv->hw_cap_support = stmmac_get_hw_features(priv);
4174 if (priv->hw_cap_support) {
4175 dev_info(priv->device, "DMA HW capability register supported\n");
4177 /* We can override some gmac/dma configuration fields: e.g.
4178 * enh_desc, tx_coe (e.g. that are passed through the
4179 * platform) with the values from the HW capability
4180 * register (if supported).
4182 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4183 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4184 priv->hw->pmt = priv->plat->pmt;
4186 /* TXCOE doesn't work in thresh DMA mode */
4187 if (priv->plat->force_thresh_dma_mode)
4188 priv->plat->tx_coe = 0;
4190 priv->plat->tx_coe = priv->dma_cap.tx_coe;
4192 /* In case of GMAC4 rx_coe is from HW cap register. */
4193 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4195 if (priv->dma_cap.rx_coe_type2)
4196 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4197 else if (priv->dma_cap.rx_coe_type1)
4198 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4201 dev_info(priv->device, "No HW DMA feature register supported\n");
4204 if (priv->plat->rx_coe) {
4205 priv->hw->rx_csum = priv->plat->rx_coe;
4206 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4207 if (priv->synopsys_id < DWMAC_CORE_4_00)
4208 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4210 if (priv->plat->tx_coe)
4211 dev_info(priv->device, "TX Checksum insertion supported\n");
4213 if (priv->plat->pmt) {
4214 dev_info(priv->device, "Wake-Up On Lan supported\n");
4215 device_set_wakeup_capable(priv->device, 1);
4218 if (priv->dma_cap.tsoen)
4219 dev_info(priv->device, "TSO supported\n");
4221 /* Run HW quirks, if any */
4222 if (priv->hwif_quirks) {
4223 ret = priv->hwif_quirks(priv);
4228 /* Rx Watchdog is available in the COREs newer than the 3.40.
4229 * In some case, for example on bugged HW this feature
4230 * has to be disable and this can be done by passing the
4231 * riwt_off field from the platform.
4233 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4234 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4236 dev_info(priv->device,
4237 "Enable RX Mitigation via HW Watchdog Timer\n");
4245 * @device: device pointer
4246 * @plat_dat: platform data pointer
4247 * @res: stmmac resource pointer
4248 * Description: this is the main probe function used to
4249 * call the alloc_etherdev, allocate the priv structure.
4251 * returns 0 on success, otherwise errno.
4253 int stmmac_dvr_probe(struct device *device,
4254 struct plat_stmmacenet_data *plat_dat,
4255 struct stmmac_resources *res)
4257 struct net_device *ndev = NULL;
4258 struct stmmac_priv *priv;
4262 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4263 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
4267 SET_NETDEV_DEV(ndev, device);
4269 priv = netdev_priv(ndev);
4270 priv->device = device;
4273 stmmac_set_ethtool_ops(ndev);
4274 priv->pause = pause;
4275 priv->plat = plat_dat;
4276 priv->ioaddr = res->addr;
4277 priv->dev->base_addr = (unsigned long)res->addr;
4279 priv->dev->irq = res->irq;
4280 priv->wol_irq = res->wol_irq;
4281 priv->lpi_irq = res->lpi_irq;
4283 if (!IS_ERR_OR_NULL(res->mac))
4284 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4286 dev_set_drvdata(device, priv->dev);
4288 /* Verify driver arguments */
4289 stmmac_verify_args();
4291 /* Allocate workqueue */
4292 priv->wq = create_singlethread_workqueue("stmmac_wq");
4294 dev_err(priv->device, "failed to create workqueue\n");
4298 INIT_WORK(&priv->service_task, stmmac_service_task);
4300 /* Override with kernel parameters if supplied XXX CRS XXX
4301 * this needs to have multiple instances
4303 if ((phyaddr >= 0) && (phyaddr <= 31))
4304 priv->plat->phy_addr = phyaddr;
4306 if (priv->plat->stmmac_rst) {
4307 ret = reset_control_assert(priv->plat->stmmac_rst);
4308 reset_control_deassert(priv->plat->stmmac_rst);
4309 /* Some reset controllers have only reset callback instead of
4310 * assert + deassert callbacks pair.
4312 if (ret == -ENOTSUPP)
4313 reset_control_reset(priv->plat->stmmac_rst);
4316 /* Init MAC and get the capabilities */
4317 ret = stmmac_hw_init(priv);
4321 stmmac_check_ether_addr(priv);
4323 /* Configure real RX and TX queues */
4324 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4325 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4327 ndev->netdev_ops = &stmmac_netdev_ops;
4329 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4332 ret = stmmac_tc_init(priv, priv);
4334 ndev->hw_features |= NETIF_F_HW_TC;
4337 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4338 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4340 dev_info(priv->device, "TSO feature enabled\n");
4343 if (priv->dma_cap.addr64) {
4344 ret = dma_set_mask_and_coherent(device,
4345 DMA_BIT_MASK(priv->dma_cap.addr64));
4347 dev_info(priv->device, "Using %d bits DMA width\n",
4348 priv->dma_cap.addr64);
4350 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
4352 dev_err(priv->device, "Failed to set DMA Mask\n");
4356 priv->dma_cap.addr64 = 32;
4360 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4361 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4362 #ifdef STMMAC_VLAN_TAG_USED
4363 /* Both mac100 and gmac support receive VLAN tag detection */
4364 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4366 priv->msg_enable = netif_msg_init(debug, default_msg_level);
4368 /* MTU range: 46 - hw-specific max */
4369 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4370 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4371 ndev->max_mtu = JUMBO_LEN;
4372 else if (priv->plat->has_xgmac)
4373 ndev->max_mtu = XGMAC_JUMBO_LEN;
4375 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4376 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4377 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4379 if ((priv->plat->maxmtu < ndev->max_mtu) &&
4380 (priv->plat->maxmtu >= ndev->min_mtu))
4381 ndev->max_mtu = priv->plat->maxmtu;
4382 else if (priv->plat->maxmtu < ndev->min_mtu)
4383 dev_warn(priv->device,
4384 "%s: warning: maxmtu having invalid value (%d)\n",
4385 __func__, priv->plat->maxmtu);
4388 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
4390 /* Setup channels NAPI */
4391 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4393 for (queue = 0; queue < maxq; queue++) {
4394 struct stmmac_channel *ch = &priv->channel[queue];
4396 ch->priv_data = priv;
4399 if (queue < priv->plat->rx_queues_to_use) {
4400 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4403 if (queue < priv->plat->tx_queues_to_use) {
4404 netif_napi_add(ndev, &ch->tx_napi, stmmac_napi_poll_tx,
4409 mutex_init(&priv->lock);
4411 /* If a specific clk_csr value is passed from the platform
4412 * this means that the CSR Clock Range selection cannot be
4413 * changed at run-time and it is fixed. Viceversa the driver'll try to
4414 * set the MDC clock dynamically according to the csr actual
4417 if (priv->plat->clk_csr >= 0)
4418 priv->clk_csr = priv->plat->clk_csr;
4420 stmmac_clk_csr_set(priv);
4422 stmmac_check_pcs_mode(priv);
4424 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4425 priv->hw->pcs != STMMAC_PCS_TBI &&
4426 priv->hw->pcs != STMMAC_PCS_RTBI) {
4427 /* MDIO bus Registration */
4428 ret = stmmac_mdio_register(ndev);
4430 dev_err(priv->device,
4431 "%s: MDIO bus (id: %d) registration failed",
4432 __func__, priv->plat->bus_id);
4433 goto error_mdio_register;
4437 ret = stmmac_phy_setup(priv);
4439 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4440 goto error_phy_setup;
4443 ret = register_netdev(ndev);
4445 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4447 goto error_netdev_register;
4450 #ifdef CONFIG_DEBUG_FS
4451 ret = stmmac_init_fs(ndev);
4453 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
4459 error_netdev_register:
4460 phylink_destroy(priv->phylink);
4462 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4463 priv->hw->pcs != STMMAC_PCS_TBI &&
4464 priv->hw->pcs != STMMAC_PCS_RTBI)
4465 stmmac_mdio_unregister(ndev);
4466 error_mdio_register:
4467 for (queue = 0; queue < maxq; queue++) {
4468 struct stmmac_channel *ch = &priv->channel[queue];
4470 if (queue < priv->plat->rx_queues_to_use)
4471 netif_napi_del(&ch->rx_napi);
4472 if (queue < priv->plat->tx_queues_to_use)
4473 netif_napi_del(&ch->tx_napi);
4476 destroy_workqueue(priv->wq);
4480 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4484 * @dev: device pointer
4485 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4486 * changes the link status, releases the DMA descriptor rings.
4488 int stmmac_dvr_remove(struct device *dev)
4490 struct net_device *ndev = dev_get_drvdata(dev);
4491 struct stmmac_priv *priv = netdev_priv(ndev);
4493 netdev_info(priv->dev, "%s: removing driver", __func__);
4495 #ifdef CONFIG_DEBUG_FS
4496 stmmac_exit_fs(ndev);
4498 stmmac_stop_all_dma(priv);
4500 stmmac_mac_set(priv, priv->ioaddr, false);
4501 netif_carrier_off(ndev);
4502 unregister_netdev(ndev);
4503 phylink_destroy(priv->phylink);
4504 if (priv->plat->stmmac_rst)
4505 reset_control_assert(priv->plat->stmmac_rst);
4506 clk_disable_unprepare(priv->plat->pclk);
4507 clk_disable_unprepare(priv->plat->stmmac_clk);
4508 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4509 priv->hw->pcs != STMMAC_PCS_TBI &&
4510 priv->hw->pcs != STMMAC_PCS_RTBI)
4511 stmmac_mdio_unregister(ndev);
4512 destroy_workqueue(priv->wq);
4513 mutex_destroy(&priv->lock);
4517 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4520 * stmmac_suspend - suspend callback
4521 * @dev: device pointer
4522 * Description: this is the function to suspend the device and it is called
4523 * by the platform driver to stop the network queue, release the resources,
4524 * program the PMT register (for WoL), clean and release driver resources.
4526 int stmmac_suspend(struct device *dev)
4528 struct net_device *ndev = dev_get_drvdata(dev);
4529 struct stmmac_priv *priv = netdev_priv(ndev);
4531 if (!ndev || !netif_running(ndev))
4534 phylink_stop(priv->phylink);
4536 mutex_lock(&priv->lock);
4538 netif_device_detach(ndev);
4539 stmmac_stop_all_queues(priv);
4541 stmmac_disable_all_queues(priv);
4543 /* Stop TX/RX DMA */
4544 stmmac_stop_all_dma(priv);
4546 /* Enable Power down mode by programming the PMT regs */
4547 if (device_may_wakeup(priv->device)) {
4548 stmmac_pmt(priv, priv->hw, priv->wolopts);
4551 stmmac_mac_set(priv, priv->ioaddr, false);
4552 pinctrl_pm_select_sleep_state(priv->device);
4553 /* Disable clock in case of PWM is off */
4554 clk_disable(priv->plat->pclk);
4555 clk_disable(priv->plat->stmmac_clk);
4557 mutex_unlock(&priv->lock);
4559 priv->speed = SPEED_UNKNOWN;
4562 EXPORT_SYMBOL_GPL(stmmac_suspend);
4565 * stmmac_reset_queues_param - reset queue parameters
4566 * @dev: device pointer
4568 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4570 u32 rx_cnt = priv->plat->rx_queues_to_use;
4571 u32 tx_cnt = priv->plat->tx_queues_to_use;
4574 for (queue = 0; queue < rx_cnt; queue++) {
4575 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4581 for (queue = 0; queue < tx_cnt; queue++) {
4582 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4591 * stmmac_resume - resume callback
4592 * @dev: device pointer
4593 * Description: when resume this function is invoked to setup the DMA and CORE
4594 * in a usable state.
4596 int stmmac_resume(struct device *dev)
4598 struct net_device *ndev = dev_get_drvdata(dev);
4599 struct stmmac_priv *priv = netdev_priv(ndev);
4601 if (!netif_running(ndev))
4604 /* Power Down bit, into the PM register, is cleared
4605 * automatically as soon as a magic packet or a Wake-up frame
4606 * is received. Anyway, it's better to manually clear
4607 * this bit because it can generate problems while resuming
4608 * from another devices (e.g. serial console).
4610 if (device_may_wakeup(priv->device)) {
4611 mutex_lock(&priv->lock);
4612 stmmac_pmt(priv, priv->hw, 0);
4613 mutex_unlock(&priv->lock);
4616 pinctrl_pm_select_default_state(priv->device);
4617 /* enable the clk previously disabled */
4618 clk_enable(priv->plat->stmmac_clk);
4619 clk_enable(priv->plat->pclk);
4620 /* reset the phy so that it's ready */
4622 stmmac_mdio_reset(priv->mii);
4625 netif_device_attach(ndev);
4627 mutex_lock(&priv->lock);
4629 stmmac_reset_queues_param(priv);
4631 stmmac_clear_descriptors(priv);
4633 stmmac_hw_setup(ndev, false);
4634 stmmac_init_tx_coalesce(priv);
4635 stmmac_set_rx_mode(ndev);
4637 stmmac_enable_all_queues(priv);
4639 stmmac_start_all_queues(priv);
4641 mutex_unlock(&priv->lock);
4643 phylink_start(priv->phylink);
4647 EXPORT_SYMBOL_GPL(stmmac_resume);
4650 static int __init stmmac_cmdline_opt(char *str)
4656 while ((opt = strsep(&str, ",")) != NULL) {
4657 if (!strncmp(opt, "debug:", 6)) {
4658 if (kstrtoint(opt + 6, 0, &debug))
4660 } else if (!strncmp(opt, "phyaddr:", 8)) {
4661 if (kstrtoint(opt + 8, 0, &phyaddr))
4663 } else if (!strncmp(opt, "buf_sz:", 7)) {
4664 if (kstrtoint(opt + 7, 0, &buf_sz))
4666 } else if (!strncmp(opt, "tc:", 3)) {
4667 if (kstrtoint(opt + 3, 0, &tc))
4669 } else if (!strncmp(opt, "watchdog:", 9)) {
4670 if (kstrtoint(opt + 9, 0, &watchdog))
4672 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4673 if (kstrtoint(opt + 10, 0, &flow_ctrl))
4675 } else if (!strncmp(opt, "pause:", 6)) {
4676 if (kstrtoint(opt + 6, 0, &pause))
4678 } else if (!strncmp(opt, "eee_timer:", 10)) {
4679 if (kstrtoint(opt + 10, 0, &eee_timer))
4681 } else if (!strncmp(opt, "chain_mode:", 11)) {
4682 if (kstrtoint(opt + 11, 0, &chain_mode))
4689 pr_err("%s: ERROR broken module parameter conversion", __func__);
4693 __setup("stmmaceth=", stmmac_cmdline_opt);
4696 static int __init stmmac_init(void)
4698 #ifdef CONFIG_DEBUG_FS
4699 /* Create debugfs main directory if it doesn't exist yet */
4700 if (!stmmac_fs_dir) {
4701 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4703 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4704 pr_err("ERROR %s, debugfs create directory failed\n",
4705 STMMAC_RESOURCE_NAME);
4715 static void __exit stmmac_exit(void)
4717 #ifdef CONFIG_DEBUG_FS
4718 debugfs_remove_recursive(stmmac_fs_dir);
4722 module_init(stmmac_init)
4723 module_exit(stmmac_exit)
4725 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4726 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4727 MODULE_LICENSE("GPL");