drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*******************************************************************************
   3   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   4   ST Ethernet IPs are built around a Synopsys IP Core.
   5
   6         Copyright(C) 2007-2011 STMicroelectronics Ltd
   7
   8
   9   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  10
  11   Documentation available at:
  12         http://www.stlinux.com
  13   Support available at:
  14         https://bugzilla.stlinux.com/
  15 *******************************************************************************/
  16
  17 #include <linux/clk.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ip.h>
  21 #include <linux/tcp.h>
  22 #include <linux/skbuff.h>
  23 #include <linux/ethtool.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/crc32.h>
  26 #include <linux/mii.h>
  27 #include <linux/if.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/prefetch.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #ifdef CONFIG_DEBUG_FS
  34 #include <linux/debugfs.h>
  35 #include <linux/seq_file.h>
  36 #endif /* CONFIG_DEBUG_FS */
  37 #include <linux/net_tstamp.h>
  38 #include <linux/phylink.h>
  39 #include <net/pkt_cls.h>
  40 #include "stmmac_ptp.h"
  41 #include "stmmac.h"
  42 #include <linux/reset.h>
  43 #include <linux/of_mdio.h>
  44 #include "dwmac1000.h"
  45 #include "dwxgmac2.h"
  46 #include "hwif.h"
  47
  48 #define STMMAC_ALIGN(x)         __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
  49 #define TSO_MAX_BUFF_SIZE       (SZ_16K - 1)
  50
  51 /* Module parameters */
  52 #define TX_TIMEO        5000
  53 static int watchdog = TX_TIMEO;
  54 module_param(watchdog, int, 0644);
  55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
  56
  57 static int debug = -1;
  58 module_param(debug, int, 0644);
  59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
  60
  61 static int phyaddr = -1;
  62 module_param(phyaddr, int, 0444);
  63 MODULE_PARM_DESC(phyaddr, "Physical device address");
  64
  65 #define STMMAC_TX_THRESH        (DMA_TX_SIZE / 4)
  66 #define STMMAC_RX_THRESH        (DMA_RX_SIZE / 4)
  67
  68 static int flow_ctrl = FLOW_AUTO;
  69 module_param(flow_ctrl, int, 0644);
  70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
  71
  72 static int pause = PAUSE_TIME;
  73 module_param(pause, int, 0644);
  74 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
  75
  76 #define TC_DEFAULT 64
  77 static int tc = TC_DEFAULT;
  78 module_param(tc, int, 0644);
  79 MODULE_PARM_DESC(tc, "DMA threshold control value");
  80
  81 #define DEFAULT_BUFSIZE 1536
  82 static int buf_sz = DEFAULT_BUFSIZE;
  83 module_param(buf_sz, int, 0644);
  84 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
  85
  86 #define STMMAC_RX_COPYBREAK     256
  87
  88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  89                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
  90                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
  91
  92 #define STMMAC_DEFAULT_LPI_TIMER        1000
  93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
  94 module_param(eee_timer, int, 0644);
  95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
  96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
  97
  98 /* By default the driver will use the ring mode to manage tx and rx descriptors,
  99  * but allow user to force to use the chain instead of the ring
 100  */
 101 static unsigned int chain_mode;
 102 module_param(chain_mode, int, 0444);
 103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
 104
 105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 106
 107 #ifdef CONFIG_DEBUG_FS
 108 static int stmmac_init_fs(struct net_device *dev);
 109 static void stmmac_exit_fs(struct net_device *dev);
 110 #endif
 111
 112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 113
 114 /**
 115  * stmmac_verify_args - verify the driver parameters.
 116  * Description: it checks the driver parameters and set a default in case of
 117  * errors.
 118  */
 119 static void stmmac_verify_args(void)
 120 {
 121         if (unlikely(watchdog < 0))
 122                 watchdog = TX_TIMEO;
 123         if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
 124                 buf_sz = DEFAULT_BUFSIZE;
 125         if (unlikely(flow_ctrl > 1))
 126                 flow_ctrl = FLOW_AUTO;
 127         else if (likely(flow_ctrl < 0))
 128                 flow_ctrl = FLOW_OFF;
 129         if (unlikely((pause < 0) || (pause > 0xffff)))
 130                 pause = PAUSE_TIME;
 131         if (eee_timer < 0)
 132                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 133 }
 134
 135 /**
 136  * stmmac_disable_all_queues - Disable all queues
 137  * @priv: driver private structure
 138  */
 139 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
 140 {
 141         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 142         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 143         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 144         u32 queue;
 145
 146         for (queue = 0; queue < maxq; queue++) {
 147                 struct stmmac_channel *ch = &priv->channel[queue];
 148
 149                 if (queue < rx_queues_cnt)
 150                         napi_disable(&ch->rx_napi);
 151                 if (queue < tx_queues_cnt)
 152                         napi_disable(&ch->tx_napi);
 153         }
 154 }
 155
 156 /**
 157  * stmmac_enable_all_queues - Enable all queues
 158  * @priv: driver private structure
 159  */
 160 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
 161 {
 162         u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
 163         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 164         u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
 165         u32 queue;
 166
 167         for (queue = 0; queue < maxq; queue++) {
 168                 struct stmmac_channel *ch = &priv->channel[queue];
 169
 170                 if (queue < rx_queues_cnt)
 171                         napi_enable(&ch->rx_napi);
 172                 if (queue < tx_queues_cnt)
 173                         napi_enable(&ch->tx_napi);
 174         }
 175 }
 176
 177 /**
 178  * stmmac_stop_all_queues - Stop all queues
 179  * @priv: driver private structure
 180  */
 181 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
 182 {
 183         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 184         u32 queue;
 185
 186         for (queue = 0; queue < tx_queues_cnt; queue++)
 187                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
 188 }
 189
 190 /**
 191  * stmmac_start_all_queues - Start all queues
 192  * @priv: driver private structure
 193  */
 194 static void stmmac_start_all_queues(struct stmmac_priv *priv)
 195 {
 196         u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
 197         u32 queue;
 198
 199         for (queue = 0; queue < tx_queues_cnt; queue++)
 200                 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
 201 }
 202
 203 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
 204 {
 205         if (!test_bit(STMMAC_DOWN, &priv->state) &&
 206             !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
 207                 queue_work(priv->wq, &priv->service_task);
 208 }
 209
 210 static void stmmac_global_err(struct stmmac_priv *priv)
 211 {
 212         netif_carrier_off(priv->dev);
 213         set_bit(STMMAC_RESET_REQUESTED, &priv->state);
 214         stmmac_service_event_schedule(priv);
 215 }
 216
 217 /**
 218  * stmmac_clk_csr_set - dynamically set the MDC clock
 219  * @priv: driver private structure
 220  * Description: this is to dynamically set the MDC clock according to the csr
 221  * clock input.
 222  * Note:
 223  *      If a specific clk_csr value is passed from the platform
 224  *      this means that the CSR Clock Range selection cannot be
 225  *      changed at run-time and it is fixed (as reported in the driver
 226  *      documentation). Viceversa the driver will try to set the MDC
 227  *      clock dynamically according to the actual clock input.
 228  */
 229 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 230 {
 231         u32 clk_rate;
 232
 233         clk_rate = clk_get_rate(priv->plat->stmmac_clk);
 234
 235         /* Platform provided default clk_csr would be assumed valid
 236          * for all other cases except for the below mentioned ones.
 237          * For values higher than the IEEE 802.3 specified frequency
 238          * we can not estimate the proper divider as it is not known
 239          * the frequency of clk_csr_i. So we do not change the default
 240          * divider.
 241          */
 242         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 243                 if (clk_rate < CSR_F_35M)
 244                         priv->clk_csr = STMMAC_CSR_20_35M;
 245                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 246                         priv->clk_csr = STMMAC_CSR_35_60M;
 247                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 248                         priv->clk_csr = STMMAC_CSR_60_100M;
 249                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 250                         priv->clk_csr = STMMAC_CSR_100_150M;
 251                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 252                         priv->clk_csr = STMMAC_CSR_150_250M;
 253                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 254                         priv->clk_csr = STMMAC_CSR_250_300M;
 255         }
 256
 257         if (priv->plat->has_sun8i) {
 258                 if (clk_rate > 160000000)
 259                         priv->clk_csr = 0x03;
 260                 else if (clk_rate > 80000000)
 261                         priv->clk_csr = 0x02;
 262                 else if (clk_rate > 40000000)
 263                         priv->clk_csr = 0x01;
 264                 else
 265                         priv->clk_csr = 0;
 266         }
 267
 268         if (priv->plat->has_xgmac) {
 269                 if (clk_rate > 400000000)
 270                         priv->clk_csr = 0x5;
 271                 else if (clk_rate > 350000000)
 272                         priv->clk_csr = 0x4;
 273                 else if (clk_rate > 300000000)
 274                         priv->clk_csr = 0x3;
 275                 else if (clk_rate > 250000000)
 276                         priv->clk_csr = 0x2;
 277                 else if (clk_rate > 150000000)
 278                         priv->clk_csr = 0x1;
 279                 else
 280                         priv->clk_csr = 0x0;
 281         }
 282 }
 283
 284 static void print_pkt(unsigned char *buf, int len)
 285 {
 286         pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
 287         print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
 288 }
 289
 290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
 291 {
 292         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 293         u32 avail;
 294
 295         if (tx_q->dirty_tx > tx_q->cur_tx)
 296                 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
 297         else
 298                 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
 299
 300         return avail;
 301 }
 302
 303 /**
 304  * stmmac_rx_dirty - Get RX queue dirty
 305  * @priv: driver private structure
 306  * @queue: RX queue index
 307  */
 308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
 309 {
 310         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
 311         u32 dirty;
 312
 313         if (rx_q->dirty_rx <= rx_q->cur_rx)
 314                 dirty = rx_q->cur_rx - rx_q->dirty_rx;
 315         else
 316                 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
 317
 318         return dirty;
 319 }
 320
 321 /**
 322  * stmmac_enable_eee_mode - check and enter in LPI mode
 323  * @priv: driver private structure
 324  * Description: this function is to verify and enter in LPI mode in case of
 325  * EEE.
 326  */
 327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 328 {
 329         u32 tx_cnt = priv->plat->tx_queues_to_use;
 330         u32 queue;
 331
 332         /* check if all TX queues have the work finished */
 333         for (queue = 0; queue < tx_cnt; queue++) {
 334                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
 335
 336                 if (tx_q->dirty_tx != tx_q->cur_tx)
 337                         return; /* still unfinished work */
 338         }
 339
 340         /* Check and enter in LPI mode */
 341         if (!priv->tx_path_in_lpi_mode)
 342                 stmmac_set_eee_mode(priv, priv->hw,
 343                                 priv->plat->en_tx_lpi_clockgating);
 344 }
 345
 346 /**
 347  * stmmac_disable_eee_mode - disable and exit from LPI mode
 348  * @priv: driver private structure
 349  * Description: this function is to exit and disable EEE in case of
 350  * LPI state is true. This is called by the xmit.
 351  */
 352 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 353 {
 354         stmmac_reset_eee_mode(priv, priv->hw);
 355         del_timer_sync(&priv->eee_ctrl_timer);
 356         priv->tx_path_in_lpi_mode = false;
 357 }
 358
 359 /**
 360  * stmmac_eee_ctrl_timer - EEE TX SW timer.
 361  * @arg : data hook
 362  * Description:
 363  *  if there is no data transfer and if we are not in LPI state,
 364  *  then MAC Transmitter can be moved to LPI state.
 365  */
 366 static void stmmac_eee_ctrl_timer(struct timer_list *t)
 367 {
 368         struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
 369
 370         stmmac_enable_eee_mode(priv);
 371         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 372 }
 373
 374 /**
 375  * stmmac_eee_init - init EEE
 376  * @priv: driver private structure
 377  * Description:
 378  *  if the GMAC supports the EEE (from the HW cap reg) and the phy device
 379  *  can also manage EEE, this function enable the LPI state and start related
 380  *  timer.
 381  */
 382 bool stmmac_eee_init(struct stmmac_priv *priv)
 383 {
 384         int tx_lpi_timer = priv->tx_lpi_timer;
 385
 386         /* Using PCS we cannot dial with the phy registers at this stage
 387          * so we do not support extra feature like EEE.
 388          */
 389         if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
 390             (priv->hw->pcs == STMMAC_PCS_TBI) ||
 391             (priv->hw->pcs == STMMAC_PCS_RTBI))
 392                 return false;
 393
 394         /* Check if MAC core supports the EEE feature. */
 395         if (!priv->dma_cap.eee)
 396                 return false;
 397
 398         mutex_lock(&priv->lock);
 399
 400         /* Check if it needs to be deactivated */
 401         if (!priv->eee_active) {
 402                 if (priv->eee_enabled) {
 403                         netdev_dbg(priv->dev, "disable EEE\n");
 404                         del_timer_sync(&priv->eee_ctrl_timer);
 405                         stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
 406                 }
 407                 mutex_unlock(&priv->lock);
 408                 return false;
 409         }
 410
 411         if (priv->eee_active && !priv->eee_enabled) {
 412                 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
 413                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
 414                 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
 415                                      tx_lpi_timer);
 416         }
 417
 418         mutex_unlock(&priv->lock);
 419         netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
 420         return true;
 421 }
 422
 423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
 424  * @priv: driver private structure
 425  * @p : descriptor pointer
 426  * @skb : the socket buffer
 427  * Description :
 428  * This function will read timestamp from the descriptor & pass it to stack.
 429  * and also perform some sanity checks.
 430  */
 431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
 432                                    struct dma_desc *p, struct sk_buff *skb)
 433 {
 434         struct skb_shared_hwtstamps shhwtstamp;
 435         u64 ns = 0;
 436
 437         if (!priv->hwts_tx_en)
 438                 return;
 439
 440         /* exit if skb doesn't support hw tstamp */
 441         if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
 442                 return;
 443
 444         /* check tx tstamp status */
 445         if (stmmac_get_tx_timestamp_status(priv, p)) {
 446                 /* get the valid tstamp */
 447                 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
 448
 449                 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 450                 shhwtstamp.hwtstamp = ns_to_ktime(ns);
 451
 452                 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
 453                 /* pass tstamp to stack */
 454                 skb_tstamp_tx(skb, &shhwtstamp);
 455         }
 456
 457         return;
 458 }
 459
 460 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
 461  * @priv: driver private structure
 462  * @p : descriptor pointer
 463  * @np : next descriptor pointer
 464  * @skb : the socket buffer
 465  * Description :
 466  * This function will read received packet's timestamp from the descriptor
 467  * and pass it to stack. It also perform some sanity checks.
 468  */
 469 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
 470                                    struct dma_desc *np, struct sk_buff *skb)
 471 {
 472         struct skb_shared_hwtstamps *shhwtstamp = NULL;
 473         struct dma_desc *desc = p;
 474         u64 ns = 0;
 475
 476         if (!priv->hwts_rx_en)
 477                 return;
 478         /* For GMAC4, the valid timestamp is from CTX next desc. */
 479         if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
 480                 desc = np;
 481
 482         /* Check if timestamp is available */
 483         if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
 484                 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
 485                 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
 486                 shhwtstamp = skb_hwtstamps(skb);
 487                 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
 488                 shhwtstamp->hwtstamp = ns_to_ktime(ns);
 489         } else  {
 490                 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
 491         }
 492 }
 493
 494 /**
 495  *  stmmac_hwtstamp_set - control hardware timestamping.
 496  *  @dev: device pointer.
 497  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 498  *  a proprietary structure used to pass information to the driver.
 499  *  Description:
 500  *  This function configures the MAC to enable/disable both outgoing(TX)
 501  *  and incoming(RX) packets time stamping based on user input.
 502  *  Return Value:
 503  *  0 on success and an appropriate -ve integer on failure.
 504  */
 505 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
 506 {
 507         struct stmmac_priv *priv = netdev_priv(dev);
 508         struct hwtstamp_config config;
 509         struct timespec64 now;
 510         u64 temp = 0;
 511         u32 ptp_v2 = 0;
 512         u32 tstamp_all = 0;
 513         u32 ptp_over_ipv4_udp = 0;
 514         u32 ptp_over_ipv6_udp = 0;
 515         u32 ptp_over_ethernet = 0;
 516         u32 snap_type_sel = 0;
 517         u32 ts_master_en = 0;
 518         u32 ts_event_en = 0;
 519         u32 sec_inc = 0;
 520         u32 value = 0;
 521         bool xmac;
 522
 523         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 524
 525         if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
 526                 netdev_alert(priv->dev, "No support for HW time stamping\n");
 527                 priv->hwts_tx_en = 0;
 528                 priv->hwts_rx_en = 0;
 529
 530                 return -EOPNOTSUPP;
 531         }
 532
 533         if (copy_from_user(&config, ifr->ifr_data,
 534                            sizeof(config)))
 535                 return -EFAULT;
 536
 537         netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
 538                    __func__, config.flags, config.tx_type, config.rx_filter);
 539
 540         /* reserved for future extensions */
 541         if (config.flags)
 542                 return -EINVAL;
 543
 544         if (config.tx_type != HWTSTAMP_TX_OFF &&
 545             config.tx_type != HWTSTAMP_TX_ON)
 546                 return -ERANGE;
 547
 548         if (priv->adv_ts) {
 549                 switch (config.rx_filter) {
 550                 case HWTSTAMP_FILTER_NONE:
 551                         /* time stamp no incoming packet at all */
 552                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 553                         break;
 554
 555                 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 556                         /* PTP v1, UDP, any kind of event packet */
 557                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 558                         /* 'xmac' hardware can support Sync, Pdelay_Req and
 559                          * Pdelay_resp by setting bit14 and bits17/16 to 01
 560                          * This leaves Delay_Req timestamps out.
 561                          * Enable all events *and* general purpose message
 562                          * timestamping
 563                          */
 564                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 565                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 566                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 567                         break;
 568
 569                 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 570                         /* PTP v1, UDP, Sync packet */
 571                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
 572                         /* take time stamp for SYNC messages only */
 573                         ts_event_en = PTP_TCR_TSEVNTENA;
 574
 575                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 576                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 577                         break;
 578
 579                 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 580                         /* PTP v1, UDP, Delay_req packet */
 581                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
 582                         /* take time stamp for Delay_Req messages only */
 583                         ts_master_en = PTP_TCR_TSMSTRENA;
 584                         ts_event_en = PTP_TCR_TSEVNTENA;
 585
 586                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 587                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 588                         break;
 589
 590                 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 591                         /* PTP v2, UDP, any kind of event packet */
 592                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
 593                         ptp_v2 = PTP_TCR_TSVER2ENA;
 594                         /* take time stamp for all event messages */
 595                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 596
 597                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 598                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 599                         break;
 600
 601                 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 602                         /* PTP v2, UDP, Sync packet */
 603                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
 604                         ptp_v2 = PTP_TCR_TSVER2ENA;
 605                         /* take time stamp for SYNC messages only */
 606                         ts_event_en = PTP_TCR_TSEVNTENA;
 607
 608                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 609                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 610                         break;
 611
 612                 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 613                         /* PTP v2, UDP, Delay_req packet */
 614                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
 615                         ptp_v2 = PTP_TCR_TSVER2ENA;
 616                         /* take time stamp for Delay_Req messages only */
 617                         ts_master_en = PTP_TCR_TSMSTRENA;
 618                         ts_event_en = PTP_TCR_TSEVNTENA;
 619
 620                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 621                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 622                         break;
 623
 624                 case HWTSTAMP_FILTER_PTP_V2_EVENT:
 625                         /* PTP v2/802.AS1 any layer, any kind of event packet */
 626                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
 627                         ptp_v2 = PTP_TCR_TSVER2ENA;
 628                         snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
 629                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 630                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 631                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 632                         break;
 633
 634                 case HWTSTAMP_FILTER_PTP_V2_SYNC:
 635                         /* PTP v2/802.AS1, any layer, Sync packet */
 636                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
 637                         ptp_v2 = PTP_TCR_TSVER2ENA;
 638                         /* take time stamp for SYNC messages only */
 639                         ts_event_en = PTP_TCR_TSEVNTENA;
 640
 641                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 642                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 643                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 644                         break;
 645
 646                 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 647                         /* PTP v2/802.AS1, any layer, Delay_req packet */
 648                         config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
 649                         ptp_v2 = PTP_TCR_TSVER2ENA;
 650                         /* take time stamp for Delay_Req messages only */
 651                         ts_master_en = PTP_TCR_TSMSTRENA;
 652                         ts_event_en = PTP_TCR_TSEVNTENA;
 653
 654                         ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
 655                         ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
 656                         ptp_over_ethernet = PTP_TCR_TSIPENA;
 657                         break;
 658
 659                 case HWTSTAMP_FILTER_NTP_ALL:
 660                 case HWTSTAMP_FILTER_ALL:
 661                         /* time stamp any incoming packet */
 662                         config.rx_filter = HWTSTAMP_FILTER_ALL;
 663                         tstamp_all = PTP_TCR_TSENALL;
 664                         break;
 665
 666                 default:
 667                         return -ERANGE;
 668                 }
 669         } else {
 670                 switch (config.rx_filter) {
 671                 case HWTSTAMP_FILTER_NONE:
 672                         config.rx_filter = HWTSTAMP_FILTER_NONE;
 673                         break;
 674                 default:
 675                         /* PTP v1, UDP, any kind of event packet */
 676                         config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
 677                         break;
 678                 }
 679         }
 680         priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
 681         priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
 682
 683         if (!priv->hwts_tx_en && !priv->hwts_rx_en)
 684                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
 685         else {
 686                 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
 687                          tstamp_all | ptp_v2 | ptp_over_ethernet |
 688                          ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
 689                          ts_master_en | snap_type_sel);
 690                 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
 691
 692                 /* program Sub Second Increment reg */
 693                 stmmac_config_sub_second_increment(priv,
 694                                 priv->ptpaddr, priv->plat->clk_ptp_rate,
 695                                 xmac, &sec_inc);
 696                 temp = div_u64(1000000000ULL, sec_inc);
 697
 698                 /* Store sub second increment and flags for later use */
 699                 priv->sub_second_inc = sec_inc;
 700                 priv->systime_flags = value;
 701
 702                 /* calculate default added value:
 703                  * formula is :
 704                  * addend = (2^32)/freq_div_ratio;
 705                  * where, freq_div_ratio = 1e9ns/sec_inc
 706                  */
 707                 temp = (u64)(temp << 32);
 708                 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
 709                 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
 710
 711                 /* initialize system time */
 712                 ktime_get_real_ts64(&now);
 713
 714                 /* lower 32 bits of tv_sec are safe until y2106 */
 715                 stmmac_init_systime(priv, priv->ptpaddr,
 716                                 (u32)now.tv_sec, now.tv_nsec);
 717         }
 718
 719         memcpy(&priv->tstamp_config, &config, sizeof(config));
 720
 721         return copy_to_user(ifr->ifr_data, &config,
 722                             sizeof(config)) ? -EFAULT : 0;
 723 }
 724
 725 /**
 726  *  stmmac_hwtstamp_get - read hardware timestamping.
 727  *  @dev: device pointer.
 728  *  @ifr: An IOCTL specific structure, that can contain a pointer to
 729  *  a proprietary structure used to pass information to the driver.
 730  *  Description:
 731  *  This function obtain the current hardware timestamping settings
 732     as requested.
 733  */
 734 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
 735 {
 736         struct stmmac_priv *priv = netdev_priv(dev);
 737         struct hwtstamp_config *config = &priv->tstamp_config;
 738
 739         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 740                 return -EOPNOTSUPP;
 741
 742         return copy_to_user(ifr->ifr_data, config,
 743                             sizeof(*config)) ? -EFAULT : 0;
 744 }
 745
 746 /**
 747  * stmmac_init_ptp - init PTP
 748  * @priv: driver private structure
 749  * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
 750  * This is done by looking at the HW cap. register.
 751  * This function also registers the ptp driver.
 752  */
 753 static int stmmac_init_ptp(struct stmmac_priv *priv)
 754 {
 755         bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
 756
 757         if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
 758                 return -EOPNOTSUPP;
 759
 760         priv->adv_ts = 0;
 761         /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
 762         if (xmac && priv->dma_cap.atime_stamp)
 763                 priv->adv_ts = 1;
 764         /* Dwmac 3.x core with extend_desc can support adv_ts */
 765         else if (priv->extend_desc && priv->dma_cap.atime_stamp)
 766                 priv->adv_ts = 1;
 767
 768         if (priv->dma_cap.time_stamp)
 769                 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
 770
 771         if (priv->adv_ts)
 772                 netdev_info(priv->dev,
 773                             "IEEE 1588-2008 Advanced Timestamp supported\n");
 774
 775         priv->hwts_tx_en = 0;
 776         priv->hwts_rx_en = 0;
 777
 778         stmmac_ptp_register(priv);
 779
 780         return 0;
 781 }
 782
 783 static void stmmac_release_ptp(struct stmmac_priv *priv)
 784 {
 785         if (priv->plat->clk_ptp_ref)
 786                 clk_disable_unprepare(priv->plat->clk_ptp_ref);
 787         stmmac_ptp_unregister(priv);
 788 }
 789
 790 /**
 791  *  stmmac_mac_flow_ctrl - Configure flow control in all queues
 792  *  @priv: driver private structure
 793  *  Description: It is used for configuring the flow control in all queues
 794  */
 795 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
 796 {
 797         u32 tx_cnt = priv->plat->tx_queues_to_use;
 798
 799         stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
 800                         priv->pause, tx_cnt);
 801 }
 802
 803 static void stmmac_validate(struct phylink_config *config,
 804                             unsigned long *supported,
 805                             struct phylink_link_state *state)
 806 {
 807         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 808         __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
 809         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 810         int tx_cnt = priv->plat->tx_queues_to_use;
 811         int max_speed = priv->plat->max_speed;
 812
 813         phylink_set(mac_supported, 10baseT_Half);
 814         phylink_set(mac_supported, 10baseT_Full);
 815         phylink_set(mac_supported, 100baseT_Half);
 816         phylink_set(mac_supported, 100baseT_Full);
 817
 818         phylink_set(mac_supported, Autoneg);
 819         phylink_set(mac_supported, Pause);
 820         phylink_set(mac_supported, Asym_Pause);
 821         phylink_set_port_modes(mac_supported);
 822
 823         if (priv->plat->has_gmac ||
 824             priv->plat->has_gmac4 ||
 825             priv->plat->has_xgmac) {
 826                 phylink_set(mac_supported, 1000baseT_Half);
 827                 phylink_set(mac_supported, 1000baseT_Full);
 828                 phylink_set(mac_supported, 1000baseKX_Full);
 829         }
 830
 831         /* Cut down 1G if asked to */
 832         if ((max_speed > 0) && (max_speed < 1000)) {
 833                 phylink_set(mask, 1000baseT_Full);
 834                 phylink_set(mask, 1000baseX_Full);
 835         } else if (priv->plat->has_xgmac) {
 836                 phylink_set(mac_supported, 2500baseT_Full);
 837                 phylink_set(mac_supported, 5000baseT_Full);
 838                 phylink_set(mac_supported, 10000baseSR_Full);
 839                 phylink_set(mac_supported, 10000baseLR_Full);
 840                 phylink_set(mac_supported, 10000baseER_Full);
 841                 phylink_set(mac_supported, 10000baseLRM_Full);
 842                 phylink_set(mac_supported, 10000baseT_Full);
 843                 phylink_set(mac_supported, 10000baseKX4_Full);
 844                 phylink_set(mac_supported, 10000baseKR_Full);
 845         }
 846
 847         /* Half-Duplex can only work with single queue */
 848         if (tx_cnt > 1) {
 849                 phylink_set(mask, 10baseT_Half);
 850                 phylink_set(mask, 100baseT_Half);
 851                 phylink_set(mask, 1000baseT_Half);
 852         }
 853
 854         bitmap_and(supported, supported, mac_supported,
 855                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 856         bitmap_andnot(supported, supported, mask,
 857                       __ETHTOOL_LINK_MODE_MASK_NBITS);
 858         bitmap_and(state->advertising, state->advertising, mac_supported,
 859                    __ETHTOOL_LINK_MODE_MASK_NBITS);
 860         bitmap_andnot(state->advertising, state->advertising, mask,
 861                       __ETHTOOL_LINK_MODE_MASK_NBITS);
 862 }
 863
 864 static int stmmac_mac_link_state(struct phylink_config *config,
 865                                  struct phylink_link_state *state)
 866 {
 867         return -EOPNOTSUPP;
 868 }
 869
 870 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
 871                               const struct phylink_link_state *state)
 872 {
 873         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 874         u32 ctrl;
 875
 876         ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 877         ctrl &= ~priv->hw->link.speed_mask;
 878
 879         if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
 880                 switch (state->speed) {
 881                 case SPEED_10000:
 882                         ctrl |= priv->hw->link.xgmii.speed10000;
 883                         break;
 884                 case SPEED_5000:
 885                         ctrl |= priv->hw->link.xgmii.speed5000;
 886                         break;
 887                 case SPEED_2500:
 888                         ctrl |= priv->hw->link.xgmii.speed2500;
 889                         break;
 890                 default:
 891                         return;
 892                 }
 893         } else {
 894                 switch (state->speed) {
 895                 case SPEED_2500:
 896                         ctrl |= priv->hw->link.speed2500;
 897                         break;
 898                 case SPEED_1000:
 899                         ctrl |= priv->hw->link.speed1000;
 900                         break;
 901                 case SPEED_100:
 902                         ctrl |= priv->hw->link.speed100;
 903                         break;
 904                 case SPEED_10:
 905                         ctrl |= priv->hw->link.speed10;
 906                         break;
 907                 default:
 908                         return;
 909                 }
 910         }
 911
 912         priv->speed = state->speed;
 913
 914         if (priv->plat->fix_mac_speed)
 915                 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed);
 916
 917         if (!state->duplex)
 918                 ctrl &= ~priv->hw->link.duplex;
 919         else
 920                 ctrl |= priv->hw->link.duplex;
 921
 922         /* Flow Control operation */
 923         if (state->pause)
 924                 stmmac_mac_flow_ctrl(priv, state->duplex);
 925
 926         writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 927 }
 928
 929 static void stmmac_mac_an_restart(struct phylink_config *config)
 930 {
 931         /* Not Supported */
 932 }
 933
 934 static void stmmac_mac_link_down(struct phylink_config *config,
 935                                  unsigned int mode, phy_interface_t interface)
 936 {
 937         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 938
 939         stmmac_mac_set(priv, priv->ioaddr, false);
 940         priv->eee_active = false;
 941         stmmac_eee_init(priv);
 942         stmmac_set_eee_pls(priv, priv->hw, false);
 943 }
 944
 945 static void stmmac_mac_link_up(struct phylink_config *config,
 946                                unsigned int mode, phy_interface_t interface,
 947                                struct phy_device *phy)
 948 {
 949         struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
 950
 951         stmmac_mac_set(priv, priv->ioaddr, true);
 952         if (phy && priv->dma_cap.eee) {
 953                 priv->eee_active = phy_init_eee(phy, 1) >= 0;
 954                 priv->eee_enabled = stmmac_eee_init(priv);
 955                 stmmac_set_eee_pls(priv, priv->hw, true);
 956         }
 957 }
 958
 959 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
 960         .validate = stmmac_validate,
 961         .mac_link_state = stmmac_mac_link_state,
 962         .mac_config = stmmac_mac_config,
 963         .mac_an_restart = stmmac_mac_an_restart,
 964         .mac_link_down = stmmac_mac_link_down,
 965         .mac_link_up = stmmac_mac_link_up,
 966 };
 967
 968 /**
 969  * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
 970  * @priv: driver private structure
 971  * Description: this is to verify if the HW supports the PCS.
 972  * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
 973  * configured for the TBI, RTBI, or SGMII PHY interface.
 974  */
 975 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
 976 {
 977         int interface = priv->plat->interface;
 978
 979         if (priv->dma_cap.pcs) {
 980                 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
 981                     (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 982                     (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
 983                     (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
 984                         netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
 985                         priv->hw->pcs = STMMAC_PCS_RGMII;
 986                 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
 987                         netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
 988                         priv->hw->pcs = STMMAC_PCS_SGMII;
 989                 }
 990         }
 991 }
 992
 993 /**
 994  * stmmac_init_phy - PHY initialization
 995  * @dev: net device structure
 996  * Description: it initializes the driver's PHY state, and attaches the PHY
 997  * to the mac driver.
 998  *  Return value:
 999  *  0 on success
1000  */
1001 static int stmmac_init_phy(struct net_device *dev)
1002 {
1003         struct stmmac_priv *priv = netdev_priv(dev);
1004         struct device_node *node;
1005         int ret;
1006
1007         node = priv->plat->phylink_node;
1008
1009         if (node)
1010                 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1011
1012         /* Some DT bindings do not set-up the PHY handle. Let's try to
1013          * manually parse it
1014          */
1015         if (!node || ret) {
1016                 int addr = priv->plat->phy_addr;
1017                 struct phy_device *phydev;
1018
1019                 phydev = mdiobus_get_phy(priv->mii, addr);
1020                 if (!phydev) {
1021                         netdev_err(priv->dev, "no phy at addr %d\n", addr);
1022                         return -ENODEV;
1023                 }
1024
1025                 ret = phylink_connect_phy(priv->phylink, phydev);
1026         }
1027
1028         return ret;
1029 }
1030
1031 static int stmmac_phy_setup(struct stmmac_priv *priv)
1032 {
1033         struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1034         int mode = priv->plat->interface;
1035         struct phylink *phylink;
1036
1037         priv->phylink_config.dev = &priv->dev->dev;
1038         priv->phylink_config.type = PHYLINK_NETDEV;
1039
1040         phylink = phylink_create(&priv->phylink_config, fwnode,
1041                                  mode, &stmmac_phylink_mac_ops);
1042         if (IS_ERR(phylink))
1043                 return PTR_ERR(phylink);
1044
1045         priv->phylink = phylink;
1046         return 0;
1047 }
1048
1049 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1050 {
1051         u32 rx_cnt = priv->plat->rx_queues_to_use;
1052         void *head_rx;
1053         u32 queue;
1054
1055         /* Display RX rings */
1056         for (queue = 0; queue < rx_cnt; queue++) {
1057                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1058
1059                 pr_info("\tRX Queue %u rings\n", queue);
1060
1061                 if (priv->extend_desc)
1062                         head_rx = (void *)rx_q->dma_erx;
1063                 else
1064                         head_rx = (void *)rx_q->dma_rx;
1065
1066                 /* Display RX ring */
1067                 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1068         }
1069 }
1070
1071 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1072 {
1073         u32 tx_cnt = priv->plat->tx_queues_to_use;
1074         void *head_tx;
1075         u32 queue;
1076
1077         /* Display TX rings */
1078         for (queue = 0; queue < tx_cnt; queue++) {
1079                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1080
1081                 pr_info("\tTX Queue %d rings\n", queue);
1082
1083                 if (priv->extend_desc)
1084                         head_tx = (void *)tx_q->dma_etx;
1085                 else
1086                         head_tx = (void *)tx_q->dma_tx;
1087
1088                 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1089         }
1090 }
1091
1092 static void stmmac_display_rings(struct stmmac_priv *priv)
1093 {
1094         /* Display RX ring */
1095         stmmac_display_rx_rings(priv);
1096
1097         /* Display TX ring */
1098         stmmac_display_tx_rings(priv);
1099 }
1100
1101 static int stmmac_set_bfsize(int mtu, int bufsize)
1102 {
1103         int ret = bufsize;
1104
1105         if (mtu >= BUF_SIZE_4KiB)
1106                 ret = BUF_SIZE_8KiB;
1107         else if (mtu >= BUF_SIZE_2KiB)
1108                 ret = BUF_SIZE_4KiB;
1109         else if (mtu > DEFAULT_BUFSIZE)
1110                 ret = BUF_SIZE_2KiB;
1111         else
1112                 ret = DEFAULT_BUFSIZE;
1113
1114         return ret;
1115 }
1116
1117 /**
1118  * stmmac_clear_rx_descriptors - clear RX descriptors
1119  * @priv: driver private structure
1120  * @queue: RX queue index
1121  * Description: this function is called to clear the RX descriptors
1122  * in case of both basic and extended descriptors are used.
1123  */
1124 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1125 {
1126         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1127         int i;
1128
1129         /* Clear the RX descriptors */
1130         for (i = 0; i < DMA_RX_SIZE; i++)
1131                 if (priv->extend_desc)
1132                         stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1133                                         priv->use_riwt, priv->mode,
1134                                         (i == DMA_RX_SIZE - 1),
1135                                         priv->dma_buf_sz);
1136                 else
1137                         stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1138                                         priv->use_riwt, priv->mode,
1139                                         (i == DMA_RX_SIZE - 1),
1140                                         priv->dma_buf_sz);
1141 }
1142
1143 /**
1144  * stmmac_clear_tx_descriptors - clear tx descriptors
1145  * @priv: driver private structure
1146  * @queue: TX queue index.
1147  * Description: this function is called to clear the TX descriptors
1148  * in case of both basic and extended descriptors are used.
1149  */
1150 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1151 {
1152         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1153         int i;
1154
1155         /* Clear the TX descriptors */
1156         for (i = 0; i < DMA_TX_SIZE; i++)
1157                 if (priv->extend_desc)
1158                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1159                                         priv->mode, (i == DMA_TX_SIZE - 1));
1160                 else
1161                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1162                                         priv->mode, (i == DMA_TX_SIZE - 1));
1163 }
1164
1165 /**
1166  * stmmac_clear_descriptors - clear descriptors
1167  * @priv: driver private structure
1168  * Description: this function is called to clear the TX and RX descriptors
1169  * in case of both basic and extended descriptors are used.
1170  */
1171 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1172 {
1173         u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1174         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1175         u32 queue;
1176
1177         /* Clear the RX descriptors */
1178         for (queue = 0; queue < rx_queue_cnt; queue++)
1179                 stmmac_clear_rx_descriptors(priv, queue);
1180
1181         /* Clear the TX descriptors */
1182         for (queue = 0; queue < tx_queue_cnt; queue++)
1183                 stmmac_clear_tx_descriptors(priv, queue);
1184 }
1185
1186 /**
1187  * stmmac_init_rx_buffers - init the RX descriptor buffer.
1188  * @priv: driver private structure
1189  * @p: descriptor pointer
1190  * @i: descriptor index
1191  * @flags: gfp flag
1192  * @queue: RX queue index
1193  * Description: this function is called to allocate a receive buffer, perform
1194  * the DMA mapping and init the descriptor.
1195  */
1196 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1197                                   int i, gfp_t flags, u32 queue)
1198 {
1199         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1200         struct sk_buff *skb;
1201
1202         skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags);
1203         if (!skb) {
1204                 netdev_err(priv->dev,
1205                            "%s: Rx init fails; skb is NULL\n", __func__);
1206                 return -ENOMEM;
1207         }
1208         rx_q->rx_skbuff[i] = skb;
1209         rx_q->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
1210                                                 priv->dma_buf_sz,
1211                                                 DMA_FROM_DEVICE);
1212         if (dma_mapping_error(priv->device, rx_q->rx_skbuff_dma[i])) {
1213                 netdev_err(priv->dev, "%s: DMA mapping error\n", __func__);
1214                 dev_kfree_skb_any(skb);
1215                 return -EINVAL;
1216         }
1217
1218         stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[i]);
1219
1220         if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1221                 stmmac_init_desc3(priv, p);
1222
1223         return 0;
1224 }
1225
1226 /**
1227  * stmmac_free_rx_buffer - free RX dma buffers
1228  * @priv: private structure
1229  * @queue: RX queue index
1230  * @i: buffer index.
1231  */
1232 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1233 {
1234         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1235
1236         if (rx_q->rx_skbuff[i]) {
1237                 dma_unmap_single(priv->device, rx_q->rx_skbuff_dma[i],
1238                                  priv->dma_buf_sz, DMA_FROM_DEVICE);
1239                 dev_kfree_skb_any(rx_q->rx_skbuff[i]);
1240         }
1241         rx_q->rx_skbuff[i] = NULL;
1242 }
1243
1244 /**
1245  * stmmac_free_tx_buffer - free RX dma buffers
1246  * @priv: private structure
1247  * @queue: RX queue index
1248  * @i: buffer index.
1249  */
1250 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1251 {
1252         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1253
1254         if (tx_q->tx_skbuff_dma[i].buf) {
1255                 if (tx_q->tx_skbuff_dma[i].map_as_page)
1256                         dma_unmap_page(priv->device,
1257                                        tx_q->tx_skbuff_dma[i].buf,
1258                                        tx_q->tx_skbuff_dma[i].len,
1259                                        DMA_TO_DEVICE);
1260                 else
1261                         dma_unmap_single(priv->device,
1262                                          tx_q->tx_skbuff_dma[i].buf,
1263                                          tx_q->tx_skbuff_dma[i].len,
1264                                          DMA_TO_DEVICE);
1265         }
1266
1267         if (tx_q->tx_skbuff[i]) {
1268                 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1269                 tx_q->tx_skbuff[i] = NULL;
1270                 tx_q->tx_skbuff_dma[i].buf = 0;
1271                 tx_q->tx_skbuff_dma[i].map_as_page = false;
1272         }
1273 }
1274
1275 /**
1276  * init_dma_rx_desc_rings - init the RX descriptor rings
1277  * @dev: net device structure
1278  * @flags: gfp flag.
1279  * Description: this function initializes the DMA RX descriptors
1280  * and allocates the socket buffers. It supports the chained and ring
1281  * modes.
1282  */
1283 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1284 {
1285         struct stmmac_priv *priv = netdev_priv(dev);
1286         u32 rx_count = priv->plat->rx_queues_to_use;
1287         int ret = -ENOMEM;
1288         int bfsize = 0;
1289         int queue;
1290         int i;
1291
1292         bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1293         if (bfsize < 0)
1294                 bfsize = 0;
1295
1296         if (bfsize < BUF_SIZE_16KiB)
1297                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1298
1299         priv->dma_buf_sz = bfsize;
1300
1301         /* RX INITIALIZATION */
1302         netif_dbg(priv, probe, priv->dev,
1303                   "SKB addresses:\nskb\t\tskb data\tdma data\n");
1304
1305         for (queue = 0; queue < rx_count; queue++) {
1306                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1307
1308                 netif_dbg(priv, probe, priv->dev,
1309                           "(%s) dma_rx_phy=0x%08x\n", __func__,
1310                           (u32)rx_q->dma_rx_phy);
1311
1312                 for (i = 0; i < DMA_RX_SIZE; i++) {
1313                         struct dma_desc *p;
1314
1315                         if (priv->extend_desc)
1316                                 p = &((rx_q->dma_erx + i)->basic);
1317                         else
1318                                 p = rx_q->dma_rx + i;
1319
1320                         ret = stmmac_init_rx_buffers(priv, p, i, flags,
1321                                                      queue);
1322                         if (ret)
1323                                 goto err_init_rx_buffers;
1324
1325                         netif_dbg(priv, probe, priv->dev, "[%p]\t[%p]\t[%x]\n",
1326                                   rx_q->rx_skbuff[i], rx_q->rx_skbuff[i]->data,
1327                                   (unsigned int)rx_q->rx_skbuff_dma[i]);
1328                 }
1329
1330                 rx_q->cur_rx = 0;
1331                 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1332
1333                 stmmac_clear_rx_descriptors(priv, queue);
1334
1335                 /* Setup the chained descriptor addresses */
1336                 if (priv->mode == STMMAC_CHAIN_MODE) {
1337                         if (priv->extend_desc)
1338                                 stmmac_mode_init(priv, rx_q->dma_erx,
1339                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1340                         else
1341                                 stmmac_mode_init(priv, rx_q->dma_rx,
1342                                                 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1343                 }
1344         }
1345
1346         buf_sz = bfsize;
1347
1348         return 0;
1349
1350 err_init_rx_buffers:
1351         while (queue >= 0) {
1352                 while (--i >= 0)
1353                         stmmac_free_rx_buffer(priv, queue, i);
1354
1355                 if (queue == 0)
1356                         break;
1357
1358                 i = DMA_RX_SIZE;
1359                 queue--;
1360         }
1361
1362         return ret;
1363 }
1364
1365 /**
1366  * init_dma_tx_desc_rings - init the TX descriptor rings
1367  * @dev: net device structure.
1368  * Description: this function initializes the DMA TX descriptors
1369  * and allocates the socket buffers. It supports the chained and ring
1370  * modes.
1371  */
1372 static int init_dma_tx_desc_rings(struct net_device *dev)
1373 {
1374         struct stmmac_priv *priv = netdev_priv(dev);
1375         u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1376         u32 queue;
1377         int i;
1378
1379         for (queue = 0; queue < tx_queue_cnt; queue++) {
1380                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1381
1382                 netif_dbg(priv, probe, priv->dev,
1383                           "(%s) dma_tx_phy=0x%08x\n", __func__,
1384                          (u32)tx_q->dma_tx_phy);
1385
1386                 /* Setup the chained descriptor addresses */
1387                 if (priv->mode == STMMAC_CHAIN_MODE) {
1388                         if (priv->extend_desc)
1389                                 stmmac_mode_init(priv, tx_q->dma_etx,
1390                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1391                         else
1392                                 stmmac_mode_init(priv, tx_q->dma_tx,
1393                                                 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1394                 }
1395
1396                 for (i = 0; i < DMA_TX_SIZE; i++) {
1397                         struct dma_desc *p;
1398                         if (priv->extend_desc)
1399                                 p = &((tx_q->dma_etx + i)->basic);
1400                         else
1401                                 p = tx_q->dma_tx + i;
1402
1403                         stmmac_clear_desc(priv, p);
1404
1405                         tx_q->tx_skbuff_dma[i].buf = 0;
1406                         tx_q->tx_skbuff_dma[i].map_as_page = false;
1407                         tx_q->tx_skbuff_dma[i].len = 0;
1408                         tx_q->tx_skbuff_dma[i].last_segment = false;
1409                         tx_q->tx_skbuff[i] = NULL;
1410                 }
1411
1412                 tx_q->dirty_tx = 0;
1413                 tx_q->cur_tx = 0;
1414                 tx_q->mss = 0;
1415
1416                 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1417         }
1418
1419         return 0;
1420 }
1421
1422 /**
1423  * init_dma_desc_rings - init the RX/TX descriptor rings
1424  * @dev: net device structure
1425  * @flags: gfp flag.
1426  * Description: this function initializes the DMA RX/TX descriptors
1427  * and allocates the socket buffers. It supports the chained and ring
1428  * modes.
1429  */
1430 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1431 {
1432         struct stmmac_priv *priv = netdev_priv(dev);
1433         int ret;
1434
1435         ret = init_dma_rx_desc_rings(dev, flags);
1436         if (ret)
1437                 return ret;
1438
1439         ret = init_dma_tx_desc_rings(dev);
1440
1441         stmmac_clear_descriptors(priv);
1442
1443         if (netif_msg_hw(priv))
1444                 stmmac_display_rings(priv);
1445
1446         return ret;
1447 }
1448
1449 /**
1450  * dma_free_rx_skbufs - free RX dma buffers
1451  * @priv: private structure
1452  * @queue: RX queue index
1453  */
1454 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1455 {
1456         int i;
1457
1458         for (i = 0; i < DMA_RX_SIZE; i++)
1459                 stmmac_free_rx_buffer(priv, queue, i);
1460 }
1461
1462 /**
1463  * dma_free_tx_skbufs - free TX dma buffers
1464  * @priv: private structure
1465  * @queue: TX queue index
1466  */
1467 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1468 {
1469         int i;
1470
1471         for (i = 0; i < DMA_TX_SIZE; i++)
1472                 stmmac_free_tx_buffer(priv, queue, i);
1473 }
1474
1475 /**
1476  * free_dma_rx_desc_resources - free RX dma desc resources
1477  * @priv: private structure
1478  */
1479 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1480 {
1481         u32 rx_count = priv->plat->rx_queues_to_use;
1482         u32 queue;
1483
1484         /* Free RX queue resources */
1485         for (queue = 0; queue < rx_count; queue++) {
1486                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1487
1488                 /* Release the DMA RX socket buffers */
1489                 dma_free_rx_skbufs(priv, queue);
1490
1491                 /* Free DMA regions of consistent memory previously allocated */
1492                 if (!priv->extend_desc)
1493                         dma_free_coherent(priv->device,
1494                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1495                                           rx_q->dma_rx, rx_q->dma_rx_phy);
1496                 else
1497                         dma_free_coherent(priv->device, DMA_RX_SIZE *
1498                                           sizeof(struct dma_extended_desc),
1499                                           rx_q->dma_erx, rx_q->dma_rx_phy);
1500
1501                 kfree(rx_q->rx_skbuff_dma);
1502                 kfree(rx_q->rx_skbuff);
1503         }
1504 }
1505
1506 /**
1507  * free_dma_tx_desc_resources - free TX dma desc resources
1508  * @priv: private structure
1509  */
1510 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1511 {
1512         u32 tx_count = priv->plat->tx_queues_to_use;
1513         u32 queue;
1514
1515         /* Free TX queue resources */
1516         for (queue = 0; queue < tx_count; queue++) {
1517                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1518
1519                 /* Release the DMA TX socket buffers */
1520                 dma_free_tx_skbufs(priv, queue);
1521
1522                 /* Free DMA regions of consistent memory previously allocated */
1523                 if (!priv->extend_desc)
1524                         dma_free_coherent(priv->device,
1525                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1526                                           tx_q->dma_tx, tx_q->dma_tx_phy);
1527                 else
1528                         dma_free_coherent(priv->device, DMA_TX_SIZE *
1529                                           sizeof(struct dma_extended_desc),
1530                                           tx_q->dma_etx, tx_q->dma_tx_phy);
1531
1532                 kfree(tx_q->tx_skbuff_dma);
1533                 kfree(tx_q->tx_skbuff);
1534         }
1535 }
1536
1537 /**
1538  * alloc_dma_rx_desc_resources - alloc RX resources.
1539  * @priv: private structure
1540  * Description: according to which descriptor can be used (extend or basic)
1541  * this function allocates the resources for TX and RX paths. In case of
1542  * reception, for example, it pre-allocated the RX socket buffer in order to
1543  * allow zero-copy mechanism.
1544  */
1545 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1546 {
1547         u32 rx_count = priv->plat->rx_queues_to_use;
1548         int ret = -ENOMEM;
1549         u32 queue;
1550
1551         /* RX queues buffers and DMA */
1552         for (queue = 0; queue < rx_count; queue++) {
1553                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1554
1555                 rx_q->queue_index = queue;
1556                 rx_q->priv_data = priv;
1557
1558                 rx_q->rx_skbuff_dma = kmalloc_array(DMA_RX_SIZE,
1559                                                     sizeof(dma_addr_t),
1560                                                     GFP_KERNEL);
1561                 if (!rx_q->rx_skbuff_dma)
1562                         goto err_dma;
1563
1564                 rx_q->rx_skbuff = kmalloc_array(DMA_RX_SIZE,
1565                                                 sizeof(struct sk_buff *),
1566                                                 GFP_KERNEL);
1567                 if (!rx_q->rx_skbuff)
1568                         goto err_dma;
1569
1570                 if (priv->extend_desc) {
1571                         rx_q->dma_erx = dma_alloc_coherent(priv->device,
1572                                                            DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1573                                                            &rx_q->dma_rx_phy,
1574                                                            GFP_KERNEL);
1575                         if (!rx_q->dma_erx)
1576                                 goto err_dma;
1577
1578                 } else {
1579                         rx_q->dma_rx = dma_alloc_coherent(priv->device,
1580                                                           DMA_RX_SIZE * sizeof(struct dma_desc),
1581                                                           &rx_q->dma_rx_phy,
1582                                                           GFP_KERNEL);
1583                         if (!rx_q->dma_rx)
1584                                 goto err_dma;
1585                 }
1586         }
1587
1588         return 0;
1589
1590 err_dma:
1591         free_dma_rx_desc_resources(priv);
1592
1593         return ret;
1594 }
1595
1596 /**
1597  * alloc_dma_tx_desc_resources - alloc TX resources.
1598  * @priv: private structure
1599  * Description: according to which descriptor can be used (extend or basic)
1600  * this function allocates the resources for TX and RX paths. In case of
1601  * reception, for example, it pre-allocated the RX socket buffer in order to
1602  * allow zero-copy mechanism.
1603  */
1604 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1605 {
1606         u32 tx_count = priv->plat->tx_queues_to_use;
1607         int ret = -ENOMEM;
1608         u32 queue;
1609
1610         /* TX queues buffers and DMA */
1611         for (queue = 0; queue < tx_count; queue++) {
1612                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1613
1614                 tx_q->queue_index = queue;
1615                 tx_q->priv_data = priv;
1616
1617                 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE,
1618                                                     sizeof(*tx_q->tx_skbuff_dma),
1619                                                     GFP_KERNEL);
1620                 if (!tx_q->tx_skbuff_dma)
1621                         goto err_dma;
1622
1623                 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE,
1624                                                 sizeof(struct sk_buff *),
1625                                                 GFP_KERNEL);
1626                 if (!tx_q->tx_skbuff)
1627                         goto err_dma;
1628
1629                 if (priv->extend_desc) {
1630                         tx_q->dma_etx = dma_alloc_coherent(priv->device,
1631                                                            DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1632                                                            &tx_q->dma_tx_phy,
1633                                                            GFP_KERNEL);
1634                         if (!tx_q->dma_etx)
1635                                 goto err_dma;
1636                 } else {
1637                         tx_q->dma_tx = dma_alloc_coherent(priv->device,
1638                                                           DMA_TX_SIZE * sizeof(struct dma_desc),
1639                                                           &tx_q->dma_tx_phy,
1640                                                           GFP_KERNEL);
1641                         if (!tx_q->dma_tx)
1642                                 goto err_dma;
1643                 }
1644         }
1645
1646         return 0;
1647
1648 err_dma:
1649         free_dma_tx_desc_resources(priv);
1650
1651         return ret;
1652 }
1653
1654 /**
1655  * alloc_dma_desc_resources - alloc TX/RX resources.
1656  * @priv: private structure
1657  * Description: according to which descriptor can be used (extend or basic)
1658  * this function allocates the resources for TX and RX paths. In case of
1659  * reception, for example, it pre-allocated the RX socket buffer in order to
1660  * allow zero-copy mechanism.
1661  */
1662 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1663 {
1664         /* RX Allocation */
1665         int ret = alloc_dma_rx_desc_resources(priv);
1666
1667         if (ret)
1668                 return ret;
1669
1670         ret = alloc_dma_tx_desc_resources(priv);
1671
1672         return ret;
1673 }
1674
1675 /**
1676  * free_dma_desc_resources - free dma desc resources
1677  * @priv: private structure
1678  */
1679 static void free_dma_desc_resources(struct stmmac_priv *priv)
1680 {
1681         /* Release the DMA RX socket buffers */
1682         free_dma_rx_desc_resources(priv);
1683
1684         /* Release the DMA TX socket buffers */
1685         free_dma_tx_desc_resources(priv);
1686 }
1687
1688 /**
1689  *  stmmac_mac_enable_rx_queues - Enable MAC rx queues
1690  *  @priv: driver private structure
1691  *  Description: It is used for enabling the rx queues in the MAC
1692  */
1693 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1694 {
1695         u32 rx_queues_count = priv->plat->rx_queues_to_use;
1696         int queue;
1697         u8 mode;
1698
1699         for (queue = 0; queue < rx_queues_count; queue++) {
1700                 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1701                 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1702         }
1703 }
1704
1705 /**
1706  * stmmac_start_rx_dma - start RX DMA channel
1707  * @priv: driver private structure
1708  * @chan: RX channel index
1709  * Description:
1710  * This starts a RX DMA channel
1711  */
1712 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1713 {
1714         netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1715         stmmac_start_rx(priv, priv->ioaddr, chan);
1716 }
1717
1718 /**
1719  * stmmac_start_tx_dma - start TX DMA channel
1720  * @priv: driver private structure
1721  * @chan: TX channel index
1722  * Description:
1723  * This starts a TX DMA channel
1724  */
1725 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1726 {
1727         netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1728         stmmac_start_tx(priv, priv->ioaddr, chan);
1729 }
1730
1731 /**
1732  * stmmac_stop_rx_dma - stop RX DMA channel
1733  * @priv: driver private structure
1734  * @chan: RX channel index
1735  * Description:
1736  * This stops a RX DMA channel
1737  */
1738 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1739 {
1740         netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1741         stmmac_stop_rx(priv, priv->ioaddr, chan);
1742 }
1743
1744 /**
1745  * stmmac_stop_tx_dma - stop TX DMA channel
1746  * @priv: driver private structure
1747  * @chan: TX channel index
1748  * Description:
1749  * This stops a TX DMA channel
1750  */
1751 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1752 {
1753         netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1754         stmmac_stop_tx(priv, priv->ioaddr, chan);
1755 }
1756
1757 /**
1758  * stmmac_start_all_dma - start all RX and TX DMA channels
1759  * @priv: driver private structure
1760  * Description:
1761  * This starts all the RX and TX DMA channels
1762  */
1763 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1764 {
1765         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1766         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1767         u32 chan = 0;
1768
1769         for (chan = 0; chan < rx_channels_count; chan++)
1770                 stmmac_start_rx_dma(priv, chan);
1771
1772         for (chan = 0; chan < tx_channels_count; chan++)
1773                 stmmac_start_tx_dma(priv, chan);
1774 }
1775
1776 /**
1777  * stmmac_stop_all_dma - stop all RX and TX DMA channels
1778  * @priv: driver private structure
1779  * Description:
1780  * This stops the RX and TX DMA channels
1781  */
1782 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1783 {
1784         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1785         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1786         u32 chan = 0;
1787
1788         for (chan = 0; chan < rx_channels_count; chan++)
1789                 stmmac_stop_rx_dma(priv, chan);
1790
1791         for (chan = 0; chan < tx_channels_count; chan++)
1792                 stmmac_stop_tx_dma(priv, chan);
1793 }
1794
1795 /**
1796  *  stmmac_dma_operation_mode - HW DMA operation mode
1797  *  @priv: driver private structure
1798  *  Description: it is used for configuring the DMA operation mode register in
1799  *  order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1800  */
1801 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1802 {
1803         u32 rx_channels_count = priv->plat->rx_queues_to_use;
1804         u32 tx_channels_count = priv->plat->tx_queues_to_use;
1805         int rxfifosz = priv->plat->rx_fifo_size;
1806         int txfifosz = priv->plat->tx_fifo_size;
1807         u32 txmode = 0;
1808         u32 rxmode = 0;
1809         u32 chan = 0;
1810         u8 qmode = 0;
1811
1812         if (rxfifosz == 0)
1813                 rxfifosz = priv->dma_cap.rx_fifo_size;
1814         if (txfifosz == 0)
1815                 txfifosz = priv->dma_cap.tx_fifo_size;
1816
1817         /* Adjust for real per queue fifo size */
1818         rxfifosz /= rx_channels_count;
1819         txfifosz /= tx_channels_count;
1820
1821         if (priv->plat->force_thresh_dma_mode) {
1822                 txmode = tc;
1823                 rxmode = tc;
1824         } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1825                 /*
1826                  * In case of GMAC, SF mode can be enabled
1827                  * to perform the TX COE in HW. This depends on:
1828                  * 1) TX COE if actually supported
1829                  * 2) There is no bugged Jumbo frame support
1830                  *    that needs to not insert csum in the TDES.
1831                  */
1832                 txmode = SF_DMA_MODE;
1833                 rxmode = SF_DMA_MODE;
1834                 priv->xstats.threshold = SF_DMA_MODE;
1835         } else {
1836                 txmode = tc;
1837                 rxmode = SF_DMA_MODE;
1838         }
1839
1840         /* configure all channels */
1841         for (chan = 0; chan < rx_channels_count; chan++) {
1842                 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1843
1844                 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1845                                 rxfifosz, qmode);
1846                 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1847                                 chan);
1848         }
1849
1850         for (chan = 0; chan < tx_channels_count; chan++) {
1851                 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1852
1853                 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1854                                 txfifosz, qmode);
1855         }
1856 }
1857
1858 /**
1859  * stmmac_tx_clean - to manage the transmission completion
1860  * @priv: driver private structure
1861  * @queue: TX queue index
1862  * Description: it reclaims the transmit resources after transmission completes.
1863  */
1864 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1865 {
1866         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1867         unsigned int bytes_compl = 0, pkts_compl = 0;
1868         unsigned int entry, count = 0;
1869
1870         __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1871
1872         priv->xstats.tx_clean++;
1873
1874         entry = tx_q->dirty_tx;
1875         while ((entry != tx_q->cur_tx) && (count < budget)) {
1876                 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1877                 struct dma_desc *p;
1878                 int status;
1879
1880                 if (priv->extend_desc)
1881                         p = (struct dma_desc *)(tx_q->dma_etx + entry);
1882                 else
1883                         p = tx_q->dma_tx + entry;
1884
1885                 status = stmmac_tx_status(priv, &priv->dev->stats,
1886                                 &priv->xstats, p, priv->ioaddr);
1887                 /* Check if the descriptor is owned by the DMA */
1888                 if (unlikely(status & tx_dma_own))
1889                         break;
1890
1891                 count++;
1892
1893                 /* Make sure descriptor fields are read after reading
1894                  * the own bit.
1895                  */
1896                 dma_rmb();
1897
1898                 /* Just consider the last segment and ...*/
1899                 if (likely(!(status & tx_not_ls))) {
1900                         /* ... verify the status error condition */
1901                         if (unlikely(status & tx_err)) {
1902                                 priv->dev->stats.tx_errors++;
1903                         } else {
1904                                 priv->dev->stats.tx_packets++;
1905                                 priv->xstats.tx_pkt_n++;
1906                         }
1907                         stmmac_get_tx_hwtstamp(priv, p, skb);
1908                 }
1909
1910                 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1911                         if (tx_q->tx_skbuff_dma[entry].map_as_page)
1912                                 dma_unmap_page(priv->device,
1913                                                tx_q->tx_skbuff_dma[entry].buf,
1914                                                tx_q->tx_skbuff_dma[entry].len,
1915                                                DMA_TO_DEVICE);
1916                         else
1917                                 dma_unmap_single(priv->device,
1918                                                  tx_q->tx_skbuff_dma[entry].buf,
1919                                                  tx_q->tx_skbuff_dma[entry].len,
1920                                                  DMA_TO_DEVICE);
1921                         tx_q->tx_skbuff_dma[entry].buf = 0;
1922                         tx_q->tx_skbuff_dma[entry].len = 0;
1923                         tx_q->tx_skbuff_dma[entry].map_as_page = false;
1924                 }
1925
1926                 stmmac_clean_desc3(priv, tx_q, p);
1927
1928                 tx_q->tx_skbuff_dma[entry].last_segment = false;
1929                 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1930
1931                 if (likely(skb != NULL)) {
1932                         pkts_compl++;
1933                         bytes_compl += skb->len;
1934                         dev_consume_skb_any(skb);
1935                         tx_q->tx_skbuff[entry] = NULL;
1936                 }
1937
1938                 stmmac_release_tx_desc(priv, p, priv->mode);
1939
1940                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1941         }
1942         tx_q->dirty_tx = entry;
1943
1944         netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1945                                   pkts_compl, bytes_compl);
1946
1947         if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1948                                                                 queue))) &&
1949             stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1950
1951                 netif_dbg(priv, tx_done, priv->dev,
1952                           "%s: restart transmit\n", __func__);
1953                 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1954         }
1955
1956         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1957                 stmmac_enable_eee_mode(priv);
1958                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1959         }
1960
1961         /* We still have pending packets, let's call for a new scheduling */
1962         if (tx_q->dirty_tx != tx_q->cur_tx)
1963                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1964
1965         __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1966
1967         return count;
1968 }
1969
1970 /**
1971  * stmmac_tx_err - to manage the tx error
1972  * @priv: driver private structure
1973  * @chan: channel index
1974  * Description: it cleans the descriptors and restarts the transmission
1975  * in case of transmission errors.
1976  */
1977 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1978 {
1979         struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1980         int i;
1981
1982         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
1983
1984         stmmac_stop_tx_dma(priv, chan);
1985         dma_free_tx_skbufs(priv, chan);
1986         for (i = 0; i < DMA_TX_SIZE; i++)
1987                 if (priv->extend_desc)
1988                         stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1989                                         priv->mode, (i == DMA_TX_SIZE - 1));
1990                 else
1991                         stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1992                                         priv->mode, (i == DMA_TX_SIZE - 1));
1993         tx_q->dirty_tx = 0;
1994         tx_q->cur_tx = 0;
1995         tx_q->mss = 0;
1996         netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
1997         stmmac_start_tx_dma(priv, chan);
1998
1999         priv->dev->stats.tx_errors++;
2000         netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2001 }
2002
2003 /**
2004  *  stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2005  *  @priv: driver private structure
2006  *  @txmode: TX operating mode
2007  *  @rxmode: RX operating mode
2008  *  @chan: channel index
2009  *  Description: it is used for configuring of the DMA operation mode in
2010  *  runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2011  *  mode.
2012  */
2013 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2014                                           u32 rxmode, u32 chan)
2015 {
2016         u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2017         u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2018         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2019         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2020         int rxfifosz = priv->plat->rx_fifo_size;
2021         int txfifosz = priv->plat->tx_fifo_size;
2022
2023         if (rxfifosz == 0)
2024                 rxfifosz = priv->dma_cap.rx_fifo_size;
2025         if (txfifosz == 0)
2026                 txfifosz = priv->dma_cap.tx_fifo_size;
2027
2028         /* Adjust for real per queue fifo size */
2029         rxfifosz /= rx_channels_count;
2030         txfifosz /= tx_channels_count;
2031
2032         stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2033         stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2034 }
2035
2036 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2037 {
2038         int ret;
2039
2040         ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2041                         priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2042         if (ret && (ret != -EINVAL)) {
2043                 stmmac_global_err(priv);
2044                 return true;
2045         }
2046
2047         return false;
2048 }
2049
2050 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
2051 {
2052         int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2053                                                  &priv->xstats, chan);
2054         struct stmmac_channel *ch = &priv->channel[chan];
2055
2056         if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2057                 if (napi_schedule_prep(&ch->rx_napi)) {
2058                         stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2059                         __napi_schedule_irqoff(&ch->rx_napi);
2060                         status |= handle_tx;
2061                 }
2062         }
2063
2064         if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use))
2065                 napi_schedule_irqoff(&ch->tx_napi);
2066
2067         return status;
2068 }
2069
2070 /**
2071  * stmmac_dma_interrupt - DMA ISR
2072  * @priv: driver private structure
2073  * Description: this is the DMA ISR. It is called by the main ISR.
2074  * It calls the dwmac dma routine and schedule poll method in case of some
2075  * work can be done.
2076  */
2077 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2078 {
2079         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2080         u32 rx_channel_count = priv->plat->rx_queues_to_use;
2081         u32 channels_to_check = tx_channel_count > rx_channel_count ?
2082                                 tx_channel_count : rx_channel_count;
2083         u32 chan;
2084         int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2085
2086         /* Make sure we never check beyond our status buffer. */
2087         if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2088                 channels_to_check = ARRAY_SIZE(status);
2089
2090         for (chan = 0; chan < channels_to_check; chan++)
2091                 status[chan] = stmmac_napi_check(priv, chan);
2092
2093         for (chan = 0; chan < tx_channel_count; chan++) {
2094                 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2095                         /* Try to bump up the dma threshold on this failure */
2096                         if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2097                             (tc <= 256)) {
2098                                 tc += 64;
2099                                 if (priv->plat->force_thresh_dma_mode)
2100                                         stmmac_set_dma_operation_mode(priv,
2101                                                                       tc,
2102                                                                       tc,
2103                                                                       chan);
2104                                 else
2105                                         stmmac_set_dma_operation_mode(priv,
2106                                                                     tc,
2107                                                                     SF_DMA_MODE,
2108                                                                     chan);
2109                                 priv->xstats.threshold = tc;
2110                         }
2111                 } else if (unlikely(status[chan] == tx_hard_error)) {
2112                         stmmac_tx_err(priv, chan);
2113                 }
2114         }
2115 }
2116
2117 /**
2118  * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2119  * @priv: driver private structure
2120  * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2121  */
2122 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2123 {
2124         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2125                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2126
2127         stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2128
2129         if (priv->dma_cap.rmon) {
2130                 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2131                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2132         } else
2133                 netdev_info(priv->dev, "No MAC Management Counters available\n");
2134 }
2135
2136 /**
2137  * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2138  * @priv: driver private structure
2139  * Description:
2140  *  new GMAC chip generations have a new register to indicate the
2141  *  presence of the optional feature/functions.
2142  *  This can be also used to override the value passed through the
2143  *  platform and necessary for old MAC10/100 and GMAC chips.
2144  */
2145 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2146 {
2147         return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2148 }
2149
2150 /**
2151  * stmmac_check_ether_addr - check if the MAC addr is valid
2152  * @priv: driver private structure
2153  * Description:
2154  * it is to verify if the MAC address is valid, in case of failures it
2155  * generates a random MAC address
2156  */
2157 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2158 {
2159         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2160                 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2161                 if (!is_valid_ether_addr(priv->dev->dev_addr))
2162                         eth_hw_addr_random(priv->dev);
2163                 dev_info(priv->device, "device MAC address %pM\n",
2164                          priv->dev->dev_addr);
2165         }
2166 }
2167
2168 /**
2169  * stmmac_init_dma_engine - DMA init.
2170  * @priv: driver private structure
2171  * Description:
2172  * It inits the DMA invoking the specific MAC/GMAC callback.
2173  * Some DMA parameters can be passed from the platform;
2174  * in case of these are not passed a default is kept for the MAC or GMAC.
2175  */
2176 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2177 {
2178         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2179         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2180         u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2181         struct stmmac_rx_queue *rx_q;
2182         struct stmmac_tx_queue *tx_q;
2183         u32 chan = 0;
2184         int atds = 0;
2185         int ret = 0;
2186
2187         if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2188                 dev_err(priv->device, "Invalid DMA configuration\n");
2189                 return -EINVAL;
2190         }
2191
2192         if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2193                 atds = 1;
2194
2195         ret = stmmac_reset(priv, priv->ioaddr);
2196         if (ret) {
2197                 dev_err(priv->device, "Failed to reset the dma\n");
2198                 return ret;
2199         }
2200
2201         /* DMA Configuration */
2202         stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2203
2204         if (priv->plat->axi)
2205                 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2206
2207         /* DMA CSR Channel configuration */
2208         for (chan = 0; chan < dma_csr_ch; chan++)
2209                 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2210
2211         /* DMA RX Channel Configuration */
2212         for (chan = 0; chan < rx_channels_count; chan++) {
2213                 rx_q = &priv->rx_queue[chan];
2214
2215                 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2216                                     rx_q->dma_rx_phy, chan);
2217
2218                 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2219                             (DMA_RX_SIZE * sizeof(struct dma_desc));
2220                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2221                                        rx_q->rx_tail_addr, chan);
2222         }
2223
2224         /* DMA TX Channel Configuration */
2225         for (chan = 0; chan < tx_channels_count; chan++) {
2226                 tx_q = &priv->tx_queue[chan];
2227
2228                 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2229                                     tx_q->dma_tx_phy, chan);
2230
2231                 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2232                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2233                                        tx_q->tx_tail_addr, chan);
2234         }
2235
2236         return ret;
2237 }
2238
2239 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2240 {
2241         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2242
2243         mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2244 }
2245
2246 /**
2247  * stmmac_tx_timer - mitigation sw timer for tx.
2248  * @data: data pointer
2249  * Description:
2250  * This is the timer handler to directly invoke the stmmac_tx_clean.
2251  */
2252 static void stmmac_tx_timer(struct timer_list *t)
2253 {
2254         struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2255         struct stmmac_priv *priv = tx_q->priv_data;
2256         struct stmmac_channel *ch;
2257
2258         ch = &priv->channel[tx_q->queue_index];
2259
2260         /*
2261          * If NAPI is already running we can miss some events. Let's rearm
2262          * the timer and try again.
2263          */
2264         if (likely(napi_schedule_prep(&ch->tx_napi)))
2265                 __napi_schedule(&ch->tx_napi);
2266         else
2267                 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2268 }
2269
2270 /**
2271  * stmmac_init_tx_coalesce - init tx mitigation options.
2272  * @priv: driver private structure
2273  * Description:
2274  * This inits the transmit coalesce parameters: i.e. timer rate,
2275  * timer handler and default threshold used for enabling the
2276  * interrupt on completion bit.
2277  */
2278 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
2279 {
2280         u32 tx_channel_count = priv->plat->tx_queues_to_use;
2281         u32 chan;
2282
2283         priv->tx_coal_frames = STMMAC_TX_FRAMES;
2284         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2285
2286         for (chan = 0; chan < tx_channel_count; chan++) {
2287                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2288
2289                 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2290         }
2291 }
2292
2293 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2294 {
2295         u32 rx_channels_count = priv->plat->rx_queues_to_use;
2296         u32 tx_channels_count = priv->plat->tx_queues_to_use;
2297         u32 chan;
2298
2299         /* set TX ring length */
2300         for (chan = 0; chan < tx_channels_count; chan++)
2301                 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2302                                 (DMA_TX_SIZE - 1), chan);
2303
2304         /* set RX ring length */
2305         for (chan = 0; chan < rx_channels_count; chan++)
2306                 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2307                                 (DMA_RX_SIZE - 1), chan);
2308 }
2309
2310 /**
2311  *  stmmac_set_tx_queue_weight - Set TX queue weight
2312  *  @priv: driver private structure
2313  *  Description: It is used for setting TX queues weight
2314  */
2315 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2316 {
2317         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2318         u32 weight;
2319         u32 queue;
2320
2321         for (queue = 0; queue < tx_queues_count; queue++) {
2322                 weight = priv->plat->tx_queues_cfg[queue].weight;
2323                 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2324         }
2325 }
2326
2327 /**
2328  *  stmmac_configure_cbs - Configure CBS in TX queue
2329  *  @priv: driver private structure
2330  *  Description: It is used for configuring CBS in AVB TX queues
2331  */
2332 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2333 {
2334         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2335         u32 mode_to_use;
2336         u32 queue;
2337
2338         /* queue 0 is reserved for legacy traffic */
2339         for (queue = 1; queue < tx_queues_count; queue++) {
2340                 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2341                 if (mode_to_use == MTL_QUEUE_DCB)
2342                         continue;
2343
2344                 stmmac_config_cbs(priv, priv->hw,
2345                                 priv->plat->tx_queues_cfg[queue].send_slope,
2346                                 priv->plat->tx_queues_cfg[queue].idle_slope,
2347                                 priv->plat->tx_queues_cfg[queue].high_credit,
2348                                 priv->plat->tx_queues_cfg[queue].low_credit,
2349                                 queue);
2350         }
2351 }
2352
2353 /**
2354  *  stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2355  *  @priv: driver private structure
2356  *  Description: It is used for mapping RX queues to RX dma channels
2357  */
2358 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2359 {
2360         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2361         u32 queue;
2362         u32 chan;
2363
2364         for (queue = 0; queue < rx_queues_count; queue++) {
2365                 chan = priv->plat->rx_queues_cfg[queue].chan;
2366                 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2367         }
2368 }
2369
2370 /**
2371  *  stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2372  *  @priv: driver private structure
2373  *  Description: It is used for configuring the RX Queue Priority
2374  */
2375 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2376 {
2377         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2378         u32 queue;
2379         u32 prio;
2380
2381         for (queue = 0; queue < rx_queues_count; queue++) {
2382                 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2383                         continue;
2384
2385                 prio = priv->plat->rx_queues_cfg[queue].prio;
2386                 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2387         }
2388 }
2389
2390 /**
2391  *  stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2392  *  @priv: driver private structure
2393  *  Description: It is used for configuring the TX Queue Priority
2394  */
2395 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2396 {
2397         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2398         u32 queue;
2399         u32 prio;
2400
2401         for (queue = 0; queue < tx_queues_count; queue++) {
2402                 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2403                         continue;
2404
2405                 prio = priv->plat->tx_queues_cfg[queue].prio;
2406                 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2407         }
2408 }
2409
2410 /**
2411  *  stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2412  *  @priv: driver private structure
2413  *  Description: It is used for configuring the RX queue routing
2414  */
2415 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2416 {
2417         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2418         u32 queue;
2419         u8 packet;
2420
2421         for (queue = 0; queue < rx_queues_count; queue++) {
2422                 /* no specific packet type routing specified for the queue */
2423                 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2424                         continue;
2425
2426                 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2427                 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2428         }
2429 }
2430
2431 /**
2432  *  stmmac_mtl_configuration - Configure MTL
2433  *  @priv: driver private structure
2434  *  Description: It is used for configurring MTL
2435  */
2436 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2437 {
2438         u32 rx_queues_count = priv->plat->rx_queues_to_use;
2439         u32 tx_queues_count = priv->plat->tx_queues_to_use;
2440
2441         if (tx_queues_count > 1)
2442                 stmmac_set_tx_queue_weight(priv);
2443
2444         /* Configure MTL RX algorithms */
2445         if (rx_queues_count > 1)
2446                 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2447                                 priv->plat->rx_sched_algorithm);
2448
2449         /* Configure MTL TX algorithms */
2450         if (tx_queues_count > 1)
2451                 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2452                                 priv->plat->tx_sched_algorithm);
2453
2454         /* Configure CBS in AVB TX queues */
2455         if (tx_queues_count > 1)
2456                 stmmac_configure_cbs(priv);
2457
2458         /* Map RX MTL to DMA channels */
2459         stmmac_rx_queue_dma_chan_map(priv);
2460
2461         /* Enable MAC RX Queues */
2462         stmmac_mac_enable_rx_queues(priv);
2463
2464         /* Set RX priorities */
2465         if (rx_queues_count > 1)
2466                 stmmac_mac_config_rx_queues_prio(priv);
2467
2468         /* Set TX priorities */
2469         if (tx_queues_count > 1)
2470                 stmmac_mac_config_tx_queues_prio(priv);
2471
2472         /* Set RX routing */
2473         if (rx_queues_count > 1)
2474                 stmmac_mac_config_rx_queues_routing(priv);
2475 }
2476
2477 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2478 {
2479         if (priv->dma_cap.asp) {
2480                 netdev_info(priv->dev, "Enabling Safety Features\n");
2481                 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2482         } else {
2483                 netdev_info(priv->dev, "No Safety Features support found\n");
2484         }
2485 }
2486
2487 /**
2488  * stmmac_hw_setup - setup mac in a usable state.
2489  *  @dev : pointer to the device structure.
2490  *  Description:
2491  *  this is the main function to setup the HW in a usable state because the
2492  *  dma engine is reset, the core registers are configured (e.g. AXI,
2493  *  Checksum features, timers). The DMA is ready to start receiving and
2494  *  transmitting.
2495  *  Return value:
2496  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2497  *  file on failure.
2498  */
2499 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2500 {
2501         struct stmmac_priv *priv = netdev_priv(dev);
2502         u32 rx_cnt = priv->plat->rx_queues_to_use;
2503         u32 tx_cnt = priv->plat->tx_queues_to_use;
2504         u32 chan;
2505         int ret;
2506
2507         /* DMA initialization and SW reset */
2508         ret = stmmac_init_dma_engine(priv);
2509         if (ret < 0) {
2510                 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2511                            __func__);
2512                 return ret;
2513         }
2514
2515         /* Copy the MAC addr into the HW  */
2516         stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2517
2518         /* PS and related bits will be programmed according to the speed */
2519         if (priv->hw->pcs) {
2520                 int speed = priv->plat->mac_port_sel_speed;
2521
2522                 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2523                     (speed == SPEED_1000)) {
2524                         priv->hw->ps = speed;
2525                 } else {
2526                         dev_warn(priv->device, "invalid port speed\n");
2527                         priv->hw->ps = 0;
2528                 }
2529         }
2530
2531         /* Initialize the MAC Core */
2532         stmmac_core_init(priv, priv->hw, dev);
2533
2534         /* Initialize MTL*/
2535         stmmac_mtl_configuration(priv);
2536
2537         /* Initialize Safety Features */
2538         stmmac_safety_feat_configuration(priv);
2539
2540         ret = stmmac_rx_ipc(priv, priv->hw);
2541         if (!ret) {
2542                 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2543                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2544                 priv->hw->rx_csum = 0;
2545         }
2546
2547         /* Enable the MAC Rx/Tx */
2548         stmmac_mac_set(priv, priv->ioaddr, true);
2549
2550         /* Set the HW DMA mode and the COE */
2551         stmmac_dma_operation_mode(priv);
2552
2553         stmmac_mmc_setup(priv);
2554
2555         if (init_ptp) {
2556                 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2557                 if (ret < 0)
2558                         netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2559
2560                 ret = stmmac_init_ptp(priv);
2561                 if (ret == -EOPNOTSUPP)
2562                         netdev_warn(priv->dev, "PTP not supported by HW\n");
2563                 else if (ret)
2564                         netdev_warn(priv->dev, "PTP init failed\n");
2565         }
2566
2567         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2568
2569         if (priv->use_riwt) {
2570                 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MIN_DMA_RIWT, rx_cnt);
2571                 if (!ret)
2572                         priv->rx_riwt = MIN_DMA_RIWT;
2573         }
2574
2575         if (priv->hw->pcs)
2576                 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2577
2578         /* set TX and RX rings length */
2579         stmmac_set_rings_length(priv);
2580
2581         /* Enable TSO */
2582         if (priv->tso) {
2583                 for (chan = 0; chan < tx_cnt; chan++)
2584                         stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2585         }
2586
2587         /* Start the ball rolling... */
2588         stmmac_start_all_dma(priv);
2589
2590         return 0;
2591 }
2592
2593 static void stmmac_hw_teardown(struct net_device *dev)
2594 {
2595         struct stmmac_priv *priv = netdev_priv(dev);
2596
2597         clk_disable_unprepare(priv->plat->clk_ptp_ref);
2598 }
2599
2600 /**
2601  *  stmmac_open - open entry point of the driver
2602  *  @dev : pointer to the device structure.
2603  *  Description:
2604  *  This function is the open entry point of the driver.
2605  *  Return value:
2606  *  0 on success and an appropriate (-)ve integer as defined in errno.h
2607  *  file on failure.
2608  */
2609 static int stmmac_open(struct net_device *dev)
2610 {
2611         struct stmmac_priv *priv = netdev_priv(dev);
2612         u32 chan;
2613         int ret;
2614
2615         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2616             priv->hw->pcs != STMMAC_PCS_TBI &&
2617             priv->hw->pcs != STMMAC_PCS_RTBI) {
2618                 ret = stmmac_init_phy(dev);
2619                 if (ret) {
2620                         netdev_err(priv->dev,
2621                                    "%s: Cannot attach to PHY (error: %d)\n",
2622                                    __func__, ret);
2623                         return ret;
2624                 }
2625         }
2626
2627         /* Extra statistics */
2628         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2629         priv->xstats.threshold = tc;
2630
2631         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2632         priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2633
2634         ret = alloc_dma_desc_resources(priv);
2635         if (ret < 0) {
2636                 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2637                            __func__);
2638                 goto dma_desc_error;
2639         }
2640
2641         ret = init_dma_desc_rings(dev, GFP_KERNEL);
2642         if (ret < 0) {
2643                 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2644                            __func__);
2645                 goto init_error;
2646         }
2647
2648         ret = stmmac_hw_setup(dev, true);
2649         if (ret < 0) {
2650                 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2651                 goto init_error;
2652         }
2653
2654         stmmac_init_tx_coalesce(priv);
2655
2656         phylink_start(priv->phylink);
2657
2658         /* Request the IRQ lines */
2659         ret = request_irq(dev->irq, stmmac_interrupt,
2660                           IRQF_SHARED, dev->name, dev);
2661         if (unlikely(ret < 0)) {
2662                 netdev_err(priv->dev,
2663                            "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2664                            __func__, dev->irq, ret);
2665                 goto irq_error;
2666         }
2667
2668         /* Request the Wake IRQ in case of another line is used for WoL */
2669         if (priv->wol_irq != dev->irq) {
2670                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2671                                   IRQF_SHARED, dev->name, dev);
2672                 if (unlikely(ret < 0)) {
2673                         netdev_err(priv->dev,
2674                                    "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2675                                    __func__, priv->wol_irq, ret);
2676                         goto wolirq_error;
2677                 }
2678         }
2679
2680         /* Request the IRQ lines */
2681         if (priv->lpi_irq > 0) {
2682                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2683                                   dev->name, dev);
2684                 if (unlikely(ret < 0)) {
2685                         netdev_err(priv->dev,
2686                                    "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2687                                    __func__, priv->lpi_irq, ret);
2688                         goto lpiirq_error;
2689                 }
2690         }
2691
2692         stmmac_enable_all_queues(priv);
2693         stmmac_start_all_queues(priv);
2694
2695         return 0;
2696
2697 lpiirq_error:
2698         if (priv->wol_irq != dev->irq)
2699                 free_irq(priv->wol_irq, dev);
2700 wolirq_error:
2701         free_irq(dev->irq, dev);
2702 irq_error:
2703         phylink_stop(priv->phylink);
2704
2705         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2706                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2707
2708         stmmac_hw_teardown(dev);
2709 init_error:
2710         free_dma_desc_resources(priv);
2711 dma_desc_error:
2712         phylink_disconnect_phy(priv->phylink);
2713         return ret;
2714 }
2715
2716 /**
2717  *  stmmac_release - close entry point of the driver
2718  *  @dev : device pointer.
2719  *  Description:
2720  *  This is the stop entry point of the driver.
2721  */
2722 static int stmmac_release(struct net_device *dev)
2723 {
2724         struct stmmac_priv *priv = netdev_priv(dev);
2725         u32 chan;
2726
2727         if (priv->eee_enabled)
2728                 del_timer_sync(&priv->eee_ctrl_timer);
2729
2730         /* Stop and disconnect the PHY */
2731         phylink_stop(priv->phylink);
2732         phylink_disconnect_phy(priv->phylink);
2733
2734         stmmac_stop_all_queues(priv);
2735
2736         stmmac_disable_all_queues(priv);
2737
2738         for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2739                 del_timer_sync(&priv->tx_queue[chan].txtimer);
2740
2741         /* Free the IRQ lines */
2742         free_irq(dev->irq, dev);
2743         if (priv->wol_irq != dev->irq)
2744                 free_irq(priv->wol_irq, dev);
2745         if (priv->lpi_irq > 0)
2746                 free_irq(priv->lpi_irq, dev);
2747
2748         /* Stop TX/RX DMA and clear the descriptors */
2749         stmmac_stop_all_dma(priv);
2750
2751         /* Release and free the Rx/Tx resources */
2752         free_dma_desc_resources(priv);
2753
2754         /* Disable the MAC Rx/Tx */
2755         stmmac_mac_set(priv, priv->ioaddr, false);
2756
2757         netif_carrier_off(dev);
2758
2759         stmmac_release_ptp(priv);
2760
2761         return 0;
2762 }
2763
2764 /**
2765  *  stmmac_tso_allocator - close entry point of the driver
2766  *  @priv: driver private structure
2767  *  @des: buffer start address
2768  *  @total_len: total length to fill in descriptors
2769  *  @last_segmant: condition for the last descriptor
2770  *  @queue: TX queue index
2771  *  Description:
2772  *  This function fills descriptor and request new descriptors according to
2773  *  buffer length to fill
2774  */
2775 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
2776                                  int total_len, bool last_segment, u32 queue)
2777 {
2778         struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2779         struct dma_desc *desc;
2780         u32 buff_size;
2781         int tmp_len;
2782
2783         tmp_len = total_len;
2784
2785         while (tmp_len > 0) {
2786                 dma_addr_t curr_addr;
2787
2788                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2789                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2790                 desc = tx_q->dma_tx + tx_q->cur_tx;
2791
2792                 curr_addr = des + (total_len - tmp_len);
2793                 if (priv->dma_cap.addr64 <= 32)
2794                         desc->des0 = cpu_to_le32(curr_addr);
2795                 else
2796                         stmmac_set_desc_addr(priv, desc, curr_addr);
2797
2798                 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2799                             TSO_MAX_BUFF_SIZE : tmp_len;
2800
2801                 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2802                                 0, 1,
2803                                 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2804                                 0, 0);
2805
2806                 tmp_len -= TSO_MAX_BUFF_SIZE;
2807         }
2808 }
2809
2810 /**
2811  *  stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2812  *  @skb : the socket buffer
2813  *  @dev : device pointer
2814  *  Description: this is the transmit function that is called on TSO frames
2815  *  (support available on GMAC4 and newer chips).
2816  *  Diagram below show the ring programming in case of TSO frames:
2817  *
2818  *  First Descriptor
2819  *   --------
2820  *   | DES0 |---> buffer1 = L2/L3/L4 header
2821  *   | DES1 |---> TCP Payload (can continue on next descr...)
2822  *   | DES2 |---> buffer 1 and 2 len
2823  *   | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2824  *   --------
2825  *      |
2826  *     ...
2827  *      |
2828  *   --------
2829  *   | DES0 | --| Split TCP Payload on Buffers 1 and 2
2830  *   | DES1 | --|
2831  *   | DES2 | --> buffer 1 and 2 len
2832  *   | DES3 |
2833  *   --------
2834  *
2835  * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2836  */
2837 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2838 {
2839         struct dma_desc *desc, *first, *mss_desc = NULL;
2840         struct stmmac_priv *priv = netdev_priv(dev);
2841         int nfrags = skb_shinfo(skb)->nr_frags;
2842         u32 queue = skb_get_queue_mapping(skb);
2843         unsigned int first_entry;
2844         struct stmmac_tx_queue *tx_q;
2845         int tmp_pay_len = 0;
2846         u32 pay_len, mss;
2847         u8 proto_hdr_len;
2848         dma_addr_t des;
2849         int i;
2850
2851         tx_q = &priv->tx_queue[queue];
2852
2853         /* Compute header lengths */
2854         proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2855
2856         /* Desc availability based on threshold should be enough safe */
2857         if (unlikely(stmmac_tx_avail(priv, queue) <
2858                 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2859                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2860                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2861                                                                 queue));
2862                         /* This is a hard error, log it. */
2863                         netdev_err(priv->dev,
2864                                    "%s: Tx Ring full when queue awake\n",
2865                                    __func__);
2866                 }
2867                 return NETDEV_TX_BUSY;
2868         }
2869
2870         pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2871
2872         mss = skb_shinfo(skb)->gso_size;
2873
2874         /* set new MSS value if needed */
2875         if (mss != tx_q->mss) {
2876                 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2877                 stmmac_set_mss(priv, mss_desc, mss);
2878                 tx_q->mss = mss;
2879                 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2880                 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2881         }
2882
2883         if (netif_msg_tx_queued(priv)) {
2884                 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2885                         __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2886                 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2887                         skb->data_len);
2888         }
2889
2890         first_entry = tx_q->cur_tx;
2891         WARN_ON(tx_q->tx_skbuff[first_entry]);
2892
2893         desc = tx_q->dma_tx + first_entry;
2894         first = desc;
2895
2896         /* first descriptor: fill Headers on Buf1 */
2897         des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2898                              DMA_TO_DEVICE);
2899         if (dma_mapping_error(priv->device, des))
2900                 goto dma_map_err;
2901
2902         tx_q->tx_skbuff_dma[first_entry].buf = des;
2903         tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2904
2905         if (priv->dma_cap.addr64 <= 32) {
2906                 first->des0 = cpu_to_le32(des);
2907
2908                 /* Fill start of payload in buff2 of first descriptor */
2909                 if (pay_len)
2910                         first->des1 = cpu_to_le32(des + proto_hdr_len);
2911
2912                 /* If needed take extra descriptors to fill the remaining payload */
2913                 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2914         } else {
2915                 stmmac_set_desc_addr(priv, first, des);
2916                 tmp_pay_len = pay_len;
2917         }
2918
2919         stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
2920
2921         /* Prepare fragments */
2922         for (i = 0; i < nfrags; i++) {
2923                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2924
2925                 des = skb_frag_dma_map(priv->device, frag, 0,
2926                                        skb_frag_size(frag),
2927                                        DMA_TO_DEVICE);
2928                 if (dma_mapping_error(priv->device, des))
2929                         goto dma_map_err;
2930
2931                 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
2932                                      (i == nfrags - 1), queue);
2933
2934                 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
2935                 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
2936                 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
2937         }
2938
2939         tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
2940
2941         /* Only the last descriptor gets to point to the skb. */
2942         tx_q->tx_skbuff[tx_q->cur_tx] = skb;
2943
2944         /* We've used all descriptors we need for this skb, however,
2945          * advance cur_tx so that it references a fresh descriptor.
2946          * ndo_start_xmit will fill this descriptor the next time it's
2947          * called and stmmac_tx_clean may clean up to this descriptor.
2948          */
2949         tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2950
2951         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
2952                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
2953                           __func__);
2954                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
2955         }
2956
2957         dev->stats.tx_bytes += skb->len;
2958         priv->xstats.tx_tso_frames++;
2959         priv->xstats.tx_tso_nfrags += nfrags;
2960
2961         /* Manage tx mitigation */
2962         tx_q->tx_count_frames += nfrags + 1;
2963         if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
2964             !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
2965             (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2966             priv->hwts_tx_en)) {
2967                 stmmac_tx_timer_arm(priv, queue);
2968         } else {
2969                 tx_q->tx_count_frames = 0;
2970                 stmmac_set_tx_ic(priv, desc);
2971                 priv->xstats.tx_set_ic_bit++;
2972         }
2973
2974         skb_tx_timestamp(skb);
2975
2976         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
2977                      priv->hwts_tx_en)) {
2978                 /* declare that device is doing timestamping */
2979                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2980                 stmmac_enable_tx_timestamp(priv, first);
2981         }
2982
2983         /* Complete the first descriptor before granting the DMA */
2984         stmmac_prepare_tso_tx_desc(priv, first, 1,
2985                         proto_hdr_len,
2986                         pay_len,
2987                         1, tx_q->tx_skbuff_dma[first_entry].last_segment,
2988                         tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
2989
2990         /* If context desc is used to change MSS */
2991         if (mss_desc) {
2992                 /* Make sure that first descriptor has been completely
2993                  * written, including its own bit. This is because MSS is
2994                  * actually before first descriptor, so we need to make
2995                  * sure that MSS's own bit is the last thing written.
2996                  */
2997                 dma_wmb();
2998                 stmmac_set_tx_owner(priv, mss_desc);
2999         }
3000
3001         /* The own bit must be the latest setting done when prepare the
3002          * descriptor and then barrier is needed to make sure that
3003          * all is coherent before granting the DMA engine.
3004          */
3005         wmb();
3006
3007         if (netif_msg_pktdata(priv)) {
3008                 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
3009                         __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3010                         tx_q->cur_tx, first, nfrags);
3011
3012                 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
3013
3014                 pr_info(">>> frame to be transmitted: ");
3015                 print_pkt(skb->data, skb_headlen(skb));
3016         }
3017
3018         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3019
3020         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3021         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3022
3023         return NETDEV_TX_OK;
3024
3025 dma_map_err:
3026         dev_err(priv->device, "Tx dma map failed\n");
3027         dev_kfree_skb(skb);
3028         priv->dev->stats.tx_dropped++;
3029         return NETDEV_TX_OK;
3030 }
3031
3032 /**
3033  *  stmmac_xmit - Tx entry point of the driver
3034  *  @skb : the socket buffer
3035  *  @dev : device pointer
3036  *  Description : this is the tx entry point of the driver.
3037  *  It programs the chain or the ring and supports oversized frames
3038  *  and SG feature.
3039  */
3040 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
3041 {
3042         struct stmmac_priv *priv = netdev_priv(dev);
3043         unsigned int nopaged_len = skb_headlen(skb);
3044         int i, csum_insertion = 0, is_jumbo = 0;
3045         u32 queue = skb_get_queue_mapping(skb);
3046         int nfrags = skb_shinfo(skb)->nr_frags;
3047         struct dma_desc *desc, *first;
3048         struct stmmac_tx_queue *tx_q;
3049         unsigned int first_entry;
3050         unsigned int enh_desc;
3051         dma_addr_t des;
3052         int entry;
3053
3054         tx_q = &priv->tx_queue[queue];
3055
3056         if (priv->tx_path_in_lpi_mode)
3057                 stmmac_disable_eee_mode(priv);
3058
3059         /* Manage oversized TCP frames for GMAC4 device */
3060         if (skb_is_gso(skb) && priv->tso) {
3061                 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
3062                         return stmmac_tso_xmit(skb, dev);
3063         }
3064
3065         if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3066                 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3067                         netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3068                                                                 queue));
3069                         /* This is a hard error, log it. */
3070                         netdev_err(priv->dev,
3071                                    "%s: Tx Ring full when queue awake\n",
3072                                    __func__);
3073                 }
3074                 return NETDEV_TX_BUSY;
3075         }
3076
3077         entry = tx_q->cur_tx;
3078         first_entry = entry;
3079         WARN_ON(tx_q->tx_skbuff[first_entry]);
3080
3081         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3082
3083         if (likely(priv->extend_desc))
3084                 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3085         else
3086                 desc = tx_q->dma_tx + entry;
3087
3088         first = desc;
3089
3090         enh_desc = priv->plat->enh_desc;
3091         /* To program the descriptors according to the size of the frame */
3092         if (enh_desc)
3093                 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3094
3095         if (unlikely(is_jumbo)) {
3096                 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3097                 if (unlikely(entry < 0) && (entry != -EINVAL))
3098                         goto dma_map_err;
3099         }
3100
3101         for (i = 0; i < nfrags; i++) {
3102                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3103                 int len = skb_frag_size(frag);
3104                 bool last_segment = (i == (nfrags - 1));
3105
3106                 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3107                 WARN_ON(tx_q->tx_skbuff[entry]);
3108
3109                 if (likely(priv->extend_desc))
3110                         desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3111                 else
3112                         desc = tx_q->dma_tx + entry;
3113
3114                 des = skb_frag_dma_map(priv->device, frag, 0, len,
3115                                        DMA_TO_DEVICE);
3116                 if (dma_mapping_error(priv->device, des))
3117                         goto dma_map_err; /* should reuse desc w/o issues */
3118
3119                 tx_q->tx_skbuff_dma[entry].buf = des;
3120
3121                 stmmac_set_desc_addr(priv, desc, des);
3122
3123                 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3124                 tx_q->tx_skbuff_dma[entry].len = len;
3125                 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3126
3127                 /* Prepare the descriptor and set the own bit too */
3128                 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3129                                 priv->mode, 1, last_segment, skb->len);
3130         }
3131
3132         /* Only the last descriptor gets to point to the skb. */
3133         tx_q->tx_skbuff[entry] = skb;
3134
3135         /* We've used all descriptors we need for this skb, however,
3136          * advance cur_tx so that it references a fresh descriptor.
3137          * ndo_start_xmit will fill this descriptor the next time it's
3138          * called and stmmac_tx_clean may clean up to this descriptor.
3139          */
3140         entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3141         tx_q->cur_tx = entry;
3142
3143         if (netif_msg_pktdata(priv)) {
3144                 void *tx_head;
3145
3146                 netdev_dbg(priv->dev,
3147                            "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3148                            __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3149                            entry, first, nfrags);
3150
3151                 if (priv->extend_desc)
3152                         tx_head = (void *)tx_q->dma_etx;
3153                 else
3154                         tx_head = (void *)tx_q->dma_tx;
3155
3156                 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3157
3158                 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3159                 print_pkt(skb->data, skb->len);
3160         }
3161
3162         if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3163                 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3164                           __func__);
3165                 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3166         }
3167
3168         dev->stats.tx_bytes += skb->len;
3169
3170         /* According to the coalesce parameter the IC bit for the latest
3171          * segment is reset and the timer re-started to clean the tx status.
3172          * This approach takes care about the fragments: desc is the first
3173          * element in case of no SG.
3174          */
3175         tx_q->tx_count_frames += nfrags + 1;
3176         if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
3177             !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
3178             (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3179             priv->hwts_tx_en)) {
3180                 stmmac_tx_timer_arm(priv, queue);
3181         } else {
3182                 tx_q->tx_count_frames = 0;
3183                 stmmac_set_tx_ic(priv, desc);
3184                 priv->xstats.tx_set_ic_bit++;
3185         }
3186
3187         skb_tx_timestamp(skb);
3188
3189         /* Ready to fill the first descriptor and set the OWN bit w/o any
3190          * problems because all the descriptors are actually ready to be
3191          * passed to the DMA engine.
3192          */
3193         if (likely(!is_jumbo)) {
3194                 bool last_segment = (nfrags == 0);
3195
3196                 des = dma_map_single(priv->device, skb->data,
3197                                      nopaged_len, DMA_TO_DEVICE);
3198                 if (dma_mapping_error(priv->device, des))
3199                         goto dma_map_err;
3200
3201                 tx_q->tx_skbuff_dma[first_entry].buf = des;
3202
3203                 stmmac_set_desc_addr(priv, first, des);
3204
3205                 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3206                 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3207
3208                 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3209                              priv->hwts_tx_en)) {
3210                         /* declare that device is doing timestamping */
3211                         skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3212                         stmmac_enable_tx_timestamp(priv, first);
3213                 }
3214
3215                 /* Prepare the first descriptor setting the OWN bit too */
3216                 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3217                                 csum_insertion, priv->mode, 1, last_segment,
3218                                 skb->len);
3219         } else {
3220                 stmmac_set_tx_owner(priv, first);
3221         }
3222
3223         /* The own bit must be the latest setting done when prepare the
3224          * descriptor and then barrier is needed to make sure that
3225          * all is coherent before granting the DMA engine.
3226          */
3227         wmb();
3228
3229         netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3230
3231         stmmac_enable_dma_transmission(priv, priv->ioaddr);
3232
3233         tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3234         stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3235
3236         return NETDEV_TX_OK;
3237
3238 dma_map_err:
3239         netdev_err(priv->dev, "Tx DMA map failed\n");
3240         dev_kfree_skb(skb);
3241         priv->dev->stats.tx_dropped++;
3242         return NETDEV_TX_OK;
3243 }
3244
3245 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3246 {
3247         struct vlan_ethhdr *veth;
3248         __be16 vlan_proto;
3249         u16 vlanid;
3250
3251         veth = (struct vlan_ethhdr *)skb->data;
3252         vlan_proto = veth->h_vlan_proto;
3253
3254         if ((vlan_proto == htons(ETH_P_8021Q) &&
3255              dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3256             (vlan_proto == htons(ETH_P_8021AD) &&
3257              dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3258                 /* pop the vlan tag */
3259                 vlanid = ntohs(veth->h_vlan_TCI);
3260                 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3261                 skb_pull(skb, VLAN_HLEN);
3262                 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3263         }
3264 }
3265
3266
3267 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3268 {
3269         if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3270                 return 0;
3271
3272         return 1;
3273 }
3274
3275 /**
3276  * stmmac_rx_refill - refill used skb preallocated buffers
3277  * @priv: driver private structure
3278  * @queue: RX queue index
3279  * Description : this is to reallocate the skb for the reception process
3280  * that is based on zero-copy.
3281  */
3282 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3283 {
3284         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3285         int dirty = stmmac_rx_dirty(priv, queue);
3286         unsigned int entry = rx_q->dirty_rx;
3287
3288         int bfsize = priv->dma_buf_sz;
3289
3290         while (dirty-- > 0) {
3291                 struct dma_desc *p;
3292
3293                 if (priv->extend_desc)
3294                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3295                 else
3296                         p = rx_q->dma_rx + entry;
3297
3298                 if (likely(!rx_q->rx_skbuff[entry])) {
3299                         struct sk_buff *skb;
3300
3301                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
3302                         if (unlikely(!skb)) {
3303                                 /* so for a while no zero-copy! */
3304                                 rx_q->rx_zeroc_thresh = STMMAC_RX_THRESH;
3305                                 if (unlikely(net_ratelimit()))
3306                                         dev_err(priv->device,
3307                                                 "fail to alloc skb entry %d\n",
3308                                                 entry);
3309                                 break;
3310                         }
3311
3312                         rx_q->rx_skbuff[entry] = skb;
3313                         rx_q->rx_skbuff_dma[entry] =
3314                             dma_map_single(priv->device, skb->data, bfsize,
3315                                            DMA_FROM_DEVICE);
3316                         if (dma_mapping_error(priv->device,
3317                                               rx_q->rx_skbuff_dma[entry])) {
3318                                 netdev_err(priv->dev, "Rx DMA map failed\n");
3319                                 dev_kfree_skb(skb);
3320                                 break;
3321                         }
3322
3323                         stmmac_set_desc_addr(priv, p, rx_q->rx_skbuff_dma[entry]);
3324                         stmmac_refill_desc3(priv, rx_q, p);
3325
3326                         if (rx_q->rx_zeroc_thresh > 0)
3327                                 rx_q->rx_zeroc_thresh--;
3328
3329                         netif_dbg(priv, rx_status, priv->dev,
3330                                   "refill entry #%d\n", entry);
3331                 }
3332                 dma_wmb();
3333
3334                 stmmac_set_rx_owner(priv, p, priv->use_riwt);
3335
3336                 dma_wmb();
3337
3338                 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3339         }
3340         rx_q->dirty_rx = entry;
3341         rx_q->rx_tail_addr = rx_q->dma_rx_phy +
3342                             (rx_q->dirty_rx * sizeof(struct dma_desc));
3343         stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3344 }
3345
3346 /**
3347  * stmmac_rx - manage the receive process
3348  * @priv: driver private structure
3349  * @limit: napi bugget
3350  * @queue: RX queue index.
3351  * Description :  this the function called by the napi poll method.
3352  * It gets all the frames inside the ring.
3353  */
3354 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3355 {
3356         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3357         struct stmmac_channel *ch = &priv->channel[queue];
3358         unsigned int next_entry = rx_q->cur_rx;
3359         int coe = priv->hw->rx_csum;
3360         unsigned int count = 0;
3361         bool xmac;
3362
3363         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3364
3365         if (netif_msg_rx_status(priv)) {
3366                 void *rx_head;
3367
3368                 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3369                 if (priv->extend_desc)
3370                         rx_head = (void *)rx_q->dma_erx;
3371                 else
3372                         rx_head = (void *)rx_q->dma_rx;
3373
3374                 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3375         }
3376         while (count < limit) {
3377                 int entry, status;
3378                 struct dma_desc *p;
3379                 struct dma_desc *np;
3380
3381                 entry = next_entry;
3382
3383                 if (priv->extend_desc)
3384                         p = (struct dma_desc *)(rx_q->dma_erx + entry);
3385                 else
3386                         p = rx_q->dma_rx + entry;
3387
3388                 /* read the status of the incoming frame */
3389                 status = stmmac_rx_status(priv, &priv->dev->stats,
3390                                 &priv->xstats, p);
3391                 /* check if managed by the DMA otherwise go ahead */
3392                 if (unlikely(status & dma_own))
3393                         break;
3394
3395                 count++;
3396
3397                 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3398                 next_entry = rx_q->cur_rx;
3399
3400                 if (priv->extend_desc)
3401                         np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3402                 else
3403                         np = rx_q->dma_rx + next_entry;
3404
3405                 prefetch(np);
3406
3407                 if (priv->extend_desc)
3408                         stmmac_rx_extended_status(priv, &priv->dev->stats,
3409                                         &priv->xstats, rx_q->dma_erx + entry);
3410                 if (unlikely(status == discard_frame)) {
3411                         priv->dev->stats.rx_errors++;
3412                         if (priv->hwts_rx_en && !priv->extend_desc) {
3413                                 /* DESC2 & DESC3 will be overwritten by device
3414                                  * with timestamp value, hence reinitialize
3415                                  * them in stmmac_rx_refill() function so that
3416                                  * device can reuse it.
3417                                  */
3418                                 dev_kfree_skb_any(rx_q->rx_skbuff[entry]);
3419                                 rx_q->rx_skbuff[entry] = NULL;
3420                                 dma_unmap_single(priv->device,
3421                                                  rx_q->rx_skbuff_dma[entry],
3422                                                  priv->dma_buf_sz,
3423                                                  DMA_FROM_DEVICE);
3424                         }
3425                 } else {
3426                         struct sk_buff *skb;
3427                         int frame_len;
3428                         unsigned int des;
3429
3430                         stmmac_get_desc_addr(priv, p, &des);
3431                         frame_len = stmmac_get_rx_frame_len(priv, p, coe);
3432
3433                         /*  If frame length is greater than skb buffer size
3434                          *  (preallocated during init) then the packet is
3435                          *  ignored
3436                          */
3437                         if (frame_len > priv->dma_buf_sz) {
3438                                 if (net_ratelimit())
3439                                         netdev_err(priv->dev,
3440                                                    "len %d larger than size (%d)\n",
3441                                                    frame_len, priv->dma_buf_sz);
3442                                 priv->dev->stats.rx_length_errors++;
3443                                 continue;
3444                         }
3445
3446                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3447                          * Type frames (LLC/LLC-SNAP)
3448                          *
3449                          * llc_snap is never checked in GMAC >= 4, so this ACS
3450                          * feature is always disabled and packets need to be
3451                          * stripped manually.
3452                          */
3453                         if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3454                             unlikely(status != llc_snap))
3455                                 frame_len -= ETH_FCS_LEN;
3456
3457                         if (netif_msg_rx_status(priv)) {
3458                                 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n",
3459                                            p, entry, des);
3460                                 netdev_dbg(priv->dev, "frame size %d, COE: %d\n",
3461                                            frame_len, status);
3462                         }
3463
3464                         /* The zero-copy is always used for all the sizes
3465                          * in case of GMAC4 because it needs
3466                          * to refill the used descriptors, always.
3467                          */
3468                         if (unlikely(!xmac &&
3469                                      ((frame_len < priv->rx_copybreak) ||
3470                                      stmmac_rx_threshold_count(rx_q)))) {
3471                                 skb = netdev_alloc_skb_ip_align(priv->dev,
3472                                                                 frame_len);
3473                                 if (unlikely(!skb)) {
3474                                         if (net_ratelimit())
3475                                                 dev_warn(priv->device,
3476                                                          "packet dropped\n");
3477                                         priv->dev->stats.rx_dropped++;
3478                                         continue;
3479                                 }
3480
3481                                 dma_sync_single_for_cpu(priv->device,
3482                                                         rx_q->rx_skbuff_dma
3483                                                         [entry], frame_len,
3484                                                         DMA_FROM_DEVICE);
3485                                 skb_copy_to_linear_data(skb,
3486                                                         rx_q->
3487                                                         rx_skbuff[entry]->data,
3488                                                         frame_len);
3489
3490                                 skb_put(skb, frame_len);
3491                                 dma_sync_single_for_device(priv->device,
3492                                                            rx_q->rx_skbuff_dma
3493                                                            [entry], frame_len,
3494                                                            DMA_FROM_DEVICE);
3495                         } else {
3496                                 skb = rx_q->rx_skbuff[entry];
3497                                 if (unlikely(!skb)) {
3498                                         if (net_ratelimit())
3499                                                 netdev_err(priv->dev,
3500                                                            "%s: Inconsistent Rx chain\n",
3501                                                            priv->dev->name);
3502                                         priv->dev->stats.rx_dropped++;
3503                                         continue;
3504                                 }
3505                                 prefetch(skb->data - NET_IP_ALIGN);
3506                                 rx_q->rx_skbuff[entry] = NULL;
3507                                 rx_q->rx_zeroc_thresh++;
3508
3509                                 skb_put(skb, frame_len);
3510                                 dma_unmap_single(priv->device,
3511                                                  rx_q->rx_skbuff_dma[entry],
3512                                                  priv->dma_buf_sz,
3513                                                  DMA_FROM_DEVICE);
3514                         }
3515
3516                         if (netif_msg_pktdata(priv)) {
3517                                 netdev_dbg(priv->dev, "frame received (%dbytes)",
3518                                            frame_len);
3519                                 print_pkt(skb->data, frame_len);
3520                         }
3521
3522                         stmmac_get_rx_hwtstamp(priv, p, np, skb);
3523
3524                         stmmac_rx_vlan(priv->dev, skb);
3525
3526                         skb->protocol = eth_type_trans(skb, priv->dev);
3527
3528                         if (unlikely(!coe))
3529                                 skb_checksum_none_assert(skb);
3530                         else
3531                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3532
3533                         napi_gro_receive(&ch->rx_napi, skb);
3534
3535                         priv->dev->stats.rx_packets++;
3536                         priv->dev->stats.rx_bytes += frame_len;
3537                 }
3538         }
3539
3540         stmmac_rx_refill(priv, queue);
3541
3542         priv->xstats.rx_pkt_n += count;
3543
3544         return count;
3545 }
3546
3547 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3548 {
3549         struct stmmac_channel *ch =
3550                 container_of(napi, struct stmmac_channel, rx_napi);
3551         struct stmmac_priv *priv = ch->priv_data;
3552         u32 chan = ch->index;
3553         int work_done;
3554
3555         priv->xstats.napi_poll++;
3556
3557         work_done = stmmac_rx(priv, budget, chan);
3558         if (work_done < budget && napi_complete_done(napi, work_done))
3559                 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3560         return work_done;
3561 }
3562
3563 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3564 {
3565         struct stmmac_channel *ch =
3566                 container_of(napi, struct stmmac_channel, tx_napi);
3567         struct stmmac_priv *priv = ch->priv_data;
3568         struct stmmac_tx_queue *tx_q;
3569         u32 chan = ch->index;
3570         int work_done;
3571
3572         priv->xstats.napi_poll++;
3573
3574         work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3575         work_done = min(work_done, budget);
3576
3577         if (work_done < budget)
3578                 napi_complete_done(napi, work_done);
3579
3580         /* Force transmission restart */
3581         tx_q = &priv->tx_queue[chan];
3582         if (tx_q->cur_tx != tx_q->dirty_tx) {
3583                 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3584                 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3585                                        chan);
3586         }
3587
3588         return work_done;
3589 }
3590
3591 /**
3592  *  stmmac_tx_timeout
3593  *  @dev : Pointer to net device structure
3594  *  Description: this function is called when a packet transmission fails to
3595  *   complete within a reasonable time. The driver will mark the error in the
3596  *   netdev structure and arrange for the device to be reset to a sane state
3597  *   in order to transmit a new packet.
3598  */
3599 static void stmmac_tx_timeout(struct net_device *dev)
3600 {
3601         struct stmmac_priv *priv = netdev_priv(dev);
3602
3603         stmmac_global_err(priv);
3604 }
3605
3606 /**
3607  *  stmmac_set_rx_mode - entry point for multicast addressing
3608  *  @dev : pointer to the device structure
3609  *  Description:
3610  *  This function is a driver entry point which gets called by the kernel
3611  *  whenever multicast addresses must be enabled/disabled.
3612  *  Return value:
3613  *  void.
3614  */
3615 static void stmmac_set_rx_mode(struct net_device *dev)
3616 {
3617         struct stmmac_priv *priv = netdev_priv(dev);
3618
3619         stmmac_set_filter(priv, priv->hw, dev);
3620 }
3621
3622 /**
3623  *  stmmac_change_mtu - entry point to change MTU size for the device.
3624  *  @dev : device pointer.
3625  *  @new_mtu : the new MTU size for the device.
3626  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
3627  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
3628  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
3629  *  Return value:
3630  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3631  *  file on failure.
3632  */
3633 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3634 {
3635         struct stmmac_priv *priv = netdev_priv(dev);
3636
3637         if (netif_running(dev)) {
3638                 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3639                 return -EBUSY;
3640         }
3641
3642         dev->mtu = new_mtu;
3643
3644         netdev_update_features(dev);
3645
3646         return 0;
3647 }
3648
3649 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3650                                              netdev_features_t features)
3651 {
3652         struct stmmac_priv *priv = netdev_priv(dev);
3653
3654         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3655                 features &= ~NETIF_F_RXCSUM;
3656
3657         if (!priv->plat->tx_coe)
3658                 features &= ~NETIF_F_CSUM_MASK;
3659
3660         /* Some GMAC devices have a bugged Jumbo frame support that
3661          * needs to have the Tx COE disabled for oversized frames
3662          * (due to limited buffer sizes). In this case we disable
3663          * the TX csum insertion in the TDES and not use SF.
3664          */
3665         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3666                 features &= ~NETIF_F_CSUM_MASK;
3667
3668         /* Disable tso if asked by ethtool */
3669         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3670                 if (features & NETIF_F_TSO)
3671                         priv->tso = true;
3672                 else
3673                         priv->tso = false;
3674         }
3675
3676         return features;
3677 }
3678
3679 static int stmmac_set_features(struct net_device *netdev,
3680                                netdev_features_t features)
3681 {
3682         struct stmmac_priv *priv = netdev_priv(netdev);
3683
3684         /* Keep the COE Type in case of csum is supporting */
3685         if (features & NETIF_F_RXCSUM)
3686                 priv->hw->rx_csum = priv->plat->rx_coe;
3687         else
3688                 priv->hw->rx_csum = 0;
3689         /* No check needed because rx_coe has been set before and it will be
3690          * fixed in case of issue.
3691          */
3692         stmmac_rx_ipc(priv, priv->hw);
3693
3694         return 0;
3695 }
3696
3697 /**
3698  *  stmmac_interrupt - main ISR
3699  *  @irq: interrupt number.
3700  *  @dev_id: to pass the net device pointer.
3701  *  Description: this is the main driver interrupt service routine.
3702  *  It can call:
3703  *  o DMA service routine (to manage incoming frame reception and transmission
3704  *    status)
3705  *  o Core interrupts to manage: remote wake-up, management counter, LPI
3706  *    interrupts.
3707  */
3708 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3709 {
3710         struct net_device *dev = (struct net_device *)dev_id;
3711         struct stmmac_priv *priv = netdev_priv(dev);
3712         u32 rx_cnt = priv->plat->rx_queues_to_use;
3713         u32 tx_cnt = priv->plat->tx_queues_to_use;
3714         u32 queues_count;
3715         u32 queue;
3716         bool xmac;
3717
3718         xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3719         queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3720
3721         if (priv->irq_wake)
3722                 pm_wakeup_event(priv->device, 0);
3723
3724         if (unlikely(!dev)) {
3725                 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3726                 return IRQ_NONE;
3727         }
3728
3729         /* Check if adapter is up */
3730         if (test_bit(STMMAC_DOWN, &priv->state))
3731                 return IRQ_HANDLED;
3732         /* Check if a fatal error happened */
3733         if (stmmac_safety_feat_interrupt(priv))
3734                 return IRQ_HANDLED;
3735
3736         /* To handle GMAC own interrupts */
3737         if ((priv->plat->has_gmac) || xmac) {
3738                 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3739                 int mtl_status;
3740
3741                 if (unlikely(status)) {
3742                         /* For LPI we need to save the tx status */
3743                         if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3744                                 priv->tx_path_in_lpi_mode = true;
3745                         if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3746                                 priv->tx_path_in_lpi_mode = false;
3747                 }
3748
3749                 for (queue = 0; queue < queues_count; queue++) {
3750                         struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3751
3752                         mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3753                                                                 queue);
3754                         if (mtl_status != -EINVAL)
3755                                 status |= mtl_status;
3756
3757                         if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3758                                 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3759                                                        rx_q->rx_tail_addr,
3760                                                        queue);
3761                 }
3762
3763                 /* PCS link status */
3764                 if (priv->hw->pcs) {
3765                         if (priv->xstats.pcs_link)
3766                                 netif_carrier_on(dev);
3767                         else
3768                                 netif_carrier_off(dev);
3769                 }
3770         }
3771
3772         /* To handle DMA interrupts */
3773         stmmac_dma_interrupt(priv);
3774
3775         return IRQ_HANDLED;
3776 }
3777
3778 #ifdef CONFIG_NET_POLL_CONTROLLER
3779 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3780  * to allow network I/O with interrupts disabled.
3781  */
3782 static void stmmac_poll_controller(struct net_device *dev)
3783 {
3784         disable_irq(dev->irq);
3785         stmmac_interrupt(dev->irq, dev);
3786         enable_irq(dev->irq);
3787 }
3788 #endif
3789
3790 /**
3791  *  stmmac_ioctl - Entry point for the Ioctl
3792  *  @dev: Device pointer.
3793  *  @rq: An IOCTL specefic structure, that can contain a pointer to
3794  *  a proprietary structure used to pass information to the driver.
3795  *  @cmd: IOCTL command
3796  *  Description:
3797  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3798  */
3799 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3800 {
3801         struct stmmac_priv *priv = netdev_priv (dev);
3802         int ret = -EOPNOTSUPP;
3803
3804         if (!netif_running(dev))
3805                 return -EINVAL;
3806
3807         switch (cmd) {
3808         case SIOCGMIIPHY:
3809         case SIOCGMIIREG:
3810         case SIOCSMIIREG:
3811                 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
3812                 break;
3813         case SIOCSHWTSTAMP:
3814                 ret = stmmac_hwtstamp_set(dev, rq);
3815                 break;
3816         case SIOCGHWTSTAMP:
3817                 ret = stmmac_hwtstamp_get(dev, rq);
3818                 break;
3819         default:
3820                 break;
3821         }
3822
3823         return ret;
3824 }
3825
3826 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3827                                     void *cb_priv)
3828 {
3829         struct stmmac_priv *priv = cb_priv;
3830         int ret = -EOPNOTSUPP;
3831
3832         stmmac_disable_all_queues(priv);
3833
3834         switch (type) {
3835         case TC_SETUP_CLSU32:
3836                 if (tc_cls_can_offload_and_chain0(priv->dev, type_data))
3837                         ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3838                 break;
3839         default:
3840                 break;
3841         }
3842
3843         stmmac_enable_all_queues(priv);
3844         return ret;
3845 }
3846
3847 static int stmmac_setup_tc_block(struct stmmac_priv *priv,
3848                                  struct tc_block_offload *f)
3849 {
3850         if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3851                 return -EOPNOTSUPP;
3852
3853         switch (f->command) {
3854         case TC_BLOCK_BIND:
3855                 return tcf_block_cb_register(f->block, stmmac_setup_tc_block_cb,
3856                                 priv, priv, f->extack);
3857         case TC_BLOCK_UNBIND:
3858                 tcf_block_cb_unregister(f->block, stmmac_setup_tc_block_cb, priv);
3859                 return 0;
3860         default:
3861                 return -EOPNOTSUPP;
3862         }
3863 }
3864
3865 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3866                            void *type_data)
3867 {
3868         struct stmmac_priv *priv = netdev_priv(ndev);
3869
3870         switch (type) {
3871         case TC_SETUP_BLOCK:
3872                 return stmmac_setup_tc_block(priv, type_data);
3873         case TC_SETUP_QDISC_CBS:
3874                 return stmmac_tc_setup_cbs(priv, priv, type_data);
3875         default:
3876                 return -EOPNOTSUPP;
3877         }
3878 }
3879
3880 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
3881                                struct net_device *sb_dev)
3882 {
3883         if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3884                 /*
3885                  * There is no way to determine the number of TSO
3886                  * capable Queues. Let's use always the Queue 0
3887                  * because if TSO is supported then at least this
3888                  * one will be capable.
3889                  */
3890                 return 0;
3891         }
3892
3893         return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
3894 }
3895
3896 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
3897 {
3898         struct stmmac_priv *priv = netdev_priv(ndev);
3899         int ret = 0;
3900
3901         ret = eth_mac_addr(ndev, addr);
3902         if (ret)
3903                 return ret;
3904
3905         stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
3906
3907         return ret;
3908 }
3909
3910 #ifdef CONFIG_DEBUG_FS
3911 static struct dentry *stmmac_fs_dir;
3912
3913 static void sysfs_display_ring(void *head, int size, int extend_desc,
3914                                struct seq_file *seq)
3915 {
3916         int i;
3917         struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
3918         struct dma_desc *p = (struct dma_desc *)head;
3919
3920         for (i = 0; i < size; i++) {
3921                 if (extend_desc) {
3922                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3923                                    i, (unsigned int)virt_to_phys(ep),
3924                                    le32_to_cpu(ep->basic.des0),
3925                                    le32_to_cpu(ep->basic.des1),
3926                                    le32_to_cpu(ep->basic.des2),
3927                                    le32_to_cpu(ep->basic.des3));
3928                         ep++;
3929                 } else {
3930                         seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
3931                                    i, (unsigned int)virt_to_phys(p),
3932                                    le32_to_cpu(p->des0), le32_to_cpu(p->des1),
3933                                    le32_to_cpu(p->des2), le32_to_cpu(p->des3));
3934                         p++;
3935                 }
3936                 seq_printf(seq, "\n");
3937         }
3938 }
3939
3940 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
3941 {
3942         struct net_device *dev = seq->private;
3943         struct stmmac_priv *priv = netdev_priv(dev);
3944         u32 rx_count = priv->plat->rx_queues_to_use;
3945         u32 tx_count = priv->plat->tx_queues_to_use;
3946         u32 queue;
3947
3948         if ((dev->flags & IFF_UP) == 0)
3949                 return 0;
3950
3951         for (queue = 0; queue < rx_count; queue++) {
3952                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3953
3954                 seq_printf(seq, "RX Queue %d:\n", queue);
3955
3956                 if (priv->extend_desc) {
3957                         seq_printf(seq, "Extended descriptor ring:\n");
3958                         sysfs_display_ring((void *)rx_q->dma_erx,
3959                                            DMA_RX_SIZE, 1, seq);
3960                 } else {
3961                         seq_printf(seq, "Descriptor ring:\n");
3962                         sysfs_display_ring((void *)rx_q->dma_rx,
3963                                            DMA_RX_SIZE, 0, seq);
3964                 }
3965         }
3966
3967         for (queue = 0; queue < tx_count; queue++) {
3968                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
3969
3970                 seq_printf(seq, "TX Queue %d:\n", queue);
3971
3972                 if (priv->extend_desc) {
3973                         seq_printf(seq, "Extended descriptor ring:\n");
3974                         sysfs_display_ring((void *)tx_q->dma_etx,
3975                                            DMA_TX_SIZE, 1, seq);
3976                 } else {
3977                         seq_printf(seq, "Descriptor ring:\n");
3978                         sysfs_display_ring((void *)tx_q->dma_tx,
3979                                            DMA_TX_SIZE, 0, seq);
3980                 }
3981         }
3982
3983         return 0;
3984 }
3985 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
3986
3987 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
3988 {
3989         struct net_device *dev = seq->private;
3990         struct stmmac_priv *priv = netdev_priv(dev);
3991
3992         if (!priv->hw_cap_support) {
3993                 seq_printf(seq, "DMA HW features not supported\n");
3994                 return 0;
3995         }
3996
3997         seq_printf(seq, "==============================\n");
3998         seq_printf(seq, "\tDMA HW features\n");
3999         seq_printf(seq, "==============================\n");
4000
4001         seq_printf(seq, "\t10/100 Mbps: %s\n",
4002                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
4003         seq_printf(seq, "\t1000 Mbps: %s\n",
4004                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
4005         seq_printf(seq, "\tHalf duplex: %s\n",
4006                    (priv->dma_cap.half_duplex) ? "Y" : "N");
4007         seq_printf(seq, "\tHash Filter: %s\n",
4008                    (priv->dma_cap.hash_filter) ? "Y" : "N");
4009         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
4010                    (priv->dma_cap.multi_addr) ? "Y" : "N");
4011         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
4012                    (priv->dma_cap.pcs) ? "Y" : "N");
4013         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
4014                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
4015         seq_printf(seq, "\tPMT Remote wake up: %s\n",
4016                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
4017         seq_printf(seq, "\tPMT Magic Frame: %s\n",
4018                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
4019         seq_printf(seq, "\tRMON module: %s\n",
4020                    (priv->dma_cap.rmon) ? "Y" : "N");
4021         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
4022                    (priv->dma_cap.time_stamp) ? "Y" : "N");
4023         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
4024                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
4025         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
4026                    (priv->dma_cap.eee) ? "Y" : "N");
4027         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
4028         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
4029                    (priv->dma_cap.tx_coe) ? "Y" : "N");
4030         if (priv->synopsys_id >= DWMAC_CORE_4_00) {
4031                 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
4032                            (priv->dma_cap.rx_coe) ? "Y" : "N");
4033         } else {
4034                 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
4035                            (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
4036                 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
4037                            (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
4038         }
4039         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
4040                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
4041         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
4042                    priv->dma_cap.number_rx_channel);
4043         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
4044                    priv->dma_cap.number_tx_channel);
4045         seq_printf(seq, "\tEnhanced descriptors: %s\n",
4046                    (priv->dma_cap.enh_desc) ? "Y" : "N");
4047
4048         return 0;
4049 }
4050 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
4051
4052 static int stmmac_init_fs(struct net_device *dev)
4053 {
4054         struct stmmac_priv *priv = netdev_priv(dev);
4055
4056         /* Create per netdev entries */
4057         priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
4058
4059         if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
4060                 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n");
4061
4062                 return -ENOMEM;
4063         }
4064
4065         /* Entry to report DMA RX/TX rings */
4066         priv->dbgfs_rings_status =
4067                 debugfs_create_file("descriptors_status", 0444,
4068                                     priv->dbgfs_dir, dev,
4069                                     &stmmac_rings_status_fops);
4070
4071         if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
4072                 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n");
4073                 debugfs_remove_recursive(priv->dbgfs_dir);
4074
4075                 return -ENOMEM;
4076         }
4077
4078         /* Entry to report the DMA HW features */
4079         priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444,
4080                                                   priv->dbgfs_dir,
4081                                                   dev, &stmmac_dma_cap_fops);
4082
4083         if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
4084                 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n");
4085                 debugfs_remove_recursive(priv->dbgfs_dir);
4086
4087                 return -ENOMEM;
4088         }
4089
4090         return 0;
4091 }
4092
4093 static void stmmac_exit_fs(struct net_device *dev)
4094 {
4095         struct stmmac_priv *priv = netdev_priv(dev);
4096
4097         debugfs_remove_recursive(priv->dbgfs_dir);
4098 }
4099 #endif /* CONFIG_DEBUG_FS */
4100
4101 static const struct net_device_ops stmmac_netdev_ops = {
4102         .ndo_open = stmmac_open,
4103         .ndo_start_xmit = stmmac_xmit,
4104         .ndo_stop = stmmac_release,
4105         .ndo_change_mtu = stmmac_change_mtu,
4106         .ndo_fix_features = stmmac_fix_features,
4107         .ndo_set_features = stmmac_set_features,
4108         .ndo_set_rx_mode = stmmac_set_rx_mode,
4109         .ndo_tx_timeout = stmmac_tx_timeout,
4110         .ndo_do_ioctl = stmmac_ioctl,
4111         .ndo_setup_tc = stmmac_setup_tc,
4112         .ndo_select_queue = stmmac_select_queue,
4113 #ifdef CONFIG_NET_POLL_CONTROLLER
4114         .ndo_poll_controller = stmmac_poll_controller,
4115 #endif
4116         .ndo_set_mac_address = stmmac_set_mac_address,
4117 };
4118
4119 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4120 {
4121         if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4122                 return;
4123         if (test_bit(STMMAC_DOWN, &priv->state))
4124                 return;
4125
4126         netdev_err(priv->dev, "Reset adapter.\n");
4127
4128         rtnl_lock();
4129         netif_trans_update(priv->dev);
4130         while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4131                 usleep_range(1000, 2000);
4132
4133         set_bit(STMMAC_DOWN, &priv->state);
4134         dev_close(priv->dev);
4135         dev_open(priv->dev, NULL);
4136         clear_bit(STMMAC_DOWN, &priv->state);
4137         clear_bit(STMMAC_RESETING, &priv->state);
4138         rtnl_unlock();
4139 }
4140
4141 static void stmmac_service_task(struct work_struct *work)
4142 {
4143         struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4144                         service_task);
4145
4146         stmmac_reset_subtask(priv);
4147         clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4148 }
4149
4150 /**
4151  *  stmmac_hw_init - Init the MAC device
4152  *  @priv: driver private structure
4153  *  Description: this function is to configure the MAC device according to
4154  *  some platform parameters or the HW capability register. It prepares the
4155  *  driver to use either ring or chain modes and to setup either enhanced or
4156  *  normal descriptors.
4157  */
4158 static int stmmac_hw_init(struct stmmac_priv *priv)
4159 {
4160         int ret;
4161
4162         /* dwmac-sun8i only work in chain mode */
4163         if (priv->plat->has_sun8i)
4164                 chain_mode = 1;
4165         priv->chain_mode = chain_mode;
4166
4167         /* Initialize HW Interface */
4168         ret = stmmac_hwif_init(priv);
4169         if (ret)
4170                 return ret;
4171
4172         /* Get the HW capability (new GMAC newer than 3.50a) */
4173         priv->hw_cap_support = stmmac_get_hw_features(priv);
4174         if (priv->hw_cap_support) {
4175                 dev_info(priv->device, "DMA HW capability register supported\n");
4176
4177                 /* We can override some gmac/dma configuration fields: e.g.
4178                  * enh_desc, tx_coe (e.g. that are passed through the
4179                  * platform) with the values from the HW capability
4180                  * register (if supported).
4181                  */
4182                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4183                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4184                 priv->hw->pmt = priv->plat->pmt;
4185
4186                 /* TXCOE doesn't work in thresh DMA mode */
4187                 if (priv->plat->force_thresh_dma_mode)
4188                         priv->plat->tx_coe = 0;
4189                 else
4190                         priv->plat->tx_coe = priv->dma_cap.tx_coe;
4191
4192                 /* In case of GMAC4 rx_coe is from HW cap register. */
4193                 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4194
4195                 if (priv->dma_cap.rx_coe_type2)
4196                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4197                 else if (priv->dma_cap.rx_coe_type1)
4198                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4199
4200         } else {
4201                 dev_info(priv->device, "No HW DMA feature register supported\n");
4202         }
4203
4204         if (priv->plat->rx_coe) {
4205                 priv->hw->rx_csum = priv->plat->rx_coe;
4206                 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4207                 if (priv->synopsys_id < DWMAC_CORE_4_00)
4208                         dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4209         }
4210         if (priv->plat->tx_coe)
4211                 dev_info(priv->device, "TX Checksum insertion supported\n");
4212
4213         if (priv->plat->pmt) {
4214                 dev_info(priv->device, "Wake-Up On Lan supported\n");
4215                 device_set_wakeup_capable(priv->device, 1);
4216         }
4217
4218         if (priv->dma_cap.tsoen)
4219                 dev_info(priv->device, "TSO supported\n");
4220
4221         /* Run HW quirks, if any */
4222         if (priv->hwif_quirks) {
4223                 ret = priv->hwif_quirks(priv);
4224                 if (ret)
4225                         return ret;
4226         }
4227
4228         /* Rx Watchdog is available in the COREs newer than the 3.40.
4229          * In some case, for example on bugged HW this feature
4230          * has to be disable and this can be done by passing the
4231          * riwt_off field from the platform.
4232          */
4233         if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4234             (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4235                 priv->use_riwt = 1;
4236                 dev_info(priv->device,
4237                          "Enable RX Mitigation via HW Watchdog Timer\n");
4238         }
4239
4240         return 0;
4241 }
4242
4243 /**
4244  * stmmac_dvr_probe
4245  * @device: device pointer
4246  * @plat_dat: platform data pointer
4247  * @res: stmmac resource pointer
4248  * Description: this is the main probe function used to
4249  * call the alloc_etherdev, allocate the priv structure.
4250  * Return:
4251  * returns 0 on success, otherwise errno.
4252  */
4253 int stmmac_dvr_probe(struct device *device,
4254                      struct plat_stmmacenet_data *plat_dat,
4255                      struct stmmac_resources *res)
4256 {
4257         struct net_device *ndev = NULL;
4258         struct stmmac_priv *priv;
4259         u32 queue, maxq;
4260         int ret = 0;
4261
4262         ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4263                                        MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
4264         if (!ndev)
4265                 return -ENOMEM;
4266
4267         SET_NETDEV_DEV(ndev, device);
4268
4269         priv = netdev_priv(ndev);
4270         priv->device = device;
4271         priv->dev = ndev;
4272
4273         stmmac_set_ethtool_ops(ndev);
4274         priv->pause = pause;
4275         priv->plat = plat_dat;
4276         priv->ioaddr = res->addr;
4277         priv->dev->base_addr = (unsigned long)res->addr;
4278
4279         priv->dev->irq = res->irq;
4280         priv->wol_irq = res->wol_irq;
4281         priv->lpi_irq = res->lpi_irq;
4282
4283         if (!IS_ERR_OR_NULL(res->mac))
4284                 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4285
4286         dev_set_drvdata(device, priv->dev);
4287
4288         /* Verify driver arguments */
4289         stmmac_verify_args();
4290
4291         /* Allocate workqueue */
4292         priv->wq = create_singlethread_workqueue("stmmac_wq");
4293         if (!priv->wq) {
4294                 dev_err(priv->device, "failed to create workqueue\n");
4295                 return -ENOMEM;
4296         }
4297
4298         INIT_WORK(&priv->service_task, stmmac_service_task);
4299
4300         /* Override with kernel parameters if supplied XXX CRS XXX
4301          * this needs to have multiple instances
4302          */
4303         if ((phyaddr >= 0) && (phyaddr <= 31))
4304                 priv->plat->phy_addr = phyaddr;
4305
4306         if (priv->plat->stmmac_rst) {
4307                 ret = reset_control_assert(priv->plat->stmmac_rst);
4308                 reset_control_deassert(priv->plat->stmmac_rst);
4309                 /* Some reset controllers have only reset callback instead of
4310                  * assert + deassert callbacks pair.
4311                  */
4312                 if (ret == -ENOTSUPP)
4313                         reset_control_reset(priv->plat->stmmac_rst);
4314         }
4315
4316         /* Init MAC and get the capabilities */
4317         ret = stmmac_hw_init(priv);
4318         if (ret)
4319                 goto error_hw_init;
4320
4321         stmmac_check_ether_addr(priv);
4322
4323         /* Configure real RX and TX queues */
4324         netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4325         netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4326
4327         ndev->netdev_ops = &stmmac_netdev_ops;
4328
4329         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4330                             NETIF_F_RXCSUM;
4331
4332         ret = stmmac_tc_init(priv, priv);
4333         if (!ret) {
4334                 ndev->hw_features |= NETIF_F_HW_TC;
4335         }
4336
4337         if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4338                 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4339                 priv->tso = true;
4340                 dev_info(priv->device, "TSO feature enabled\n");
4341         }
4342
4343         if (priv->dma_cap.addr64) {
4344                 ret = dma_set_mask_and_coherent(device,
4345                                 DMA_BIT_MASK(priv->dma_cap.addr64));
4346                 if (!ret) {
4347                         dev_info(priv->device, "Using %d bits DMA width\n",
4348                                  priv->dma_cap.addr64);
4349                 } else {
4350                         ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
4351                         if (ret) {
4352                                 dev_err(priv->device, "Failed to set DMA Mask\n");
4353                                 goto error_hw_init;
4354                         }
4355
4356                         priv->dma_cap.addr64 = 32;
4357                 }
4358         }
4359
4360         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4361         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4362 #ifdef STMMAC_VLAN_TAG_USED
4363         /* Both mac100 and gmac support receive VLAN tag detection */
4364         ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4365 #endif
4366         priv->msg_enable = netif_msg_init(debug, default_msg_level);
4367
4368         /* MTU range: 46 - hw-specific max */
4369         ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4370         if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4371                 ndev->max_mtu = JUMBO_LEN;
4372         else if (priv->plat->has_xgmac)
4373                 ndev->max_mtu = XGMAC_JUMBO_LEN;
4374         else
4375                 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4376         /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4377          * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4378          */
4379         if ((priv->plat->maxmtu < ndev->max_mtu) &&
4380             (priv->plat->maxmtu >= ndev->min_mtu))
4381                 ndev->max_mtu = priv->plat->maxmtu;
4382         else if (priv->plat->maxmtu < ndev->min_mtu)
4383                 dev_warn(priv->device,
4384                          "%s: warning: maxmtu having invalid value (%d)\n",
4385                          __func__, priv->plat->maxmtu);
4386
4387         if (flow_ctrl)
4388                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
4389
4390         /* Setup channels NAPI */
4391         maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4392
4393         for (queue = 0; queue < maxq; queue++) {
4394                 struct stmmac_channel *ch = &priv->channel[queue];
4395
4396                 ch->priv_data = priv;
4397                 ch->index = queue;
4398
4399                 if (queue < priv->plat->rx_queues_to_use) {
4400                         netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4401                                        NAPI_POLL_WEIGHT);
4402                 }
4403                 if (queue < priv->plat->tx_queues_to_use) {
4404                         netif_napi_add(ndev, &ch->tx_napi, stmmac_napi_poll_tx,
4405                                        NAPI_POLL_WEIGHT);
4406                 }
4407         }
4408
4409         mutex_init(&priv->lock);
4410
4411         /* If a specific clk_csr value is passed from the platform
4412          * this means that the CSR Clock Range selection cannot be
4413          * changed at run-time and it is fixed. Viceversa the driver'll try to
4414          * set the MDC clock dynamically according to the csr actual
4415          * clock input.
4416          */
4417         if (priv->plat->clk_csr >= 0)
4418                 priv->clk_csr = priv->plat->clk_csr;
4419         else
4420                 stmmac_clk_csr_set(priv);
4421
4422         stmmac_check_pcs_mode(priv);
4423
4424         if (priv->hw->pcs != STMMAC_PCS_RGMII  &&
4425             priv->hw->pcs != STMMAC_PCS_TBI &&
4426             priv->hw->pcs != STMMAC_PCS_RTBI) {
4427                 /* MDIO bus Registration */
4428                 ret = stmmac_mdio_register(ndev);
4429                 if (ret < 0) {
4430                         dev_err(priv->device,
4431                                 "%s: MDIO bus (id: %d) registration failed",
4432                                 __func__, priv->plat->bus_id);
4433                         goto error_mdio_register;
4434                 }
4435         }
4436
4437         ret = stmmac_phy_setup(priv);
4438         if (ret) {
4439                 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4440                 goto error_phy_setup;
4441         }
4442
4443         ret = register_netdev(ndev);
4444         if (ret) {
4445                 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4446                         __func__, ret);
4447                 goto error_netdev_register;
4448         }
4449
4450 #ifdef CONFIG_DEBUG_FS
4451         ret = stmmac_init_fs(ndev);
4452         if (ret < 0)
4453                 netdev_warn(priv->dev, "%s: failed debugFS registration\n",
4454                             __func__);
4455 #endif
4456
4457         return ret;
4458
4459 error_netdev_register:
4460         phylink_destroy(priv->phylink);
4461 error_phy_setup:
4462         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4463             priv->hw->pcs != STMMAC_PCS_TBI &&
4464             priv->hw->pcs != STMMAC_PCS_RTBI)
4465                 stmmac_mdio_unregister(ndev);
4466 error_mdio_register:
4467         for (queue = 0; queue < maxq; queue++) {
4468                 struct stmmac_channel *ch = &priv->channel[queue];
4469
4470                 if (queue < priv->plat->rx_queues_to_use)
4471                         netif_napi_del(&ch->rx_napi);
4472                 if (queue < priv->plat->tx_queues_to_use)
4473                         netif_napi_del(&ch->tx_napi);
4474         }
4475 error_hw_init:
4476         destroy_workqueue(priv->wq);
4477
4478         return ret;
4479 }
4480 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4481
4482 /**
4483  * stmmac_dvr_remove
4484  * @dev: device pointer
4485  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4486  * changes the link status, releases the DMA descriptor rings.
4487  */
4488 int stmmac_dvr_remove(struct device *dev)
4489 {
4490         struct net_device *ndev = dev_get_drvdata(dev);
4491         struct stmmac_priv *priv = netdev_priv(ndev);
4492
4493         netdev_info(priv->dev, "%s: removing driver", __func__);
4494
4495 #ifdef CONFIG_DEBUG_FS
4496         stmmac_exit_fs(ndev);
4497 #endif
4498         stmmac_stop_all_dma(priv);
4499
4500         stmmac_mac_set(priv, priv->ioaddr, false);
4501         netif_carrier_off(ndev);
4502         unregister_netdev(ndev);
4503         phylink_destroy(priv->phylink);
4504         if (priv->plat->stmmac_rst)
4505                 reset_control_assert(priv->plat->stmmac_rst);
4506         clk_disable_unprepare(priv->plat->pclk);
4507         clk_disable_unprepare(priv->plat->stmmac_clk);
4508         if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4509             priv->hw->pcs != STMMAC_PCS_TBI &&
4510             priv->hw->pcs != STMMAC_PCS_RTBI)
4511                 stmmac_mdio_unregister(ndev);
4512         destroy_workqueue(priv->wq);
4513         mutex_destroy(&priv->lock);
4514
4515         return 0;
4516 }
4517 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4518
4519 /**
4520  * stmmac_suspend - suspend callback
4521  * @dev: device pointer
4522  * Description: this is the function to suspend the device and it is called
4523  * by the platform driver to stop the network queue, release the resources,
4524  * program the PMT register (for WoL), clean and release driver resources.
4525  */
4526 int stmmac_suspend(struct device *dev)
4527 {
4528         struct net_device *ndev = dev_get_drvdata(dev);
4529         struct stmmac_priv *priv = netdev_priv(ndev);
4530
4531         if (!ndev || !netif_running(ndev))
4532                 return 0;
4533
4534         phylink_stop(priv->phylink);
4535
4536         mutex_lock(&priv->lock);
4537
4538         netif_device_detach(ndev);
4539         stmmac_stop_all_queues(priv);
4540
4541         stmmac_disable_all_queues(priv);
4542
4543         /* Stop TX/RX DMA */
4544         stmmac_stop_all_dma(priv);
4545
4546         /* Enable Power down mode by programming the PMT regs */
4547         if (device_may_wakeup(priv->device)) {
4548                 stmmac_pmt(priv, priv->hw, priv->wolopts);
4549                 priv->irq_wake = 1;
4550         } else {
4551                 stmmac_mac_set(priv, priv->ioaddr, false);
4552                 pinctrl_pm_select_sleep_state(priv->device);
4553                 /* Disable clock in case of PWM is off */
4554                 clk_disable(priv->plat->pclk);
4555                 clk_disable(priv->plat->stmmac_clk);
4556         }
4557         mutex_unlock(&priv->lock);
4558
4559         priv->speed = SPEED_UNKNOWN;
4560         return 0;
4561 }
4562 EXPORT_SYMBOL_GPL(stmmac_suspend);
4563
4564 /**
4565  * stmmac_reset_queues_param - reset queue parameters
4566  * @dev: device pointer
4567  */
4568 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4569 {
4570         u32 rx_cnt = priv->plat->rx_queues_to_use;
4571         u32 tx_cnt = priv->plat->tx_queues_to_use;
4572         u32 queue;
4573
4574         for (queue = 0; queue < rx_cnt; queue++) {
4575                 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4576
4577                 rx_q->cur_rx = 0;
4578                 rx_q->dirty_rx = 0;
4579         }
4580
4581         for (queue = 0; queue < tx_cnt; queue++) {
4582                 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4583
4584                 tx_q->cur_tx = 0;
4585                 tx_q->dirty_tx = 0;
4586                 tx_q->mss = 0;
4587         }
4588 }
4589
4590 /**
4591  * stmmac_resume - resume callback
4592  * @dev: device pointer
4593  * Description: when resume this function is invoked to setup the DMA and CORE
4594  * in a usable state.
4595  */
4596 int stmmac_resume(struct device *dev)
4597 {
4598         struct net_device *ndev = dev_get_drvdata(dev);
4599         struct stmmac_priv *priv = netdev_priv(ndev);
4600
4601         if (!netif_running(ndev))
4602                 return 0;
4603
4604         /* Power Down bit, into the PM register, is cleared
4605          * automatically as soon as a magic packet or a Wake-up frame
4606          * is received. Anyway, it's better to manually clear
4607          * this bit because it can generate problems while resuming
4608          * from another devices (e.g. serial console).
4609          */
4610         if (device_may_wakeup(priv->device)) {
4611                 mutex_lock(&priv->lock);
4612                 stmmac_pmt(priv, priv->hw, 0);
4613                 mutex_unlock(&priv->lock);
4614                 priv->irq_wake = 0;
4615         } else {
4616                 pinctrl_pm_select_default_state(priv->device);
4617                 /* enable the clk previously disabled */
4618                 clk_enable(priv->plat->stmmac_clk);
4619                 clk_enable(priv->plat->pclk);
4620                 /* reset the phy so that it's ready */
4621                 if (priv->mii)
4622                         stmmac_mdio_reset(priv->mii);
4623         }
4624
4625         netif_device_attach(ndev);
4626
4627         mutex_lock(&priv->lock);
4628
4629         stmmac_reset_queues_param(priv);
4630
4631         stmmac_clear_descriptors(priv);
4632
4633         stmmac_hw_setup(ndev, false);
4634         stmmac_init_tx_coalesce(priv);
4635         stmmac_set_rx_mode(ndev);
4636
4637         stmmac_enable_all_queues(priv);
4638
4639         stmmac_start_all_queues(priv);
4640
4641         mutex_unlock(&priv->lock);
4642
4643         phylink_start(priv->phylink);
4644
4645         return 0;
4646 }
4647 EXPORT_SYMBOL_GPL(stmmac_resume);
4648
4649 #ifndef MODULE
4650 static int __init stmmac_cmdline_opt(char *str)
4651 {
4652         char *opt;
4653
4654         if (!str || !*str)
4655                 return -EINVAL;
4656         while ((opt = strsep(&str, ",")) != NULL) {
4657                 if (!strncmp(opt, "debug:", 6)) {
4658                         if (kstrtoint(opt + 6, 0, &debug))
4659                                 goto err;
4660                 } else if (!strncmp(opt, "phyaddr:", 8)) {
4661                         if (kstrtoint(opt + 8, 0, &phyaddr))
4662                                 goto err;
4663                 } else if (!strncmp(opt, "buf_sz:", 7)) {
4664                         if (kstrtoint(opt + 7, 0, &buf_sz))
4665                                 goto err;
4666                 } else if (!strncmp(opt, "tc:", 3)) {
4667                         if (kstrtoint(opt + 3, 0, &tc))
4668                                 goto err;
4669                 } else if (!strncmp(opt, "watchdog:", 9)) {
4670                         if (kstrtoint(opt + 9, 0, &watchdog))
4671                                 goto err;
4672                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4673                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
4674                                 goto err;
4675                 } else if (!strncmp(opt, "pause:", 6)) {
4676                         if (kstrtoint(opt + 6, 0, &pause))
4677                                 goto err;
4678                 } else if (!strncmp(opt, "eee_timer:", 10)) {
4679                         if (kstrtoint(opt + 10, 0, &eee_timer))
4680                                 goto err;
4681                 } else if (!strncmp(opt, "chain_mode:", 11)) {
4682                         if (kstrtoint(opt + 11, 0, &chain_mode))
4683                                 goto err;
4684                 }
4685         }
4686         return 0;
4687
4688 err:
4689         pr_err("%s: ERROR broken module parameter conversion", __func__);
4690         return -EINVAL;
4691 }
4692
4693 __setup("stmmaceth=", stmmac_cmdline_opt);
4694 #endif /* MODULE */
4695
4696 static int __init stmmac_init(void)
4697 {
4698 #ifdef CONFIG_DEBUG_FS
4699         /* Create debugfs main directory if it doesn't exist yet */
4700         if (!stmmac_fs_dir) {
4701                 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4702
4703                 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
4704                         pr_err("ERROR %s, debugfs create directory failed\n",
4705                                STMMAC_RESOURCE_NAME);
4706
4707                         return -ENOMEM;
4708                 }
4709         }
4710 #endif
4711
4712         return 0;
4713 }
4714
4715 static void __exit stmmac_exit(void)
4716 {
4717 #ifdef CONFIG_DEBUG_FS
4718         debugfs_remove_recursive(stmmac_fs_dir);
4719 #endif
4720 }
4721
4722 module_init(stmmac_init)
4723 module_exit(stmmac_exit)
4724
4725 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4726 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4727 MODULE_LICENSE("GPL");