drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

   1 /*******************************************************************************
   2   This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
   3   ST Ethernet IPs are built around a Synopsys IP Core.
   4
   5         Copyright(C) 2007-2011 STMicroelectronics Ltd
   6
   7   This program is free software; you can redistribute it and/or modify it
   8   under the terms and conditions of the GNU General Public License,
   9   version 2, as published by the Free Software Foundation.
  10
  11   This program is distributed in the hope it will be useful, but WITHOUT
  12   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14   more details.
  15
  16   You should have received a copy of the GNU General Public License along with
  17   this program; if not, write to the Free Software Foundation, Inc.,
  18   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19
  20   The full GNU General Public License is included in this distribution in
  21   the file called "COPYING".
  22
  23   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  24
  25   Documentation available at:
  26         http://www.stlinux.com
  27   Support available at:
  28         https://bugzilla.stlinux.com/
  29 *******************************************************************************/
  30
  31 #include <linux/clk.h>
  32 #include <linux/kernel.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ip.h>
  35 #include <linux/tcp.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/ethtool.h>
  38 #include <linux/if_ether.h>
  39 #include <linux/crc32.h>
  40 #include <linux/mii.h>
  41 #include <linux/if.h>
  42 #include <linux/if_vlan.h>
  43 #include <linux/dma-mapping.h>
  44 #include <linux/slab.h>
  45 #include <linux/prefetch.h>
  46 #ifdef CONFIG_STMMAC_DEBUG_FS
  47 #include <linux/debugfs.h>
  48 #include <linux/seq_file.h>
  49 #endif
  50 #include "stmmac.h"
  51
  52 #undef STMMAC_DEBUG
  53 /*#define STMMAC_DEBUG*/
  54 #ifdef STMMAC_DEBUG
  55 #define DBG(nlevel, klevel, fmt, args...) \
  56                 ((void)(netif_msg_##nlevel(priv) && \
  57                 printk(KERN_##klevel fmt, ## args)))
  58 #else
  59 #define DBG(nlevel, klevel, fmt, args...) do { } while (0)
  60 #endif
  61
  62 #undef STMMAC_RX_DEBUG
  63 /*#define STMMAC_RX_DEBUG*/
  64 #ifdef STMMAC_RX_DEBUG
  65 #define RX_DBG(fmt, args...)  printk(fmt, ## args)
  66 #else
  67 #define RX_DBG(fmt, args...)  do { } while (0)
  68 #endif
  69
  70 #undef STMMAC_XMIT_DEBUG
  71 /*#define STMMAC_XMIT_DEBUG*/
  72 #ifdef STMMAC_TX_DEBUG
  73 #define TX_DBG(fmt, args...)  printk(fmt, ## args)
  74 #else
  75 #define TX_DBG(fmt, args...)  do { } while (0)
  76 #endif
  77
  78 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x)
  79 #define JUMBO_LEN       9000
  80
  81 /* Module parameters */
  82 #define TX_TIMEO 5000 /* default 5 seconds */
  83 static int watchdog = TX_TIMEO;
  84 module_param(watchdog, int, S_IRUGO | S_IWUSR);
  85 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
  86
  87 static int debug = -1;          /* -1: default, 0: no output, 16:  all */
  88 module_param(debug, int, S_IRUGO | S_IWUSR);
  89 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)");
  90
  91 int phyaddr = -1;
  92 module_param(phyaddr, int, S_IRUGO);
  93 MODULE_PARM_DESC(phyaddr, "Physical device address");
  94
  95 #define DMA_TX_SIZE 256
  96 static int dma_txsize = DMA_TX_SIZE;
  97 module_param(dma_txsize, int, S_IRUGO | S_IWUSR);
  98 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list");
  99
 100 #define DMA_RX_SIZE 256
 101 static int dma_rxsize = DMA_RX_SIZE;
 102 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR);
 103 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list");
 104
 105 static int flow_ctrl = FLOW_OFF;
 106 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
 107 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
 108
 109 static int pause = PAUSE_TIME;
 110 module_param(pause, int, S_IRUGO | S_IWUSR);
 111 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
 112
 113 #define TC_DEFAULT 64
 114 static int tc = TC_DEFAULT;
 115 module_param(tc, int, S_IRUGO | S_IWUSR);
 116 MODULE_PARM_DESC(tc, "DMA threshold control value");
 117
 118 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
 119 static int buf_sz = DMA_BUFFER_SIZE;
 120 module_param(buf_sz, int, S_IRUGO | S_IWUSR);
 121 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
 122
 123 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
 124                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
 125                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
 126
 127 #define STMMAC_DEFAULT_LPI_TIMER        1000
 128 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 129 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
 130 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
 131 #define STMMAC_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
 132
 133 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 134
 135 #ifdef CONFIG_STMMAC_DEBUG_FS
 136 static int stmmac_init_fs(struct net_device *dev);
 137 static void stmmac_exit_fs(void);
 138 #endif
 139
 140 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
 141
 142 /**
 143  * stmmac_verify_args - verify the driver parameters.
 144  * Description: it verifies if some wrong parameter is passed to the driver.
 145  * Note that wrong parameters are replaced with the default values.
 146  */
 147 static void stmmac_verify_args(void)
 148 {
 149         if (unlikely(watchdog < 0))
 150                 watchdog = TX_TIMEO;
 151         if (unlikely(dma_rxsize < 0))
 152                 dma_rxsize = DMA_RX_SIZE;
 153         if (unlikely(dma_txsize < 0))
 154                 dma_txsize = DMA_TX_SIZE;
 155         if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB)))
 156                 buf_sz = DMA_BUFFER_SIZE;
 157         if (unlikely(flow_ctrl > 1))
 158                 flow_ctrl = FLOW_AUTO;
 159         else if (likely(flow_ctrl < 0))
 160                 flow_ctrl = FLOW_OFF;
 161         if (unlikely((pause < 0) || (pause > 0xffff)))
 162                 pause = PAUSE_TIME;
 163         if (eee_timer < 0)
 164                 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
 165 }
 166
 167 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
 168 {
 169         u32 clk_rate;
 170
 171         clk_rate = clk_get_rate(priv->stmmac_clk);
 172
 173         /* Platform provided default clk_csr would be assumed valid
 174          * for all other cases except for the below mentioned ones. */
 175         if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
 176                 if (clk_rate < CSR_F_35M)
 177                         priv->clk_csr = STMMAC_CSR_20_35M;
 178                 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
 179                         priv->clk_csr = STMMAC_CSR_35_60M;
 180                 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
 181                         priv->clk_csr = STMMAC_CSR_60_100M;
 182                 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
 183                         priv->clk_csr = STMMAC_CSR_100_150M;
 184                 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
 185                         priv->clk_csr = STMMAC_CSR_150_250M;
 186                 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
 187                         priv->clk_csr = STMMAC_CSR_250_300M;
 188         } /* For values higher than the IEEE 802.3 specified frequency
 189            * we can not estimate the proper divider as it is not known
 190            * the frequency of clk_csr_i. So we do not change the default
 191            * divider. */
 192 }
 193
 194 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG)
 195 static void print_pkt(unsigned char *buf, int len)
 196 {
 197         int j;
 198         pr_info("len = %d byte, buf addr: 0x%p", len, buf);
 199         for (j = 0; j < len; j++) {
 200                 if ((j % 16) == 0)
 201                         pr_info("\n %03x:", j);
 202                 pr_info(" %02x", buf[j]);
 203         }
 204         pr_info("\n");
 205 }
 206 #endif
 207
 208 /* minimum number of free TX descriptors required to wake up TX process */
 209 #define STMMAC_TX_THRESH(x)     (x->dma_tx_size/4)
 210
 211 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv)
 212 {
 213         return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1;
 214 }
 215
 216 /* On some ST platforms, some HW system configuraton registers have to be
 217  * set according to the link speed negotiated.
 218  */
 219 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv)
 220 {
 221         struct phy_device *phydev = priv->phydev;
 222
 223         if (likely(priv->plat->fix_mac_speed))
 224                 priv->plat->fix_mac_speed(priv->plat->bsp_priv,
 225                                           phydev->speed);
 226 }
 227
 228 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
 229 {
 230         /* Check and enter in LPI mode */
 231         if ((priv->dirty_tx == priv->cur_tx) &&
 232             (priv->tx_path_in_lpi_mode == false))
 233                 priv->hw->mac->set_eee_mode(priv->ioaddr);
 234 }
 235
 236 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
 237 {
 238         /* Exit and disable EEE in case of we are are in LPI state. */
 239         priv->hw->mac->reset_eee_mode(priv->ioaddr);
 240         del_timer_sync(&priv->eee_ctrl_timer);
 241         priv->tx_path_in_lpi_mode = false;
 242 }
 243
 244 /**
 245  * stmmac_eee_ctrl_timer
 246  * @arg : data hook
 247  * Description:
 248  *  If there is no data transfer and if we are not in LPI state,
 249  *  then MAC Transmitter can be moved to LPI state.
 250  */
 251 static void stmmac_eee_ctrl_timer(unsigned long arg)
 252 {
 253         struct stmmac_priv *priv = (struct stmmac_priv *)arg;
 254
 255         stmmac_enable_eee_mode(priv);
 256         mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 257 }
 258
 259 /**
 260  * stmmac_eee_init
 261  * @priv: private device pointer
 262  * Description:
 263  *  If the EEE support has been enabled while configuring the driver,
 264  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 265  *  phy can also manage EEE, so enable the LPI state and start the timer
 266  *  to verify if the tx path can enter in LPI state.
 267  */
 268 bool stmmac_eee_init(struct stmmac_priv *priv)
 269 {
 270         bool ret = false;
 271
 272         /* MAC core supports the EEE feature. */
 273         if (priv->dma_cap.eee) {
 274                 /* Check if the PHY supports EEE */
 275                 if (phy_init_eee(priv->phydev, 1))
 276                         goto out;
 277
 278                 priv->eee_active = 1;
 279                 init_timer(&priv->eee_ctrl_timer);
 280                 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer;
 281                 priv->eee_ctrl_timer.data = (unsigned long)priv;
 282                 priv->eee_ctrl_timer.expires = STMMAC_LPI_TIMER(eee_timer);
 283                 add_timer(&priv->eee_ctrl_timer);
 284
 285                 priv->hw->mac->set_eee_timer(priv->ioaddr,
 286                                              STMMAC_DEFAULT_LIT_LS_TIMER,
 287                                              priv->tx_lpi_timer);
 288
 289                 pr_info("stmmac: Energy-Efficient Ethernet initialized\n");
 290
 291                 ret = true;
 292         }
 293 out:
 294         return ret;
 295 }
 296
 297 static void stmmac_eee_adjust(struct stmmac_priv *priv)
 298 {
 299         /* When the EEE has been already initialised we have to
 300          * modify the PLS bit in the LPI ctrl & status reg according
 301          * to the PHY link status. For this reason.
 302          */
 303         if (priv->eee_enabled)
 304                 priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
 305 }
 306
 307 /**
 308  * stmmac_adjust_link
 309  * @dev: net device structure
 310  * Description: it adjusts the link parameters.
 311  */
 312 static void stmmac_adjust_link(struct net_device *dev)
 313 {
 314         struct stmmac_priv *priv = netdev_priv(dev);
 315         struct phy_device *phydev = priv->phydev;
 316         unsigned long flags;
 317         int new_state = 0;
 318         unsigned int fc = priv->flow_ctrl, pause_time = priv->pause;
 319
 320         if (phydev == NULL)
 321                 return;
 322
 323         DBG(probe, DEBUG, "stmmac_adjust_link: called.  address %d link %d\n",
 324             phydev->addr, phydev->link);
 325
 326         spin_lock_irqsave(&priv->lock, flags);
 327
 328         if (phydev->link) {
 329                 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
 330
 331                 /* Now we make sure that we can be in full duplex mode.
 332                  * If not, we operate in half-duplex mode. */
 333                 if (phydev->duplex != priv->oldduplex) {
 334                         new_state = 1;
 335                         if (!(phydev->duplex))
 336                                 ctrl &= ~priv->hw->link.duplex;
 337                         else
 338                                 ctrl |= priv->hw->link.duplex;
 339                         priv->oldduplex = phydev->duplex;
 340                 }
 341                 /* Flow Control operation */
 342                 if (phydev->pause)
 343                         priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex,
 344                                                  fc, pause_time);
 345
 346                 if (phydev->speed != priv->speed) {
 347                         new_state = 1;
 348                         switch (phydev->speed) {
 349                         case 1000:
 350                                 if (likely(priv->plat->has_gmac))
 351                                         ctrl &= ~priv->hw->link.port;
 352                                         stmmac_hw_fix_mac_speed(priv);
 353                                 break;
 354                         case 100:
 355                         case 10:
 356                                 if (priv->plat->has_gmac) {
 357                                         ctrl |= priv->hw->link.port;
 358                                         if (phydev->speed == SPEED_100) {
 359                                                 ctrl |= priv->hw->link.speed;
 360                                         } else {
 361                                                 ctrl &= ~(priv->hw->link.speed);
 362                                         }
 363                                 } else {
 364                                         ctrl &= ~priv->hw->link.port;
 365                                 }
 366                                 stmmac_hw_fix_mac_speed(priv);
 367                                 break;
 368                         default:
 369                                 if (netif_msg_link(priv))
 370                                         pr_warning("%s: Speed (%d) is not 10"
 371                                        " or 100!\n", dev->name, phydev->speed);
 372                                 break;
 373                         }
 374
 375                         priv->speed = phydev->speed;
 376                 }
 377
 378                 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
 379
 380                 if (!priv->oldlink) {
 381                         new_state = 1;
 382                         priv->oldlink = 1;
 383                 }
 384         } else if (priv->oldlink) {
 385                 new_state = 1;
 386                 priv->oldlink = 0;
 387                 priv->speed = 0;
 388                 priv->oldduplex = -1;
 389         }
 390
 391         if (new_state && netif_msg_link(priv))
 392                 phy_print_status(phydev);
 393
 394         stmmac_eee_adjust(priv);
 395
 396         spin_unlock_irqrestore(&priv->lock, flags);
 397
 398         DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n");
 399 }
 400
 401 /**
 402  * stmmac_init_phy - PHY initialization
 403  * @dev: net device structure
 404  * Description: it initializes the driver's PHY state, and attaches the PHY
 405  * to the mac driver.
 406  *  Return value:
 407  *  0 on success
 408  */
 409 static int stmmac_init_phy(struct net_device *dev)
 410 {
 411         struct stmmac_priv *priv = netdev_priv(dev);
 412         struct phy_device *phydev;
 413         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 414         char bus_id[MII_BUS_ID_SIZE];
 415         int interface = priv->plat->interface;
 416         priv->oldlink = 0;
 417         priv->speed = 0;
 418         priv->oldduplex = -1;
 419
 420         if (priv->plat->phy_bus_name)
 421                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 422                                 priv->plat->phy_bus_name, priv->plat->bus_id);
 423         else
 424                 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
 425                                 priv->plat->bus_id);
 426
 427         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 428                  priv->plat->phy_addr);
 429         pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
 430
 431         phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
 432
 433         if (IS_ERR(phydev)) {
 434                 pr_err("%s: Could not attach to PHY\n", dev->name);
 435                 return PTR_ERR(phydev);
 436         }
 437
 438         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 439         if ((interface == PHY_INTERFACE_MODE_MII) ||
 440             (interface == PHY_INTERFACE_MODE_RMII))
 441                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 442                                          SUPPORTED_1000baseT_Full);
 443
 444         /*
 445          * Broken HW is sometimes missing the pull-up resistor on the
 446          * MDIO line, which results in reads to non-existent devices returning
 447          * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent
 448          * device as well.
 449          * Note: phydev->phy_id is the result of reading the UID PHY registers.
 450          */
 451         if (phydev->phy_id == 0) {
 452                 phy_disconnect(phydev);
 453                 return -ENODEV;
 454         }
 455         pr_debug("stmmac_init_phy:  %s: attached to PHY (UID 0x%x)"
 456                  " Link = %d\n", dev->name, phydev->phy_id, phydev->link);
 457
 458         priv->phydev = phydev;
 459
 460         return 0;
 461 }
 462
 463 /**
 464  * display_ring
 465  * @p: pointer to the ring.
 466  * @size: size of the ring.
 467  * Description: display all the descriptors within the ring.
 468  */
 469 static void display_ring(struct dma_desc *p, int size)
 470 {
 471         struct tmp_s {
 472                 u64 a;
 473                 unsigned int b;
 474                 unsigned int c;
 475         };
 476         int i;
 477         for (i = 0; i < size; i++) {
 478                 struct tmp_s *x = (struct tmp_s *)(p + i);
 479                 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
 480                        i, (unsigned int)virt_to_phys(&p[i]),
 481                        (unsigned int)(x->a), (unsigned int)((x->a) >> 32),
 482                        x->b, x->c);
 483                 pr_info("\n");
 484         }
 485 }
 486
 487 static int stmmac_set_bfsize(int mtu, int bufsize)
 488 {
 489         int ret = bufsize;
 490
 491         if (mtu >= BUF_SIZE_4KiB)
 492                 ret = BUF_SIZE_8KiB;
 493         else if (mtu >= BUF_SIZE_2KiB)
 494                 ret = BUF_SIZE_4KiB;
 495         else if (mtu >= DMA_BUFFER_SIZE)
 496                 ret = BUF_SIZE_2KiB;
 497         else
 498                 ret = DMA_BUFFER_SIZE;
 499
 500         return ret;
 501 }
 502
 503 /**
 504  * init_dma_desc_rings - init the RX/TX descriptor rings
 505  * @dev: net device structure
 506  * Description:  this function initializes the DMA RX/TX descriptors
 507  * and allocates the socket buffers. It suppors the chained and ring
 508  * modes.
 509  */
 510 static void init_dma_desc_rings(struct net_device *dev)
 511 {
 512         int i;
 513         struct stmmac_priv *priv = netdev_priv(dev);
 514         struct sk_buff *skb;
 515         unsigned int txsize = priv->dma_tx_size;
 516         unsigned int rxsize = priv->dma_rx_size;
 517         unsigned int bfsize;
 518         int dis_ic = 0;
 519         int des3_as_data_buf = 0;
 520
 521         /* Set the max buffer size according to the DESC mode
 522          * and the MTU. Note that RING mode allows 16KiB bsize. */
 523         bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu);
 524
 525         if (bfsize == BUF_SIZE_16KiB)
 526                 des3_as_data_buf = 1;
 527         else
 528                 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
 529
 530         DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n",
 531             txsize, rxsize, bfsize);
 532
 533         priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL);
 534         priv->rx_skbuff =
 535             kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL);
 536         priv->dma_rx =
 537             (struct dma_desc *)dma_alloc_coherent(priv->device,
 538                                                   rxsize *
 539                                                   sizeof(struct dma_desc),
 540                                                   &priv->dma_rx_phy,
 541                                                   GFP_KERNEL);
 542         priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize,
 543                                        GFP_KERNEL);
 544         priv->dma_tx =
 545             (struct dma_desc *)dma_alloc_coherent(priv->device,
 546                                                   txsize *
 547                                                   sizeof(struct dma_desc),
 548                                                   &priv->dma_tx_phy,
 549                                                   GFP_KERNEL);
 550
 551         if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) {
 552                 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__);
 553                 return;
 554         }
 555
 556         DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, "
 557             "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n",
 558             dev->name, priv->dma_rx, priv->dma_tx,
 559             (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy);
 560
 561         /* RX INITIALIZATION */
 562         DBG(probe, INFO, "stmmac: SKB addresses:\n"
 563                          "skb\t\tskb data\tdma data\n");
 564
 565         for (i = 0; i < rxsize; i++) {
 566                 struct dma_desc *p = priv->dma_rx + i;
 567
 568                 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN,
 569                                          GFP_KERNEL);
 570                 if (unlikely(skb == NULL)) {
 571                         pr_err("%s: Rx init fails; skb is NULL\n", __func__);
 572                         break;
 573                 }
 574                 skb_reserve(skb, NET_IP_ALIGN);
 575                 priv->rx_skbuff[i] = skb;
 576                 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 577                                                 bfsize, DMA_FROM_DEVICE);
 578
 579                 p->des2 = priv->rx_skbuff_dma[i];
 580
 581                 priv->hw->ring->init_desc3(des3_as_data_buf, p);
 582
 583                 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i],
 584                         priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]);
 585         }
 586         priv->cur_rx = 0;
 587         priv->dirty_rx = (unsigned int)(i - rxsize);
 588         priv->dma_buf_sz = bfsize;
 589         buf_sz = bfsize;
 590
 591         /* TX INITIALIZATION */
 592         for (i = 0; i < txsize; i++) {
 593                 priv->tx_skbuff[i] = NULL;
 594                 priv->dma_tx[i].des2 = 0;
 595         }
 596
 597         /* In case of Chained mode this sets the des3 to the next
 598          * element in the chain */
 599         priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize);
 600         priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize);
 601
 602         priv->dirty_tx = 0;
 603         priv->cur_tx = 0;
 604
 605         if (priv->use_riwt)
 606                 dis_ic = 1;
 607         /* Clear the Rx/Tx descriptors */
 608         priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
 609         priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
 610
 611         if (netif_msg_hw(priv)) {
 612                 pr_info("RX descriptor ring:\n");
 613                 display_ring(priv->dma_rx, rxsize);
 614                 pr_info("TX descriptor ring:\n");
 615                 display_ring(priv->dma_tx, txsize);
 616         }
 617 }
 618
 619 static void dma_free_rx_skbufs(struct stmmac_priv *priv)
 620 {
 621         int i;
 622
 623         for (i = 0; i < priv->dma_rx_size; i++) {
 624                 if (priv->rx_skbuff[i]) {
 625                         dma_unmap_single(priv->device, priv->rx_skbuff_dma[i],
 626                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
 627                         dev_kfree_skb_any(priv->rx_skbuff[i]);
 628                 }
 629                 priv->rx_skbuff[i] = NULL;
 630         }
 631 }
 632
 633 static void dma_free_tx_skbufs(struct stmmac_priv *priv)
 634 {
 635         int i;
 636
 637         for (i = 0; i < priv->dma_tx_size; i++) {
 638                 if (priv->tx_skbuff[i] != NULL) {
 639                         struct dma_desc *p = priv->dma_tx + i;
 640                         if (p->des2)
 641                                 dma_unmap_single(priv->device, p->des2,
 642                                                  priv->hw->desc->get_tx_len(p),
 643                                                  DMA_TO_DEVICE);
 644                         dev_kfree_skb_any(priv->tx_skbuff[i]);
 645                         priv->tx_skbuff[i] = NULL;
 646                 }
 647         }
 648 }
 649
 650 static void free_dma_desc_resources(struct stmmac_priv *priv)
 651 {
 652         /* Release the DMA TX/RX socket buffers */
 653         dma_free_rx_skbufs(priv);
 654         dma_free_tx_skbufs(priv);
 655
 656         /* Free the region of consistent memory previously allocated for
 657          * the DMA */
 658         dma_free_coherent(priv->device,
 659                           priv->dma_tx_size * sizeof(struct dma_desc),
 660                           priv->dma_tx, priv->dma_tx_phy);
 661         dma_free_coherent(priv->device,
 662                           priv->dma_rx_size * sizeof(struct dma_desc),
 663                           priv->dma_rx, priv->dma_rx_phy);
 664         kfree(priv->rx_skbuff_dma);
 665         kfree(priv->rx_skbuff);
 666         kfree(priv->tx_skbuff);
 667 }
 668
 669 /**
 670  *  stmmac_dma_operation_mode - HW DMA operation mode
 671  *  @priv : pointer to the private device structure.
 672  *  Description: it sets the DMA operation mode: tx/rx DMA thresholds
 673  *  or Store-And-Forward capability.
 674  */
 675 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
 676 {
 677         if (likely(priv->plat->force_sf_dma_mode ||
 678                 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) {
 679                 /*
 680                  * In case of GMAC, SF mode can be enabled
 681                  * to perform the TX COE in HW. This depends on:
 682                  * 1) TX COE if actually supported
 683                  * 2) There is no bugged Jumbo frame support
 684                  *    that needs to not insert csum in the TDES.
 685                  */
 686                 priv->hw->dma->dma_mode(priv->ioaddr,
 687                                         SF_DMA_MODE, SF_DMA_MODE);
 688                 tc = SF_DMA_MODE;
 689         } else
 690                 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
 691 }
 692
 693 /**
 694  * stmmac_tx_clean:
 695  * @priv: private data pointer
 696  * Description: it reclaims resources after transmission completes.
 697  */
 698 static void stmmac_tx_clean(struct stmmac_priv *priv)
 699 {
 700         unsigned int txsize = priv->dma_tx_size;
 701
 702         spin_lock(&priv->tx_lock);
 703
 704         priv->xstats.tx_clean++;
 705
 706         while (priv->dirty_tx != priv->cur_tx) {
 707                 int last;
 708                 unsigned int entry = priv->dirty_tx % txsize;
 709                 struct sk_buff *skb = priv->tx_skbuff[entry];
 710                 struct dma_desc *p = priv->dma_tx + entry;
 711
 712                 /* Check if the descriptor is owned by the DMA. */
 713                 if (priv->hw->desc->get_tx_owner(p))
 714                         break;
 715
 716                 /* Verify tx error by looking at the last segment */
 717                 last = priv->hw->desc->get_tx_ls(p);
 718                 if (likely(last)) {
 719                         int tx_error =
 720                                 priv->hw->desc->tx_status(&priv->dev->stats,
 721                                                           &priv->xstats, p,
 722                                                           priv->ioaddr);
 723                         if (likely(tx_error == 0)) {
 724                                 priv->dev->stats.tx_packets++;
 725                                 priv->xstats.tx_pkt_n++;
 726                         } else
 727                                 priv->dev->stats.tx_errors++;
 728                 }
 729                 TX_DBG("%s: curr %d, dirty %d\n", __func__,
 730                         priv->cur_tx, priv->dirty_tx);
 731
 732                 if (likely(p->des2))
 733                         dma_unmap_single(priv->device, p->des2,
 734                                          priv->hw->desc->get_tx_len(p),
 735                                          DMA_TO_DEVICE);
 736                 priv->hw->ring->clean_desc3(p);
 737
 738                 if (likely(skb != NULL)) {
 739                         dev_kfree_skb(skb);
 740                         priv->tx_skbuff[entry] = NULL;
 741                 }
 742
 743                 priv->hw->desc->release_tx_desc(p);
 744
 745                 priv->dirty_tx++;
 746         }
 747         if (unlikely(netif_queue_stopped(priv->dev) &&
 748                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) {
 749                 netif_tx_lock(priv->dev);
 750                 if (netif_queue_stopped(priv->dev) &&
 751                      stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) {
 752                         TX_DBG("%s: restart transmit\n", __func__);
 753                         netif_wake_queue(priv->dev);
 754                 }
 755                 netif_tx_unlock(priv->dev);
 756         }
 757
 758         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
 759                 stmmac_enable_eee_mode(priv);
 760                 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer));
 761         }
 762         spin_unlock(&priv->tx_lock);
 763 }
 764
 765 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv)
 766 {
 767         priv->hw->dma->enable_dma_irq(priv->ioaddr);
 768 }
 769
 770 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv)
 771 {
 772         priv->hw->dma->disable_dma_irq(priv->ioaddr);
 773 }
 774
 775
 776 /**
 777  * stmmac_tx_err:
 778  * @priv: pointer to the private device structure
 779  * Description: it cleans the descriptors and restarts the transmission
 780  * in case of errors.
 781  */
 782 static void stmmac_tx_err(struct stmmac_priv *priv)
 783 {
 784         netif_stop_queue(priv->dev);
 785
 786         priv->hw->dma->stop_tx(priv->ioaddr);
 787         dma_free_tx_skbufs(priv);
 788         priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
 789         priv->dirty_tx = 0;
 790         priv->cur_tx = 0;
 791         priv->hw->dma->start_tx(priv->ioaddr);
 792
 793         priv->dev->stats.tx_errors++;
 794         netif_wake_queue(priv->dev);
 795 }
 796
 797 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
 798 {
 799         int status;
 800
 801         status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats);
 802         if (likely((status & handle_rx)) || (status & handle_tx)) {
 803                 if (likely(napi_schedule_prep(&priv->napi))) {
 804                         stmmac_disable_dma_irq(priv);
 805                         __napi_schedule(&priv->napi);
 806                 }
 807         }
 808         if (unlikely(status & tx_hard_error_bump_tc)) {
 809                 /* Try to bump up the dma threshold on this failure */
 810                 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
 811                         tc += 64;
 812                         priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE);
 813                         priv->xstats.threshold = tc;
 814                 }
 815         } else if (unlikely(status == tx_hard_error))
 816                 stmmac_tx_err(priv);
 817 }
 818
 819 static void stmmac_mmc_setup(struct stmmac_priv *priv)
 820 {
 821         unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
 822                             MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
 823
 824         /* Mask MMC irq, counters are managed in SW and registers
 825          * are cleared on each READ eventually. */
 826         dwmac_mmc_intr_all_mask(priv->ioaddr);
 827
 828         if (priv->dma_cap.rmon) {
 829                 dwmac_mmc_ctrl(priv->ioaddr, mode);
 830                 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
 831         } else
 832                 pr_info(" No MAC Management Counters available\n");
 833 }
 834
 835 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
 836 {
 837         u32 hwid = priv->hw->synopsys_uid;
 838
 839         /* Only check valid Synopsys Id because old MAC chips
 840          * have no HW registers where get the ID */
 841         if (likely(hwid)) {
 842                 u32 uid = ((hwid & 0x0000ff00) >> 8);
 843                 u32 synid = (hwid & 0x000000ff);
 844
 845                 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
 846                         uid, synid);
 847
 848                 return synid;
 849         }
 850         return 0;
 851 }
 852
 853 /**
 854  * stmmac_selec_desc_mode
 855  * @priv : private structure
 856  * Description: select the Enhanced/Alternate or Normal descriptors
 857  */
 858 static void stmmac_selec_desc_mode(struct stmmac_priv *priv)
 859 {
 860         if (priv->plat->enh_desc) {
 861                 pr_info(" Enhanced/Alternate descriptors\n");
 862                 priv->hw->desc = &enh_desc_ops;
 863         } else {
 864                 pr_info(" Normal descriptors\n");
 865                 priv->hw->desc = &ndesc_ops;
 866         }
 867 }
 868
 869 /**
 870  * stmmac_get_hw_features
 871  * @priv : private device pointer
 872  * Description:
 873  *  new GMAC chip generations have a new register to indicate the
 874  *  presence of the optional feature/functions.
 875  *  This can be also used to override the value passed through the
 876  *  platform and necessary for old MAC10/100 and GMAC chips.
 877  */
 878 static int stmmac_get_hw_features(struct stmmac_priv *priv)
 879 {
 880         u32 hw_cap = 0;
 881
 882         if (priv->hw->dma->get_hw_feature) {
 883                 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
 884
 885                 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
 886                 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
 887                 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
 888                 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4;
 889                 priv->dma_cap.multi_addr =
 890                         (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5;
 891                 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6;
 892                 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8;
 893                 priv->dma_cap.pmt_remote_wake_up =
 894                         (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9;
 895                 priv->dma_cap.pmt_magic_frame =
 896                         (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10;
 897                 /* MMC */
 898                 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11;
 899                 /* IEEE 1588-2002*/
 900                 priv->dma_cap.time_stamp =
 901                         (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12;
 902                 /* IEEE 1588-2008*/
 903                 priv->dma_cap.atime_stamp =
 904                         (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13;
 905                 /* 802.3az - Energy-Efficient Ethernet (EEE) */
 906                 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14;
 907                 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15;
 908                 /* TX and RX csum */
 909                 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16;
 910                 priv->dma_cap.rx_coe_type1 =
 911                         (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17;
 912                 priv->dma_cap.rx_coe_type2 =
 913                         (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18;
 914                 priv->dma_cap.rxfifo_over_2048 =
 915                         (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19;
 916                 /* TX and RX number of channels */
 917                 priv->dma_cap.number_rx_channel =
 918                         (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20;
 919                 priv->dma_cap.number_tx_channel =
 920                         (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22;
 921                 /* Alternate (enhanced) DESC mode*/
 922                 priv->dma_cap.enh_desc =
 923                         (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24;
 924         }
 925
 926         return hw_cap;
 927 }
 928
 929 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
 930 {
 931         /* verify if the MAC address is valid, in case of failures it
 932          * generates a random MAC address */
 933         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
 934                 priv->hw->mac->get_umac_addr((void __iomem *)
 935                                              priv->dev->base_addr,
 936                                              priv->dev->dev_addr, 0);
 937                 if  (!is_valid_ether_addr(priv->dev->dev_addr))
 938                         eth_hw_addr_random(priv->dev);
 939         }
 940         pr_warning("%s: device MAC address %pM\n", priv->dev->name,
 941                                                    priv->dev->dev_addr);
 942 }
 943
 944 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
 945 {
 946         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0;
 947         int mixed_burst = 0;
 948
 949         /* Some DMA parameters can be passed from the platform;
 950          * in case of these are not passed we keep a default
 951          * (good for all the chips) and init the DMA! */
 952         if (priv->plat->dma_cfg) {
 953                 pbl = priv->plat->dma_cfg->pbl;
 954                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
 955                 mixed_burst = priv->plat->dma_cfg->mixed_burst;
 956                 burst_len = priv->plat->dma_cfg->burst_len;
 957         }
 958
 959         return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst,
 960                                    burst_len, priv->dma_tx_phy,
 961                                    priv->dma_rx_phy);
 962 }
 963
 964 /**
 965  * stmmac_tx_timer:
 966  * @data: data pointer
 967  * Description:
 968  * This is the timer handler to directly invoke the stmmac_tx_clean.
 969  */
 970 static void stmmac_tx_timer(unsigned long data)
 971 {
 972         struct stmmac_priv *priv = (struct stmmac_priv *)data;
 973
 974         stmmac_tx_clean(priv);
 975 }
 976
 977 /**
 978  * stmmac_tx_timer:
 979  * @priv: private data structure
 980  * Description:
 981  * This inits the transmit coalesce parameters: i.e. timer rate,
 982  * timer handler and default threshold used for enabling the
 983  * interrupt on completion bit.
 984  */
 985 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv)
 986 {
 987         priv->tx_coal_frames = STMMAC_TX_FRAMES;
 988         priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
 989         init_timer(&priv->txtimer);
 990         priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer);
 991         priv->txtimer.data = (unsigned long)priv;
 992         priv->txtimer.function = stmmac_tx_timer;
 993         add_timer(&priv->txtimer);
 994 }
 995
 996 /**
 997  *  stmmac_open - open entry point of the driver
 998  *  @dev : pointer to the device structure.
 999  *  Description:
1000  *  This function is the open entry point of the driver.
1001  *  Return value:
1002  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1003  *  file on failure.
1004  */
1005 static int stmmac_open(struct net_device *dev)
1006 {
1007         struct stmmac_priv *priv = netdev_priv(dev);
1008         int ret;
1009
1010         clk_prepare_enable(priv->stmmac_clk);
1011
1012         stmmac_check_ether_addr(priv);
1013
1014         ret = stmmac_init_phy(dev);
1015         if (unlikely(ret)) {
1016                 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret);
1017                 goto open_error;
1018         }
1019
1020         /* Create and initialize the TX/RX descriptors chains. */
1021         priv->dma_tx_size = STMMAC_ALIGN(dma_txsize);
1022         priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize);
1023         priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
1024         init_dma_desc_rings(dev);
1025
1026         /* DMA initialization and SW reset */
1027         ret = stmmac_init_dma_engine(priv);
1028         if (ret < 0) {
1029                 pr_err("%s: DMA initialization failed\n", __func__);
1030                 goto open_error;
1031         }
1032
1033         /* Copy the MAC addr into the HW  */
1034         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1035
1036         /* If required, perform hw setup of the bus. */
1037         if (priv->plat->bus_setup)
1038                 priv->plat->bus_setup(priv->ioaddr);
1039
1040         /* Initialize the MAC Core */
1041         priv->hw->mac->core_init(priv->ioaddr);
1042
1043         /* Request the IRQ lines */
1044         ret = request_irq(dev->irq, stmmac_interrupt,
1045                          IRQF_SHARED, dev->name, dev);
1046         if (unlikely(ret < 0)) {
1047                 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n",
1048                        __func__, dev->irq, ret);
1049                 goto open_error;
1050         }
1051
1052         /* Request the Wake IRQ in case of another line is used for WoL */
1053         if (priv->wol_irq != dev->irq) {
1054                 ret = request_irq(priv->wol_irq, stmmac_interrupt,
1055                                   IRQF_SHARED, dev->name, dev);
1056                 if (unlikely(ret < 0)) {
1057                         pr_err("%s: ERROR: allocating the ext WoL IRQ %d "
1058                                "(error: %d)\n", __func__, priv->wol_irq, ret);
1059                         goto open_error_wolirq;
1060                 }
1061         }
1062
1063         /* Request the IRQ lines */
1064         if (priv->lpi_irq != -ENXIO) {
1065                 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
1066                                   dev->name, dev);
1067                 if (unlikely(ret < 0)) {
1068                         pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1069                                __func__, priv->lpi_irq, ret);
1070                         goto open_error_lpiirq;
1071                 }
1072         }
1073
1074         /* Enable the MAC Rx/Tx */
1075         stmmac_set_mac(priv->ioaddr, true);
1076
1077         /* Set the HW DMA mode and the COE */
1078         stmmac_dma_operation_mode(priv);
1079
1080         /* Extra statistics */
1081         memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
1082         priv->xstats.threshold = tc;
1083
1084         stmmac_mmc_setup(priv);
1085
1086 #ifdef CONFIG_STMMAC_DEBUG_FS
1087         ret = stmmac_init_fs(dev);
1088         if (ret < 0)
1089                 pr_warning("%s: failed debugFS registration\n", __func__);
1090 #endif
1091         /* Start the ball rolling... */
1092         DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1093         priv->hw->dma->start_tx(priv->ioaddr);
1094         priv->hw->dma->start_rx(priv->ioaddr);
1095
1096         /* Dump DMA/MAC registers */
1097         if (netif_msg_hw(priv)) {
1098                 priv->hw->mac->dump_regs(priv->ioaddr);
1099                 priv->hw->dma->dump_regs(priv->ioaddr);
1100         }
1101
1102         if (priv->phydev)
1103                 phy_start(priv->phydev);
1104
1105         priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS_TIMER;
1106         priv->eee_enabled = stmmac_eee_init(priv);
1107
1108         stmmac_init_tx_coalesce(priv);
1109
1110         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1111                 priv->rx_riwt = MAX_DMA_RIWT;
1112                 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT);
1113         }
1114
1115         napi_enable(&priv->napi);
1116         netif_start_queue(dev);
1117
1118         return 0;
1119
1120 open_error_lpiirq:
1121         if (priv->wol_irq != dev->irq)
1122                 free_irq(priv->wol_irq, dev);
1123
1124 open_error_wolirq:
1125         free_irq(dev->irq, dev);
1126
1127 open_error:
1128         if (priv->phydev)
1129                 phy_disconnect(priv->phydev);
1130
1131         clk_disable_unprepare(priv->stmmac_clk);
1132
1133         return ret;
1134 }
1135
1136 /**
1137  *  stmmac_release - close entry point of the driver
1138  *  @dev : device pointer.
1139  *  Description:
1140  *  This is the stop entry point of the driver.
1141  */
1142 static int stmmac_release(struct net_device *dev)
1143 {
1144         struct stmmac_priv *priv = netdev_priv(dev);
1145
1146         if (priv->eee_enabled)
1147                 del_timer_sync(&priv->eee_ctrl_timer);
1148
1149         /* Stop and disconnect the PHY */
1150         if (priv->phydev) {
1151                 phy_stop(priv->phydev);
1152                 phy_disconnect(priv->phydev);
1153                 priv->phydev = NULL;
1154         }
1155
1156         netif_stop_queue(dev);
1157
1158         napi_disable(&priv->napi);
1159
1160         del_timer_sync(&priv->txtimer);
1161
1162         /* Free the IRQ lines */
1163         free_irq(dev->irq, dev);
1164         if (priv->wol_irq != dev->irq)
1165                 free_irq(priv->wol_irq, dev);
1166         if (priv->lpi_irq != -ENXIO)
1167                 free_irq(priv->lpi_irq, dev);
1168
1169         /* Stop TX/RX DMA and clear the descriptors */
1170         priv->hw->dma->stop_tx(priv->ioaddr);
1171         priv->hw->dma->stop_rx(priv->ioaddr);
1172
1173         /* Release and free the Rx/Tx resources */
1174         free_dma_desc_resources(priv);
1175
1176         /* Disable the MAC Rx/Tx */
1177         stmmac_set_mac(priv->ioaddr, false);
1178
1179         netif_carrier_off(dev);
1180
1181 #ifdef CONFIG_STMMAC_DEBUG_FS
1182         stmmac_exit_fs();
1183 #endif
1184         clk_disable_unprepare(priv->stmmac_clk);
1185
1186         return 0;
1187 }
1188
1189 /**
1190  *  stmmac_xmit:
1191  *  @skb : the socket buffer
1192  *  @dev : device pointer
1193  *  Description : Tx entry point of the driver.
1194  */
1195 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1196 {
1197         struct stmmac_priv *priv = netdev_priv(dev);
1198         unsigned int txsize = priv->dma_tx_size;
1199         unsigned int entry;
1200         int i, csum_insertion = 0;
1201         int nfrags = skb_shinfo(skb)->nr_frags;
1202         struct dma_desc *desc, *first;
1203         unsigned int nopaged_len = skb_headlen(skb);
1204
1205         if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) {
1206                 if (!netif_queue_stopped(dev)) {
1207                         netif_stop_queue(dev);
1208                         /* This is a hard error, log it. */
1209                         pr_err("%s: BUG! Tx Ring full when queue awake\n",
1210                                 __func__);
1211                 }
1212                 return NETDEV_TX_BUSY;
1213         }
1214
1215         spin_lock(&priv->tx_lock);
1216
1217         if (priv->tx_path_in_lpi_mode)
1218                 stmmac_disable_eee_mode(priv);
1219
1220         entry = priv->cur_tx % txsize;
1221
1222 #ifdef STMMAC_XMIT_DEBUG
1223         if ((skb->len > ETH_FRAME_LEN) || nfrags)
1224                 pr_debug("stmmac xmit: [entry %d]\n"
1225                          "\tskb addr %p - len: %d - nopaged_len: %d\n"
1226                          "\tn_frags: %d - ip_summed: %d - %s gso\n"
1227                          "\ttx_count_frames %d\n", entry,
1228                          skb, skb->len, nopaged_len, nfrags, skb->ip_summed,
1229                          !skb_is_gso(skb) ? "isn't" : "is",
1230                          priv->tx_count_frames);
1231 #endif
1232
1233         csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
1234
1235         desc = priv->dma_tx + entry;
1236         first = desc;
1237
1238 #ifdef STMMAC_XMIT_DEBUG
1239         if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN))
1240                 pr_debug("\tskb len: %d, nopaged_len: %d,\n"
1241                          "\t\tn_frags: %d, ip_summed: %d\n",
1242                          skb->len, nopaged_len, nfrags, skb->ip_summed);
1243 #endif
1244         priv->tx_skbuff[entry] = skb;
1245
1246         if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) {
1247                 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion);
1248                 desc = priv->dma_tx + entry;
1249         } else {
1250                 desc->des2 = dma_map_single(priv->device, skb->data,
1251                                         nopaged_len, DMA_TO_DEVICE);
1252                 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1253                                                 csum_insertion);
1254         }
1255
1256         for (i = 0; i < nfrags; i++) {
1257                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1258                 int len = skb_frag_size(frag);
1259
1260                 entry = (++priv->cur_tx) % txsize;
1261                 desc = priv->dma_tx + entry;
1262
1263                 TX_DBG("\t[entry %d] segment len: %d\n", entry, len);
1264                 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len,
1265                                               DMA_TO_DEVICE);
1266                 priv->tx_skbuff[entry] = NULL;
1267                 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1268                 wmb();
1269                 priv->hw->desc->set_tx_owner(desc);
1270                 wmb();
1271         }
1272
1273         /* Finalize the latest segment. */
1274         priv->hw->desc->close_tx_desc(desc);
1275
1276         wmb();
1277         /* According to the coalesce parameter the IC bit for the latest
1278          * segment could be reset and the timer re-started to invoke the
1279          * stmmac_tx function. This approach takes care about the fragments.
1280          */
1281         priv->tx_count_frames += nfrags + 1;
1282         if (priv->tx_coal_frames > priv->tx_count_frames) {
1283                 priv->hw->desc->clear_tx_ic(desc);
1284                 priv->xstats.tx_reset_ic_bit++;
1285                 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry,
1286                        priv->tx_count_frames);
1287                 mod_timer(&priv->txtimer,
1288                           STMMAC_COAL_TIMER(priv->tx_coal_timer));
1289         } else
1290                 priv->tx_count_frames = 0;
1291
1292         /* To avoid raise condition */
1293         priv->hw->desc->set_tx_owner(first);
1294         wmb();
1295
1296         priv->cur_tx++;
1297
1298 #ifdef STMMAC_XMIT_DEBUG
1299         if (netif_msg_pktdata(priv)) {
1300                 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, "
1301                        "first=%p, nfrags=%d\n",
1302                        (priv->cur_tx % txsize), (priv->dirty_tx % txsize),
1303                        entry, first, nfrags);
1304                 display_ring(priv->dma_tx, txsize);
1305                 pr_info(">>> frame to be transmitted: ");
1306                 print_pkt(skb->data, skb->len);
1307         }
1308 #endif
1309         if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) {
1310                 TX_DBG("%s: stop transmitted packets\n", __func__);
1311                 netif_stop_queue(dev);
1312         }
1313
1314         dev->stats.tx_bytes += skb->len;
1315
1316         skb_tx_timestamp(skb);
1317
1318         priv->hw->dma->enable_dma_transmission(priv->ioaddr);
1319
1320         spin_unlock(&priv->tx_lock);
1321
1322         return NETDEV_TX_OK;
1323 }
1324
1325 static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1326 {
1327         unsigned int rxsize = priv->dma_rx_size;
1328         int bfsize = priv->dma_buf_sz;
1329         struct dma_desc *p = priv->dma_rx;
1330
1331         for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) {
1332                 unsigned int entry = priv->dirty_rx % rxsize;
1333                 if (likely(priv->rx_skbuff[entry] == NULL)) {
1334                         struct sk_buff *skb;
1335
1336                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1337
1338                         if (unlikely(skb == NULL))
1339                                 break;
1340
1341                         priv->rx_skbuff[entry] = skb;
1342                         priv->rx_skbuff_dma[entry] =
1343                             dma_map_single(priv->device, skb->data, bfsize,
1344                                            DMA_FROM_DEVICE);
1345
1346                         (p + entry)->des2 = priv->rx_skbuff_dma[entry];
1347
1348                         if (unlikely(priv->plat->has_gmac))
1349                                 priv->hw->ring->refill_desc3(bfsize, p + entry);
1350
1351                         RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1352                 }
1353                 wmb();
1354                 priv->hw->desc->set_rx_owner(p + entry);
1355                 wmb();
1356         }
1357 }
1358
1359 static int stmmac_rx(struct stmmac_priv *priv, int limit)
1360 {
1361         unsigned int rxsize = priv->dma_rx_size;
1362         unsigned int entry = priv->cur_rx % rxsize;
1363         unsigned int next_entry;
1364         unsigned int count = 0;
1365         struct dma_desc *p = priv->dma_rx + entry;
1366         struct dma_desc *p_next;
1367
1368 #ifdef STMMAC_RX_DEBUG
1369         if (netif_msg_hw(priv)) {
1370                 pr_debug(">>> stmmac_rx: descriptor ring:\n");
1371                 display_ring(priv->dma_rx, rxsize);
1372         }
1373 #endif
1374         while (!priv->hw->desc->get_rx_owner(p)) {
1375                 int status;
1376
1377                 if (count >= limit)
1378                         break;
1379
1380                 count++;
1381
1382                 next_entry = (++priv->cur_rx) % rxsize;
1383                 p_next = priv->dma_rx + next_entry;
1384                 prefetch(p_next);
1385
1386                 /* read the status of the incoming frame */
1387                 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1388                                                     &priv->xstats, p));
1389                 if (unlikely(status == discard_frame))
1390                         priv->dev->stats.rx_errors++;
1391                 else {
1392                         struct sk_buff *skb;
1393                         int frame_len;
1394
1395                         frame_len = priv->hw->desc->get_rx_frame_len(p,
1396                                         priv->plat->rx_coe);
1397                         /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
1398                          * Type frames (LLC/LLC-SNAP) */
1399                         if (unlikely(status != llc_snap))
1400                                 frame_len -= ETH_FCS_LEN;
1401 #ifdef STMMAC_RX_DEBUG
1402                         if (frame_len > ETH_FRAME_LEN)
1403                                 pr_debug("\tRX frame size %d, COE status: %d\n",
1404                                         frame_len, status);
1405
1406                         if (netif_msg_hw(priv))
1407                                 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n",
1408                                         p, entry, p->des2);
1409 #endif
1410                         skb = priv->rx_skbuff[entry];
1411                         if (unlikely(!skb)) {
1412                                 pr_err("%s: Inconsistent Rx descriptor chain\n",
1413                                         priv->dev->name);
1414                                 priv->dev->stats.rx_dropped++;
1415                                 break;
1416                         }
1417                         prefetch(skb->data - NET_IP_ALIGN);
1418                         priv->rx_skbuff[entry] = NULL;
1419
1420                         skb_put(skb, frame_len);
1421                         dma_unmap_single(priv->device,
1422                                          priv->rx_skbuff_dma[entry],
1423                                          priv->dma_buf_sz, DMA_FROM_DEVICE);
1424 #ifdef STMMAC_RX_DEBUG
1425                         if (netif_msg_pktdata(priv)) {
1426                                 pr_info(" frame received (%dbytes)", frame_len);
1427                                 print_pkt(skb->data, frame_len);
1428                         }
1429 #endif
1430                         skb->protocol = eth_type_trans(skb, priv->dev);
1431
1432                         if (unlikely(!priv->plat->rx_coe))
1433                                 skb_checksum_none_assert(skb);
1434                         else
1435                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1436
1437                         napi_gro_receive(&priv->napi, skb);
1438
1439                         priv->dev->stats.rx_packets++;
1440                         priv->dev->stats.rx_bytes += frame_len;
1441                 }
1442                 entry = next_entry;
1443                 p = p_next;     /* use prefetched values */
1444         }
1445
1446         stmmac_rx_refill(priv);
1447
1448         priv->xstats.rx_pkt_n += count;
1449
1450         return count;
1451 }
1452
1453 /**
1454  *  stmmac_poll - stmmac poll method (NAPI)
1455  *  @napi : pointer to the napi structure.
1456  *  @budget : maximum number of packets that the current CPU can receive from
1457  *            all interfaces.
1458  *  Description :
1459  *  To look at the incoming frames and clear the tx resources.
1460  */
1461 static int stmmac_poll(struct napi_struct *napi, int budget)
1462 {
1463         struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi);
1464         int work_done = 0;
1465
1466         priv->xstats.napi_poll++;
1467         stmmac_tx_clean(priv);
1468
1469         work_done = stmmac_rx(priv, budget);
1470         if (work_done < budget) {
1471                 napi_complete(napi);
1472                 stmmac_enable_dma_irq(priv);
1473         }
1474         return work_done;
1475 }
1476
1477 /**
1478  *  stmmac_tx_timeout
1479  *  @dev : Pointer to net device structure
1480  *  Description: this function is called when a packet transmission fails to
1481  *   complete within a reasonable time. The driver will mark the error in the
1482  *   netdev structure and arrange for the device to be reset to a sane state
1483  *   in order to transmit a new packet.
1484  */
1485 static void stmmac_tx_timeout(struct net_device *dev)
1486 {
1487         struct stmmac_priv *priv = netdev_priv(dev);
1488
1489         /* Clear Tx resources and restart transmitting again */
1490         stmmac_tx_err(priv);
1491 }
1492
1493 /* Configuration changes (passed on by ifconfig) */
1494 static int stmmac_config(struct net_device *dev, struct ifmap *map)
1495 {
1496         if (dev->flags & IFF_UP)        /* can't act on a running interface */
1497                 return -EBUSY;
1498
1499         /* Don't allow changing the I/O address */
1500         if (map->base_addr != dev->base_addr) {
1501                 pr_warning("%s: can't change I/O address\n", dev->name);
1502                 return -EOPNOTSUPP;
1503         }
1504
1505         /* Don't allow changing the IRQ */
1506         if (map->irq != dev->irq) {
1507                 pr_warning("%s: can't change IRQ number %d\n",
1508                        dev->name, dev->irq);
1509                 return -EOPNOTSUPP;
1510         }
1511
1512         /* ignore other fields */
1513         return 0;
1514 }
1515
1516 /**
1517  *  stmmac_set_rx_mode - entry point for multicast addressing
1518  *  @dev : pointer to the device structure
1519  *  Description:
1520  *  This function is a driver entry point which gets called by the kernel
1521  *  whenever multicast addresses must be enabled/disabled.
1522  *  Return value:
1523  *  void.
1524  */
1525 static void stmmac_set_rx_mode(struct net_device *dev)
1526 {
1527         struct stmmac_priv *priv = netdev_priv(dev);
1528
1529         spin_lock(&priv->lock);
1530         priv->hw->mac->set_filter(dev, priv->synopsys_id);
1531         spin_unlock(&priv->lock);
1532 }
1533
1534 /**
1535  *  stmmac_change_mtu - entry point to change MTU size for the device.
1536  *  @dev : device pointer.
1537  *  @new_mtu : the new MTU size for the device.
1538  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1539  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1540  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1541  *  Return value:
1542  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1543  *  file on failure.
1544  */
1545 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
1546 {
1547         struct stmmac_priv *priv = netdev_priv(dev);
1548         int max_mtu;
1549
1550         if (netif_running(dev)) {
1551                 pr_err("%s: must be stopped to change its MTU\n", dev->name);
1552                 return -EBUSY;
1553         }
1554
1555         if (priv->plat->enh_desc)
1556                 max_mtu = JUMBO_LEN;
1557         else
1558                 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
1559
1560         if ((new_mtu < 46) || (new_mtu > max_mtu)) {
1561                 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu);
1562                 return -EINVAL;
1563         }
1564
1565         dev->mtu = new_mtu;
1566         netdev_update_features(dev);
1567
1568         return 0;
1569 }
1570
1571 static netdev_features_t stmmac_fix_features(struct net_device *dev,
1572         netdev_features_t features)
1573 {
1574         struct stmmac_priv *priv = netdev_priv(dev);
1575
1576         if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
1577                 features &= ~NETIF_F_RXCSUM;
1578         else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1)
1579                 features &= ~NETIF_F_IPV6_CSUM;
1580         if (!priv->plat->tx_coe)
1581                 features &= ~NETIF_F_ALL_CSUM;
1582
1583         /* Some GMAC devices have a bugged Jumbo frame support that
1584          * needs to have the Tx COE disabled for oversized frames
1585          * (due to limited buffer sizes). In this case we disable
1586          * the TX csum insertionin the TDES and not use SF. */
1587         if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
1588                 features &= ~NETIF_F_ALL_CSUM;
1589
1590         return features;
1591 }
1592
1593 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1594 {
1595         struct net_device *dev = (struct net_device *)dev_id;
1596         struct stmmac_priv *priv = netdev_priv(dev);
1597
1598         if (unlikely(!dev)) {
1599                 pr_err("%s: invalid dev pointer\n", __func__);
1600                 return IRQ_NONE;
1601         }
1602
1603         /* To handle GMAC own interrupts */
1604         if (priv->plat->has_gmac) {
1605                 int status = priv->hw->mac->host_irq_status((void __iomem *)
1606                                                             dev->base_addr);
1607                 if (unlikely(status)) {
1608                         if (status & core_mmc_tx_irq)
1609                                 priv->xstats.mmc_tx_irq_n++;
1610                         if (status & core_mmc_rx_irq)
1611                                 priv->xstats.mmc_rx_irq_n++;
1612                         if (status & core_mmc_rx_csum_offload_irq)
1613                                 priv->xstats.mmc_rx_csum_offload_irq_n++;
1614                         if (status & core_irq_receive_pmt_irq)
1615                                 priv->xstats.irq_receive_pmt_irq_n++;
1616
1617                         /* For LPI we need to save the tx status */
1618                         if (status & core_irq_tx_path_in_lpi_mode) {
1619                                 priv->xstats.irq_tx_path_in_lpi_mode_n++;
1620                                 priv->tx_path_in_lpi_mode = true;
1621                         }
1622                         if (status & core_irq_tx_path_exit_lpi_mode) {
1623                                 priv->xstats.irq_tx_path_exit_lpi_mode_n++;
1624                                 priv->tx_path_in_lpi_mode = false;
1625                         }
1626                         if (status & core_irq_rx_path_in_lpi_mode)
1627                                 priv->xstats.irq_rx_path_in_lpi_mode_n++;
1628                         if (status & core_irq_rx_path_exit_lpi_mode)
1629                                 priv->xstats.irq_rx_path_exit_lpi_mode_n++;
1630                 }
1631         }
1632
1633         /* To handle DMA interrupts */
1634         stmmac_dma_interrupt(priv);
1635
1636         return IRQ_HANDLED;
1637 }
1638
1639 #ifdef CONFIG_NET_POLL_CONTROLLER
1640 /* Polling receive - used by NETCONSOLE and other diagnostic tools
1641  * to allow network I/O with interrupts disabled. */
1642 static void stmmac_poll_controller(struct net_device *dev)
1643 {
1644         disable_irq(dev->irq);
1645         stmmac_interrupt(dev->irq, dev);
1646         enable_irq(dev->irq);
1647 }
1648 #endif
1649
1650 /**
1651  *  stmmac_ioctl - Entry point for the Ioctl
1652  *  @dev: Device pointer.
1653  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1654  *  a proprietary structure used to pass information to the driver.
1655  *  @cmd: IOCTL command
1656  *  Description:
1657  *  Currently there are no special functionality supported in IOCTL, just the
1658  *  phy_mii_ioctl(...) can be invoked.
1659  */
1660 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1661 {
1662         struct stmmac_priv *priv = netdev_priv(dev);
1663         int ret;
1664
1665         if (!netif_running(dev))
1666                 return -EINVAL;
1667
1668         if (!priv->phydev)
1669                 return -EINVAL;
1670
1671         ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1672
1673         return ret;
1674 }
1675
1676 #ifdef CONFIG_STMMAC_DEBUG_FS
1677 static struct dentry *stmmac_fs_dir;
1678 static struct dentry *stmmac_rings_status;
1679 static struct dentry *stmmac_dma_cap;
1680
1681 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v)
1682 {
1683         struct tmp_s {
1684                 u64 a;
1685                 unsigned int b;
1686                 unsigned int c;
1687         };
1688         int i;
1689         struct net_device *dev = seq->private;
1690         struct stmmac_priv *priv = netdev_priv(dev);
1691
1692         seq_printf(seq, "=======================\n");
1693         seq_printf(seq, " RX descriptor ring\n");
1694         seq_printf(seq, "=======================\n");
1695
1696         for (i = 0; i < priv->dma_rx_size; i++) {
1697                 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i);
1698                 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1699                            i, (unsigned int)(x->a),
1700                            (unsigned int)((x->a) >> 32), x->b, x->c);
1701                 seq_printf(seq, "\n");
1702         }
1703
1704         seq_printf(seq, "\n");
1705         seq_printf(seq, "=======================\n");
1706         seq_printf(seq, "  TX descriptor ring\n");
1707         seq_printf(seq, "=======================\n");
1708
1709         for (i = 0; i < priv->dma_tx_size; i++) {
1710                 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i);
1711                 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x",
1712                            i, (unsigned int)(x->a),
1713                            (unsigned int)((x->a) >> 32), x->b, x->c);
1714                 seq_printf(seq, "\n");
1715         }
1716
1717         return 0;
1718 }
1719
1720 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file)
1721 {
1722         return single_open(file, stmmac_sysfs_ring_read, inode->i_private);
1723 }
1724
1725 static const struct file_operations stmmac_rings_status_fops = {
1726         .owner = THIS_MODULE,
1727         .open = stmmac_sysfs_ring_open,
1728         .read = seq_read,
1729         .llseek = seq_lseek,
1730         .release = single_release,
1731 };
1732
1733 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v)
1734 {
1735         struct net_device *dev = seq->private;
1736         struct stmmac_priv *priv = netdev_priv(dev);
1737
1738         if (!priv->hw_cap_support) {
1739                 seq_printf(seq, "DMA HW features not supported\n");
1740                 return 0;
1741         }
1742
1743         seq_printf(seq, "==============================\n");
1744         seq_printf(seq, "\tDMA HW features\n");
1745         seq_printf(seq, "==============================\n");
1746
1747         seq_printf(seq, "\t10/100 Mbps %s\n",
1748                    (priv->dma_cap.mbps_10_100) ? "Y" : "N");
1749         seq_printf(seq, "\t1000 Mbps %s\n",
1750                    (priv->dma_cap.mbps_1000) ? "Y" : "N");
1751         seq_printf(seq, "\tHalf duple %s\n",
1752                    (priv->dma_cap.half_duplex) ? "Y" : "N");
1753         seq_printf(seq, "\tHash Filter: %s\n",
1754                    (priv->dma_cap.hash_filter) ? "Y" : "N");
1755         seq_printf(seq, "\tMultiple MAC address registers: %s\n",
1756                    (priv->dma_cap.multi_addr) ? "Y" : "N");
1757         seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n",
1758                    (priv->dma_cap.pcs) ? "Y" : "N");
1759         seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
1760                    (priv->dma_cap.sma_mdio) ? "Y" : "N");
1761         seq_printf(seq, "\tPMT Remote wake up: %s\n",
1762                    (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
1763         seq_printf(seq, "\tPMT Magic Frame: %s\n",
1764                    (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
1765         seq_printf(seq, "\tRMON module: %s\n",
1766                    (priv->dma_cap.rmon) ? "Y" : "N");
1767         seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
1768                    (priv->dma_cap.time_stamp) ? "Y" : "N");
1769         seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n",
1770                    (priv->dma_cap.atime_stamp) ? "Y" : "N");
1771         seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n",
1772                    (priv->dma_cap.eee) ? "Y" : "N");
1773         seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
1774         seq_printf(seq, "\tChecksum Offload in TX: %s\n",
1775                    (priv->dma_cap.tx_coe) ? "Y" : "N");
1776         seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
1777                    (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
1778         seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
1779                    (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
1780         seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
1781                    (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
1782         seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
1783                    priv->dma_cap.number_rx_channel);
1784         seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
1785                    priv->dma_cap.number_tx_channel);
1786         seq_printf(seq, "\tEnhanced descriptors: %s\n",
1787                    (priv->dma_cap.enh_desc) ? "Y" : "N");
1788
1789         return 0;
1790 }
1791
1792 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file)
1793 {
1794         return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private);
1795 }
1796
1797 static const struct file_operations stmmac_dma_cap_fops = {
1798         .owner = THIS_MODULE,
1799         .open = stmmac_sysfs_dma_cap_open,
1800         .read = seq_read,
1801         .llseek = seq_lseek,
1802         .release = single_release,
1803 };
1804
1805 static int stmmac_init_fs(struct net_device *dev)
1806 {
1807         /* Create debugfs entries */
1808         stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
1809
1810         if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
1811                 pr_err("ERROR %s, debugfs create directory failed\n",
1812                        STMMAC_RESOURCE_NAME);
1813
1814                 return -ENOMEM;
1815         }
1816
1817         /* Entry to report DMA RX/TX rings */
1818         stmmac_rings_status = debugfs_create_file("descriptors_status",
1819                                            S_IRUGO, stmmac_fs_dir, dev,
1820                                            &stmmac_rings_status_fops);
1821
1822         if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
1823                 pr_info("ERROR creating stmmac ring debugfs file\n");
1824                 debugfs_remove(stmmac_fs_dir);
1825
1826                 return -ENOMEM;
1827         }
1828
1829         /* Entry to report the DMA HW features */
1830         stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
1831                                              dev, &stmmac_dma_cap_fops);
1832
1833         if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
1834                 pr_info("ERROR creating stmmac MMC debugfs file\n");
1835                 debugfs_remove(stmmac_rings_status);
1836                 debugfs_remove(stmmac_fs_dir);
1837
1838                 return -ENOMEM;
1839         }
1840
1841         return 0;
1842 }
1843
1844 static void stmmac_exit_fs(void)
1845 {
1846         debugfs_remove(stmmac_rings_status);
1847         debugfs_remove(stmmac_dma_cap);
1848         debugfs_remove(stmmac_fs_dir);
1849 }
1850 #endif /* CONFIG_STMMAC_DEBUG_FS */
1851
1852 static const struct net_device_ops stmmac_netdev_ops = {
1853         .ndo_open = stmmac_open,
1854         .ndo_start_xmit = stmmac_xmit,
1855         .ndo_stop = stmmac_release,
1856         .ndo_change_mtu = stmmac_change_mtu,
1857         .ndo_fix_features = stmmac_fix_features,
1858         .ndo_set_rx_mode = stmmac_set_rx_mode,
1859         .ndo_tx_timeout = stmmac_tx_timeout,
1860         .ndo_do_ioctl = stmmac_ioctl,
1861         .ndo_set_config = stmmac_config,
1862 #ifdef CONFIG_NET_POLL_CONTROLLER
1863         .ndo_poll_controller = stmmac_poll_controller,
1864 #endif
1865         .ndo_set_mac_address = eth_mac_addr,
1866 };
1867
1868 /**
1869  *  stmmac_hw_init - Init the MAC device
1870  *  @priv : pointer to the private device structure.
1871  *  Description: this function detects which MAC device
1872  *  (GMAC/MAC10-100) has to attached, checks the HW capability
1873  *  (if supported) and sets the driver's features (for example
1874  *  to use the ring or chaine mode or support the normal/enh
1875  *  descriptor structure).
1876  */
1877 static int stmmac_hw_init(struct stmmac_priv *priv)
1878 {
1879         int ret = 0;
1880         struct mac_device_info *mac;
1881
1882         /* Identify the MAC HW device */
1883         if (priv->plat->has_gmac) {
1884                 priv->dev->priv_flags |= IFF_UNICAST_FLT;
1885                 mac = dwmac1000_setup(priv->ioaddr);
1886         } else {
1887                 mac = dwmac100_setup(priv->ioaddr);
1888         }
1889         if (!mac)
1890                 return -ENOMEM;
1891
1892         priv->hw = mac;
1893
1894         /* To use the chained or ring mode */
1895         priv->hw->ring = &ring_mode_ops;
1896
1897         /* Get and dump the chip ID */
1898         priv->synopsys_id = stmmac_get_synopsys_id(priv);
1899
1900         /* Get the HW capability (new GMAC newer than 3.50a) */
1901         priv->hw_cap_support = stmmac_get_hw_features(priv);
1902         if (priv->hw_cap_support) {
1903                 pr_info(" DMA HW capability register supported");
1904
1905                 /* We can override some gmac/dma configuration fields: e.g.
1906                  * enh_desc, tx_coe (e.g. that are passed through the
1907                  * platform) with the values from the HW capability
1908                  * register (if supported).
1909                  */
1910                 priv->plat->enh_desc = priv->dma_cap.enh_desc;
1911                 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
1912
1913                 priv->plat->tx_coe = priv->dma_cap.tx_coe;
1914
1915                 if (priv->dma_cap.rx_coe_type2)
1916                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
1917                 else if (priv->dma_cap.rx_coe_type1)
1918                         priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
1919
1920         } else
1921                 pr_info(" No HW DMA feature register supported");
1922
1923         /* Select the enhnaced/normal descriptor structures */
1924         stmmac_selec_desc_mode(priv);
1925
1926         /* Enable the IPC (Checksum Offload) and check if the feature has been
1927          * enabled during the core configuration. */
1928         ret = priv->hw->mac->rx_ipc(priv->ioaddr);
1929         if (!ret) {
1930                 pr_warning(" RX IPC Checksum Offload not configured.\n");
1931                 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
1932         }
1933
1934         if (priv->plat->rx_coe)
1935                 pr_info(" RX Checksum Offload Engine supported (type %d)\n",
1936                         priv->plat->rx_coe);
1937         if (priv->plat->tx_coe)
1938                 pr_info(" TX Checksum insertion supported\n");
1939
1940         if (priv->plat->pmt) {
1941                 pr_info(" Wake-Up On Lan supported\n");
1942                 device_set_wakeup_capable(priv->device, 1);
1943         }
1944
1945         return ret;
1946 }
1947
1948 /**
1949  * stmmac_dvr_probe
1950  * @device: device pointer
1951  * @plat_dat: platform data pointer
1952  * @addr: iobase memory address
1953  * Description: this is the main probe function used to
1954  * call the alloc_etherdev, allocate the priv structure.
1955  */
1956 struct stmmac_priv *stmmac_dvr_probe(struct device *device,
1957                                      struct plat_stmmacenet_data *plat_dat,
1958                                      void __iomem *addr)
1959 {
1960         int ret = 0;
1961         struct net_device *ndev = NULL;
1962         struct stmmac_priv *priv;
1963
1964         ndev = alloc_etherdev(sizeof(struct stmmac_priv));
1965         if (!ndev)
1966                 return NULL;
1967
1968         SET_NETDEV_DEV(ndev, device);
1969
1970         priv = netdev_priv(ndev);
1971         priv->device = device;
1972         priv->dev = ndev;
1973
1974         ether_setup(ndev);
1975
1976         stmmac_set_ethtool_ops(ndev);
1977         priv->pause = pause;
1978         priv->plat = plat_dat;
1979         priv->ioaddr = addr;
1980         priv->dev->base_addr = (unsigned long)addr;
1981
1982         /* Verify driver arguments */
1983         stmmac_verify_args();
1984
1985         /* Override with kernel parameters if supplied XXX CRS XXX
1986          * this needs to have multiple instances */
1987         if ((phyaddr >= 0) && (phyaddr <= 31))
1988                 priv->plat->phy_addr = phyaddr;
1989
1990         /* Init MAC and get the capabilities */
1991         stmmac_hw_init(priv);
1992
1993         ndev->netdev_ops = &stmmac_netdev_ops;
1994
1995         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
1996                             NETIF_F_RXCSUM;
1997         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
1998         ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
1999 #ifdef STMMAC_VLAN_TAG_USED
2000         /* Both mac100 and gmac support receive VLAN tag detection */
2001         ndev->features |= NETIF_F_HW_VLAN_RX;
2002 #endif
2003         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2004
2005         if (flow_ctrl)
2006                 priv->flow_ctrl = FLOW_AUTO;    /* RX/TX pause on */
2007
2008         /* Rx Watchdog is available in the COREs newer than the 3.40.
2009          * In some case, for example on bugged HW this feature
2010          * has to be disable and this can be done by passing the
2011          * riwt_off field from the platform.
2012          */
2013         if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) {
2014                 priv->use_riwt = 1;
2015                 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n");
2016         }
2017
2018         netif_napi_add(ndev, &priv->napi, stmmac_poll, 64);
2019
2020         spin_lock_init(&priv->lock);
2021         spin_lock_init(&priv->tx_lock);
2022
2023         ret = register_netdev(ndev);
2024         if (ret) {
2025                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2026                 goto error_netdev_register;
2027         }
2028
2029         priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME);
2030         if (IS_ERR(priv->stmmac_clk)) {
2031                 pr_warning("%s: warning: cannot get CSR clock\n", __func__);
2032                 goto error_clk_get;
2033         }
2034
2035         /* If a specific clk_csr value is passed from the platform
2036          * this means that the CSR Clock Range selection cannot be
2037          * changed at run-time and it is fixed. Viceversa the driver'll try to
2038          * set the MDC clock dynamically according to the csr actual
2039          * clock input.
2040          */
2041         if (!priv->plat->clk_csr)
2042                 stmmac_clk_csr_set(priv);
2043         else
2044                 priv->clk_csr = priv->plat->clk_csr;
2045
2046         /* MDIO bus Registration */
2047         ret = stmmac_mdio_register(ndev);
2048         if (ret < 0) {
2049                 pr_debug("%s: MDIO bus (id: %d) registration failed",
2050                          __func__, priv->plat->bus_id);
2051                 goto error_mdio_register;
2052         }
2053
2054         return priv;
2055
2056 error_mdio_register:
2057         clk_put(priv->stmmac_clk);
2058 error_clk_get:
2059         unregister_netdev(ndev);
2060 error_netdev_register:
2061         netif_napi_del(&priv->napi);
2062         free_netdev(ndev);
2063
2064         return NULL;
2065 }
2066
2067 /**
2068  * stmmac_dvr_remove
2069  * @ndev: net device pointer
2070  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2071  * changes the link status, releases the DMA descriptor rings.
2072  */
2073 int stmmac_dvr_remove(struct net_device *ndev)
2074 {
2075         struct stmmac_priv *priv = netdev_priv(ndev);
2076
2077         pr_info("%s:\n\tremoving driver", __func__);
2078
2079         priv->hw->dma->stop_rx(priv->ioaddr);
2080         priv->hw->dma->stop_tx(priv->ioaddr);
2081
2082         stmmac_set_mac(priv->ioaddr, false);
2083         stmmac_mdio_unregister(ndev);
2084         netif_carrier_off(ndev);
2085         unregister_netdev(ndev);
2086         free_netdev(ndev);
2087
2088         return 0;
2089 }
2090
2091 #ifdef CONFIG_PM
2092 int stmmac_suspend(struct net_device *ndev)
2093 {
2094         struct stmmac_priv *priv = netdev_priv(ndev);
2095         int dis_ic = 0;
2096         unsigned long flags;
2097
2098         if (!ndev || !netif_running(ndev))
2099                 return 0;
2100
2101         if (priv->phydev)
2102                 phy_stop(priv->phydev);
2103
2104         spin_lock_irqsave(&priv->lock, flags);
2105
2106         netif_device_detach(ndev);
2107         netif_stop_queue(ndev);
2108
2109         if (priv->use_riwt)
2110                 dis_ic = 1;
2111
2112         napi_disable(&priv->napi);
2113
2114         /* Stop TX/RX DMA */
2115         priv->hw->dma->stop_tx(priv->ioaddr);
2116         priv->hw->dma->stop_rx(priv->ioaddr);
2117         /* Clear the Rx/Tx descriptors */
2118         priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
2119                                      dis_ic);
2120         priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
2121
2122         /* Enable Power down mode by programming the PMT regs */
2123         if (device_may_wakeup(priv->device))
2124                 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts);
2125         else {
2126                 stmmac_set_mac(priv->ioaddr, false);
2127                 /* Disable clock in case of PWM is off */
2128                 clk_disable_unprepare(priv->stmmac_clk);
2129         }
2130         spin_unlock_irqrestore(&priv->lock, flags);
2131         return 0;
2132 }
2133
2134 int stmmac_resume(struct net_device *ndev)
2135 {
2136         struct stmmac_priv *priv = netdev_priv(ndev);
2137         unsigned long flags;
2138
2139         if (!netif_running(ndev))
2140                 return 0;
2141
2142         spin_lock_irqsave(&priv->lock, flags);
2143
2144         /* Power Down bit, into the PM register, is cleared
2145          * automatically as soon as a magic packet or a Wake-up frame
2146          * is received. Anyway, it's better to manually clear
2147          * this bit because it can generate problems while resuming
2148          * from another devices (e.g. serial console). */
2149         if (device_may_wakeup(priv->device))
2150                 priv->hw->mac->pmt(priv->ioaddr, 0);
2151         else
2152                 /* enable the clk prevously disabled */
2153                 clk_prepare_enable(priv->stmmac_clk);
2154
2155         netif_device_attach(ndev);
2156
2157         /* Enable the MAC and DMA */
2158         stmmac_set_mac(priv->ioaddr, true);
2159         priv->hw->dma->start_tx(priv->ioaddr);
2160         priv->hw->dma->start_rx(priv->ioaddr);
2161
2162         napi_enable(&priv->napi);
2163
2164         netif_start_queue(ndev);
2165
2166         spin_unlock_irqrestore(&priv->lock, flags);
2167
2168         if (priv->phydev)
2169                 phy_start(priv->phydev);
2170
2171         return 0;
2172 }
2173
2174 int stmmac_freeze(struct net_device *ndev)
2175 {
2176         if (!ndev || !netif_running(ndev))
2177                 return 0;
2178
2179         return stmmac_release(ndev);
2180 }
2181
2182 int stmmac_restore(struct net_device *ndev)
2183 {
2184         if (!ndev || !netif_running(ndev))
2185                 return 0;
2186
2187         return stmmac_open(ndev);
2188 }
2189 #endif /* CONFIG_PM */
2190
2191 /* Driver can be configured w/ and w/ both PCI and Platf drivers
2192  * depending on the configuration selected.
2193  */
2194 static int __init stmmac_init(void)
2195 {
2196         int ret;
2197
2198         ret = stmmac_register_platform();
2199         if (ret)
2200                 goto err;
2201         ret = stmmac_register_pci();
2202         if (ret)
2203                 goto err_pci;
2204         return 0;
2205 err_pci:
2206         stmmac_unregister_platform();
2207 err:
2208         pr_err("stmmac: driver registration failed\n");
2209         return ret;
2210 }
2211
2212 static void __exit stmmac_exit(void)
2213 {
2214         stmmac_unregister_platform();
2215         stmmac_unregister_pci();
2216 }
2217
2218 module_init(stmmac_init);
2219 module_exit(stmmac_exit);
2220
2221 #ifndef MODULE
2222 static int __init stmmac_cmdline_opt(char *str)
2223 {
2224         char *opt;
2225
2226         if (!str || !*str)
2227                 return -EINVAL;
2228         while ((opt = strsep(&str, ",")) != NULL) {
2229                 if (!strncmp(opt, "debug:", 6)) {
2230                         if (kstrtoint(opt + 6, 0, &debug))
2231                                 goto err;
2232                 } else if (!strncmp(opt, "phyaddr:", 8)) {
2233                         if (kstrtoint(opt + 8, 0, &phyaddr))
2234                                 goto err;
2235                 } else if (!strncmp(opt, "dma_txsize:", 11)) {
2236                         if (kstrtoint(opt + 11, 0, &dma_txsize))
2237                                 goto err;
2238                 } else if (!strncmp(opt, "dma_rxsize:", 11)) {
2239                         if (kstrtoint(opt + 11, 0, &dma_rxsize))
2240                                 goto err;
2241                 } else if (!strncmp(opt, "buf_sz:", 7)) {
2242                         if (kstrtoint(opt + 7, 0, &buf_sz))
2243                                 goto err;
2244                 } else if (!strncmp(opt, "tc:", 3)) {
2245                         if (kstrtoint(opt + 3, 0, &tc))
2246                                 goto err;
2247                 } else if (!strncmp(opt, "watchdog:", 9)) {
2248                         if (kstrtoint(opt + 9, 0, &watchdog))
2249                                 goto err;
2250                 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
2251                         if (kstrtoint(opt + 10, 0, &flow_ctrl))
2252                                 goto err;
2253                 } else if (!strncmp(opt, "pause:", 6)) {
2254                         if (kstrtoint(opt + 6, 0, &pause))
2255                                 goto err;
2256                 } else if (!strncmp(opt, "eee_timer:", 6)) {
2257                         if (kstrtoint(opt + 10, 0, &eee_timer))
2258                                 goto err;
2259                 }
2260         }
2261         return 0;
2262
2263 err:
2264         pr_err("%s: ERROR broken module parameter conversion", __func__);
2265         return -EINVAL;
2266 }
2267
2268 __setup("stmmaceth=", stmmac_cmdline_opt);
2269 #endif
2270
2271 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
2272 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
2273 MODULE_LICENSE("GPL");