1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers.
4 ST Ethernet IPs are built around a Synopsys IP Core.
6 Copyright(C) 2007-2011 STMicroelectronics Ltd
9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
11 Documentation available at:
12 http://www.stlinux.com
14 https://bugzilla.stlinux.com/
15 *******************************************************************************/
17 #include <linux/clk.h>
18 #include <linux/kernel.h>
19 #include <linux/interrupt.h>
21 #include <linux/tcp.h>
22 #include <linux/skbuff.h>
23 #include <linux/ethtool.h>
24 #include <linux/if_ether.h>
25 #include <linux/crc32.h>
26 #include <linux/mii.h>
28 #include <linux/if_vlan.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/slab.h>
31 #include <linux/prefetch.h>
32 #include <linux/pinctrl/consumer.h>
33 #ifdef CONFIG_DEBUG_FS
34 #include <linux/debugfs.h>
35 #include <linux/seq_file.h>
36 #endif /* CONFIG_DEBUG_FS */
37 #include <linux/net_tstamp.h>
38 #include <linux/phylink.h>
39 #include <net/pkt_cls.h>
40 #include "stmmac_ptp.h"
42 #include <linux/reset.h>
43 #include <linux/of_mdio.h>
44 #include "dwmac1000.h"
48 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES)
49 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1)
51 /* Module parameters */
53 static int watchdog = TX_TIMEO;
54 module_param(watchdog, int, 0644);
55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)");
57 static int debug = -1;
58 module_param(debug, int, 0644);
59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
61 static int phyaddr = -1;
62 module_param(phyaddr, int, 0444);
63 MODULE_PARM_DESC(phyaddr, "Physical device address");
65 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4)
66 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4)
68 static int flow_ctrl = FLOW_AUTO;
69 module_param(flow_ctrl, int, 0644);
70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]");
72 static int pause = PAUSE_TIME;
73 module_param(pause, int, 0644);
74 MODULE_PARM_DESC(pause, "Flow Control Pause Time");
77 static int tc = TC_DEFAULT;
78 module_param(tc, int, 0644);
79 MODULE_PARM_DESC(tc, "DMA threshold control value");
81 #define DEFAULT_BUFSIZE 1536
82 static int buf_sz = DEFAULT_BUFSIZE;
83 module_param(buf_sz, int, 0644);
84 MODULE_PARM_DESC(buf_sz, "DMA buffer size");
86 #define STMMAC_RX_COPYBREAK 256
88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
89 NETIF_MSG_LINK | NETIF_MSG_IFUP |
90 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
92 #define STMMAC_DEFAULT_LPI_TIMER 1000
93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER;
94 module_param(eee_timer, int, 0644);
95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec");
96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x))
98 /* By default the driver will use the ring mode to manage tx and rx descriptors,
99 * but allow user to force to use the chain instead of the ring
101 static unsigned int chain_mode;
102 module_param(chain_mode, int, 0444);
103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode");
105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
107 #ifdef CONFIG_DEBUG_FS
108 static void stmmac_init_fs(struct net_device *dev);
109 static void stmmac_exit_fs(struct net_device *dev);
112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
115 * stmmac_verify_args - verify the driver parameters.
116 * Description: it checks the driver parameters and set a default in case of
119 static void stmmac_verify_args(void)
121 if (unlikely(watchdog < 0))
123 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB)))
124 buf_sz = DEFAULT_BUFSIZE;
125 if (unlikely(flow_ctrl > 1))
126 flow_ctrl = FLOW_AUTO;
127 else if (likely(flow_ctrl < 0))
128 flow_ctrl = FLOW_OFF;
129 if (unlikely((pause < 0) || (pause > 0xffff)))
132 eee_timer = STMMAC_DEFAULT_LPI_TIMER;
136 * stmmac_disable_all_queues - Disable all queues
137 * @priv: driver private structure
139 static void stmmac_disable_all_queues(struct stmmac_priv *priv)
141 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
142 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
143 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
146 for (queue = 0; queue < maxq; queue++) {
147 struct stmmac_channel *ch = &priv->channel[queue];
149 if (queue < rx_queues_cnt)
150 napi_disable(&ch->rx_napi);
151 if (queue < tx_queues_cnt)
152 napi_disable(&ch->tx_napi);
157 * stmmac_enable_all_queues - Enable all queues
158 * @priv: driver private structure
160 static void stmmac_enable_all_queues(struct stmmac_priv *priv)
162 u32 rx_queues_cnt = priv->plat->rx_queues_to_use;
163 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
164 u32 maxq = max(rx_queues_cnt, tx_queues_cnt);
167 for (queue = 0; queue < maxq; queue++) {
168 struct stmmac_channel *ch = &priv->channel[queue];
170 if (queue < rx_queues_cnt)
171 napi_enable(&ch->rx_napi);
172 if (queue < tx_queues_cnt)
173 napi_enable(&ch->tx_napi);
178 * stmmac_stop_all_queues - Stop all queues
179 * @priv: driver private structure
181 static void stmmac_stop_all_queues(struct stmmac_priv *priv)
183 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
186 for (queue = 0; queue < tx_queues_cnt; queue++)
187 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
191 * stmmac_start_all_queues - Start all queues
192 * @priv: driver private structure
194 static void stmmac_start_all_queues(struct stmmac_priv *priv)
196 u32 tx_queues_cnt = priv->plat->tx_queues_to_use;
199 for (queue = 0; queue < tx_queues_cnt; queue++)
200 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue));
203 static void stmmac_service_event_schedule(struct stmmac_priv *priv)
205 if (!test_bit(STMMAC_DOWN, &priv->state) &&
206 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state))
207 queue_work(priv->wq, &priv->service_task);
210 static void stmmac_global_err(struct stmmac_priv *priv)
212 netif_carrier_off(priv->dev);
213 set_bit(STMMAC_RESET_REQUESTED, &priv->state);
214 stmmac_service_event_schedule(priv);
218 * stmmac_clk_csr_set - dynamically set the MDC clock
219 * @priv: driver private structure
220 * Description: this is to dynamically set the MDC clock according to the csr
223 * If a specific clk_csr value is passed from the platform
224 * this means that the CSR Clock Range selection cannot be
225 * changed at run-time and it is fixed (as reported in the driver
226 * documentation). Viceversa the driver will try to set the MDC
227 * clock dynamically according to the actual clock input.
229 static void stmmac_clk_csr_set(struct stmmac_priv *priv)
233 clk_rate = clk_get_rate(priv->plat->stmmac_clk);
235 /* Platform provided default clk_csr would be assumed valid
236 * for all other cases except for the below mentioned ones.
237 * For values higher than the IEEE 802.3 specified frequency
238 * we can not estimate the proper divider as it is not known
239 * the frequency of clk_csr_i. So we do not change the default
242 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
243 if (clk_rate < CSR_F_35M)
244 priv->clk_csr = STMMAC_CSR_20_35M;
245 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
246 priv->clk_csr = STMMAC_CSR_35_60M;
247 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
248 priv->clk_csr = STMMAC_CSR_60_100M;
249 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
250 priv->clk_csr = STMMAC_CSR_100_150M;
251 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
252 priv->clk_csr = STMMAC_CSR_150_250M;
253 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M))
254 priv->clk_csr = STMMAC_CSR_250_300M;
257 if (priv->plat->has_sun8i) {
258 if (clk_rate > 160000000)
259 priv->clk_csr = 0x03;
260 else if (clk_rate > 80000000)
261 priv->clk_csr = 0x02;
262 else if (clk_rate > 40000000)
263 priv->clk_csr = 0x01;
268 if (priv->plat->has_xgmac) {
269 if (clk_rate > 400000000)
271 else if (clk_rate > 350000000)
273 else if (clk_rate > 300000000)
275 else if (clk_rate > 250000000)
277 else if (clk_rate > 150000000)
284 static void print_pkt(unsigned char *buf, int len)
286 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
287 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue)
292 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
295 if (tx_q->dirty_tx > tx_q->cur_tx)
296 avail = tx_q->dirty_tx - tx_q->cur_tx - 1;
298 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1;
304 * stmmac_rx_dirty - Get RX queue dirty
305 * @priv: driver private structure
306 * @queue: RX queue index
308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue)
310 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
313 if (rx_q->dirty_rx <= rx_q->cur_rx)
314 dirty = rx_q->cur_rx - rx_q->dirty_rx;
316 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx;
322 * stmmac_enable_eee_mode - check and enter in LPI mode
323 * @priv: driver private structure
324 * Description: this function is to verify and enter in LPI mode in case of
327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv)
329 u32 tx_cnt = priv->plat->tx_queues_to_use;
332 /* check if all TX queues have the work finished */
333 for (queue = 0; queue < tx_cnt; queue++) {
334 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
336 if (tx_q->dirty_tx != tx_q->cur_tx)
337 return; /* still unfinished work */
340 /* Check and enter in LPI mode */
341 if (!priv->tx_path_in_lpi_mode)
342 stmmac_set_eee_mode(priv, priv->hw,
343 priv->plat->en_tx_lpi_clockgating);
347 * stmmac_disable_eee_mode - disable and exit from LPI mode
348 * @priv: driver private structure
349 * Description: this function is to exit and disable EEE in case of
350 * LPI state is true. This is called by the xmit.
352 void stmmac_disable_eee_mode(struct stmmac_priv *priv)
354 stmmac_reset_eee_mode(priv, priv->hw);
355 del_timer_sync(&priv->eee_ctrl_timer);
356 priv->tx_path_in_lpi_mode = false;
360 * stmmac_eee_ctrl_timer - EEE TX SW timer.
363 * if there is no data transfer and if we are not in LPI state,
364 * then MAC Transmitter can be moved to LPI state.
366 static void stmmac_eee_ctrl_timer(struct timer_list *t)
368 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer);
370 stmmac_enable_eee_mode(priv);
371 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
375 * stmmac_eee_init - init EEE
376 * @priv: driver private structure
378 * if the GMAC supports the EEE (from the HW cap reg) and the phy device
379 * can also manage EEE, this function enable the LPI state and start related
382 bool stmmac_eee_init(struct stmmac_priv *priv)
384 int tx_lpi_timer = priv->tx_lpi_timer;
386 /* Using PCS we cannot dial with the phy registers at this stage
387 * so we do not support extra feature like EEE.
389 if ((priv->hw->pcs == STMMAC_PCS_RGMII) ||
390 (priv->hw->pcs == STMMAC_PCS_TBI) ||
391 (priv->hw->pcs == STMMAC_PCS_RTBI))
394 /* Check if MAC core supports the EEE feature. */
395 if (!priv->dma_cap.eee)
398 mutex_lock(&priv->lock);
400 /* Check if it needs to be deactivated */
401 if (!priv->eee_active) {
402 if (priv->eee_enabled) {
403 netdev_dbg(priv->dev, "disable EEE\n");
404 del_timer_sync(&priv->eee_ctrl_timer);
405 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer);
407 mutex_unlock(&priv->lock);
411 if (priv->eee_active && !priv->eee_enabled) {
412 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0);
413 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
414 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS,
418 mutex_unlock(&priv->lock);
419 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n");
423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps
424 * @priv: driver private structure
425 * @p : descriptor pointer
426 * @skb : the socket buffer
428 * This function will read timestamp from the descriptor & pass it to stack.
429 * and also perform some sanity checks.
431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv,
432 struct dma_desc *p, struct sk_buff *skb)
434 struct skb_shared_hwtstamps shhwtstamp;
438 if (!priv->hwts_tx_en)
441 /* exit if skb doesn't support hw tstamp */
442 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)))
445 /* check tx tstamp status */
446 if (stmmac_get_tx_timestamp_status(priv, p)) {
447 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns);
449 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) {
454 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
455 shhwtstamp.hwtstamp = ns_to_ktime(ns);
457 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns);
458 /* pass tstamp to stack */
459 skb_tstamp_tx(skb, &shhwtstamp);
463 /* stmmac_get_rx_hwtstamp - get HW RX timestamps
464 * @priv: driver private structure
465 * @p : descriptor pointer
466 * @np : next descriptor pointer
467 * @skb : the socket buffer
469 * This function will read received packet's timestamp from the descriptor
470 * and pass it to stack. It also perform some sanity checks.
472 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p,
473 struct dma_desc *np, struct sk_buff *skb)
475 struct skb_shared_hwtstamps *shhwtstamp = NULL;
476 struct dma_desc *desc = p;
479 if (!priv->hwts_rx_en)
481 /* For GMAC4, the valid timestamp is from CTX next desc. */
482 if (priv->plat->has_gmac4 || priv->plat->has_xgmac)
485 /* Check if timestamp is available */
486 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) {
487 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns);
488 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns);
489 shhwtstamp = skb_hwtstamps(skb);
490 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps));
491 shhwtstamp->hwtstamp = ns_to_ktime(ns);
493 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n");
498 * stmmac_hwtstamp_set - control hardware timestamping.
499 * @dev: device pointer.
500 * @ifr: An IOCTL specific structure, that can contain a pointer to
501 * a proprietary structure used to pass information to the driver.
503 * This function configures the MAC to enable/disable both outgoing(TX)
504 * and incoming(RX) packets time stamping based on user input.
506 * 0 on success and an appropriate -ve integer on failure.
508 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
510 struct stmmac_priv *priv = netdev_priv(dev);
511 struct hwtstamp_config config;
512 struct timespec64 now;
516 u32 ptp_over_ipv4_udp = 0;
517 u32 ptp_over_ipv6_udp = 0;
518 u32 ptp_over_ethernet = 0;
519 u32 snap_type_sel = 0;
520 u32 ts_master_en = 0;
526 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
528 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) {
529 netdev_alert(priv->dev, "No support for HW time stamping\n");
530 priv->hwts_tx_en = 0;
531 priv->hwts_rx_en = 0;
536 if (copy_from_user(&config, ifr->ifr_data,
540 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n",
541 __func__, config.flags, config.tx_type, config.rx_filter);
543 /* reserved for future extensions */
547 if (config.tx_type != HWTSTAMP_TX_OFF &&
548 config.tx_type != HWTSTAMP_TX_ON)
552 switch (config.rx_filter) {
553 case HWTSTAMP_FILTER_NONE:
554 /* time stamp no incoming packet at all */
555 config.rx_filter = HWTSTAMP_FILTER_NONE;
558 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
559 /* PTP v1, UDP, any kind of event packet */
560 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
561 /* 'xmac' hardware can support Sync, Pdelay_Req and
562 * Pdelay_resp by setting bit14 and bits17/16 to 01
563 * This leaves Delay_Req timestamps out.
564 * Enable all events *and* general purpose message
567 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
568 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
569 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
572 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
573 /* PTP v1, UDP, Sync packet */
574 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
575 /* take time stamp for SYNC messages only */
576 ts_event_en = PTP_TCR_TSEVNTENA;
578 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
579 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
582 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
583 /* PTP v1, UDP, Delay_req packet */
584 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
585 /* take time stamp for Delay_Req messages only */
586 ts_master_en = PTP_TCR_TSMSTRENA;
587 ts_event_en = PTP_TCR_TSEVNTENA;
589 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
590 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
593 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
594 /* PTP v2, UDP, any kind of event packet */
595 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
596 ptp_v2 = PTP_TCR_TSVER2ENA;
597 /* take time stamp for all event messages */
598 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
600 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
601 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
604 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
605 /* PTP v2, UDP, Sync packet */
606 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
607 ptp_v2 = PTP_TCR_TSVER2ENA;
608 /* take time stamp for SYNC messages only */
609 ts_event_en = PTP_TCR_TSEVNTENA;
611 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
612 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
615 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
616 /* PTP v2, UDP, Delay_req packet */
617 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
618 ptp_v2 = PTP_TCR_TSVER2ENA;
619 /* take time stamp for Delay_Req messages only */
620 ts_master_en = PTP_TCR_TSMSTRENA;
621 ts_event_en = PTP_TCR_TSEVNTENA;
623 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
624 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
627 case HWTSTAMP_FILTER_PTP_V2_EVENT:
628 /* PTP v2/802.AS1 any layer, any kind of event packet */
629 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
630 ptp_v2 = PTP_TCR_TSVER2ENA;
631 snap_type_sel = PTP_TCR_SNAPTYPSEL_1;
632 ts_event_en = PTP_TCR_TSEVNTENA;
633 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
634 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
635 ptp_over_ethernet = PTP_TCR_TSIPENA;
638 case HWTSTAMP_FILTER_PTP_V2_SYNC:
639 /* PTP v2/802.AS1, any layer, Sync packet */
640 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
641 ptp_v2 = PTP_TCR_TSVER2ENA;
642 /* take time stamp for SYNC messages only */
643 ts_event_en = PTP_TCR_TSEVNTENA;
645 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
646 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
647 ptp_over_ethernet = PTP_TCR_TSIPENA;
650 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
651 /* PTP v2/802.AS1, any layer, Delay_req packet */
652 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
653 ptp_v2 = PTP_TCR_TSVER2ENA;
654 /* take time stamp for Delay_Req messages only */
655 ts_master_en = PTP_TCR_TSMSTRENA;
656 ts_event_en = PTP_TCR_TSEVNTENA;
658 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA;
659 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA;
660 ptp_over_ethernet = PTP_TCR_TSIPENA;
663 case HWTSTAMP_FILTER_NTP_ALL:
664 case HWTSTAMP_FILTER_ALL:
665 /* time stamp any incoming packet */
666 config.rx_filter = HWTSTAMP_FILTER_ALL;
667 tstamp_all = PTP_TCR_TSENALL;
674 switch (config.rx_filter) {
675 case HWTSTAMP_FILTER_NONE:
676 config.rx_filter = HWTSTAMP_FILTER_NONE;
679 /* PTP v1, UDP, any kind of event packet */
680 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
684 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1);
685 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON;
687 if (!priv->hwts_tx_en && !priv->hwts_rx_en)
688 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0);
690 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR |
691 tstamp_all | ptp_v2 | ptp_over_ethernet |
692 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en |
693 ts_master_en | snap_type_sel);
694 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value);
696 /* program Sub Second Increment reg */
697 stmmac_config_sub_second_increment(priv,
698 priv->ptpaddr, priv->plat->clk_ptp_rate,
700 temp = div_u64(1000000000ULL, sec_inc);
702 /* Store sub second increment and flags for later use */
703 priv->sub_second_inc = sec_inc;
704 priv->systime_flags = value;
706 /* calculate default added value:
708 * addend = (2^32)/freq_div_ratio;
709 * where, freq_div_ratio = 1e9ns/sec_inc
711 temp = (u64)(temp << 32);
712 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate);
713 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend);
715 /* initialize system time */
716 ktime_get_real_ts64(&now);
718 /* lower 32 bits of tv_sec are safe until y2106 */
719 stmmac_init_systime(priv, priv->ptpaddr,
720 (u32)now.tv_sec, now.tv_nsec);
723 memcpy(&priv->tstamp_config, &config, sizeof(config));
725 return copy_to_user(ifr->ifr_data, &config,
726 sizeof(config)) ? -EFAULT : 0;
730 * stmmac_hwtstamp_get - read hardware timestamping.
731 * @dev: device pointer.
732 * @ifr: An IOCTL specific structure, that can contain a pointer to
733 * a proprietary structure used to pass information to the driver.
735 * This function obtain the current hardware timestamping settings
738 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
740 struct stmmac_priv *priv = netdev_priv(dev);
741 struct hwtstamp_config *config = &priv->tstamp_config;
743 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
746 return copy_to_user(ifr->ifr_data, config,
747 sizeof(*config)) ? -EFAULT : 0;
751 * stmmac_init_ptp - init PTP
752 * @priv: driver private structure
753 * Description: this is to verify if the HW supports the PTPv1 or PTPv2.
754 * This is done by looking at the HW cap. register.
755 * This function also registers the ptp driver.
757 static int stmmac_init_ptp(struct stmmac_priv *priv)
759 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
761 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp))
765 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */
766 if (xmac && priv->dma_cap.atime_stamp)
768 /* Dwmac 3.x core with extend_desc can support adv_ts */
769 else if (priv->extend_desc && priv->dma_cap.atime_stamp)
772 if (priv->dma_cap.time_stamp)
773 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n");
776 netdev_info(priv->dev,
777 "IEEE 1588-2008 Advanced Timestamp supported\n");
779 priv->hwts_tx_en = 0;
780 priv->hwts_rx_en = 0;
782 stmmac_ptp_register(priv);
787 static void stmmac_release_ptp(struct stmmac_priv *priv)
789 if (priv->plat->clk_ptp_ref)
790 clk_disable_unprepare(priv->plat->clk_ptp_ref);
791 stmmac_ptp_unregister(priv);
795 * stmmac_mac_flow_ctrl - Configure flow control in all queues
796 * @priv: driver private structure
797 * Description: It is used for configuring the flow control in all queues
799 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex)
801 u32 tx_cnt = priv->plat->tx_queues_to_use;
803 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl,
804 priv->pause, tx_cnt);
807 static void stmmac_validate(struct phylink_config *config,
808 unsigned long *supported,
809 struct phylink_link_state *state)
811 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
812 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, };
813 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
814 int tx_cnt = priv->plat->tx_queues_to_use;
815 int max_speed = priv->plat->max_speed;
817 phylink_set(mac_supported, 10baseT_Half);
818 phylink_set(mac_supported, 10baseT_Full);
819 phylink_set(mac_supported, 100baseT_Half);
820 phylink_set(mac_supported, 100baseT_Full);
821 phylink_set(mac_supported, 1000baseT_Half);
822 phylink_set(mac_supported, 1000baseT_Full);
823 phylink_set(mac_supported, 1000baseKX_Full);
825 phylink_set(mac_supported, Autoneg);
826 phylink_set(mac_supported, Pause);
827 phylink_set(mac_supported, Asym_Pause);
828 phylink_set_port_modes(mac_supported);
830 /* Cut down 1G if asked to */
831 if ((max_speed > 0) && (max_speed < 1000)) {
832 phylink_set(mask, 1000baseT_Full);
833 phylink_set(mask, 1000baseX_Full);
834 } else if (priv->plat->has_xgmac) {
835 if (!max_speed || (max_speed >= 2500)) {
836 phylink_set(mac_supported, 2500baseT_Full);
837 phylink_set(mac_supported, 2500baseX_Full);
839 if (!max_speed || (max_speed >= 5000)) {
840 phylink_set(mac_supported, 5000baseT_Full);
842 if (!max_speed || (max_speed >= 10000)) {
843 phylink_set(mac_supported, 10000baseSR_Full);
844 phylink_set(mac_supported, 10000baseLR_Full);
845 phylink_set(mac_supported, 10000baseER_Full);
846 phylink_set(mac_supported, 10000baseLRM_Full);
847 phylink_set(mac_supported, 10000baseT_Full);
848 phylink_set(mac_supported, 10000baseKX4_Full);
849 phylink_set(mac_supported, 10000baseKR_Full);
853 /* Half-Duplex can only work with single queue */
855 phylink_set(mask, 10baseT_Half);
856 phylink_set(mask, 100baseT_Half);
857 phylink_set(mask, 1000baseT_Half);
860 bitmap_and(supported, supported, mac_supported,
861 __ETHTOOL_LINK_MODE_MASK_NBITS);
862 bitmap_andnot(supported, supported, mask,
863 __ETHTOOL_LINK_MODE_MASK_NBITS);
864 bitmap_and(state->advertising, state->advertising, mac_supported,
865 __ETHTOOL_LINK_MODE_MASK_NBITS);
866 bitmap_andnot(state->advertising, state->advertising, mask,
867 __ETHTOOL_LINK_MODE_MASK_NBITS);
870 static int stmmac_mac_link_state(struct phylink_config *config,
871 struct phylink_link_state *state)
876 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode,
877 const struct phylink_link_state *state)
879 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
882 ctrl = readl(priv->ioaddr + MAC_CTRL_REG);
883 ctrl &= ~priv->hw->link.speed_mask;
885 if (state->interface == PHY_INTERFACE_MODE_USXGMII) {
886 switch (state->speed) {
888 ctrl |= priv->hw->link.xgmii.speed10000;
891 ctrl |= priv->hw->link.xgmii.speed5000;
894 ctrl |= priv->hw->link.xgmii.speed2500;
900 switch (state->speed) {
902 ctrl |= priv->hw->link.speed2500;
905 ctrl |= priv->hw->link.speed1000;
908 ctrl |= priv->hw->link.speed100;
911 ctrl |= priv->hw->link.speed10;
918 priv->speed = state->speed;
920 if (priv->plat->fix_mac_speed)
921 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed);
924 ctrl &= ~priv->hw->link.duplex;
926 ctrl |= priv->hw->link.duplex;
928 /* Flow Control operation */
930 stmmac_mac_flow_ctrl(priv, state->duplex);
932 writel(ctrl, priv->ioaddr + MAC_CTRL_REG);
935 static void stmmac_mac_an_restart(struct phylink_config *config)
940 static void stmmac_mac_link_down(struct phylink_config *config,
941 unsigned int mode, phy_interface_t interface)
943 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
945 stmmac_mac_set(priv, priv->ioaddr, false);
946 priv->eee_active = false;
947 stmmac_eee_init(priv);
948 stmmac_set_eee_pls(priv, priv->hw, false);
951 static void stmmac_mac_link_up(struct phylink_config *config,
952 unsigned int mode, phy_interface_t interface,
953 struct phy_device *phy)
955 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev));
957 stmmac_mac_set(priv, priv->ioaddr, true);
958 if (phy && priv->dma_cap.eee) {
959 priv->eee_active = phy_init_eee(phy, 1) >= 0;
960 priv->eee_enabled = stmmac_eee_init(priv);
961 stmmac_set_eee_pls(priv, priv->hw, true);
965 static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
966 .validate = stmmac_validate,
967 .mac_link_state = stmmac_mac_link_state,
968 .mac_config = stmmac_mac_config,
969 .mac_an_restart = stmmac_mac_an_restart,
970 .mac_link_down = stmmac_mac_link_down,
971 .mac_link_up = stmmac_mac_link_up,
975 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported
976 * @priv: driver private structure
977 * Description: this is to verify if the HW supports the PCS.
978 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is
979 * configured for the TBI, RTBI, or SGMII PHY interface.
981 static void stmmac_check_pcs_mode(struct stmmac_priv *priv)
983 int interface = priv->plat->interface;
985 if (priv->dma_cap.pcs) {
986 if ((interface == PHY_INTERFACE_MODE_RGMII) ||
987 (interface == PHY_INTERFACE_MODE_RGMII_ID) ||
988 (interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
989 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
990 netdev_dbg(priv->dev, "PCS RGMII support enabled\n");
991 priv->hw->pcs = STMMAC_PCS_RGMII;
992 } else if (interface == PHY_INTERFACE_MODE_SGMII) {
993 netdev_dbg(priv->dev, "PCS SGMII support enabled\n");
994 priv->hw->pcs = STMMAC_PCS_SGMII;
1000 * stmmac_init_phy - PHY initialization
1001 * @dev: net device structure
1002 * Description: it initializes the driver's PHY state, and attaches the PHY
1003 * to the mac driver.
1007 static int stmmac_init_phy(struct net_device *dev)
1009 struct stmmac_priv *priv = netdev_priv(dev);
1010 struct device_node *node;
1013 node = priv->plat->phylink_node;
1016 ret = phylink_of_phy_connect(priv->phylink, node, 0);
1018 /* Some DT bindings do not set-up the PHY handle. Let's try to
1022 int addr = priv->plat->phy_addr;
1023 struct phy_device *phydev;
1025 phydev = mdiobus_get_phy(priv->mii, addr);
1027 netdev_err(priv->dev, "no phy at addr %d\n", addr);
1031 ret = phylink_connect_phy(priv->phylink, phydev);
1037 static int stmmac_phy_setup(struct stmmac_priv *priv)
1039 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node);
1040 int mode = priv->plat->phy_interface;
1041 struct phylink *phylink;
1043 priv->phylink_config.dev = &priv->dev->dev;
1044 priv->phylink_config.type = PHYLINK_NETDEV;
1046 phylink = phylink_create(&priv->phylink_config, fwnode,
1047 mode, &stmmac_phylink_mac_ops);
1048 if (IS_ERR(phylink))
1049 return PTR_ERR(phylink);
1051 priv->phylink = phylink;
1055 static void stmmac_display_rx_rings(struct stmmac_priv *priv)
1057 u32 rx_cnt = priv->plat->rx_queues_to_use;
1061 /* Display RX rings */
1062 for (queue = 0; queue < rx_cnt; queue++) {
1063 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1065 pr_info("\tRX Queue %u rings\n", queue);
1067 if (priv->extend_desc)
1068 head_rx = (void *)rx_q->dma_erx;
1070 head_rx = (void *)rx_q->dma_rx;
1072 /* Display RX ring */
1073 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true);
1077 static void stmmac_display_tx_rings(struct stmmac_priv *priv)
1079 u32 tx_cnt = priv->plat->tx_queues_to_use;
1083 /* Display TX rings */
1084 for (queue = 0; queue < tx_cnt; queue++) {
1085 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1087 pr_info("\tTX Queue %d rings\n", queue);
1089 if (priv->extend_desc)
1090 head_tx = (void *)tx_q->dma_etx;
1092 head_tx = (void *)tx_q->dma_tx;
1094 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false);
1098 static void stmmac_display_rings(struct stmmac_priv *priv)
1100 /* Display RX ring */
1101 stmmac_display_rx_rings(priv);
1103 /* Display TX ring */
1104 stmmac_display_tx_rings(priv);
1107 static int stmmac_set_bfsize(int mtu, int bufsize)
1111 if (mtu >= BUF_SIZE_4KiB)
1112 ret = BUF_SIZE_8KiB;
1113 else if (mtu >= BUF_SIZE_2KiB)
1114 ret = BUF_SIZE_4KiB;
1115 else if (mtu > DEFAULT_BUFSIZE)
1116 ret = BUF_SIZE_2KiB;
1118 ret = DEFAULT_BUFSIZE;
1124 * stmmac_clear_rx_descriptors - clear RX descriptors
1125 * @priv: driver private structure
1126 * @queue: RX queue index
1127 * Description: this function is called to clear the RX descriptors
1128 * in case of both basic and extended descriptors are used.
1130 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
1132 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1135 /* Clear the RX descriptors */
1136 for (i = 0; i < DMA_RX_SIZE; i++)
1137 if (priv->extend_desc)
1138 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic,
1139 priv->use_riwt, priv->mode,
1140 (i == DMA_RX_SIZE - 1),
1143 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i],
1144 priv->use_riwt, priv->mode,
1145 (i == DMA_RX_SIZE - 1),
1150 * stmmac_clear_tx_descriptors - clear tx descriptors
1151 * @priv: driver private structure
1152 * @queue: TX queue index.
1153 * Description: this function is called to clear the TX descriptors
1154 * in case of both basic and extended descriptors are used.
1156 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
1158 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1161 /* Clear the TX descriptors */
1162 for (i = 0; i < DMA_TX_SIZE; i++)
1163 if (priv->extend_desc)
1164 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
1165 priv->mode, (i == DMA_TX_SIZE - 1));
1167 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
1168 priv->mode, (i == DMA_TX_SIZE - 1));
1172 * stmmac_clear_descriptors - clear descriptors
1173 * @priv: driver private structure
1174 * Description: this function is called to clear the TX and RX descriptors
1175 * in case of both basic and extended descriptors are used.
1177 static void stmmac_clear_descriptors(struct stmmac_priv *priv)
1179 u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
1180 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1183 /* Clear the RX descriptors */
1184 for (queue = 0; queue < rx_queue_cnt; queue++)
1185 stmmac_clear_rx_descriptors(priv, queue);
1187 /* Clear the TX descriptors */
1188 for (queue = 0; queue < tx_queue_cnt; queue++)
1189 stmmac_clear_tx_descriptors(priv, queue);
1193 * stmmac_init_rx_buffers - init the RX descriptor buffer.
1194 * @priv: driver private structure
1195 * @p: descriptor pointer
1196 * @i: descriptor index
1198 * @queue: RX queue index
1199 * Description: this function is called to allocate a receive buffer, perform
1200 * the DMA mapping and init the descriptor.
1202 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
1203 int i, gfp_t flags, u32 queue)
1205 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1206 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1208 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
1213 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
1217 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
1218 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr);
1220 buf->sec_page = NULL;
1223 buf->addr = page_pool_get_dma_addr(buf->page);
1224 stmmac_set_desc_addr(priv, p, buf->addr);
1225 if (priv->dma_buf_sz == BUF_SIZE_16KiB)
1226 stmmac_init_desc3(priv, p);
1232 * stmmac_free_rx_buffer - free RX dma buffers
1233 * @priv: private structure
1234 * @queue: RX queue index
1237 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1239 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1240 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
1243 page_pool_put_page(rx_q->page_pool, buf->page, false);
1247 page_pool_put_page(rx_q->page_pool, buf->sec_page, false);
1248 buf->sec_page = NULL;
1252 * stmmac_free_tx_buffer - free RX dma buffers
1253 * @priv: private structure
1254 * @queue: RX queue index
1257 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
1259 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1261 if (tx_q->tx_skbuff_dma[i].buf) {
1262 if (tx_q->tx_skbuff_dma[i].map_as_page)
1263 dma_unmap_page(priv->device,
1264 tx_q->tx_skbuff_dma[i].buf,
1265 tx_q->tx_skbuff_dma[i].len,
1268 dma_unmap_single(priv->device,
1269 tx_q->tx_skbuff_dma[i].buf,
1270 tx_q->tx_skbuff_dma[i].len,
1274 if (tx_q->tx_skbuff[i]) {
1275 dev_kfree_skb_any(tx_q->tx_skbuff[i]);
1276 tx_q->tx_skbuff[i] = NULL;
1277 tx_q->tx_skbuff_dma[i].buf = 0;
1278 tx_q->tx_skbuff_dma[i].map_as_page = false;
1283 * init_dma_rx_desc_rings - init the RX descriptor rings
1284 * @dev: net device structure
1286 * Description: this function initializes the DMA RX descriptors
1287 * and allocates the socket buffers. It supports the chained and ring
1290 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags)
1292 struct stmmac_priv *priv = netdev_priv(dev);
1293 u32 rx_count = priv->plat->rx_queues_to_use;
1299 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu);
1303 if (bfsize < BUF_SIZE_16KiB)
1304 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz);
1306 priv->dma_buf_sz = bfsize;
1308 /* RX INITIALIZATION */
1309 netif_dbg(priv, probe, priv->dev,
1310 "SKB addresses:\nskb\t\tskb data\tdma data\n");
1312 for (queue = 0; queue < rx_count; queue++) {
1313 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1315 netif_dbg(priv, probe, priv->dev,
1316 "(%s) dma_rx_phy=0x%08x\n", __func__,
1317 (u32)rx_q->dma_rx_phy);
1319 stmmac_clear_rx_descriptors(priv, queue);
1321 for (i = 0; i < DMA_RX_SIZE; i++) {
1324 if (priv->extend_desc)
1325 p = &((rx_q->dma_erx + i)->basic);
1327 p = rx_q->dma_rx + i;
1329 ret = stmmac_init_rx_buffers(priv, p, i, flags,
1332 goto err_init_rx_buffers;
1336 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE);
1338 /* Setup the chained descriptor addresses */
1339 if (priv->mode == STMMAC_CHAIN_MODE) {
1340 if (priv->extend_desc)
1341 stmmac_mode_init(priv, rx_q->dma_erx,
1342 rx_q->dma_rx_phy, DMA_RX_SIZE, 1);
1344 stmmac_mode_init(priv, rx_q->dma_rx,
1345 rx_q->dma_rx_phy, DMA_RX_SIZE, 0);
1353 err_init_rx_buffers:
1354 while (queue >= 0) {
1356 stmmac_free_rx_buffer(priv, queue, i);
1369 * init_dma_tx_desc_rings - init the TX descriptor rings
1370 * @dev: net device structure.
1371 * Description: this function initializes the DMA TX descriptors
1372 * and allocates the socket buffers. It supports the chained and ring
1375 static int init_dma_tx_desc_rings(struct net_device *dev)
1377 struct stmmac_priv *priv = netdev_priv(dev);
1378 u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
1382 for (queue = 0; queue < tx_queue_cnt; queue++) {
1383 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1385 netif_dbg(priv, probe, priv->dev,
1386 "(%s) dma_tx_phy=0x%08x\n", __func__,
1387 (u32)tx_q->dma_tx_phy);
1389 /* Setup the chained descriptor addresses */
1390 if (priv->mode == STMMAC_CHAIN_MODE) {
1391 if (priv->extend_desc)
1392 stmmac_mode_init(priv, tx_q->dma_etx,
1393 tx_q->dma_tx_phy, DMA_TX_SIZE, 1);
1395 stmmac_mode_init(priv, tx_q->dma_tx,
1396 tx_q->dma_tx_phy, DMA_TX_SIZE, 0);
1399 for (i = 0; i < DMA_TX_SIZE; i++) {
1401 if (priv->extend_desc)
1402 p = &((tx_q->dma_etx + i)->basic);
1404 p = tx_q->dma_tx + i;
1406 stmmac_clear_desc(priv, p);
1408 tx_q->tx_skbuff_dma[i].buf = 0;
1409 tx_q->tx_skbuff_dma[i].map_as_page = false;
1410 tx_q->tx_skbuff_dma[i].len = 0;
1411 tx_q->tx_skbuff_dma[i].last_segment = false;
1412 tx_q->tx_skbuff[i] = NULL;
1419 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue));
1426 * init_dma_desc_rings - init the RX/TX descriptor rings
1427 * @dev: net device structure
1429 * Description: this function initializes the DMA RX/TX descriptors
1430 * and allocates the socket buffers. It supports the chained and ring
1433 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags)
1435 struct stmmac_priv *priv = netdev_priv(dev);
1438 ret = init_dma_rx_desc_rings(dev, flags);
1442 ret = init_dma_tx_desc_rings(dev);
1444 stmmac_clear_descriptors(priv);
1446 if (netif_msg_hw(priv))
1447 stmmac_display_rings(priv);
1453 * dma_free_rx_skbufs - free RX dma buffers
1454 * @priv: private structure
1455 * @queue: RX queue index
1457 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue)
1461 for (i = 0; i < DMA_RX_SIZE; i++)
1462 stmmac_free_rx_buffer(priv, queue, i);
1466 * dma_free_tx_skbufs - free TX dma buffers
1467 * @priv: private structure
1468 * @queue: TX queue index
1470 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
1474 for (i = 0; i < DMA_TX_SIZE; i++)
1475 stmmac_free_tx_buffer(priv, queue, i);
1479 * free_dma_rx_desc_resources - free RX dma desc resources
1480 * @priv: private structure
1482 static void free_dma_rx_desc_resources(struct stmmac_priv *priv)
1484 u32 rx_count = priv->plat->rx_queues_to_use;
1487 /* Free RX queue resources */
1488 for (queue = 0; queue < rx_count; queue++) {
1489 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1491 /* Release the DMA RX socket buffers */
1492 dma_free_rx_skbufs(priv, queue);
1494 /* Free DMA regions of consistent memory previously allocated */
1495 if (!priv->extend_desc)
1496 dma_free_coherent(priv->device,
1497 DMA_RX_SIZE * sizeof(struct dma_desc),
1498 rx_q->dma_rx, rx_q->dma_rx_phy);
1500 dma_free_coherent(priv->device, DMA_RX_SIZE *
1501 sizeof(struct dma_extended_desc),
1502 rx_q->dma_erx, rx_q->dma_rx_phy);
1504 kfree(rx_q->buf_pool);
1505 if (rx_q->page_pool) {
1506 page_pool_request_shutdown(rx_q->page_pool);
1507 page_pool_destroy(rx_q->page_pool);
1513 * free_dma_tx_desc_resources - free TX dma desc resources
1514 * @priv: private structure
1516 static void free_dma_tx_desc_resources(struct stmmac_priv *priv)
1518 u32 tx_count = priv->plat->tx_queues_to_use;
1521 /* Free TX queue resources */
1522 for (queue = 0; queue < tx_count; queue++) {
1523 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1525 /* Release the DMA TX socket buffers */
1526 dma_free_tx_skbufs(priv, queue);
1528 /* Free DMA regions of consistent memory previously allocated */
1529 if (!priv->extend_desc)
1530 dma_free_coherent(priv->device,
1531 DMA_TX_SIZE * sizeof(struct dma_desc),
1532 tx_q->dma_tx, tx_q->dma_tx_phy);
1534 dma_free_coherent(priv->device, DMA_TX_SIZE *
1535 sizeof(struct dma_extended_desc),
1536 tx_q->dma_etx, tx_q->dma_tx_phy);
1538 kfree(tx_q->tx_skbuff_dma);
1539 kfree(tx_q->tx_skbuff);
1544 * alloc_dma_rx_desc_resources - alloc RX resources.
1545 * @priv: private structure
1546 * Description: according to which descriptor can be used (extend or basic)
1547 * this function allocates the resources for TX and RX paths. In case of
1548 * reception, for example, it pre-allocated the RX socket buffer in order to
1549 * allow zero-copy mechanism.
1551 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv)
1553 u32 rx_count = priv->plat->rx_queues_to_use;
1557 /* RX queues buffers and DMA */
1558 for (queue = 0; queue < rx_count; queue++) {
1559 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
1560 struct page_pool_params pp_params = { 0 };
1561 unsigned int num_pages;
1563 rx_q->queue_index = queue;
1564 rx_q->priv_data = priv;
1566 pp_params.flags = PP_FLAG_DMA_MAP;
1567 pp_params.pool_size = DMA_RX_SIZE;
1568 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE);
1569 pp_params.order = ilog2(num_pages);
1570 pp_params.nid = dev_to_node(priv->device);
1571 pp_params.dev = priv->device;
1572 pp_params.dma_dir = DMA_FROM_DEVICE;
1574 rx_q->page_pool = page_pool_create(&pp_params);
1575 if (IS_ERR(rx_q->page_pool)) {
1576 ret = PTR_ERR(rx_q->page_pool);
1577 rx_q->page_pool = NULL;
1581 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool),
1583 if (!rx_q->buf_pool)
1586 if (priv->extend_desc) {
1587 rx_q->dma_erx = dma_alloc_coherent(priv->device,
1588 DMA_RX_SIZE * sizeof(struct dma_extended_desc),
1595 rx_q->dma_rx = dma_alloc_coherent(priv->device,
1596 DMA_RX_SIZE * sizeof(struct dma_desc),
1607 free_dma_rx_desc_resources(priv);
1613 * alloc_dma_tx_desc_resources - alloc TX resources.
1614 * @priv: private structure
1615 * Description: according to which descriptor can be used (extend or basic)
1616 * this function allocates the resources for TX and RX paths. In case of
1617 * reception, for example, it pre-allocated the RX socket buffer in order to
1618 * allow zero-copy mechanism.
1620 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv)
1622 u32 tx_count = priv->plat->tx_queues_to_use;
1626 /* TX queues buffers and DMA */
1627 for (queue = 0; queue < tx_count; queue++) {
1628 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1630 tx_q->queue_index = queue;
1631 tx_q->priv_data = priv;
1633 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE,
1634 sizeof(*tx_q->tx_skbuff_dma),
1636 if (!tx_q->tx_skbuff_dma)
1639 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE,
1640 sizeof(struct sk_buff *),
1642 if (!tx_q->tx_skbuff)
1645 if (priv->extend_desc) {
1646 tx_q->dma_etx = dma_alloc_coherent(priv->device,
1647 DMA_TX_SIZE * sizeof(struct dma_extended_desc),
1653 tx_q->dma_tx = dma_alloc_coherent(priv->device,
1654 DMA_TX_SIZE * sizeof(struct dma_desc),
1665 free_dma_tx_desc_resources(priv);
1671 * alloc_dma_desc_resources - alloc TX/RX resources.
1672 * @priv: private structure
1673 * Description: according to which descriptor can be used (extend or basic)
1674 * this function allocates the resources for TX and RX paths. In case of
1675 * reception, for example, it pre-allocated the RX socket buffer in order to
1676 * allow zero-copy mechanism.
1678 static int alloc_dma_desc_resources(struct stmmac_priv *priv)
1681 int ret = alloc_dma_rx_desc_resources(priv);
1686 ret = alloc_dma_tx_desc_resources(priv);
1692 * free_dma_desc_resources - free dma desc resources
1693 * @priv: private structure
1695 static void free_dma_desc_resources(struct stmmac_priv *priv)
1697 /* Release the DMA RX socket buffers */
1698 free_dma_rx_desc_resources(priv);
1700 /* Release the DMA TX socket buffers */
1701 free_dma_tx_desc_resources(priv);
1705 * stmmac_mac_enable_rx_queues - Enable MAC rx queues
1706 * @priv: driver private structure
1707 * Description: It is used for enabling the rx queues in the MAC
1709 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
1711 u32 rx_queues_count = priv->plat->rx_queues_to_use;
1715 for (queue = 0; queue < rx_queues_count; queue++) {
1716 mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
1717 stmmac_rx_queue_enable(priv, priv->hw, mode, queue);
1722 * stmmac_start_rx_dma - start RX DMA channel
1723 * @priv: driver private structure
1724 * @chan: RX channel index
1726 * This starts a RX DMA channel
1728 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan)
1730 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan);
1731 stmmac_start_rx(priv, priv->ioaddr, chan);
1735 * stmmac_start_tx_dma - start TX DMA channel
1736 * @priv: driver private structure
1737 * @chan: TX channel index
1739 * This starts a TX DMA channel
1741 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan)
1743 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan);
1744 stmmac_start_tx(priv, priv->ioaddr, chan);
1748 * stmmac_stop_rx_dma - stop RX DMA channel
1749 * @priv: driver private structure
1750 * @chan: RX channel index
1752 * This stops a RX DMA channel
1754 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan)
1756 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan);
1757 stmmac_stop_rx(priv, priv->ioaddr, chan);
1761 * stmmac_stop_tx_dma - stop TX DMA channel
1762 * @priv: driver private structure
1763 * @chan: TX channel index
1765 * This stops a TX DMA channel
1767 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan)
1769 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan);
1770 stmmac_stop_tx(priv, priv->ioaddr, chan);
1774 * stmmac_start_all_dma - start all RX and TX DMA channels
1775 * @priv: driver private structure
1777 * This starts all the RX and TX DMA channels
1779 static void stmmac_start_all_dma(struct stmmac_priv *priv)
1781 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1782 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1785 for (chan = 0; chan < rx_channels_count; chan++)
1786 stmmac_start_rx_dma(priv, chan);
1788 for (chan = 0; chan < tx_channels_count; chan++)
1789 stmmac_start_tx_dma(priv, chan);
1793 * stmmac_stop_all_dma - stop all RX and TX DMA channels
1794 * @priv: driver private structure
1796 * This stops the RX and TX DMA channels
1798 static void stmmac_stop_all_dma(struct stmmac_priv *priv)
1800 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1801 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1804 for (chan = 0; chan < rx_channels_count; chan++)
1805 stmmac_stop_rx_dma(priv, chan);
1807 for (chan = 0; chan < tx_channels_count; chan++)
1808 stmmac_stop_tx_dma(priv, chan);
1812 * stmmac_dma_operation_mode - HW DMA operation mode
1813 * @priv: driver private structure
1814 * Description: it is used for configuring the DMA operation mode register in
1815 * order to program the tx/rx DMA thresholds or Store-And-Forward mode.
1817 static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
1819 u32 rx_channels_count = priv->plat->rx_queues_to_use;
1820 u32 tx_channels_count = priv->plat->tx_queues_to_use;
1821 int rxfifosz = priv->plat->rx_fifo_size;
1822 int txfifosz = priv->plat->tx_fifo_size;
1829 rxfifosz = priv->dma_cap.rx_fifo_size;
1831 txfifosz = priv->dma_cap.tx_fifo_size;
1833 /* Adjust for real per queue fifo size */
1834 rxfifosz /= rx_channels_count;
1835 txfifosz /= tx_channels_count;
1837 if (priv->plat->force_thresh_dma_mode) {
1840 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) {
1842 * In case of GMAC, SF mode can be enabled
1843 * to perform the TX COE in HW. This depends on:
1844 * 1) TX COE if actually supported
1845 * 2) There is no bugged Jumbo frame support
1846 * that needs to not insert csum in the TDES.
1848 txmode = SF_DMA_MODE;
1849 rxmode = SF_DMA_MODE;
1850 priv->xstats.threshold = SF_DMA_MODE;
1853 rxmode = SF_DMA_MODE;
1856 /* configure all channels */
1857 for (chan = 0; chan < rx_channels_count; chan++) {
1858 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
1860 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan,
1862 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz,
1866 for (chan = 0; chan < tx_channels_count; chan++) {
1867 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
1869 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan,
1875 * stmmac_tx_clean - to manage the transmission completion
1876 * @priv: driver private structure
1877 * @queue: TX queue index
1878 * Description: it reclaims the transmit resources after transmission completes.
1880 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
1882 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
1883 unsigned int bytes_compl = 0, pkts_compl = 0;
1884 unsigned int entry, count = 0;
1886 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue));
1888 priv->xstats.tx_clean++;
1890 entry = tx_q->dirty_tx;
1891 while ((entry != tx_q->cur_tx) && (count < budget)) {
1892 struct sk_buff *skb = tx_q->tx_skbuff[entry];
1896 if (priv->extend_desc)
1897 p = (struct dma_desc *)(tx_q->dma_etx + entry);
1899 p = tx_q->dma_tx + entry;
1901 status = stmmac_tx_status(priv, &priv->dev->stats,
1902 &priv->xstats, p, priv->ioaddr);
1903 /* Check if the descriptor is owned by the DMA */
1904 if (unlikely(status & tx_dma_own))
1909 /* Make sure descriptor fields are read after reading
1914 /* Just consider the last segment and ...*/
1915 if (likely(!(status & tx_not_ls))) {
1916 /* ... verify the status error condition */
1917 if (unlikely(status & tx_err)) {
1918 priv->dev->stats.tx_errors++;
1920 priv->dev->stats.tx_packets++;
1921 priv->xstats.tx_pkt_n++;
1923 stmmac_get_tx_hwtstamp(priv, p, skb);
1926 if (likely(tx_q->tx_skbuff_dma[entry].buf)) {
1927 if (tx_q->tx_skbuff_dma[entry].map_as_page)
1928 dma_unmap_page(priv->device,
1929 tx_q->tx_skbuff_dma[entry].buf,
1930 tx_q->tx_skbuff_dma[entry].len,
1933 dma_unmap_single(priv->device,
1934 tx_q->tx_skbuff_dma[entry].buf,
1935 tx_q->tx_skbuff_dma[entry].len,
1937 tx_q->tx_skbuff_dma[entry].buf = 0;
1938 tx_q->tx_skbuff_dma[entry].len = 0;
1939 tx_q->tx_skbuff_dma[entry].map_as_page = false;
1942 stmmac_clean_desc3(priv, tx_q, p);
1944 tx_q->tx_skbuff_dma[entry].last_segment = false;
1945 tx_q->tx_skbuff_dma[entry].is_jumbo = false;
1947 if (likely(skb != NULL)) {
1949 bytes_compl += skb->len;
1950 dev_consume_skb_any(skb);
1951 tx_q->tx_skbuff[entry] = NULL;
1954 stmmac_release_tx_desc(priv, p, priv->mode);
1956 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
1958 tx_q->dirty_tx = entry;
1960 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue),
1961 pkts_compl, bytes_compl);
1963 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev,
1965 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) {
1967 netif_dbg(priv, tx_done, priv->dev,
1968 "%s: restart transmit\n", __func__);
1969 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue));
1972 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
1973 stmmac_enable_eee_mode(priv);
1974 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer));
1977 /* We still have pending packets, let's call for a new scheduling */
1978 if (tx_q->dirty_tx != tx_q->cur_tx)
1979 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
1981 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
1987 * stmmac_tx_err - to manage the tx error
1988 * @priv: driver private structure
1989 * @chan: channel index
1990 * Description: it cleans the descriptors and restarts the transmission
1991 * in case of transmission errors.
1993 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
1995 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
1998 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
2000 stmmac_stop_tx_dma(priv, chan);
2001 dma_free_tx_skbufs(priv, chan);
2002 for (i = 0; i < DMA_TX_SIZE; i++)
2003 if (priv->extend_desc)
2004 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic,
2005 priv->mode, (i == DMA_TX_SIZE - 1));
2007 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i],
2008 priv->mode, (i == DMA_TX_SIZE - 1));
2012 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan));
2013 stmmac_start_tx_dma(priv, chan);
2015 priv->dev->stats.tx_errors++;
2016 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan));
2020 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel
2021 * @priv: driver private structure
2022 * @txmode: TX operating mode
2023 * @rxmode: RX operating mode
2024 * @chan: channel index
2025 * Description: it is used for configuring of the DMA operation mode in
2026 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward
2029 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode,
2030 u32 rxmode, u32 chan)
2032 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
2033 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use;
2034 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2035 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2036 int rxfifosz = priv->plat->rx_fifo_size;
2037 int txfifosz = priv->plat->tx_fifo_size;
2040 rxfifosz = priv->dma_cap.rx_fifo_size;
2042 txfifosz = priv->dma_cap.tx_fifo_size;
2044 /* Adjust for real per queue fifo size */
2045 rxfifosz /= rx_channels_count;
2046 txfifosz /= tx_channels_count;
2048 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode);
2049 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode);
2052 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv)
2056 ret = stmmac_safety_feat_irq_status(priv, priv->dev,
2057 priv->ioaddr, priv->dma_cap.asp, &priv->sstats);
2058 if (ret && (ret != -EINVAL)) {
2059 stmmac_global_err(priv);
2066 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan)
2068 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
2069 &priv->xstats, chan);
2070 struct stmmac_channel *ch = &priv->channel[chan];
2072 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) {
2073 if (napi_schedule_prep(&ch->rx_napi)) {
2074 stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
2075 __napi_schedule_irqoff(&ch->rx_napi);
2076 status |= handle_tx;
2080 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use))
2081 napi_schedule_irqoff(&ch->tx_napi);
2087 * stmmac_dma_interrupt - DMA ISR
2088 * @priv: driver private structure
2089 * Description: this is the DMA ISR. It is called by the main ISR.
2090 * It calls the dwmac dma routine and schedule poll method in case of some
2093 static void stmmac_dma_interrupt(struct stmmac_priv *priv)
2095 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2096 u32 rx_channel_count = priv->plat->rx_queues_to_use;
2097 u32 channels_to_check = tx_channel_count > rx_channel_count ?
2098 tx_channel_count : rx_channel_count;
2100 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)];
2102 /* Make sure we never check beyond our status buffer. */
2103 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status)))
2104 channels_to_check = ARRAY_SIZE(status);
2106 for (chan = 0; chan < channels_to_check; chan++)
2107 status[chan] = stmmac_napi_check(priv, chan);
2109 for (chan = 0; chan < tx_channel_count; chan++) {
2110 if (unlikely(status[chan] & tx_hard_error_bump_tc)) {
2111 /* Try to bump up the dma threshold on this failure */
2112 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) &&
2115 if (priv->plat->force_thresh_dma_mode)
2116 stmmac_set_dma_operation_mode(priv,
2121 stmmac_set_dma_operation_mode(priv,
2125 priv->xstats.threshold = tc;
2127 } else if (unlikely(status[chan] == tx_hard_error)) {
2128 stmmac_tx_err(priv, chan);
2134 * stmmac_mmc_setup: setup the Mac Management Counters (MMC)
2135 * @priv: driver private structure
2136 * Description: this masks the MMC irq, in fact, the counters are managed in SW.
2138 static void stmmac_mmc_setup(struct stmmac_priv *priv)
2140 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
2141 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
2143 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
2145 if (priv->dma_cap.rmon) {
2146 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
2147 memset(&priv->mmc, 0, sizeof(struct stmmac_counters));
2149 netdev_info(priv->dev, "No MAC Management Counters available\n");
2153 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register.
2154 * @priv: driver private structure
2156 * new GMAC chip generations have a new register to indicate the
2157 * presence of the optional feature/functions.
2158 * This can be also used to override the value passed through the
2159 * platform and necessary for old MAC10/100 and GMAC chips.
2161 static int stmmac_get_hw_features(struct stmmac_priv *priv)
2163 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0;
2167 * stmmac_check_ether_addr - check if the MAC addr is valid
2168 * @priv: driver private structure
2170 * it is to verify if the MAC address is valid, in case of failures it
2171 * generates a random MAC address
2173 static void stmmac_check_ether_addr(struct stmmac_priv *priv)
2175 if (!is_valid_ether_addr(priv->dev->dev_addr)) {
2176 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0);
2177 if (!is_valid_ether_addr(priv->dev->dev_addr))
2178 eth_hw_addr_random(priv->dev);
2179 dev_info(priv->device, "device MAC address %pM\n",
2180 priv->dev->dev_addr);
2185 * stmmac_init_dma_engine - DMA init.
2186 * @priv: driver private structure
2188 * It inits the DMA invoking the specific MAC/GMAC callback.
2189 * Some DMA parameters can be passed from the platform;
2190 * in case of these are not passed a default is kept for the MAC or GMAC.
2192 static int stmmac_init_dma_engine(struct stmmac_priv *priv)
2194 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2195 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2196 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count);
2197 struct stmmac_rx_queue *rx_q;
2198 struct stmmac_tx_queue *tx_q;
2203 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) {
2204 dev_err(priv->device, "Invalid DMA configuration\n");
2208 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE))
2211 ret = stmmac_reset(priv, priv->ioaddr);
2213 dev_err(priv->device, "Failed to reset the dma\n");
2217 /* DMA Configuration */
2218 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds);
2220 if (priv->plat->axi)
2221 stmmac_axi(priv, priv->ioaddr, priv->plat->axi);
2223 /* DMA CSR Channel configuration */
2224 for (chan = 0; chan < dma_csr_ch; chan++)
2225 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan);
2227 /* DMA RX Channel Configuration */
2228 for (chan = 0; chan < rx_channels_count; chan++) {
2229 rx_q = &priv->rx_queue[chan];
2231 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2232 rx_q->dma_rx_phy, chan);
2234 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
2235 (DMA_RX_SIZE * sizeof(struct dma_desc));
2236 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
2237 rx_q->rx_tail_addr, chan);
2240 /* DMA TX Channel Configuration */
2241 for (chan = 0; chan < tx_channels_count; chan++) {
2242 tx_q = &priv->tx_queue[chan];
2244 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
2245 tx_q->dma_tx_phy, chan);
2247 tx_q->tx_tail_addr = tx_q->dma_tx_phy;
2248 stmmac_set_tx_tail_ptr(priv, priv->ioaddr,
2249 tx_q->tx_tail_addr, chan);
2255 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
2257 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2259 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer));
2263 * stmmac_tx_timer - mitigation sw timer for tx.
2264 * @data: data pointer
2266 * This is the timer handler to directly invoke the stmmac_tx_clean.
2268 static void stmmac_tx_timer(struct timer_list *t)
2270 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer);
2271 struct stmmac_priv *priv = tx_q->priv_data;
2272 struct stmmac_channel *ch;
2274 ch = &priv->channel[tx_q->queue_index];
2277 * If NAPI is already running we can miss some events. Let's rearm
2278 * the timer and try again.
2280 if (likely(napi_schedule_prep(&ch->tx_napi)))
2281 __napi_schedule(&ch->tx_napi);
2283 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10));
2287 * stmmac_init_coalesce - init mitigation options.
2288 * @priv: driver private structure
2290 * This inits the coalesce parameters: i.e. timer rate,
2291 * timer handler and default threshold used for enabling the
2292 * interrupt on completion bit.
2294 static void stmmac_init_coalesce(struct stmmac_priv *priv)
2296 u32 tx_channel_count = priv->plat->tx_queues_to_use;
2299 priv->tx_coal_frames = STMMAC_TX_FRAMES;
2300 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER;
2301 priv->rx_coal_frames = STMMAC_RX_FRAMES;
2303 for (chan = 0; chan < tx_channel_count; chan++) {
2304 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan];
2306 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0);
2310 static void stmmac_set_rings_length(struct stmmac_priv *priv)
2312 u32 rx_channels_count = priv->plat->rx_queues_to_use;
2313 u32 tx_channels_count = priv->plat->tx_queues_to_use;
2316 /* set TX ring length */
2317 for (chan = 0; chan < tx_channels_count; chan++)
2318 stmmac_set_tx_ring_len(priv, priv->ioaddr,
2319 (DMA_TX_SIZE - 1), chan);
2321 /* set RX ring length */
2322 for (chan = 0; chan < rx_channels_count; chan++)
2323 stmmac_set_rx_ring_len(priv, priv->ioaddr,
2324 (DMA_RX_SIZE - 1), chan);
2328 * stmmac_set_tx_queue_weight - Set TX queue weight
2329 * @priv: driver private structure
2330 * Description: It is used for setting TX queues weight
2332 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv)
2334 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2338 for (queue = 0; queue < tx_queues_count; queue++) {
2339 weight = priv->plat->tx_queues_cfg[queue].weight;
2340 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue);
2345 * stmmac_configure_cbs - Configure CBS in TX queue
2346 * @priv: driver private structure
2347 * Description: It is used for configuring CBS in AVB TX queues
2349 static void stmmac_configure_cbs(struct stmmac_priv *priv)
2351 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2355 /* queue 0 is reserved for legacy traffic */
2356 for (queue = 1; queue < tx_queues_count; queue++) {
2357 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use;
2358 if (mode_to_use == MTL_QUEUE_DCB)
2361 stmmac_config_cbs(priv, priv->hw,
2362 priv->plat->tx_queues_cfg[queue].send_slope,
2363 priv->plat->tx_queues_cfg[queue].idle_slope,
2364 priv->plat->tx_queues_cfg[queue].high_credit,
2365 priv->plat->tx_queues_cfg[queue].low_credit,
2371 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel
2372 * @priv: driver private structure
2373 * Description: It is used for mapping RX queues to RX dma channels
2375 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv)
2377 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2381 for (queue = 0; queue < rx_queues_count; queue++) {
2382 chan = priv->plat->rx_queues_cfg[queue].chan;
2383 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan);
2388 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority
2389 * @priv: driver private structure
2390 * Description: It is used for configuring the RX Queue Priority
2392 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv)
2394 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2398 for (queue = 0; queue < rx_queues_count; queue++) {
2399 if (!priv->plat->rx_queues_cfg[queue].use_prio)
2402 prio = priv->plat->rx_queues_cfg[queue].prio;
2403 stmmac_rx_queue_prio(priv, priv->hw, prio, queue);
2408 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority
2409 * @priv: driver private structure
2410 * Description: It is used for configuring the TX Queue Priority
2412 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv)
2414 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2418 for (queue = 0; queue < tx_queues_count; queue++) {
2419 if (!priv->plat->tx_queues_cfg[queue].use_prio)
2422 prio = priv->plat->tx_queues_cfg[queue].prio;
2423 stmmac_tx_queue_prio(priv, priv->hw, prio, queue);
2428 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing
2429 * @priv: driver private structure
2430 * Description: It is used for configuring the RX queue routing
2432 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv)
2434 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2438 for (queue = 0; queue < rx_queues_count; queue++) {
2439 /* no specific packet type routing specified for the queue */
2440 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0)
2443 packet = priv->plat->rx_queues_cfg[queue].pkt_route;
2444 stmmac_rx_queue_routing(priv, priv->hw, packet, queue);
2448 static void stmmac_mac_config_rss(struct stmmac_priv *priv)
2450 if (!priv->dma_cap.rssen || !priv->plat->rss_en) {
2451 priv->rss.enable = false;
2455 if (priv->dev->features & NETIF_F_RXHASH)
2456 priv->rss.enable = true;
2458 priv->rss.enable = false;
2460 stmmac_rss_configure(priv, priv->hw, &priv->rss,
2461 priv->plat->rx_queues_to_use);
2465 * stmmac_mtl_configuration - Configure MTL
2466 * @priv: driver private structure
2467 * Description: It is used for configurring MTL
2469 static void stmmac_mtl_configuration(struct stmmac_priv *priv)
2471 u32 rx_queues_count = priv->plat->rx_queues_to_use;
2472 u32 tx_queues_count = priv->plat->tx_queues_to_use;
2474 if (tx_queues_count > 1)
2475 stmmac_set_tx_queue_weight(priv);
2477 /* Configure MTL RX algorithms */
2478 if (rx_queues_count > 1)
2479 stmmac_prog_mtl_rx_algorithms(priv, priv->hw,
2480 priv->plat->rx_sched_algorithm);
2482 /* Configure MTL TX algorithms */
2483 if (tx_queues_count > 1)
2484 stmmac_prog_mtl_tx_algorithms(priv, priv->hw,
2485 priv->plat->tx_sched_algorithm);
2487 /* Configure CBS in AVB TX queues */
2488 if (tx_queues_count > 1)
2489 stmmac_configure_cbs(priv);
2491 /* Map RX MTL to DMA channels */
2492 stmmac_rx_queue_dma_chan_map(priv);
2494 /* Enable MAC RX Queues */
2495 stmmac_mac_enable_rx_queues(priv);
2497 /* Set RX priorities */
2498 if (rx_queues_count > 1)
2499 stmmac_mac_config_rx_queues_prio(priv);
2501 /* Set TX priorities */
2502 if (tx_queues_count > 1)
2503 stmmac_mac_config_tx_queues_prio(priv);
2505 /* Set RX routing */
2506 if (rx_queues_count > 1)
2507 stmmac_mac_config_rx_queues_routing(priv);
2509 /* Receive Side Scaling */
2510 if (rx_queues_count > 1)
2511 stmmac_mac_config_rss(priv);
2514 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv)
2516 if (priv->dma_cap.asp) {
2517 netdev_info(priv->dev, "Enabling Safety Features\n");
2518 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp);
2520 netdev_info(priv->dev, "No Safety Features support found\n");
2525 * stmmac_hw_setup - setup mac in a usable state.
2526 * @dev : pointer to the device structure.
2528 * this is the main function to setup the HW in a usable state because the
2529 * dma engine is reset, the core registers are configured (e.g. AXI,
2530 * Checksum features, timers). The DMA is ready to start receiving and
2533 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2536 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
2538 struct stmmac_priv *priv = netdev_priv(dev);
2539 u32 rx_cnt = priv->plat->rx_queues_to_use;
2540 u32 tx_cnt = priv->plat->tx_queues_to_use;
2544 /* DMA initialization and SW reset */
2545 ret = stmmac_init_dma_engine(priv);
2547 netdev_err(priv->dev, "%s: DMA engine initialization failed\n",
2552 /* Copy the MAC addr into the HW */
2553 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0);
2555 /* PS and related bits will be programmed according to the speed */
2556 if (priv->hw->pcs) {
2557 int speed = priv->plat->mac_port_sel_speed;
2559 if ((speed == SPEED_10) || (speed == SPEED_100) ||
2560 (speed == SPEED_1000)) {
2561 priv->hw->ps = speed;
2563 dev_warn(priv->device, "invalid port speed\n");
2568 /* Initialize the MAC Core */
2569 stmmac_core_init(priv, priv->hw, dev);
2572 stmmac_mtl_configuration(priv);
2574 /* Initialize Safety Features */
2575 stmmac_safety_feat_configuration(priv);
2577 ret = stmmac_rx_ipc(priv, priv->hw);
2579 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n");
2580 priv->plat->rx_coe = STMMAC_RX_COE_NONE;
2581 priv->hw->rx_csum = 0;
2584 /* Enable the MAC Rx/Tx */
2585 stmmac_mac_set(priv, priv->ioaddr, true);
2587 /* Set the HW DMA mode and the COE */
2588 stmmac_dma_operation_mode(priv);
2590 stmmac_mmc_setup(priv);
2593 ret = clk_prepare_enable(priv->plat->clk_ptp_ref);
2595 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret);
2597 ret = stmmac_init_ptp(priv);
2598 if (ret == -EOPNOTSUPP)
2599 netdev_warn(priv->dev, "PTP not supported by HW\n");
2601 netdev_warn(priv->dev, "PTP init failed\n");
2604 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS;
2606 if (priv->use_riwt) {
2607 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MIN_DMA_RIWT, rx_cnt);
2609 priv->rx_riwt = MIN_DMA_RIWT;
2613 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0);
2615 /* set TX and RX rings length */
2616 stmmac_set_rings_length(priv);
2620 for (chan = 0; chan < tx_cnt; chan++)
2621 stmmac_enable_tso(priv, priv->ioaddr, 1, chan);
2624 /* Enable Split Header */
2625 if (priv->sph && priv->hw->rx_csum) {
2626 for (chan = 0; chan < rx_cnt; chan++)
2627 stmmac_enable_sph(priv, priv->ioaddr, 1, chan);
2630 /* VLAN Tag Insertion */
2631 if (priv->dma_cap.vlins)
2632 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT);
2634 /* Start the ball rolling... */
2635 stmmac_start_all_dma(priv);
2640 static void stmmac_hw_teardown(struct net_device *dev)
2642 struct stmmac_priv *priv = netdev_priv(dev);
2644 clk_disable_unprepare(priv->plat->clk_ptp_ref);
2648 * stmmac_open - open entry point of the driver
2649 * @dev : pointer to the device structure.
2651 * This function is the open entry point of the driver.
2653 * 0 on success and an appropriate (-)ve integer as defined in errno.h
2656 static int stmmac_open(struct net_device *dev)
2658 struct stmmac_priv *priv = netdev_priv(dev);
2662 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
2663 priv->hw->pcs != STMMAC_PCS_TBI &&
2664 priv->hw->pcs != STMMAC_PCS_RTBI) {
2665 ret = stmmac_init_phy(dev);
2667 netdev_err(priv->dev,
2668 "%s: Cannot attach to PHY (error: %d)\n",
2674 /* Extra statistics */
2675 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
2676 priv->xstats.threshold = tc;
2678 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz);
2679 priv->rx_copybreak = STMMAC_RX_COPYBREAK;
2681 ret = alloc_dma_desc_resources(priv);
2683 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n",
2685 goto dma_desc_error;
2688 ret = init_dma_desc_rings(dev, GFP_KERNEL);
2690 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n",
2695 ret = stmmac_hw_setup(dev, true);
2697 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__);
2701 stmmac_init_coalesce(priv);
2703 phylink_start(priv->phylink);
2705 /* Request the IRQ lines */
2706 ret = request_irq(dev->irq, stmmac_interrupt,
2707 IRQF_SHARED, dev->name, dev);
2708 if (unlikely(ret < 0)) {
2709 netdev_err(priv->dev,
2710 "%s: ERROR: allocating the IRQ %d (error: %d)\n",
2711 __func__, dev->irq, ret);
2715 /* Request the Wake IRQ in case of another line is used for WoL */
2716 if (priv->wol_irq != dev->irq) {
2717 ret = request_irq(priv->wol_irq, stmmac_interrupt,
2718 IRQF_SHARED, dev->name, dev);
2719 if (unlikely(ret < 0)) {
2720 netdev_err(priv->dev,
2721 "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
2722 __func__, priv->wol_irq, ret);
2727 /* Request the IRQ lines */
2728 if (priv->lpi_irq > 0) {
2729 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
2731 if (unlikely(ret < 0)) {
2732 netdev_err(priv->dev,
2733 "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
2734 __func__, priv->lpi_irq, ret);
2739 stmmac_enable_all_queues(priv);
2740 stmmac_start_all_queues(priv);
2745 if (priv->wol_irq != dev->irq)
2746 free_irq(priv->wol_irq, dev);
2748 free_irq(dev->irq, dev);
2750 phylink_stop(priv->phylink);
2752 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2753 del_timer_sync(&priv->tx_queue[chan].txtimer);
2755 stmmac_hw_teardown(dev);
2757 free_dma_desc_resources(priv);
2759 phylink_disconnect_phy(priv->phylink);
2764 * stmmac_release - close entry point of the driver
2765 * @dev : device pointer.
2767 * This is the stop entry point of the driver.
2769 static int stmmac_release(struct net_device *dev)
2771 struct stmmac_priv *priv = netdev_priv(dev);
2774 if (priv->eee_enabled)
2775 del_timer_sync(&priv->eee_ctrl_timer);
2777 /* Stop and disconnect the PHY */
2778 phylink_stop(priv->phylink);
2779 phylink_disconnect_phy(priv->phylink);
2781 stmmac_stop_all_queues(priv);
2783 stmmac_disable_all_queues(priv);
2785 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
2786 del_timer_sync(&priv->tx_queue[chan].txtimer);
2788 /* Free the IRQ lines */
2789 free_irq(dev->irq, dev);
2790 if (priv->wol_irq != dev->irq)
2791 free_irq(priv->wol_irq, dev);
2792 if (priv->lpi_irq > 0)
2793 free_irq(priv->lpi_irq, dev);
2795 /* Stop TX/RX DMA and clear the descriptors */
2796 stmmac_stop_all_dma(priv);
2798 /* Release and free the Rx/Tx resources */
2799 free_dma_desc_resources(priv);
2801 /* Disable the MAC Rx/Tx */
2802 stmmac_mac_set(priv, priv->ioaddr, false);
2804 netif_carrier_off(dev);
2806 stmmac_release_ptp(priv);
2811 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb,
2812 struct stmmac_tx_queue *tx_q)
2814 u16 tag = 0x0, inner_tag = 0x0;
2815 u32 inner_type = 0x0;
2818 if (!priv->dma_cap.vlins)
2820 if (!skb_vlan_tag_present(skb))
2822 if (skb->vlan_proto == htons(ETH_P_8021AD)) {
2823 inner_tag = skb_vlan_tag_get(skb);
2824 inner_type = STMMAC_VLAN_INSERT;
2827 tag = skb_vlan_tag_get(skb);
2829 p = tx_q->dma_tx + tx_q->cur_tx;
2830 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type))
2833 stmmac_set_tx_owner(priv, p);
2834 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2839 * stmmac_tso_allocator - close entry point of the driver
2840 * @priv: driver private structure
2841 * @des: buffer start address
2842 * @total_len: total length to fill in descriptors
2843 * @last_segmant: condition for the last descriptor
2844 * @queue: TX queue index
2846 * This function fills descriptor and request new descriptors according to
2847 * buffer length to fill
2849 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
2850 int total_len, bool last_segment, u32 queue)
2852 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
2853 struct dma_desc *desc;
2857 tmp_len = total_len;
2859 while (tmp_len > 0) {
2860 dma_addr_t curr_addr;
2862 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2863 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2864 desc = tx_q->dma_tx + tx_q->cur_tx;
2866 curr_addr = des + (total_len - tmp_len);
2867 if (priv->dma_cap.addr64 <= 32)
2868 desc->des0 = cpu_to_le32(curr_addr);
2870 stmmac_set_desc_addr(priv, desc, curr_addr);
2872 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ?
2873 TSO_MAX_BUFF_SIZE : tmp_len;
2875 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size,
2877 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE),
2880 tmp_len -= TSO_MAX_BUFF_SIZE;
2885 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO)
2886 * @skb : the socket buffer
2887 * @dev : device pointer
2888 * Description: this is the transmit function that is called on TSO frames
2889 * (support available on GMAC4 and newer chips).
2890 * Diagram below show the ring programming in case of TSO frames:
2894 * | DES0 |---> buffer1 = L2/L3/L4 header
2895 * | DES1 |---> TCP Payload (can continue on next descr...)
2896 * | DES2 |---> buffer 1 and 2 len
2897 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0]
2903 * | DES0 | --| Split TCP Payload on Buffers 1 and 2
2905 * | DES2 | --> buffer 1 and 2 len
2909 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field.
2911 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev)
2913 struct dma_desc *desc, *first, *mss_desc = NULL;
2914 struct stmmac_priv *priv = netdev_priv(dev);
2915 int nfrags = skb_shinfo(skb)->nr_frags;
2916 u32 queue = skb_get_queue_mapping(skb);
2917 struct stmmac_tx_queue *tx_q;
2918 unsigned int first_entry;
2919 int tmp_pay_len = 0;
2926 tx_q = &priv->tx_queue[queue];
2928 /* Compute header lengths */
2929 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2931 /* Desc availability based on threshold should be enough safe */
2932 if (unlikely(stmmac_tx_avail(priv, queue) <
2933 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) {
2934 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
2935 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
2937 /* This is a hard error, log it. */
2938 netdev_err(priv->dev,
2939 "%s: Tx Ring full when queue awake\n",
2942 return NETDEV_TX_BUSY;
2945 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */
2947 mss = skb_shinfo(skb)->gso_size;
2949 /* set new MSS value if needed */
2950 if (mss != tx_q->mss) {
2951 mss_desc = tx_q->dma_tx + tx_q->cur_tx;
2952 stmmac_set_mss(priv, mss_desc, mss);
2954 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
2955 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
2958 if (netif_msg_tx_queued(priv)) {
2959 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n",
2960 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss);
2961 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len,
2965 /* Check if VLAN can be inserted by HW */
2966 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
2968 first_entry = tx_q->cur_tx;
2969 WARN_ON(tx_q->tx_skbuff[first_entry]);
2971 desc = tx_q->dma_tx + first_entry;
2975 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
2977 /* first descriptor: fill Headers on Buf1 */
2978 des = dma_map_single(priv->device, skb->data, skb_headlen(skb),
2980 if (dma_mapping_error(priv->device, des))
2983 tx_q->tx_skbuff_dma[first_entry].buf = des;
2984 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb);
2986 if (priv->dma_cap.addr64 <= 32) {
2987 first->des0 = cpu_to_le32(des);
2989 /* Fill start of payload in buff2 of first descriptor */
2991 first->des1 = cpu_to_le32(des + proto_hdr_len);
2993 /* If needed take extra descriptors to fill the remaining payload */
2994 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE;
2996 stmmac_set_desc_addr(priv, first, des);
2997 tmp_pay_len = pay_len;
3000 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue);
3002 /* Prepare fragments */
3003 for (i = 0; i < nfrags; i++) {
3004 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3006 des = skb_frag_dma_map(priv->device, frag, 0,
3007 skb_frag_size(frag),
3009 if (dma_mapping_error(priv->device, des))
3012 stmmac_tso_allocator(priv, des, skb_frag_size(frag),
3013 (i == nfrags - 1), queue);
3015 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des;
3016 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag);
3017 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true;
3020 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true;
3022 /* Only the last descriptor gets to point to the skb. */
3023 tx_q->tx_skbuff[tx_q->cur_tx] = skb;
3025 /* We've used all descriptors we need for this skb, however,
3026 * advance cur_tx so that it references a fresh descriptor.
3027 * ndo_start_xmit will fill this descriptor the next time it's
3028 * called and stmmac_tx_clean may clean up to this descriptor.
3030 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE);
3032 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3033 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3035 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3038 dev->stats.tx_bytes += skb->len;
3039 priv->xstats.tx_tso_frames++;
3040 priv->xstats.tx_tso_nfrags += nfrags;
3042 /* Manage tx mitigation */
3043 tx_q->tx_count_frames += nfrags + 1;
3044 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
3045 !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
3046 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3047 priv->hwts_tx_en)) {
3048 stmmac_tx_timer_arm(priv, queue);
3050 tx_q->tx_count_frames = 0;
3051 stmmac_set_tx_ic(priv, desc);
3052 priv->xstats.tx_set_ic_bit++;
3055 if (priv->sarc_type)
3056 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
3058 skb_tx_timestamp(skb);
3060 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3061 priv->hwts_tx_en)) {
3062 /* declare that device is doing timestamping */
3063 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3064 stmmac_enable_tx_timestamp(priv, first);
3067 /* Complete the first descriptor before granting the DMA */
3068 stmmac_prepare_tso_tx_desc(priv, first, 1,
3071 1, tx_q->tx_skbuff_dma[first_entry].last_segment,
3072 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len));
3074 /* If context desc is used to change MSS */
3076 /* Make sure that first descriptor has been completely
3077 * written, including its own bit. This is because MSS is
3078 * actually before first descriptor, so we need to make
3079 * sure that MSS's own bit is the last thing written.
3082 stmmac_set_tx_owner(priv, mss_desc);
3085 /* The own bit must be the latest setting done when prepare the
3086 * descriptor and then barrier is needed to make sure that
3087 * all is coherent before granting the DMA engine.
3091 if (netif_msg_pktdata(priv)) {
3092 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n",
3093 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3094 tx_q->cur_tx, first, nfrags);
3096 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0);
3098 pr_info(">>> frame to be transmitted: ");
3099 print_pkt(skb->data, skb_headlen(skb));
3102 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3104 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3105 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3107 return NETDEV_TX_OK;
3110 dev_err(priv->device, "Tx dma map failed\n");
3112 priv->dev->stats.tx_dropped++;
3113 return NETDEV_TX_OK;
3117 * stmmac_xmit - Tx entry point of the driver
3118 * @skb : the socket buffer
3119 * @dev : device pointer
3120 * Description : this is the tx entry point of the driver.
3121 * It programs the chain or the ring and supports oversized frames
3124 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
3126 struct stmmac_priv *priv = netdev_priv(dev);
3127 unsigned int nopaged_len = skb_headlen(skb);
3128 int i, csum_insertion = 0, is_jumbo = 0;
3129 u32 queue = skb_get_queue_mapping(skb);
3130 int nfrags = skb_shinfo(skb)->nr_frags;
3131 struct dma_desc *desc, *first;
3132 struct stmmac_tx_queue *tx_q;
3133 unsigned int first_entry;
3134 unsigned int enh_desc;
3139 tx_q = &priv->tx_queue[queue];
3141 if (priv->tx_path_in_lpi_mode)
3142 stmmac_disable_eee_mode(priv);
3144 /* Manage oversized TCP frames for GMAC4 device */
3145 if (skb_is_gso(skb) && priv->tso) {
3146 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6))
3147 return stmmac_tso_xmit(skb, dev);
3150 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) {
3151 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) {
3152 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev,
3154 /* This is a hard error, log it. */
3155 netdev_err(priv->dev,
3156 "%s: Tx Ring full when queue awake\n",
3159 return NETDEV_TX_BUSY;
3162 /* Check if VLAN can be inserted by HW */
3163 has_vlan = stmmac_vlan_insert(priv, skb, tx_q);
3165 entry = tx_q->cur_tx;
3166 first_entry = entry;
3167 WARN_ON(tx_q->tx_skbuff[first_entry]);
3169 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL);
3171 if (likely(priv->extend_desc))
3172 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3174 desc = tx_q->dma_tx + entry;
3179 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT);
3181 enh_desc = priv->plat->enh_desc;
3182 /* To program the descriptors according to the size of the frame */
3184 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc);
3186 if (unlikely(is_jumbo)) {
3187 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion);
3188 if (unlikely(entry < 0) && (entry != -EINVAL))
3192 for (i = 0; i < nfrags; i++) {
3193 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3194 int len = skb_frag_size(frag);
3195 bool last_segment = (i == (nfrags - 1));
3197 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3198 WARN_ON(tx_q->tx_skbuff[entry]);
3200 if (likely(priv->extend_desc))
3201 desc = (struct dma_desc *)(tx_q->dma_etx + entry);
3203 desc = tx_q->dma_tx + entry;
3205 des = skb_frag_dma_map(priv->device, frag, 0, len,
3207 if (dma_mapping_error(priv->device, des))
3208 goto dma_map_err; /* should reuse desc w/o issues */
3210 tx_q->tx_skbuff_dma[entry].buf = des;
3212 stmmac_set_desc_addr(priv, desc, des);
3214 tx_q->tx_skbuff_dma[entry].map_as_page = true;
3215 tx_q->tx_skbuff_dma[entry].len = len;
3216 tx_q->tx_skbuff_dma[entry].last_segment = last_segment;
3218 /* Prepare the descriptor and set the own bit too */
3219 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion,
3220 priv->mode, 1, last_segment, skb->len);
3223 /* Only the last descriptor gets to point to the skb. */
3224 tx_q->tx_skbuff[entry] = skb;
3226 /* We've used all descriptors we need for this skb, however,
3227 * advance cur_tx so that it references a fresh descriptor.
3228 * ndo_start_xmit will fill this descriptor the next time it's
3229 * called and stmmac_tx_clean may clean up to this descriptor.
3231 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE);
3232 tx_q->cur_tx = entry;
3234 if (netif_msg_pktdata(priv)) {
3237 netdev_dbg(priv->dev,
3238 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d",
3239 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry,
3240 entry, first, nfrags);
3242 if (priv->extend_desc)
3243 tx_head = (void *)tx_q->dma_etx;
3245 tx_head = (void *)tx_q->dma_tx;
3247 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false);
3249 netdev_dbg(priv->dev, ">>> frame to be transmitted: ");
3250 print_pkt(skb->data, skb->len);
3253 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
3254 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
3256 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue));
3259 dev->stats.tx_bytes += skb->len;
3261 /* According to the coalesce parameter the IC bit for the latest
3262 * segment is reset and the timer re-started to clean the tx status.
3263 * This approach takes care about the fragments: desc is the first
3264 * element in case of no SG.
3266 tx_q->tx_count_frames += nfrags + 1;
3267 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) &&
3268 !(priv->synopsys_id >= DWMAC_CORE_4_00 &&
3269 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3270 priv->hwts_tx_en)) {
3271 stmmac_tx_timer_arm(priv, queue);
3273 tx_q->tx_count_frames = 0;
3274 stmmac_set_tx_ic(priv, desc);
3275 priv->xstats.tx_set_ic_bit++;
3278 if (priv->sarc_type)
3279 stmmac_set_desc_sarc(priv, first, priv->sarc_type);
3281 skb_tx_timestamp(skb);
3283 /* Ready to fill the first descriptor and set the OWN bit w/o any
3284 * problems because all the descriptors are actually ready to be
3285 * passed to the DMA engine.
3287 if (likely(!is_jumbo)) {
3288 bool last_segment = (nfrags == 0);
3290 des = dma_map_single(priv->device, skb->data,
3291 nopaged_len, DMA_TO_DEVICE);
3292 if (dma_mapping_error(priv->device, des))
3295 tx_q->tx_skbuff_dma[first_entry].buf = des;
3297 stmmac_set_desc_addr(priv, first, des);
3299 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len;
3300 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment;
3302 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
3303 priv->hwts_tx_en)) {
3304 /* declare that device is doing timestamping */
3305 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3306 stmmac_enable_tx_timestamp(priv, first);
3309 /* Prepare the first descriptor setting the OWN bit too */
3310 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len,
3311 csum_insertion, priv->mode, 1, last_segment,
3314 stmmac_set_tx_owner(priv, first);
3317 /* The own bit must be the latest setting done when prepare the
3318 * descriptor and then barrier is needed to make sure that
3319 * all is coherent before granting the DMA engine.
3323 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len);
3325 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3327 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc));
3328 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue);
3330 return NETDEV_TX_OK;
3333 netdev_err(priv->dev, "Tx DMA map failed\n");
3335 priv->dev->stats.tx_dropped++;
3336 return NETDEV_TX_OK;
3339 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb)
3341 struct vlan_ethhdr *veth;
3345 veth = (struct vlan_ethhdr *)skb->data;
3346 vlan_proto = veth->h_vlan_proto;
3348 if ((vlan_proto == htons(ETH_P_8021Q) &&
3349 dev->features & NETIF_F_HW_VLAN_CTAG_RX) ||
3350 (vlan_proto == htons(ETH_P_8021AD) &&
3351 dev->features & NETIF_F_HW_VLAN_STAG_RX)) {
3352 /* pop the vlan tag */
3353 vlanid = ntohs(veth->h_vlan_TCI);
3354 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2);
3355 skb_pull(skb, VLAN_HLEN);
3356 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid);
3361 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q)
3363 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH)
3370 * stmmac_rx_refill - refill used skb preallocated buffers
3371 * @priv: driver private structure
3372 * @queue: RX queue index
3373 * Description : this is to reallocate the skb for the reception process
3374 * that is based on zero-copy.
3376 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
3378 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3379 int len, dirty = stmmac_rx_dirty(priv, queue);
3380 unsigned int entry = rx_q->dirty_rx;
3382 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE;
3384 while (dirty-- > 0) {
3385 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry];
3389 if (priv->extend_desc)
3390 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3392 p = rx_q->dma_rx + entry;
3395 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool);
3400 if (priv->sph && !buf->sec_page) {
3401 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool);
3405 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page);
3407 dma_sync_single_for_device(priv->device, buf->sec_addr,
3408 len, DMA_FROM_DEVICE);
3411 buf->addr = page_pool_get_dma_addr(buf->page);
3413 /* Sync whole allocation to device. This will invalidate old
3416 dma_sync_single_for_device(priv->device, buf->addr, len,
3419 stmmac_set_desc_addr(priv, p, buf->addr);
3420 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr);
3421 stmmac_refill_desc3(priv, rx_q, p);
3423 rx_q->rx_count_frames++;
3424 rx_q->rx_count_frames += priv->rx_coal_frames;
3425 if (rx_q->rx_count_frames > priv->rx_coal_frames)
3426 rx_q->rx_count_frames = 0;
3427 use_rx_wd = priv->use_riwt && rx_q->rx_count_frames;
3430 stmmac_set_rx_owner(priv, p, use_rx_wd);
3432 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE);
3434 rx_q->dirty_rx = entry;
3435 rx_q->rx_tail_addr = rx_q->dma_rx_phy +
3436 (rx_q->dirty_rx * sizeof(struct dma_desc));
3437 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue);
3441 * stmmac_rx - manage the receive process
3442 * @priv: driver private structure
3443 * @limit: napi bugget
3444 * @queue: RX queue index.
3445 * Description : this the function called by the napi poll method.
3446 * It gets all the frames inside the ring.
3448 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
3450 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3451 struct stmmac_channel *ch = &priv->channel[queue];
3452 unsigned int count = 0, error = 0, len = 0;
3453 int status = 0, coe = priv->hw->rx_csum;
3454 unsigned int next_entry = rx_q->cur_rx;
3455 struct sk_buff *skb = NULL;
3457 if (netif_msg_rx_status(priv)) {
3460 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__);
3461 if (priv->extend_desc)
3462 rx_head = (void *)rx_q->dma_erx;
3464 rx_head = (void *)rx_q->dma_rx;
3466 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true);
3468 while (count < limit) {
3469 unsigned int hlen = 0, prev_len = 0;
3470 enum pkt_hash_types hash_type;
3471 struct stmmac_rx_buffer *buf;
3472 struct dma_desc *np, *p;
3473 unsigned int sec_len;
3477 if (!count && rx_q->state_saved) {
3478 skb = rx_q->state.skb;
3479 error = rx_q->state.error;
3480 len = rx_q->state.len;
3482 rx_q->state_saved = false;
3494 buf = &rx_q->buf_pool[entry];
3496 if (priv->extend_desc)
3497 p = (struct dma_desc *)(rx_q->dma_erx + entry);
3499 p = rx_q->dma_rx + entry;
3501 /* read the status of the incoming frame */
3502 status = stmmac_rx_status(priv, &priv->dev->stats,
3504 /* check if managed by the DMA otherwise go ahead */
3505 if (unlikely(status & dma_own))
3510 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE);
3511 next_entry = rx_q->cur_rx;
3513 if (priv->extend_desc)
3514 np = (struct dma_desc *)(rx_q->dma_erx + next_entry);
3516 np = rx_q->dma_rx + next_entry;
3519 prefetch(page_address(buf->page));
3521 if (priv->extend_desc)
3522 stmmac_rx_extended_status(priv, &priv->dev->stats,
3523 &priv->xstats, rx_q->dma_erx + entry);
3524 if (unlikely(status == discard_frame)) {
3525 page_pool_recycle_direct(rx_q->page_pool, buf->page);
3528 if (!priv->hwts_rx_en)
3529 priv->dev->stats.rx_errors++;
3532 if (unlikely(error && (status & rx_not_ls)))
3534 if (unlikely(error)) {
3539 /* Buffer is good. Go on. */
3541 if (likely(status & rx_not_ls)) {
3542 len += priv->dma_buf_sz;
3545 len = stmmac_get_rx_frame_len(priv, p, coe);
3547 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3
3548 * Type frames (LLC/LLC-SNAP)
3550 * llc_snap is never checked in GMAC >= 4, so this ACS
3551 * feature is always disabled and packets need to be
3552 * stripped manually.
3554 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) ||
3555 unlikely(status != llc_snap))
3560 int ret = stmmac_get_rx_header_len(priv, p, &hlen);
3562 if (priv->sph && !ret && (hlen > 0)) {
3564 if (!(status & rx_not_ls))
3565 sec_len = sec_len - hlen;
3568 prefetch(page_address(buf->sec_page));
3569 priv->xstats.rx_split_hdr_pkt_n++;
3572 skb = napi_alloc_skb(&ch->rx_napi, len);
3574 priv->dev->stats.rx_dropped++;
3578 dma_sync_single_for_cpu(priv->device, buf->addr, len,
3580 skb_copy_to_linear_data(skb, page_address(buf->page),
3584 /* Data payload copied into SKB, page ready for recycle */
3585 page_pool_recycle_direct(rx_q->page_pool, buf->page);
3588 unsigned int buf_len = len - prev_len;
3590 if (likely(status & rx_not_ls))
3591 buf_len = priv->dma_buf_sz;
3593 dma_sync_single_for_cpu(priv->device, buf->addr,
3594 buf_len, DMA_FROM_DEVICE);
3595 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
3596 buf->page, 0, buf_len,
3599 /* Data payload appended into SKB */
3600 page_pool_release_page(rx_q->page_pool, buf->page);
3605 dma_sync_single_for_cpu(priv->device, buf->sec_addr,
3606 sec_len, DMA_FROM_DEVICE);
3607 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
3608 buf->sec_page, 0, sec_len,
3613 /* Data payload appended into SKB */
3614 page_pool_release_page(rx_q->page_pool, buf->sec_page);
3615 buf->sec_page = NULL;
3618 if (likely(status & rx_not_ls))
3621 /* Got entire packet into SKB. Finish it. */
3623 stmmac_get_rx_hwtstamp(priv, p, np, skb);
3624 stmmac_rx_vlan(priv->dev, skb);
3625 skb->protocol = eth_type_trans(skb, priv->dev);
3628 skb_checksum_none_assert(skb);
3630 skb->ip_summed = CHECKSUM_UNNECESSARY;
3632 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type))
3633 skb_set_hash(skb, hash, hash_type);
3635 skb_record_rx_queue(skb, queue);
3636 napi_gro_receive(&ch->rx_napi, skb);
3638 priv->dev->stats.rx_packets++;
3639 priv->dev->stats.rx_bytes += len;
3642 if (status & rx_not_ls) {
3643 rx_q->state_saved = true;
3644 rx_q->state.skb = skb;
3645 rx_q->state.error = error;
3646 rx_q->state.len = len;
3649 stmmac_rx_refill(priv, queue);
3651 priv->xstats.rx_pkt_n += count;
3656 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget)
3658 struct stmmac_channel *ch =
3659 container_of(napi, struct stmmac_channel, rx_napi);
3660 struct stmmac_priv *priv = ch->priv_data;
3661 u32 chan = ch->index;
3664 priv->xstats.napi_poll++;
3666 work_done = stmmac_rx(priv, budget, chan);
3667 if (work_done < budget && napi_complete_done(napi, work_done))
3668 stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
3672 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget)
3674 struct stmmac_channel *ch =
3675 container_of(napi, struct stmmac_channel, tx_napi);
3676 struct stmmac_priv *priv = ch->priv_data;
3677 struct stmmac_tx_queue *tx_q;
3678 u32 chan = ch->index;
3681 priv->xstats.napi_poll++;
3683 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan);
3684 work_done = min(work_done, budget);
3686 if (work_done < budget)
3687 napi_complete_done(napi, work_done);
3689 /* Force transmission restart */
3690 tx_q = &priv->tx_queue[chan];
3691 if (tx_q->cur_tx != tx_q->dirty_tx) {
3692 stmmac_enable_dma_transmission(priv, priv->ioaddr);
3693 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr,
3702 * @dev : Pointer to net device structure
3703 * Description: this function is called when a packet transmission fails to
3704 * complete within a reasonable time. The driver will mark the error in the
3705 * netdev structure and arrange for the device to be reset to a sane state
3706 * in order to transmit a new packet.
3708 static void stmmac_tx_timeout(struct net_device *dev)
3710 struct stmmac_priv *priv = netdev_priv(dev);
3712 stmmac_global_err(priv);
3716 * stmmac_set_rx_mode - entry point for multicast addressing
3717 * @dev : pointer to the device structure
3719 * This function is a driver entry point which gets called by the kernel
3720 * whenever multicast addresses must be enabled/disabled.
3724 static void stmmac_set_rx_mode(struct net_device *dev)
3726 struct stmmac_priv *priv = netdev_priv(dev);
3728 stmmac_set_filter(priv, priv->hw, dev);
3732 * stmmac_change_mtu - entry point to change MTU size for the device.
3733 * @dev : device pointer.
3734 * @new_mtu : the new MTU size for the device.
3735 * Description: the Maximum Transfer Unit (MTU) is used by the network layer
3736 * to drive packet transmission. Ethernet has an MTU of 1500 octets
3737 * (ETH_DATA_LEN). This value can be changed with ifconfig.
3739 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3742 static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
3744 struct stmmac_priv *priv = netdev_priv(dev);
3746 if (netif_running(dev)) {
3747 netdev_err(priv->dev, "must be stopped to change its MTU\n");
3753 netdev_update_features(dev);
3758 static netdev_features_t stmmac_fix_features(struct net_device *dev,
3759 netdev_features_t features)
3761 struct stmmac_priv *priv = netdev_priv(dev);
3763 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE)
3764 features &= ~NETIF_F_RXCSUM;
3766 if (!priv->plat->tx_coe)
3767 features &= ~NETIF_F_CSUM_MASK;
3769 /* Some GMAC devices have a bugged Jumbo frame support that
3770 * needs to have the Tx COE disabled for oversized frames
3771 * (due to limited buffer sizes). In this case we disable
3772 * the TX csum insertion in the TDES and not use SF.
3774 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN))
3775 features &= ~NETIF_F_CSUM_MASK;
3777 /* Disable tso if asked by ethtool */
3778 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
3779 if (features & NETIF_F_TSO)
3788 static int stmmac_set_features(struct net_device *netdev,
3789 netdev_features_t features)
3791 struct stmmac_priv *priv = netdev_priv(netdev);
3795 /* Keep the COE Type in case of csum is supporting */
3796 if (features & NETIF_F_RXCSUM)
3797 priv->hw->rx_csum = priv->plat->rx_coe;
3799 priv->hw->rx_csum = 0;
3800 /* No check needed because rx_coe has been set before and it will be
3801 * fixed in case of issue.
3803 stmmac_rx_ipc(priv, priv->hw);
3805 sph_en = (priv->hw->rx_csum > 0) && priv->sph;
3806 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++)
3807 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan);
3813 * stmmac_interrupt - main ISR
3814 * @irq: interrupt number.
3815 * @dev_id: to pass the net device pointer.
3816 * Description: this is the main driver interrupt service routine.
3818 * o DMA service routine (to manage incoming frame reception and transmission
3820 * o Core interrupts to manage: remote wake-up, management counter, LPI
3823 static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
3825 struct net_device *dev = (struct net_device *)dev_id;
3826 struct stmmac_priv *priv = netdev_priv(dev);
3827 u32 rx_cnt = priv->plat->rx_queues_to_use;
3828 u32 tx_cnt = priv->plat->tx_queues_to_use;
3833 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
3834 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
3837 pm_wakeup_event(priv->device, 0);
3839 if (unlikely(!dev)) {
3840 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__);
3844 /* Check if adapter is up */
3845 if (test_bit(STMMAC_DOWN, &priv->state))
3847 /* Check if a fatal error happened */
3848 if (stmmac_safety_feat_interrupt(priv))
3851 /* To handle GMAC own interrupts */
3852 if ((priv->plat->has_gmac) || xmac) {
3853 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);
3856 if (unlikely(status)) {
3857 /* For LPI we need to save the tx status */
3858 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE)
3859 priv->tx_path_in_lpi_mode = true;
3860 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE)
3861 priv->tx_path_in_lpi_mode = false;
3864 for (queue = 0; queue < queues_count; queue++) {
3865 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
3867 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw,
3869 if (mtl_status != -EINVAL)
3870 status |= mtl_status;
3872 if (status & CORE_IRQ_MTL_RX_OVERFLOW)
3873 stmmac_set_rx_tail_ptr(priv, priv->ioaddr,
3878 /* PCS link status */
3879 if (priv->hw->pcs) {
3880 if (priv->xstats.pcs_link)
3881 netif_carrier_on(dev);
3883 netif_carrier_off(dev);
3887 /* To handle DMA interrupts */
3888 stmmac_dma_interrupt(priv);
3893 #ifdef CONFIG_NET_POLL_CONTROLLER
3894 /* Polling receive - used by NETCONSOLE and other diagnostic tools
3895 * to allow network I/O with interrupts disabled.
3897 static void stmmac_poll_controller(struct net_device *dev)
3899 disable_irq(dev->irq);
3900 stmmac_interrupt(dev->irq, dev);
3901 enable_irq(dev->irq);
3906 * stmmac_ioctl - Entry point for the Ioctl
3907 * @dev: Device pointer.
3908 * @rq: An IOCTL specefic structure, that can contain a pointer to
3909 * a proprietary structure used to pass information to the driver.
3910 * @cmd: IOCTL command
3912 * Currently it supports the phy_mii_ioctl(...) and HW time stamping.
3914 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3916 struct stmmac_priv *priv = netdev_priv (dev);
3917 int ret = -EOPNOTSUPP;
3919 if (!netif_running(dev))
3926 ret = phylink_mii_ioctl(priv->phylink, rq, cmd);
3929 ret = stmmac_hwtstamp_set(dev, rq);
3932 ret = stmmac_hwtstamp_get(dev, rq);
3941 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3944 struct stmmac_priv *priv = cb_priv;
3945 int ret = -EOPNOTSUPP;
3947 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data))
3950 stmmac_disable_all_queues(priv);
3953 case TC_SETUP_CLSU32:
3954 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data);
3956 case TC_SETUP_CLSFLOWER:
3957 ret = stmmac_tc_setup_cls(priv, priv, type_data);
3963 stmmac_enable_all_queues(priv);
3967 static LIST_HEAD(stmmac_block_cb_list);
3969 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type,
3972 struct stmmac_priv *priv = netdev_priv(ndev);
3975 case TC_SETUP_BLOCK:
3976 return flow_block_cb_setup_simple(type_data,
3977 &stmmac_block_cb_list,
3978 stmmac_setup_tc_block_cb,
3980 case TC_SETUP_QDISC_CBS:
3981 return stmmac_tc_setup_cbs(priv, priv, type_data);
3987 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb,
3988 struct net_device *sb_dev)
3990 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3992 * There is no way to determine the number of TSO
3993 * capable Queues. Let's use always the Queue 0
3994 * because if TSO is supported then at least this
3995 * one will be capable.
4000 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues;
4003 static int stmmac_set_mac_address(struct net_device *ndev, void *addr)
4005 struct stmmac_priv *priv = netdev_priv(ndev);
4008 ret = eth_mac_addr(ndev, addr);
4012 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0);
4017 #ifdef CONFIG_DEBUG_FS
4018 static struct dentry *stmmac_fs_dir;
4020 static void sysfs_display_ring(void *head, int size, int extend_desc,
4021 struct seq_file *seq)
4024 struct dma_extended_desc *ep = (struct dma_extended_desc *)head;
4025 struct dma_desc *p = (struct dma_desc *)head;
4027 for (i = 0; i < size; i++) {
4029 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
4030 i, (unsigned int)virt_to_phys(ep),
4031 le32_to_cpu(ep->basic.des0),
4032 le32_to_cpu(ep->basic.des1),
4033 le32_to_cpu(ep->basic.des2),
4034 le32_to_cpu(ep->basic.des3));
4037 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n",
4038 i, (unsigned int)virt_to_phys(p),
4039 le32_to_cpu(p->des0), le32_to_cpu(p->des1),
4040 le32_to_cpu(p->des2), le32_to_cpu(p->des3));
4043 seq_printf(seq, "\n");
4047 static int stmmac_rings_status_show(struct seq_file *seq, void *v)
4049 struct net_device *dev = seq->private;
4050 struct stmmac_priv *priv = netdev_priv(dev);
4051 u32 rx_count = priv->plat->rx_queues_to_use;
4052 u32 tx_count = priv->plat->tx_queues_to_use;
4055 if ((dev->flags & IFF_UP) == 0)
4058 for (queue = 0; queue < rx_count; queue++) {
4059 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4061 seq_printf(seq, "RX Queue %d:\n", queue);
4063 if (priv->extend_desc) {
4064 seq_printf(seq, "Extended descriptor ring:\n");
4065 sysfs_display_ring((void *)rx_q->dma_erx,
4066 DMA_RX_SIZE, 1, seq);
4068 seq_printf(seq, "Descriptor ring:\n");
4069 sysfs_display_ring((void *)rx_q->dma_rx,
4070 DMA_RX_SIZE, 0, seq);
4074 for (queue = 0; queue < tx_count; queue++) {
4075 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4077 seq_printf(seq, "TX Queue %d:\n", queue);
4079 if (priv->extend_desc) {
4080 seq_printf(seq, "Extended descriptor ring:\n");
4081 sysfs_display_ring((void *)tx_q->dma_etx,
4082 DMA_TX_SIZE, 1, seq);
4084 seq_printf(seq, "Descriptor ring:\n");
4085 sysfs_display_ring((void *)tx_q->dma_tx,
4086 DMA_TX_SIZE, 0, seq);
4092 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status);
4094 static int stmmac_dma_cap_show(struct seq_file *seq, void *v)
4096 struct net_device *dev = seq->private;
4097 struct stmmac_priv *priv = netdev_priv(dev);
4099 if (!priv->hw_cap_support) {
4100 seq_printf(seq, "DMA HW features not supported\n");
4104 seq_printf(seq, "==============================\n");
4105 seq_printf(seq, "\tDMA HW features\n");
4106 seq_printf(seq, "==============================\n");
4108 seq_printf(seq, "\t10/100 Mbps: %s\n",
4109 (priv->dma_cap.mbps_10_100) ? "Y" : "N");
4110 seq_printf(seq, "\t1000 Mbps: %s\n",
4111 (priv->dma_cap.mbps_1000) ? "Y" : "N");
4112 seq_printf(seq, "\tHalf duplex: %s\n",
4113 (priv->dma_cap.half_duplex) ? "Y" : "N");
4114 seq_printf(seq, "\tHash Filter: %s\n",
4115 (priv->dma_cap.hash_filter) ? "Y" : "N");
4116 seq_printf(seq, "\tMultiple MAC address registers: %s\n",
4117 (priv->dma_cap.multi_addr) ? "Y" : "N");
4118 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n",
4119 (priv->dma_cap.pcs) ? "Y" : "N");
4120 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n",
4121 (priv->dma_cap.sma_mdio) ? "Y" : "N");
4122 seq_printf(seq, "\tPMT Remote wake up: %s\n",
4123 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N");
4124 seq_printf(seq, "\tPMT Magic Frame: %s\n",
4125 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N");
4126 seq_printf(seq, "\tRMON module: %s\n",
4127 (priv->dma_cap.rmon) ? "Y" : "N");
4128 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n",
4129 (priv->dma_cap.time_stamp) ? "Y" : "N");
4130 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n",
4131 (priv->dma_cap.atime_stamp) ? "Y" : "N");
4132 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n",
4133 (priv->dma_cap.eee) ? "Y" : "N");
4134 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N");
4135 seq_printf(seq, "\tChecksum Offload in TX: %s\n",
4136 (priv->dma_cap.tx_coe) ? "Y" : "N");
4137 if (priv->synopsys_id >= DWMAC_CORE_4_00) {
4138 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n",
4139 (priv->dma_cap.rx_coe) ? "Y" : "N");
4141 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n",
4142 (priv->dma_cap.rx_coe_type1) ? "Y" : "N");
4143 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n",
4144 (priv->dma_cap.rx_coe_type2) ? "Y" : "N");
4146 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n",
4147 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N");
4148 seq_printf(seq, "\tNumber of Additional RX channel: %d\n",
4149 priv->dma_cap.number_rx_channel);
4150 seq_printf(seq, "\tNumber of Additional TX channel: %d\n",
4151 priv->dma_cap.number_tx_channel);
4152 seq_printf(seq, "\tEnhanced descriptors: %s\n",
4153 (priv->dma_cap.enh_desc) ? "Y" : "N");
4157 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap);
4159 static void stmmac_init_fs(struct net_device *dev)
4161 struct stmmac_priv *priv = netdev_priv(dev);
4163 /* Create per netdev entries */
4164 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
4166 /* Entry to report DMA RX/TX rings */
4167 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev,
4168 &stmmac_rings_status_fops);
4170 /* Entry to report the DMA HW features */
4171 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev,
4172 &stmmac_dma_cap_fops);
4175 static void stmmac_exit_fs(struct net_device *dev)
4177 struct stmmac_priv *priv = netdev_priv(dev);
4179 debugfs_remove_recursive(priv->dbgfs_dir);
4181 #endif /* CONFIG_DEBUG_FS */
4183 static u32 stmmac_vid_crc32_le(__le16 vid_le)
4185 unsigned char *data = (unsigned char *)&vid_le;
4186 unsigned char data_byte = 0;
4191 bits = get_bitmask_order(VLAN_VID_MASK);
4192 for (i = 0; i < bits; i++) {
4194 data_byte = data[i / 8];
4196 temp = ((crc & 1) ^ data_byte) & 1;
4207 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double)
4212 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) {
4213 __le16 vid_le = cpu_to_le16(vid);
4214 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28;
4218 return stmmac_update_vlan_hash(priv, priv->hw, hash, is_double);
4221 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid)
4223 struct stmmac_priv *priv = netdev_priv(ndev);
4224 bool is_double = false;
4227 if (!priv->dma_cap.vlhash)
4229 if (be16_to_cpu(proto) == ETH_P_8021AD)
4232 set_bit(vid, priv->active_vlans);
4233 ret = stmmac_vlan_update(priv, is_double);
4235 clear_bit(vid, priv->active_vlans);
4242 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid)
4244 struct stmmac_priv *priv = netdev_priv(ndev);
4245 bool is_double = false;
4247 if (!priv->dma_cap.vlhash)
4249 if (be16_to_cpu(proto) == ETH_P_8021AD)
4252 clear_bit(vid, priv->active_vlans);
4253 return stmmac_vlan_update(priv, is_double);
4256 static const struct net_device_ops stmmac_netdev_ops = {
4257 .ndo_open = stmmac_open,
4258 .ndo_start_xmit = stmmac_xmit,
4259 .ndo_stop = stmmac_release,
4260 .ndo_change_mtu = stmmac_change_mtu,
4261 .ndo_fix_features = stmmac_fix_features,
4262 .ndo_set_features = stmmac_set_features,
4263 .ndo_set_rx_mode = stmmac_set_rx_mode,
4264 .ndo_tx_timeout = stmmac_tx_timeout,
4265 .ndo_do_ioctl = stmmac_ioctl,
4266 .ndo_setup_tc = stmmac_setup_tc,
4267 .ndo_select_queue = stmmac_select_queue,
4268 #ifdef CONFIG_NET_POLL_CONTROLLER
4269 .ndo_poll_controller = stmmac_poll_controller,
4271 .ndo_set_mac_address = stmmac_set_mac_address,
4272 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid,
4273 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid,
4276 static void stmmac_reset_subtask(struct stmmac_priv *priv)
4278 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state))
4280 if (test_bit(STMMAC_DOWN, &priv->state))
4283 netdev_err(priv->dev, "Reset adapter.\n");
4286 netif_trans_update(priv->dev);
4287 while (test_and_set_bit(STMMAC_RESETING, &priv->state))
4288 usleep_range(1000, 2000);
4290 set_bit(STMMAC_DOWN, &priv->state);
4291 dev_close(priv->dev);
4292 dev_open(priv->dev, NULL);
4293 clear_bit(STMMAC_DOWN, &priv->state);
4294 clear_bit(STMMAC_RESETING, &priv->state);
4298 static void stmmac_service_task(struct work_struct *work)
4300 struct stmmac_priv *priv = container_of(work, struct stmmac_priv,
4303 stmmac_reset_subtask(priv);
4304 clear_bit(STMMAC_SERVICE_SCHED, &priv->state);
4308 * stmmac_hw_init - Init the MAC device
4309 * @priv: driver private structure
4310 * Description: this function is to configure the MAC device according to
4311 * some platform parameters or the HW capability register. It prepares the
4312 * driver to use either ring or chain modes and to setup either enhanced or
4313 * normal descriptors.
4315 static int stmmac_hw_init(struct stmmac_priv *priv)
4319 /* dwmac-sun8i only work in chain mode */
4320 if (priv->plat->has_sun8i)
4322 priv->chain_mode = chain_mode;
4324 /* Initialize HW Interface */
4325 ret = stmmac_hwif_init(priv);
4329 /* Get the HW capability (new GMAC newer than 3.50a) */
4330 priv->hw_cap_support = stmmac_get_hw_features(priv);
4331 if (priv->hw_cap_support) {
4332 dev_info(priv->device, "DMA HW capability register supported\n");
4334 /* We can override some gmac/dma configuration fields: e.g.
4335 * enh_desc, tx_coe (e.g. that are passed through the
4336 * platform) with the values from the HW capability
4337 * register (if supported).
4339 priv->plat->enh_desc = priv->dma_cap.enh_desc;
4340 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up;
4341 priv->hw->pmt = priv->plat->pmt;
4342 if (priv->dma_cap.hash_tb_sz) {
4343 priv->hw->multicast_filter_bins =
4344 (BIT(priv->dma_cap.hash_tb_sz) << 5);
4345 priv->hw->mcast_bits_log2 =
4346 ilog2(priv->hw->multicast_filter_bins);
4349 /* TXCOE doesn't work in thresh DMA mode */
4350 if (priv->plat->force_thresh_dma_mode)
4351 priv->plat->tx_coe = 0;
4353 priv->plat->tx_coe = priv->dma_cap.tx_coe;
4355 /* In case of GMAC4 rx_coe is from HW cap register. */
4356 priv->plat->rx_coe = priv->dma_cap.rx_coe;
4358 if (priv->dma_cap.rx_coe_type2)
4359 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2;
4360 else if (priv->dma_cap.rx_coe_type1)
4361 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1;
4364 dev_info(priv->device, "No HW DMA feature register supported\n");
4367 if (priv->plat->rx_coe) {
4368 priv->hw->rx_csum = priv->plat->rx_coe;
4369 dev_info(priv->device, "RX Checksum Offload Engine supported\n");
4370 if (priv->synopsys_id < DWMAC_CORE_4_00)
4371 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum);
4373 if (priv->plat->tx_coe)
4374 dev_info(priv->device, "TX Checksum insertion supported\n");
4376 if (priv->plat->pmt) {
4377 dev_info(priv->device, "Wake-Up On Lan supported\n");
4378 device_set_wakeup_capable(priv->device, 1);
4381 if (priv->dma_cap.tsoen)
4382 dev_info(priv->device, "TSO supported\n");
4384 /* Run HW quirks, if any */
4385 if (priv->hwif_quirks) {
4386 ret = priv->hwif_quirks(priv);
4391 /* Rx Watchdog is available in the COREs newer than the 3.40.
4392 * In some case, for example on bugged HW this feature
4393 * has to be disable and this can be done by passing the
4394 * riwt_off field from the platform.
4396 if (((priv->synopsys_id >= DWMAC_CORE_3_50) ||
4397 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) {
4399 dev_info(priv->device,
4400 "Enable RX Mitigation via HW Watchdog Timer\n");
4408 * @device: device pointer
4409 * @plat_dat: platform data pointer
4410 * @res: stmmac resource pointer
4411 * Description: this is the main probe function used to
4412 * call the alloc_etherdev, allocate the priv structure.
4414 * returns 0 on success, otherwise errno.
4416 int stmmac_dvr_probe(struct device *device,
4417 struct plat_stmmacenet_data *plat_dat,
4418 struct stmmac_resources *res)
4420 struct net_device *ndev = NULL;
4421 struct stmmac_priv *priv;
4422 u32 queue, rxq, maxq;
4425 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv),
4426 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES);
4430 SET_NETDEV_DEV(ndev, device);
4432 priv = netdev_priv(ndev);
4433 priv->device = device;
4436 stmmac_set_ethtool_ops(ndev);
4437 priv->pause = pause;
4438 priv->plat = plat_dat;
4439 priv->ioaddr = res->addr;
4440 priv->dev->base_addr = (unsigned long)res->addr;
4442 priv->dev->irq = res->irq;
4443 priv->wol_irq = res->wol_irq;
4444 priv->lpi_irq = res->lpi_irq;
4446 if (!IS_ERR_OR_NULL(res->mac))
4447 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN);
4449 dev_set_drvdata(device, priv->dev);
4451 /* Verify driver arguments */
4452 stmmac_verify_args();
4454 /* Allocate workqueue */
4455 priv->wq = create_singlethread_workqueue("stmmac_wq");
4457 dev_err(priv->device, "failed to create workqueue\n");
4461 INIT_WORK(&priv->service_task, stmmac_service_task);
4463 /* Override with kernel parameters if supplied XXX CRS XXX
4464 * this needs to have multiple instances
4466 if ((phyaddr >= 0) && (phyaddr <= 31))
4467 priv->plat->phy_addr = phyaddr;
4469 if (priv->plat->stmmac_rst) {
4470 ret = reset_control_assert(priv->plat->stmmac_rst);
4471 reset_control_deassert(priv->plat->stmmac_rst);
4472 /* Some reset controllers have only reset callback instead of
4473 * assert + deassert callbacks pair.
4475 if (ret == -ENOTSUPP)
4476 reset_control_reset(priv->plat->stmmac_rst);
4479 /* Init MAC and get the capabilities */
4480 ret = stmmac_hw_init(priv);
4484 stmmac_check_ether_addr(priv);
4486 /* Configure real RX and TX queues */
4487 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use);
4488 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use);
4490 ndev->netdev_ops = &stmmac_netdev_ops;
4492 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4495 ret = stmmac_tc_init(priv, priv);
4497 ndev->hw_features |= NETIF_F_HW_TC;
4500 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) {
4501 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
4503 dev_info(priv->device, "TSO feature enabled\n");
4506 if (priv->dma_cap.sphen) {
4507 ndev->hw_features |= NETIF_F_GRO;
4509 dev_info(priv->device, "SPH feature enabled\n");
4512 if (priv->dma_cap.addr64) {
4513 ret = dma_set_mask_and_coherent(device,
4514 DMA_BIT_MASK(priv->dma_cap.addr64));
4516 dev_info(priv->device, "Using %d bits DMA width\n",
4517 priv->dma_cap.addr64);
4519 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32));
4521 dev_err(priv->device, "Failed to set DMA Mask\n");
4525 priv->dma_cap.addr64 = 32;
4529 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
4530 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
4531 #ifdef STMMAC_VLAN_TAG_USED
4532 /* Both mac100 and gmac support receive VLAN tag detection */
4533 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
4534 if (priv->dma_cap.vlhash) {
4535 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4536 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4538 if (priv->dma_cap.vlins) {
4539 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
4540 if (priv->dma_cap.dvlan)
4541 ndev->features |= NETIF_F_HW_VLAN_STAG_TX;
4544 priv->msg_enable = netif_msg_init(debug, default_msg_level);
4546 /* Initialize RSS */
4547 rxq = priv->plat->rx_queues_to_use;
4548 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key));
4549 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
4550 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq);
4552 if (priv->dma_cap.rssen && priv->plat->rss_en)
4553 ndev->features |= NETIF_F_RXHASH;
4555 /* MTU range: 46 - hw-specific max */
4556 ndev->min_mtu = ETH_ZLEN - ETH_HLEN;
4557 if (priv->plat->has_xgmac)
4558 ndev->max_mtu = XGMAC_JUMBO_LEN;
4559 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00))
4560 ndev->max_mtu = JUMBO_LEN;
4562 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
4563 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu
4564 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range.
4566 if ((priv->plat->maxmtu < ndev->max_mtu) &&
4567 (priv->plat->maxmtu >= ndev->min_mtu))
4568 ndev->max_mtu = priv->plat->maxmtu;
4569 else if (priv->plat->maxmtu < ndev->min_mtu)
4570 dev_warn(priv->device,
4571 "%s: warning: maxmtu having invalid value (%d)\n",
4572 __func__, priv->plat->maxmtu);
4575 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */
4577 /* Setup channels NAPI */
4578 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
4580 for (queue = 0; queue < maxq; queue++) {
4581 struct stmmac_channel *ch = &priv->channel[queue];
4583 ch->priv_data = priv;
4586 if (queue < priv->plat->rx_queues_to_use) {
4587 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx,
4590 if (queue < priv->plat->tx_queues_to_use) {
4591 netif_tx_napi_add(ndev, &ch->tx_napi,
4592 stmmac_napi_poll_tx,
4597 mutex_init(&priv->lock);
4599 /* If a specific clk_csr value is passed from the platform
4600 * this means that the CSR Clock Range selection cannot be
4601 * changed at run-time and it is fixed. Viceversa the driver'll try to
4602 * set the MDC clock dynamically according to the csr actual
4605 if (priv->plat->clk_csr >= 0)
4606 priv->clk_csr = priv->plat->clk_csr;
4608 stmmac_clk_csr_set(priv);
4610 stmmac_check_pcs_mode(priv);
4612 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4613 priv->hw->pcs != STMMAC_PCS_TBI &&
4614 priv->hw->pcs != STMMAC_PCS_RTBI) {
4615 /* MDIO bus Registration */
4616 ret = stmmac_mdio_register(ndev);
4618 dev_err(priv->device,
4619 "%s: MDIO bus (id: %d) registration failed",
4620 __func__, priv->plat->bus_id);
4621 goto error_mdio_register;
4625 ret = stmmac_phy_setup(priv);
4627 netdev_err(ndev, "failed to setup phy (%d)\n", ret);
4628 goto error_phy_setup;
4631 ret = register_netdev(ndev);
4633 dev_err(priv->device, "%s: ERROR %i registering the device\n",
4635 goto error_netdev_register;
4638 #ifdef CONFIG_DEBUG_FS
4639 stmmac_init_fs(ndev);
4644 error_netdev_register:
4645 phylink_destroy(priv->phylink);
4647 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4648 priv->hw->pcs != STMMAC_PCS_TBI &&
4649 priv->hw->pcs != STMMAC_PCS_RTBI)
4650 stmmac_mdio_unregister(ndev);
4651 error_mdio_register:
4652 for (queue = 0; queue < maxq; queue++) {
4653 struct stmmac_channel *ch = &priv->channel[queue];
4655 if (queue < priv->plat->rx_queues_to_use)
4656 netif_napi_del(&ch->rx_napi);
4657 if (queue < priv->plat->tx_queues_to_use)
4658 netif_napi_del(&ch->tx_napi);
4661 destroy_workqueue(priv->wq);
4665 EXPORT_SYMBOL_GPL(stmmac_dvr_probe);
4669 * @dev: device pointer
4670 * Description: this function resets the TX/RX processes, disables the MAC RX/TX
4671 * changes the link status, releases the DMA descriptor rings.
4673 int stmmac_dvr_remove(struct device *dev)
4675 struct net_device *ndev = dev_get_drvdata(dev);
4676 struct stmmac_priv *priv = netdev_priv(ndev);
4678 netdev_info(priv->dev, "%s: removing driver", __func__);
4680 #ifdef CONFIG_DEBUG_FS
4681 stmmac_exit_fs(ndev);
4683 stmmac_stop_all_dma(priv);
4685 stmmac_mac_set(priv, priv->ioaddr, false);
4686 netif_carrier_off(ndev);
4687 unregister_netdev(ndev);
4688 phylink_destroy(priv->phylink);
4689 if (priv->plat->stmmac_rst)
4690 reset_control_assert(priv->plat->stmmac_rst);
4691 clk_disable_unprepare(priv->plat->pclk);
4692 clk_disable_unprepare(priv->plat->stmmac_clk);
4693 if (priv->hw->pcs != STMMAC_PCS_RGMII &&
4694 priv->hw->pcs != STMMAC_PCS_TBI &&
4695 priv->hw->pcs != STMMAC_PCS_RTBI)
4696 stmmac_mdio_unregister(ndev);
4697 destroy_workqueue(priv->wq);
4698 mutex_destroy(&priv->lock);
4702 EXPORT_SYMBOL_GPL(stmmac_dvr_remove);
4705 * stmmac_suspend - suspend callback
4706 * @dev: device pointer
4707 * Description: this is the function to suspend the device and it is called
4708 * by the platform driver to stop the network queue, release the resources,
4709 * program the PMT register (for WoL), clean and release driver resources.
4711 int stmmac_suspend(struct device *dev)
4713 struct net_device *ndev = dev_get_drvdata(dev);
4714 struct stmmac_priv *priv = netdev_priv(ndev);
4716 if (!ndev || !netif_running(ndev))
4719 mutex_lock(&priv->lock);
4721 phylink_mac_change(priv->phylink, false);
4723 netif_device_detach(ndev);
4724 stmmac_stop_all_queues(priv);
4726 stmmac_disable_all_queues(priv);
4728 /* Stop TX/RX DMA */
4729 stmmac_stop_all_dma(priv);
4731 /* Enable Power down mode by programming the PMT regs */
4732 if (device_may_wakeup(priv->device)) {
4733 stmmac_pmt(priv, priv->hw, priv->wolopts);
4737 phylink_stop(priv->phylink);
4740 stmmac_mac_set(priv, priv->ioaddr, false);
4741 pinctrl_pm_select_sleep_state(priv->device);
4742 /* Disable clock in case of PWM is off */
4743 clk_disable(priv->plat->pclk);
4744 clk_disable(priv->plat->stmmac_clk);
4746 mutex_unlock(&priv->lock);
4748 priv->speed = SPEED_UNKNOWN;
4751 EXPORT_SYMBOL_GPL(stmmac_suspend);
4754 * stmmac_reset_queues_param - reset queue parameters
4755 * @dev: device pointer
4757 static void stmmac_reset_queues_param(struct stmmac_priv *priv)
4759 u32 rx_cnt = priv->plat->rx_queues_to_use;
4760 u32 tx_cnt = priv->plat->tx_queues_to_use;
4763 for (queue = 0; queue < rx_cnt; queue++) {
4764 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue];
4770 for (queue = 0; queue < tx_cnt; queue++) {
4771 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue];
4780 * stmmac_resume - resume callback
4781 * @dev: device pointer
4782 * Description: when resume this function is invoked to setup the DMA and CORE
4783 * in a usable state.
4785 int stmmac_resume(struct device *dev)
4787 struct net_device *ndev = dev_get_drvdata(dev);
4788 struct stmmac_priv *priv = netdev_priv(ndev);
4790 if (!netif_running(ndev))
4793 /* Power Down bit, into the PM register, is cleared
4794 * automatically as soon as a magic packet or a Wake-up frame
4795 * is received. Anyway, it's better to manually clear
4796 * this bit because it can generate problems while resuming
4797 * from another devices (e.g. serial console).
4799 if (device_may_wakeup(priv->device)) {
4800 mutex_lock(&priv->lock);
4801 stmmac_pmt(priv, priv->hw, 0);
4802 mutex_unlock(&priv->lock);
4805 pinctrl_pm_select_default_state(priv->device);
4806 /* enable the clk previously disabled */
4807 clk_enable(priv->plat->stmmac_clk);
4808 clk_enable(priv->plat->pclk);
4809 /* reset the phy so that it's ready */
4811 stmmac_mdio_reset(priv->mii);
4814 netif_device_attach(ndev);
4816 mutex_lock(&priv->lock);
4818 stmmac_reset_queues_param(priv);
4820 stmmac_clear_descriptors(priv);
4822 stmmac_hw_setup(ndev, false);
4823 stmmac_init_coalesce(priv);
4824 stmmac_set_rx_mode(ndev);
4826 stmmac_enable_all_queues(priv);
4828 stmmac_start_all_queues(priv);
4830 if (!device_may_wakeup(priv->device)) {
4832 phylink_start(priv->phylink);
4836 phylink_mac_change(priv->phylink, true);
4838 mutex_unlock(&priv->lock);
4842 EXPORT_SYMBOL_GPL(stmmac_resume);
4845 static int __init stmmac_cmdline_opt(char *str)
4851 while ((opt = strsep(&str, ",")) != NULL) {
4852 if (!strncmp(opt, "debug:", 6)) {
4853 if (kstrtoint(opt + 6, 0, &debug))
4855 } else if (!strncmp(opt, "phyaddr:", 8)) {
4856 if (kstrtoint(opt + 8, 0, &phyaddr))
4858 } else if (!strncmp(opt, "buf_sz:", 7)) {
4859 if (kstrtoint(opt + 7, 0, &buf_sz))
4861 } else if (!strncmp(opt, "tc:", 3)) {
4862 if (kstrtoint(opt + 3, 0, &tc))
4864 } else if (!strncmp(opt, "watchdog:", 9)) {
4865 if (kstrtoint(opt + 9, 0, &watchdog))
4867 } else if (!strncmp(opt, "flow_ctrl:", 10)) {
4868 if (kstrtoint(opt + 10, 0, &flow_ctrl))
4870 } else if (!strncmp(opt, "pause:", 6)) {
4871 if (kstrtoint(opt + 6, 0, &pause))
4873 } else if (!strncmp(opt, "eee_timer:", 10)) {
4874 if (kstrtoint(opt + 10, 0, &eee_timer))
4876 } else if (!strncmp(opt, "chain_mode:", 11)) {
4877 if (kstrtoint(opt + 11, 0, &chain_mode))
4884 pr_err("%s: ERROR broken module parameter conversion", __func__);
4888 __setup("stmmaceth=", stmmac_cmdline_opt);
4891 static int __init stmmac_init(void)
4893 #ifdef CONFIG_DEBUG_FS
4894 /* Create debugfs main directory if it doesn't exist yet */
4896 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
4902 static void __exit stmmac_exit(void)
4904 #ifdef CONFIG_DEBUG_FS
4905 debugfs_remove_recursive(stmmac_fs_dir);
4909 module_init(stmmac_init)
4910 module_exit(stmmac_exit)
4912 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver");
4913 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>");
4914 MODULE_LICENSE("GPL");