1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9 *******************************************************************************/
11 #include <linux/etherdevice.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/mii.h>
15 #include <linux/phy.h>
16 #include <linux/net_tstamp.h>
20 #include "dwmac_dma.h"
22 #define REG_SPACE_SIZE 0x1060
23 #define MAC100_ETHTOOL_NAME "st_mac100"
24 #define GMAC_ETHTOOL_NAME "st_gmac"
26 #define ETHTOOL_DMA_OFFSET 55
29 char stat_string[ETH_GSTRING_LEN];
34 #define STMMAC_STAT(m) \
35 { #m, FIELD_SIZEOF(struct stmmac_extra_stats, m), \
36 offsetof(struct stmmac_priv, xstats.m)}
38 static const struct stmmac_stats stmmac_gstrings_stats[] = {
40 STMMAC_STAT(tx_underflow),
41 STMMAC_STAT(tx_carrier),
42 STMMAC_STAT(tx_losscarrier),
43 STMMAC_STAT(vlan_tag),
44 STMMAC_STAT(tx_deferred),
46 STMMAC_STAT(tx_jabber),
47 STMMAC_STAT(tx_frame_flushed),
48 STMMAC_STAT(tx_payload_error),
49 STMMAC_STAT(tx_ip_header_error),
52 STMMAC_STAT(sa_filter_fail),
53 STMMAC_STAT(overflow_error),
54 STMMAC_STAT(ipc_csum_error),
55 STMMAC_STAT(rx_collision),
56 STMMAC_STAT(rx_crc_errors),
57 STMMAC_STAT(dribbling_bit),
58 STMMAC_STAT(rx_length),
60 STMMAC_STAT(rx_multicast),
61 STMMAC_STAT(rx_gmac_overflow),
62 STMMAC_STAT(rx_watchdog),
63 STMMAC_STAT(da_rx_filter_fail),
64 STMMAC_STAT(sa_rx_filter_fail),
65 STMMAC_STAT(rx_missed_cntr),
66 STMMAC_STAT(rx_overflow_cntr),
68 /* Tx/Rx IRQ error info */
69 STMMAC_STAT(tx_undeflow_irq),
70 STMMAC_STAT(tx_process_stopped_irq),
71 STMMAC_STAT(tx_jabber_irq),
72 STMMAC_STAT(rx_overflow_irq),
73 STMMAC_STAT(rx_buf_unav_irq),
74 STMMAC_STAT(rx_process_stopped_irq),
75 STMMAC_STAT(rx_watchdog_irq),
76 STMMAC_STAT(tx_early_irq),
77 STMMAC_STAT(fatal_bus_error_irq),
78 /* Tx/Rx IRQ Events */
79 STMMAC_STAT(rx_early_irq),
80 STMMAC_STAT(threshold),
81 STMMAC_STAT(tx_pkt_n),
82 STMMAC_STAT(rx_pkt_n),
83 STMMAC_STAT(normal_irq_n),
84 STMMAC_STAT(rx_normal_irq_n),
85 STMMAC_STAT(napi_poll),
86 STMMAC_STAT(tx_normal_irq_n),
87 STMMAC_STAT(tx_clean),
88 STMMAC_STAT(tx_set_ic_bit),
89 STMMAC_STAT(irq_receive_pmt_irq_n),
91 STMMAC_STAT(mmc_tx_irq_n),
92 STMMAC_STAT(mmc_rx_irq_n),
93 STMMAC_STAT(mmc_rx_csum_offload_irq_n),
95 STMMAC_STAT(irq_tx_path_in_lpi_mode_n),
96 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n),
97 STMMAC_STAT(irq_rx_path_in_lpi_mode_n),
98 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n),
99 STMMAC_STAT(phy_eee_wakeup_error_n),
100 /* Extended RDES status */
101 STMMAC_STAT(ip_hdr_err),
102 STMMAC_STAT(ip_payload_err),
103 STMMAC_STAT(ip_csum_bypassed),
104 STMMAC_STAT(ipv4_pkt_rcvd),
105 STMMAC_STAT(ipv6_pkt_rcvd),
106 STMMAC_STAT(no_ptp_rx_msg_type_ext),
107 STMMAC_STAT(ptp_rx_msg_type_sync),
108 STMMAC_STAT(ptp_rx_msg_type_follow_up),
109 STMMAC_STAT(ptp_rx_msg_type_delay_req),
110 STMMAC_STAT(ptp_rx_msg_type_delay_resp),
111 STMMAC_STAT(ptp_rx_msg_type_pdelay_req),
112 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp),
113 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up),
114 STMMAC_STAT(ptp_rx_msg_type_announce),
115 STMMAC_STAT(ptp_rx_msg_type_management),
116 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type),
117 STMMAC_STAT(ptp_frame_type),
118 STMMAC_STAT(ptp_ver),
119 STMMAC_STAT(timestamp_dropped),
120 STMMAC_STAT(av_pkt_rcvd),
121 STMMAC_STAT(av_tagged_pkt_rcvd),
122 STMMAC_STAT(vlan_tag_priority_val),
123 STMMAC_STAT(l3_filter_match),
124 STMMAC_STAT(l4_filter_match),
125 STMMAC_STAT(l3_l4_filter_no_match),
127 STMMAC_STAT(irq_pcs_ane_n),
128 STMMAC_STAT(irq_pcs_link_n),
129 STMMAC_STAT(irq_rgmii_n),
131 STMMAC_STAT(mtl_tx_status_fifo_full),
132 STMMAC_STAT(mtl_tx_fifo_not_empty),
133 STMMAC_STAT(mmtl_fifo_ctrl),
134 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write),
135 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait),
136 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read),
137 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle),
138 STMMAC_STAT(mac_tx_in_pause),
139 STMMAC_STAT(mac_tx_frame_ctrl_xfer),
140 STMMAC_STAT(mac_tx_frame_ctrl_idle),
141 STMMAC_STAT(mac_tx_frame_ctrl_wait),
142 STMMAC_STAT(mac_tx_frame_ctrl_pause),
143 STMMAC_STAT(mac_gmii_tx_proto_engine),
144 STMMAC_STAT(mtl_rx_fifo_fill_level_full),
145 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh),
146 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh),
147 STMMAC_STAT(mtl_rx_fifo_fill_level_empty),
148 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush),
149 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data),
150 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status),
151 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle),
152 STMMAC_STAT(mtl_rx_fifo_ctrl_active),
153 STMMAC_STAT(mac_rx_frame_ctrl_fifo),
154 STMMAC_STAT(mac_gmii_rx_proto_engine),
156 STMMAC_STAT(tx_tso_frames),
157 STMMAC_STAT(tx_tso_nfrags),
159 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
161 /* HW MAC Management counters (if supported) */
162 #define STMMAC_MMC_STAT(m) \
163 { #m, FIELD_SIZEOF(struct stmmac_counters, m), \
164 offsetof(struct stmmac_priv, mmc.m)}
166 static const struct stmmac_stats stmmac_mmc[] = {
167 STMMAC_MMC_STAT(mmc_tx_octetcount_gb),
168 STMMAC_MMC_STAT(mmc_tx_framecount_gb),
169 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g),
170 STMMAC_MMC_STAT(mmc_tx_multicastframe_g),
171 STMMAC_MMC_STAT(mmc_tx_64_octets_gb),
172 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb),
173 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb),
174 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb),
175 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb),
176 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb),
177 STMMAC_MMC_STAT(mmc_tx_unicast_gb),
178 STMMAC_MMC_STAT(mmc_tx_multicast_gb),
179 STMMAC_MMC_STAT(mmc_tx_broadcast_gb),
180 STMMAC_MMC_STAT(mmc_tx_underflow_error),
181 STMMAC_MMC_STAT(mmc_tx_singlecol_g),
182 STMMAC_MMC_STAT(mmc_tx_multicol_g),
183 STMMAC_MMC_STAT(mmc_tx_deferred),
184 STMMAC_MMC_STAT(mmc_tx_latecol),
185 STMMAC_MMC_STAT(mmc_tx_exesscol),
186 STMMAC_MMC_STAT(mmc_tx_carrier_error),
187 STMMAC_MMC_STAT(mmc_tx_octetcount_g),
188 STMMAC_MMC_STAT(mmc_tx_framecount_g),
189 STMMAC_MMC_STAT(mmc_tx_excessdef),
190 STMMAC_MMC_STAT(mmc_tx_pause_frame),
191 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g),
192 STMMAC_MMC_STAT(mmc_rx_framecount_gb),
193 STMMAC_MMC_STAT(mmc_rx_octetcount_gb),
194 STMMAC_MMC_STAT(mmc_rx_octetcount_g),
195 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g),
196 STMMAC_MMC_STAT(mmc_rx_multicastframe_g),
197 STMMAC_MMC_STAT(mmc_rx_crc_error),
198 STMMAC_MMC_STAT(mmc_rx_align_error),
199 STMMAC_MMC_STAT(mmc_rx_run_error),
200 STMMAC_MMC_STAT(mmc_rx_jabber_error),
201 STMMAC_MMC_STAT(mmc_rx_undersize_g),
202 STMMAC_MMC_STAT(mmc_rx_oversize_g),
203 STMMAC_MMC_STAT(mmc_rx_64_octets_gb),
204 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb),
205 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb),
206 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb),
207 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb),
208 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb),
209 STMMAC_MMC_STAT(mmc_rx_unicast_g),
210 STMMAC_MMC_STAT(mmc_rx_length_error),
211 STMMAC_MMC_STAT(mmc_rx_autofrangetype),
212 STMMAC_MMC_STAT(mmc_rx_pause_frames),
213 STMMAC_MMC_STAT(mmc_rx_fifo_overflow),
214 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb),
215 STMMAC_MMC_STAT(mmc_rx_watchdog_error),
216 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask),
217 STMMAC_MMC_STAT(mmc_rx_ipc_intr),
218 STMMAC_MMC_STAT(mmc_rx_ipv4_gd),
219 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr),
220 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay),
221 STMMAC_MMC_STAT(mmc_rx_ipv4_frag),
222 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl),
223 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets),
224 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets),
225 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets),
226 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets),
227 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets),
228 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets),
229 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets),
230 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets),
231 STMMAC_MMC_STAT(mmc_rx_ipv6_gd),
232 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr),
233 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay),
234 STMMAC_MMC_STAT(mmc_rx_udp_gd),
235 STMMAC_MMC_STAT(mmc_rx_udp_err),
236 STMMAC_MMC_STAT(mmc_rx_tcp_gd),
237 STMMAC_MMC_STAT(mmc_rx_tcp_err),
238 STMMAC_MMC_STAT(mmc_rx_icmp_gd),
239 STMMAC_MMC_STAT(mmc_rx_icmp_err),
240 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets),
241 STMMAC_MMC_STAT(mmc_rx_udp_err_octets),
242 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets),
243 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets),
244 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets),
245 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets),
247 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc)
249 static void stmmac_ethtool_getdrvinfo(struct net_device *dev,
250 struct ethtool_drvinfo *info)
252 struct stmmac_priv *priv = netdev_priv(dev);
254 if (priv->plat->has_gmac || priv->plat->has_gmac4)
255 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver));
257 strlcpy(info->driver, MAC100_ETHTOOL_NAME,
258 sizeof(info->driver));
260 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
263 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev,
264 struct ethtool_link_ksettings *cmd)
266 struct stmmac_priv *priv = netdev_priv(dev);
267 struct phy_device *phy = dev->phydev;
269 if (priv->hw->pcs & STMMAC_PCS_RGMII ||
270 priv->hw->pcs & STMMAC_PCS_SGMII) {
271 struct rgmii_adv adv;
272 u32 supported, advertising, lp_advertising;
274 if (!priv->xstats.pcs_link) {
275 cmd->base.speed = SPEED_UNKNOWN;
276 cmd->base.duplex = DUPLEX_UNKNOWN;
279 cmd->base.duplex = priv->xstats.pcs_duplex;
281 cmd->base.speed = priv->xstats.pcs_speed;
283 /* Get and convert ADV/LP_ADV from the HW AN registers */
284 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv))
285 return -EOPNOTSUPP; /* should never happen indeed */
287 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */
289 ethtool_convert_link_mode_to_legacy_u32(
290 &supported, cmd->link_modes.supported);
291 ethtool_convert_link_mode_to_legacy_u32(
292 &advertising, cmd->link_modes.advertising);
293 ethtool_convert_link_mode_to_legacy_u32(
294 &lp_advertising, cmd->link_modes.lp_advertising);
296 if (adv.pause & STMMAC_PCS_PAUSE)
297 advertising |= ADVERTISED_Pause;
298 if (adv.pause & STMMAC_PCS_ASYM_PAUSE)
299 advertising |= ADVERTISED_Asym_Pause;
300 if (adv.lp_pause & STMMAC_PCS_PAUSE)
301 lp_advertising |= ADVERTISED_Pause;
302 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE)
303 lp_advertising |= ADVERTISED_Asym_Pause;
305 /* Reg49[3] always set because ANE is always supported */
306 cmd->base.autoneg = ADVERTISED_Autoneg;
307 supported |= SUPPORTED_Autoneg;
308 advertising |= ADVERTISED_Autoneg;
309 lp_advertising |= ADVERTISED_Autoneg;
312 supported |= (SUPPORTED_1000baseT_Full |
313 SUPPORTED_100baseT_Full |
314 SUPPORTED_10baseT_Full);
315 advertising |= (ADVERTISED_1000baseT_Full |
316 ADVERTISED_100baseT_Full |
317 ADVERTISED_10baseT_Full);
319 supported |= (SUPPORTED_1000baseT_Half |
320 SUPPORTED_100baseT_Half |
321 SUPPORTED_10baseT_Half);
322 advertising |= (ADVERTISED_1000baseT_Half |
323 ADVERTISED_100baseT_Half |
324 ADVERTISED_10baseT_Half);
327 lp_advertising |= (ADVERTISED_1000baseT_Full |
328 ADVERTISED_100baseT_Full |
329 ADVERTISED_10baseT_Full);
331 lp_advertising |= (ADVERTISED_1000baseT_Half |
332 ADVERTISED_100baseT_Half |
333 ADVERTISED_10baseT_Half);
334 cmd->base.port = PORT_OTHER;
336 ethtool_convert_legacy_u32_to_link_mode(
337 cmd->link_modes.supported, supported);
338 ethtool_convert_legacy_u32_to_link_mode(
339 cmd->link_modes.advertising, advertising);
340 ethtool_convert_legacy_u32_to_link_mode(
341 cmd->link_modes.lp_advertising, lp_advertising);
347 pr_err("%s: %s: PHY is not registered\n",
348 __func__, dev->name);
351 if (!netif_running(dev)) {
352 pr_err("%s: interface is disabled: we cannot track "
353 "link speed / duplex setting\n", dev->name);
356 phy_ethtool_ksettings_get(phy, cmd);
361 stmmac_ethtool_set_link_ksettings(struct net_device *dev,
362 const struct ethtool_link_ksettings *cmd)
364 struct stmmac_priv *priv = netdev_priv(dev);
365 struct phy_device *phy = dev->phydev;
368 if (priv->hw->pcs & STMMAC_PCS_RGMII ||
369 priv->hw->pcs & STMMAC_PCS_SGMII) {
370 u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause;
372 /* Only support ANE */
373 if (cmd->base.autoneg != AUTONEG_ENABLE)
376 mask &= (ADVERTISED_1000baseT_Half |
377 ADVERTISED_1000baseT_Full |
378 ADVERTISED_100baseT_Half |
379 ADVERTISED_100baseT_Full |
380 ADVERTISED_10baseT_Half |
381 ADVERTISED_10baseT_Full);
383 mutex_lock(&priv->lock);
384 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
385 mutex_unlock(&priv->lock);
390 rc = phy_ethtool_ksettings_set(phy, cmd);
395 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev)
397 struct stmmac_priv *priv = netdev_priv(dev);
398 return priv->msg_enable;
401 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)
403 struct stmmac_priv *priv = netdev_priv(dev);
404 priv->msg_enable = level;
408 static int stmmac_check_if_running(struct net_device *dev)
410 if (!netif_running(dev))
415 static int stmmac_ethtool_get_regs_len(struct net_device *dev)
417 return REG_SPACE_SIZE;
420 static void stmmac_ethtool_gregs(struct net_device *dev,
421 struct ethtool_regs *regs, void *space)
423 u32 *reg_space = (u32 *) space;
425 struct stmmac_priv *priv = netdev_priv(dev);
427 memset(reg_space, 0x0, REG_SPACE_SIZE);
429 stmmac_dump_mac_regs(priv, priv->hw, reg_space);
430 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space);
431 /* Copy DMA registers to where ethtool expects them */
432 memcpy(®_space[ETHTOOL_DMA_OFFSET], ®_space[DMA_BUS_MODE / 4],
433 NUM_DWMAC1000_DMA_REGS * 4);
437 stmmac_get_pauseparam(struct net_device *netdev,
438 struct ethtool_pauseparam *pause)
440 struct stmmac_priv *priv = netdev_priv(netdev);
441 struct rgmii_adv adv_lp;
446 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
451 if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
452 netdev->phydev->supported) ||
453 !linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
454 netdev->phydev->supported))
458 pause->autoneg = netdev->phydev->autoneg;
460 if (priv->flow_ctrl & FLOW_RX)
462 if (priv->flow_ctrl & FLOW_TX)
468 stmmac_set_pauseparam(struct net_device *netdev,
469 struct ethtool_pauseparam *pause)
471 struct stmmac_priv *priv = netdev_priv(netdev);
472 u32 tx_cnt = priv->plat->tx_queues_to_use;
473 struct phy_device *phy = netdev->phydev;
474 int new_pause = FLOW_OFF;
475 struct rgmii_adv adv_lp;
477 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
482 if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
484 !linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
490 new_pause |= FLOW_RX;
492 new_pause |= FLOW_TX;
494 priv->flow_ctrl = new_pause;
495 phy->autoneg = pause->autoneg;
498 if (netif_running(netdev))
499 return phy_start_aneg(phy);
502 stmmac_flow_ctrl(priv, priv->hw, phy->duplex, priv->flow_ctrl,
503 priv->pause, tx_cnt);
507 static void stmmac_get_ethtool_stats(struct net_device *dev,
508 struct ethtool_stats *dummy, u64 *data)
510 struct stmmac_priv *priv = netdev_priv(dev);
511 u32 rx_queues_count = priv->plat->rx_queues_to_use;
512 u32 tx_queues_count = priv->plat->tx_queues_to_use;
516 if (priv->dma_cap.asp) {
517 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
518 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i,
524 /* Update the DMA HW counters for dwmac10/100 */
525 ret = stmmac_dma_diagnostic_fr(priv, &dev->stats, (void *) &priv->xstats,
528 /* If supported, for new GMAC chips expose the MMC counters */
529 if (priv->dma_cap.rmon) {
530 dwmac_mmc_read(priv->mmcaddr, &priv->mmc);
532 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
534 p = (char *)priv + stmmac_mmc[i].stat_offset;
536 data[j++] = (stmmac_mmc[i].sizeof_stat ==
537 sizeof(u64)) ? (*(u64 *)p) :
541 if (priv->eee_enabled) {
542 int val = phy_get_eee_err(dev->phydev);
544 priv->xstats.phy_eee_wakeup_error_n = val;
547 if (priv->synopsys_id >= DWMAC_CORE_3_50)
548 stmmac_mac_debug(priv, priv->ioaddr,
549 (void *)&priv->xstats,
550 rx_queues_count, tx_queues_count);
552 for (i = 0; i < STMMAC_STATS_LEN; i++) {
553 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
554 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat ==
555 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p);
559 static int stmmac_get_sset_count(struct net_device *netdev, int sset)
561 struct stmmac_priv *priv = netdev_priv(netdev);
562 int i, len, safety_len = 0;
566 len = STMMAC_STATS_LEN;
568 if (priv->dma_cap.rmon)
569 len += STMMAC_MMC_STATS_LEN;
570 if (priv->dma_cap.asp) {
571 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
572 if (!stmmac_safety_feat_dump(priv,
587 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
591 struct stmmac_priv *priv = netdev_priv(dev);
595 if (priv->dma_cap.asp) {
596 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
598 if (!stmmac_safety_feat_dump(priv,
601 memcpy(p, desc, ETH_GSTRING_LEN);
602 p += ETH_GSTRING_LEN;
606 if (priv->dma_cap.rmon)
607 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
608 memcpy(p, stmmac_mmc[i].stat_string,
610 p += ETH_GSTRING_LEN;
612 for (i = 0; i < STMMAC_STATS_LEN; i++) {
613 memcpy(p, stmmac_gstrings_stats[i].stat_string,
615 p += ETH_GSTRING_LEN;
624 /* Currently only support WOL through Magic packet. */
625 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
627 struct stmmac_priv *priv = netdev_priv(dev);
629 mutex_lock(&priv->lock);
630 if (device_can_wakeup(priv->device)) {
631 wol->supported = WAKE_MAGIC | WAKE_UCAST;
632 wol->wolopts = priv->wolopts;
634 mutex_unlock(&priv->lock);
637 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
639 struct stmmac_priv *priv = netdev_priv(dev);
640 u32 support = WAKE_MAGIC | WAKE_UCAST;
642 /* By default almost all GMAC devices support the WoL via
643 * magic frame but we can disable it if the HW capability
644 * register shows no support for pmt_magic_frame. */
645 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame))
646 wol->wolopts &= ~WAKE_MAGIC;
648 if (!device_can_wakeup(priv->device))
651 if (wol->wolopts & ~support)
655 pr_info("stmmac: wakeup enable\n");
656 device_set_wakeup_enable(priv->device, 1);
657 enable_irq_wake(priv->wol_irq);
659 device_set_wakeup_enable(priv->device, 0);
660 disable_irq_wake(priv->wol_irq);
663 mutex_lock(&priv->lock);
664 priv->wolopts = wol->wolopts;
665 mutex_unlock(&priv->lock);
670 static int stmmac_ethtool_op_get_eee(struct net_device *dev,
671 struct ethtool_eee *edata)
673 struct stmmac_priv *priv = netdev_priv(dev);
675 if (!priv->dma_cap.eee)
678 edata->eee_enabled = priv->eee_enabled;
679 edata->eee_active = priv->eee_active;
680 edata->tx_lpi_timer = priv->tx_lpi_timer;
682 return phy_ethtool_get_eee(dev->phydev, edata);
685 static int stmmac_ethtool_op_set_eee(struct net_device *dev,
686 struct ethtool_eee *edata)
688 struct stmmac_priv *priv = netdev_priv(dev);
691 if (!edata->eee_enabled) {
692 stmmac_disable_eee_mode(priv);
694 /* We are asking for enabling the EEE but it is safe
695 * to verify all by invoking the eee_init function.
696 * In case of failure it will return an error.
698 edata->eee_enabled = stmmac_eee_init(priv);
699 if (!edata->eee_enabled)
703 ret = phy_ethtool_set_eee(dev->phydev, edata);
707 priv->eee_enabled = edata->eee_enabled;
708 priv->tx_lpi_timer = edata->tx_lpi_timer;
712 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv)
714 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
717 clk = priv->plat->clk_ref_rate;
722 return (usec * (clk / 1000000)) / 256;
725 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv)
727 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
730 clk = priv->plat->clk_ref_rate;
735 return (riwt * 256) / (clk / 1000000);
738 static int stmmac_get_coalesce(struct net_device *dev,
739 struct ethtool_coalesce *ec)
741 struct stmmac_priv *priv = netdev_priv(dev);
743 ec->tx_coalesce_usecs = priv->tx_coal_timer;
744 ec->tx_max_coalesced_frames = priv->tx_coal_frames;
747 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt, priv);
752 static int stmmac_set_coalesce(struct net_device *dev,
753 struct ethtool_coalesce *ec)
755 struct stmmac_priv *priv = netdev_priv(dev);
756 u32 rx_cnt = priv->plat->rx_queues_to_use;
757 unsigned int rx_riwt;
759 /* Check not supported parameters */
760 if ((ec->rx_max_coalesced_frames) || (ec->rx_coalesce_usecs_irq) ||
761 (ec->rx_max_coalesced_frames_irq) || (ec->tx_coalesce_usecs_irq) ||
762 (ec->use_adaptive_rx_coalesce) || (ec->use_adaptive_tx_coalesce) ||
763 (ec->pkt_rate_low) || (ec->rx_coalesce_usecs_low) ||
764 (ec->rx_max_coalesced_frames_low) || (ec->tx_coalesce_usecs_high) ||
765 (ec->tx_max_coalesced_frames_low) || (ec->pkt_rate_high) ||
766 (ec->tx_coalesce_usecs_low) || (ec->rx_coalesce_usecs_high) ||
767 (ec->rx_max_coalesced_frames_high) ||
768 (ec->tx_max_coalesced_frames_irq) ||
769 (ec->stats_block_coalesce_usecs) ||
770 (ec->tx_max_coalesced_frames_high) || (ec->rate_sample_interval))
773 if (ec->rx_coalesce_usecs == 0)
776 if ((ec->tx_coalesce_usecs == 0) &&
777 (ec->tx_max_coalesced_frames == 0))
780 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) ||
781 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES))
784 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv);
786 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT))
788 else if (!priv->use_riwt)
791 /* Only copy relevant parameters, ignore all others. */
792 priv->tx_coal_frames = ec->tx_max_coalesced_frames;
793 priv->tx_coal_timer = ec->tx_coalesce_usecs;
794 priv->rx_riwt = rx_riwt;
795 stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt);
800 static int stmmac_get_ts_info(struct net_device *dev,
801 struct ethtool_ts_info *info)
803 struct stmmac_priv *priv = netdev_priv(dev);
805 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) {
807 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
808 SOF_TIMESTAMPING_TX_HARDWARE |
809 SOF_TIMESTAMPING_RX_SOFTWARE |
810 SOF_TIMESTAMPING_RX_HARDWARE |
811 SOF_TIMESTAMPING_SOFTWARE |
812 SOF_TIMESTAMPING_RAW_HARDWARE;
815 info->phc_index = ptp_clock_index(priv->ptp_clock);
817 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
819 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) |
820 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
821 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
822 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
823 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
824 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
825 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
826 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
827 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
828 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
829 (1 << HWTSTAMP_FILTER_ALL));
832 return ethtool_op_get_ts_info(dev, info);
835 static int stmmac_get_tunable(struct net_device *dev,
836 const struct ethtool_tunable *tuna, void *data)
838 struct stmmac_priv *priv = netdev_priv(dev);
842 case ETHTOOL_RX_COPYBREAK:
843 *(u32 *)data = priv->rx_copybreak;
853 static int stmmac_set_tunable(struct net_device *dev,
854 const struct ethtool_tunable *tuna,
857 struct stmmac_priv *priv = netdev_priv(dev);
861 case ETHTOOL_RX_COPYBREAK:
862 priv->rx_copybreak = *(u32 *)data;
872 static const struct ethtool_ops stmmac_ethtool_ops = {
873 .begin = stmmac_check_if_running,
874 .get_drvinfo = stmmac_ethtool_getdrvinfo,
875 .get_msglevel = stmmac_ethtool_getmsglevel,
876 .set_msglevel = stmmac_ethtool_setmsglevel,
877 .get_regs = stmmac_ethtool_gregs,
878 .get_regs_len = stmmac_ethtool_get_regs_len,
879 .get_link = ethtool_op_get_link,
880 .nway_reset = phy_ethtool_nway_reset,
881 .get_pauseparam = stmmac_get_pauseparam,
882 .set_pauseparam = stmmac_set_pauseparam,
883 .get_ethtool_stats = stmmac_get_ethtool_stats,
884 .get_strings = stmmac_get_strings,
885 .get_wol = stmmac_get_wol,
886 .set_wol = stmmac_set_wol,
887 .get_eee = stmmac_ethtool_op_get_eee,
888 .set_eee = stmmac_ethtool_op_set_eee,
889 .get_sset_count = stmmac_get_sset_count,
890 .get_ts_info = stmmac_get_ts_info,
891 .get_coalesce = stmmac_get_coalesce,
892 .set_coalesce = stmmac_set_coalesce,
893 .get_tunable = stmmac_get_tunable,
894 .set_tunable = stmmac_set_tunable,
895 .get_link_ksettings = stmmac_ethtool_get_link_ksettings,
896 .set_link_ksettings = stmmac_ethtool_set_link_ksettings,
899 void stmmac_set_ethtool_ops(struct net_device *netdev)
901 netdev->ethtool_ops = &stmmac_ethtool_ops;