2 * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
3 * DWC Ether MAC version 4.00 has been used for developing this code.
5 * This only implements the mac core functions for this chip.
7 * Copyright (C) 2015 STMicroelectronics Ltd
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * Author: Alexandre Torgue <alexandre.torgue@st.com>
16 #include <linux/crc32.h>
17 #include <linux/slab.h>
18 #include <linux/ethtool.h>
21 #include "stmmac_pcs.h"
25 static void dwmac4_core_init(struct mac_device_info *hw,
26 struct net_device *dev)
28 void __iomem *ioaddr = hw->pcsr;
29 u32 value = readl(ioaddr + GMAC_CONFIG);
32 value |= GMAC_CORE_INIT;
34 /* Clear ACS bit because Ethernet switch tagging formats such as
35 * Broadcom tags can look like invalid LLC/SNAP packets and cause the
36 * hardware to truncate packets on reception.
38 if (netdev_uses_dsa(dev))
39 value &= ~GMAC_CONFIG_ACS;
42 value |= GMAC_CONFIG_2K;
44 value |= GMAC_CONFIG_JE;
47 value |= GMAC_CONFIG_TE;
49 value &= hw->link.speed_mask;
52 value |= hw->link.speed1000;
55 value |= hw->link.speed100;
58 value |= hw->link.speed10;
63 writel(value, ioaddr + GMAC_CONFIG);
65 /* Enable GMAC interrupts */
66 value = GMAC_INT_DEFAULT_ENABLE;
69 value |= GMAC_PCS_IRQ_DEFAULT;
71 writel(value, ioaddr + GMAC_INT_EN);
74 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
77 void __iomem *ioaddr = hw->pcsr;
78 u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
80 value &= GMAC_RX_QUEUE_CLEAR(queue);
81 if (mode == MTL_QUEUE_AVB)
82 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
83 else if (mode == MTL_QUEUE_DCB)
84 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
86 writel(value, ioaddr + GMAC_RXQ_CTRL0);
89 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
92 void __iomem *ioaddr = hw->pcsr;
96 base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
98 value = readl(ioaddr + base_register);
100 value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
101 value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
102 GMAC_RXQCTRL_PSRQX_MASK(queue);
103 writel(value, ioaddr + base_register);
106 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
109 void __iomem *ioaddr = hw->pcsr;
113 base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
115 value = readl(ioaddr + base_register);
117 value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
118 value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
119 GMAC_TXQCTRL_PSTQX_MASK(queue);
121 writel(value, ioaddr + base_register);
124 static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
125 u8 packet, u32 queue)
127 void __iomem *ioaddr = hw->pcsr;
130 static const struct stmmac_rx_routing route_possibilities[] = {
131 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
132 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
133 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
134 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
135 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
138 value = readl(ioaddr + GMAC_RXQ_CTRL1);
140 /* routing configuration */
141 value &= ~route_possibilities[packet - 1].reg_mask;
142 value |= (queue << route_possibilities[packet-1].reg_shift) &
143 route_possibilities[packet - 1].reg_mask;
145 /* some packets require extra ops */
146 if (packet == PACKET_AVCPQ) {
147 value &= ~GMAC_RXQCTRL_TACPQE;
148 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
149 } else if (packet == PACKET_MCBCQ) {
150 value &= ~GMAC_RXQCTRL_MCBCQEN;
151 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
154 writel(value, ioaddr + GMAC_RXQ_CTRL1);
157 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
160 void __iomem *ioaddr = hw->pcsr;
161 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
163 value &= ~MTL_OPERATION_RAA;
165 case MTL_RX_ALGORITHM_SP:
166 value |= MTL_OPERATION_RAA_SP;
168 case MTL_RX_ALGORITHM_WSP:
169 value |= MTL_OPERATION_RAA_WSP;
175 writel(value, ioaddr + MTL_OPERATION_MODE);
178 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
181 void __iomem *ioaddr = hw->pcsr;
182 u32 value = readl(ioaddr + MTL_OPERATION_MODE);
184 value &= ~MTL_OPERATION_SCHALG_MASK;
186 case MTL_TX_ALGORITHM_WRR:
187 value |= MTL_OPERATION_SCHALG_WRR;
189 case MTL_TX_ALGORITHM_WFQ:
190 value |= MTL_OPERATION_SCHALG_WFQ;
192 case MTL_TX_ALGORITHM_DWRR:
193 value |= MTL_OPERATION_SCHALG_DWRR;
195 case MTL_TX_ALGORITHM_SP:
196 value |= MTL_OPERATION_SCHALG_SP;
203 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
204 u32 weight, u32 queue)
206 void __iomem *ioaddr = hw->pcsr;
207 u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
209 value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
210 value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
211 writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
214 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
216 void __iomem *ioaddr = hw->pcsr;
220 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
222 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
224 if (queue == 0 || queue == 4) {
225 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
226 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
228 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
229 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
233 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
235 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
238 static void dwmac4_config_cbs(struct mac_device_info *hw,
239 u32 send_slope, u32 idle_slope,
240 u32 high_credit, u32 low_credit, u32 queue)
242 void __iomem *ioaddr = hw->pcsr;
245 pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
246 pr_debug("\tsend_slope: 0x%08x\n", send_slope);
247 pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
248 pr_debug("\thigh_credit: 0x%08x\n", high_credit);
249 pr_debug("\tlow_credit: 0x%08x\n", low_credit);
251 /* enable AV algorithm */
252 value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
253 value |= MTL_ETS_CTRL_AVALG;
254 value |= MTL_ETS_CTRL_CC;
255 writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
257 /* configure send slope */
258 value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
259 value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
260 value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
261 writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
263 /* configure idle slope (same register as tx weight) */
264 dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
266 /* configure high credit */
267 value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
268 value &= ~MTL_HIGH_CRED_HC_MASK;
269 value |= high_credit & MTL_HIGH_CRED_HC_MASK;
270 writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
272 /* configure high credit */
273 value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
274 value &= ~MTL_HIGH_CRED_LC_MASK;
275 value |= low_credit & MTL_HIGH_CRED_LC_MASK;
276 writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
279 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
281 void __iomem *ioaddr = hw->pcsr;
284 for (i = 0; i < GMAC_REG_NUM; i++)
285 reg_space[i] = readl(ioaddr + i * 4);
288 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
290 void __iomem *ioaddr = hw->pcsr;
291 u32 value = readl(ioaddr + GMAC_CONFIG);
294 value |= GMAC_CONFIG_IPC;
296 value &= ~GMAC_CONFIG_IPC;
298 writel(value, ioaddr + GMAC_CONFIG);
300 value = readl(ioaddr + GMAC_CONFIG);
302 return !!(value & GMAC_CONFIG_IPC);
305 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
307 void __iomem *ioaddr = hw->pcsr;
308 unsigned int pmt = 0;
311 if (mode & WAKE_MAGIC) {
312 pr_debug("GMAC: WOL Magic frame\n");
313 pmt |= power_down | magic_pkt_en;
315 if (mode & WAKE_UCAST) {
316 pr_debug("GMAC: WOL on global unicast\n");
317 pmt |= power_down | global_unicast | wake_up_frame_en;
321 /* The receiver must be enabled for WOL before powering down */
322 config = readl(ioaddr + GMAC_CONFIG);
323 config |= GMAC_CONFIG_RE;
324 writel(config, ioaddr + GMAC_CONFIG);
326 writel(pmt, ioaddr + GMAC_PMT);
329 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
330 unsigned char *addr, unsigned int reg_n)
332 void __iomem *ioaddr = hw->pcsr;
334 stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
335 GMAC_ADDR_LOW(reg_n));
338 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
339 unsigned char *addr, unsigned int reg_n)
341 void __iomem *ioaddr = hw->pcsr;
343 stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
344 GMAC_ADDR_LOW(reg_n));
347 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
348 bool en_tx_lpi_clockgating)
350 void __iomem *ioaddr = hw->pcsr;
353 /* Enable the link status receive on RGMII, SGMII ore SMII
354 * receive path and instruct the transmit to enter in LPI
357 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
358 value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
360 if (en_tx_lpi_clockgating)
361 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
363 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
366 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
368 void __iomem *ioaddr = hw->pcsr;
371 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
372 value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
373 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
376 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
378 void __iomem *ioaddr = hw->pcsr;
381 value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
384 value |= GMAC4_LPI_CTRL_STATUS_PLS;
386 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
388 writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
391 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
393 void __iomem *ioaddr = hw->pcsr;
394 int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
396 /* Program the timers in the LPI timer control register:
397 * LS: minimum time (ms) for which the link
398 * status from PHY should be ok before transmitting
400 * TW: minimum time (us) for which the core waits
401 * after it has stopped transmitting the LPI pattern.
403 writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
406 static void dwmac4_set_filter(struct mac_device_info *hw,
407 struct net_device *dev)
409 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
410 unsigned int value = 0;
412 if (dev->flags & IFF_PROMISC) {
413 value = GMAC_PACKET_FILTER_PR;
414 } else if ((dev->flags & IFF_ALLMULTI) ||
415 (netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
417 value = GMAC_PACKET_FILTER_PM;
418 /* Set the 64 bits of the HASH tab. To be updated if taller
421 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
422 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
423 } else if (!netdev_mc_empty(dev)) {
425 struct netdev_hw_addr *ha;
427 /* Hash filter for multicast */
428 value = GMAC_PACKET_FILTER_HMC;
430 memset(mc_filter, 0, sizeof(mc_filter));
431 netdev_for_each_mc_addr(ha, dev) {
432 /* The upper 6 bits of the calculated CRC are used to
433 * index the content of the Hash Table Reg 0 and 1.
436 (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
437 /* The most significant bit determines the register
438 * to use while the other 5 bits determines the bit
439 * within the selected register
441 mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
443 writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
444 writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
447 /* Handle multiple unicast addresses */
448 if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
449 /* Switch to promiscuous mode if more than 128 addrs
452 value |= GMAC_PACKET_FILTER_PR;
453 } else if (!netdev_uc_empty(dev)) {
455 struct netdev_hw_addr *ha;
457 netdev_for_each_uc_addr(ha, dev) {
458 dwmac4_set_umac_addr(hw, ha->addr, reg);
463 writel(value, ioaddr + GMAC_PACKET_FILTER);
466 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
467 unsigned int fc, unsigned int pause_time,
470 void __iomem *ioaddr = hw->pcsr;
471 unsigned int flow = 0;
474 pr_debug("GMAC Flow-Control:\n");
476 pr_debug("\tReceive Flow-Control ON\n");
477 flow |= GMAC_RX_FLOW_CTRL_RFE;
478 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
481 pr_debug("\tTransmit Flow-Control ON\n");
484 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
486 for (queue = 0; queue < tx_cnt; queue++) {
487 flow |= GMAC_TX_FLOW_CTRL_TFE;
491 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
493 writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
498 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
501 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
504 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
506 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
509 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
511 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
514 /* RGMII or SMII interface */
515 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
519 status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
522 /* Check the link status */
523 if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
528 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
529 GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
530 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
531 x->pcs_speed = SPEED_1000;
532 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
533 x->pcs_speed = SPEED_100;
535 x->pcs_speed = SPEED_10;
537 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
539 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
540 x->pcs_duplex ? "Full" : "Half");
543 pr_info("Link is Down\n");
547 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
549 void __iomem *ioaddr = hw->pcsr;
550 u32 mtl_int_qx_status;
553 mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
555 /* Check MTL Interrupt */
556 if (mtl_int_qx_status & MTL_INT_QX(chan)) {
557 /* read Queue x Interrupt status */
558 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
560 if (status & MTL_RX_OVERFLOW_INT) {
561 /* clear Interrupt */
562 writel(status | MTL_RX_OVERFLOW_INT,
563 ioaddr + MTL_CHAN_INT_CTRL(chan));
564 ret = CORE_IRQ_MTL_RX_OVERFLOW;
571 static int dwmac4_irq_status(struct mac_device_info *hw,
572 struct stmmac_extra_stats *x)
574 void __iomem *ioaddr = hw->pcsr;
575 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
576 u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
579 /* Discard disabled bits */
580 intr_status &= intr_enable;
582 /* Not used events (e.g. MMC interrupts) are not handled. */
583 if ((intr_status & mmc_tx_irq))
585 if (unlikely(intr_status & mmc_rx_irq))
587 if (unlikely(intr_status & mmc_rx_csum_offload_irq))
588 x->mmc_rx_csum_offload_irq_n++;
589 /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
590 if (unlikely(intr_status & pmt_irq)) {
591 readl(ioaddr + GMAC_PMT);
592 x->irq_receive_pmt_irq_n++;
595 /* MAC tx/rx EEE LPI entry/exit interrupts */
596 if (intr_status & lpi_irq) {
597 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
598 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
600 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
601 ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
602 x->irq_tx_path_in_lpi_mode_n++;
604 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
605 ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
606 x->irq_tx_path_exit_lpi_mode_n++;
608 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
609 x->irq_rx_path_in_lpi_mode_n++;
610 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
611 x->irq_rx_path_exit_lpi_mode_n++;
614 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
615 if (intr_status & PCS_RGSMIIIS_IRQ)
616 dwmac4_phystatus(ioaddr, x);
621 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
622 u32 rx_queues, u32 tx_queues)
627 for (queue = 0; queue < tx_queues; queue++) {
628 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
630 if (value & MTL_DEBUG_TXSTSFSTS)
631 x->mtl_tx_status_fifo_full++;
632 if (value & MTL_DEBUG_TXFSTS)
633 x->mtl_tx_fifo_not_empty++;
634 if (value & MTL_DEBUG_TWCSTS)
636 if (value & MTL_DEBUG_TRCSTS_MASK) {
637 u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
638 >> MTL_DEBUG_TRCSTS_SHIFT;
639 if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
640 x->mtl_tx_fifo_read_ctrl_write++;
641 else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
642 x->mtl_tx_fifo_read_ctrl_wait++;
643 else if (trcsts == MTL_DEBUG_TRCSTS_READ)
644 x->mtl_tx_fifo_read_ctrl_read++;
646 x->mtl_tx_fifo_read_ctrl_idle++;
648 if (value & MTL_DEBUG_TXPAUSED)
649 x->mac_tx_in_pause++;
652 for (queue = 0; queue < rx_queues; queue++) {
653 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
655 if (value & MTL_DEBUG_RXFSTS_MASK) {
656 u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
657 >> MTL_DEBUG_RRCSTS_SHIFT;
659 if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
660 x->mtl_rx_fifo_fill_level_full++;
661 else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
662 x->mtl_rx_fifo_fill_above_thresh++;
663 else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
664 x->mtl_rx_fifo_fill_below_thresh++;
666 x->mtl_rx_fifo_fill_level_empty++;
668 if (value & MTL_DEBUG_RRCSTS_MASK) {
669 u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
670 MTL_DEBUG_RRCSTS_SHIFT;
672 if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
673 x->mtl_rx_fifo_read_ctrl_flush++;
674 else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
675 x->mtl_rx_fifo_read_ctrl_read_data++;
676 else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
677 x->mtl_rx_fifo_read_ctrl_status++;
679 x->mtl_rx_fifo_read_ctrl_idle++;
681 if (value & MTL_DEBUG_RWCSTS)
682 x->mtl_rx_fifo_ctrl_active++;
686 value = readl(ioaddr + GMAC_DEBUG);
688 if (value & GMAC_DEBUG_TFCSTS_MASK) {
689 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
690 >> GMAC_DEBUG_TFCSTS_SHIFT;
692 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
693 x->mac_tx_frame_ctrl_xfer++;
694 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
695 x->mac_tx_frame_ctrl_pause++;
696 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
697 x->mac_tx_frame_ctrl_wait++;
699 x->mac_tx_frame_ctrl_idle++;
701 if (value & GMAC_DEBUG_TPESTS)
702 x->mac_gmii_tx_proto_engine++;
703 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
704 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
705 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
706 if (value & GMAC_DEBUG_RPESTS)
707 x->mac_gmii_rx_proto_engine++;
710 static const struct stmmac_ops dwmac4_ops = {
711 .core_init = dwmac4_core_init,
712 .set_mac = stmmac_set_mac,
713 .rx_ipc = dwmac4_rx_ipc_enable,
714 .rx_queue_enable = dwmac4_rx_queue_enable,
715 .rx_queue_prio = dwmac4_rx_queue_priority,
716 .tx_queue_prio = dwmac4_tx_queue_priority,
717 .rx_queue_routing = dwmac4_rx_queue_routing,
718 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
719 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
720 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
721 .map_mtl_to_dma = dwmac4_map_mtl_dma,
722 .config_cbs = dwmac4_config_cbs,
723 .dump_regs = dwmac4_dump_regs,
724 .host_irq_status = dwmac4_irq_status,
725 .host_mtl_irq_status = dwmac4_irq_mtl_status,
726 .flow_ctrl = dwmac4_flow_ctrl,
728 .set_umac_addr = dwmac4_set_umac_addr,
729 .get_umac_addr = dwmac4_get_umac_addr,
730 .set_eee_mode = dwmac4_set_eee_mode,
731 .reset_eee_mode = dwmac4_reset_eee_mode,
732 .set_eee_timer = dwmac4_set_eee_timer,
733 .set_eee_pls = dwmac4_set_eee_pls,
734 .pcs_ctrl_ane = dwmac4_ctrl_ane,
735 .pcs_rane = dwmac4_rane,
736 .pcs_get_adv_lp = dwmac4_get_adv_lp,
737 .debug = dwmac4_debug,
738 .set_filter = dwmac4_set_filter,
741 static const struct stmmac_ops dwmac410_ops = {
742 .core_init = dwmac4_core_init,
743 .set_mac = stmmac_dwmac4_set_mac,
744 .rx_ipc = dwmac4_rx_ipc_enable,
745 .rx_queue_enable = dwmac4_rx_queue_enable,
746 .rx_queue_prio = dwmac4_rx_queue_priority,
747 .tx_queue_prio = dwmac4_tx_queue_priority,
748 .rx_queue_routing = dwmac4_rx_queue_routing,
749 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
750 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
751 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
752 .map_mtl_to_dma = dwmac4_map_mtl_dma,
753 .config_cbs = dwmac4_config_cbs,
754 .dump_regs = dwmac4_dump_regs,
755 .host_irq_status = dwmac4_irq_status,
756 .host_mtl_irq_status = dwmac4_irq_mtl_status,
757 .flow_ctrl = dwmac4_flow_ctrl,
759 .set_umac_addr = dwmac4_set_umac_addr,
760 .get_umac_addr = dwmac4_get_umac_addr,
761 .set_eee_mode = dwmac4_set_eee_mode,
762 .reset_eee_mode = dwmac4_reset_eee_mode,
763 .set_eee_timer = dwmac4_set_eee_timer,
764 .set_eee_pls = dwmac4_set_eee_pls,
765 .pcs_ctrl_ane = dwmac4_ctrl_ane,
766 .pcs_rane = dwmac4_rane,
767 .pcs_get_adv_lp = dwmac4_get_adv_lp,
768 .debug = dwmac4_debug,
769 .set_filter = dwmac4_set_filter,
772 static const struct stmmac_ops dwmac510_ops = {
773 .core_init = dwmac4_core_init,
774 .set_mac = stmmac_dwmac4_set_mac,
775 .rx_ipc = dwmac4_rx_ipc_enable,
776 .rx_queue_enable = dwmac4_rx_queue_enable,
777 .rx_queue_prio = dwmac4_rx_queue_priority,
778 .tx_queue_prio = dwmac4_tx_queue_priority,
779 .rx_queue_routing = dwmac4_rx_queue_routing,
780 .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
781 .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
782 .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
783 .map_mtl_to_dma = dwmac4_map_mtl_dma,
784 .config_cbs = dwmac4_config_cbs,
785 .dump_regs = dwmac4_dump_regs,
786 .host_irq_status = dwmac4_irq_status,
787 .host_mtl_irq_status = dwmac4_irq_mtl_status,
788 .flow_ctrl = dwmac4_flow_ctrl,
790 .set_umac_addr = dwmac4_set_umac_addr,
791 .get_umac_addr = dwmac4_get_umac_addr,
792 .set_eee_mode = dwmac4_set_eee_mode,
793 .reset_eee_mode = dwmac4_reset_eee_mode,
794 .set_eee_timer = dwmac4_set_eee_timer,
795 .set_eee_pls = dwmac4_set_eee_pls,
796 .pcs_ctrl_ane = dwmac4_ctrl_ane,
797 .pcs_rane = dwmac4_rane,
798 .pcs_get_adv_lp = dwmac4_get_adv_lp,
799 .debug = dwmac4_debug,
800 .set_filter = dwmac4_set_filter,
801 .safety_feat_config = dwmac5_safety_feat_config,
802 .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
803 .safety_feat_dump = dwmac5_safety_feat_dump,
806 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
807 int perfect_uc_entries, int *synopsys_id)
809 struct mac_device_info *mac;
810 u32 hwid = readl(ioaddr + GMAC_VERSION);
812 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
817 mac->multicast_filter_bins = mcbins;
818 mac->unicast_filter_entries = perfect_uc_entries;
819 mac->mcast_bits_log2 = 0;
821 if (mac->multicast_filter_bins)
822 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
824 mac->link.duplex = GMAC_CONFIG_DM;
825 mac->link.speed10 = GMAC_CONFIG_PS;
826 mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
827 mac->link.speed1000 = 0;
828 mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
829 mac->mii.addr = GMAC_MDIO_ADDR;
830 mac->mii.data = GMAC_MDIO_DATA;
831 mac->mii.addr_shift = 21;
832 mac->mii.addr_mask = GENMASK(25, 21);
833 mac->mii.reg_shift = 16;
834 mac->mii.reg_mask = GENMASK(20, 16);
835 mac->mii.clk_csr_shift = 8;
836 mac->mii.clk_csr_mask = GENMASK(11, 8);
838 /* Get and dump the chip ID */
839 *synopsys_id = stmmac_get_synopsys_id(hwid);
841 if (*synopsys_id > DWMAC_CORE_4_00)
842 mac->dma = &dwmac410_dma_ops;
844 mac->dma = &dwmac4_dma_ops;
846 if (*synopsys_id >= DWMAC_CORE_5_10)
847 mac->mac = &dwmac510_ops;
848 else if (*synopsys_id >= DWMAC_CORE_4_00)
849 mac->mac = &dwmac410_ops;
851 mac->mac = &dwmac4_ops;