drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   4  * DWC Ether MAC version 4.00  has been used for developing this code.
   5  *
   6  * This only implements the mac core functions for this chip.
   7  *
   8  * Copyright (C) 2015  STMicroelectronics Ltd
   9  *
  10  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  11  */
  12
  13 #include <linux/crc32.h>
  14 #include <linux/slab.h>
  15 #include <linux/ethtool.h>
  16 #include <linux/io.h>
  17 #include <net/dsa.h>
  18 #include "stmmac.h"
  19 #include "stmmac_pcs.h"
  20 #include "dwmac4.h"
  21 #include "dwmac5.h"
  22
  23 static void dwmac4_core_init(struct mac_device_info *hw,
  24                              struct net_device *dev)
  25 {
  26         void __iomem *ioaddr = hw->pcsr;
  27         u32 value = readl(ioaddr + GMAC_CONFIG);
  28
  29         value |= GMAC_CORE_INIT;
  30
  31         if (hw->ps) {
  32                 value |= GMAC_CONFIG_TE;
  33
  34                 value &= hw->link.speed_mask;
  35                 switch (hw->ps) {
  36                 case SPEED_1000:
  37                         value |= hw->link.speed1000;
  38                         break;
  39                 case SPEED_100:
  40                         value |= hw->link.speed100;
  41                         break;
  42                 case SPEED_10:
  43                         value |= hw->link.speed10;
  44                         break;
  45                 }
  46         }
  47
  48         writel(value, ioaddr + GMAC_CONFIG);
  49
  50         /* Enable GMAC interrupts */
  51         value = GMAC_INT_DEFAULT_ENABLE;
  52
  53         if (hw->pcs)
  54                 value |= GMAC_PCS_IRQ_DEFAULT;
  55
  56         writel(value, ioaddr + GMAC_INT_EN);
  57 }
  58
  59 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
  60                                    u8 mode, u32 queue)
  61 {
  62         void __iomem *ioaddr = hw->pcsr;
  63         u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
  64
  65         value &= GMAC_RX_QUEUE_CLEAR(queue);
  66         if (mode == MTL_QUEUE_AVB)
  67                 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
  68         else if (mode == MTL_QUEUE_DCB)
  69                 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
  70
  71         writel(value, ioaddr + GMAC_RXQ_CTRL0);
  72 }
  73
  74 static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
  75                                      u32 prio, u32 queue)
  76 {
  77         void __iomem *ioaddr = hw->pcsr;
  78         u32 base_register;
  79         u32 value;
  80
  81         base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
  82         if (queue >= 4)
  83                 queue -= 4;
  84
  85         value = readl(ioaddr + base_register);
  86
  87         value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
  88         value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
  89                                                 GMAC_RXQCTRL_PSRQX_MASK(queue);
  90         writel(value, ioaddr + base_register);
  91 }
  92
  93 static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
  94                                      u32 prio, u32 queue)
  95 {
  96         void __iomem *ioaddr = hw->pcsr;
  97         u32 base_register;
  98         u32 value;
  99
 100         base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
 101         if (queue >= 4)
 102                 queue -= 4;
 103
 104         value = readl(ioaddr + base_register);
 105
 106         value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
 107         value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
 108                                                 GMAC_TXQCTRL_PSTQX_MASK(queue);
 109
 110         writel(value, ioaddr + base_register);
 111 }
 112
 113 static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
 114                                     u8 packet, u32 queue)
 115 {
 116         void __iomem *ioaddr = hw->pcsr;
 117         u32 value;
 118
 119         static const struct stmmac_rx_routing route_possibilities[] = {
 120                 { GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
 121                 { GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
 122                 { GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
 123                 { GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
 124                 { GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
 125         };
 126
 127         value = readl(ioaddr + GMAC_RXQ_CTRL1);
 128
 129         /* routing configuration */
 130         value &= ~route_possibilities[packet - 1].reg_mask;
 131         value |= (queue << route_possibilities[packet-1].reg_shift) &
 132                  route_possibilities[packet - 1].reg_mask;
 133
 134         /* some packets require extra ops */
 135         if (packet == PACKET_AVCPQ) {
 136                 value &= ~GMAC_RXQCTRL_TACPQE;
 137                 value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
 138         } else if (packet == PACKET_MCBCQ) {
 139                 value &= ~GMAC_RXQCTRL_MCBCQEN;
 140                 value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
 141         }
 142
 143         writel(value, ioaddr + GMAC_RXQ_CTRL1);
 144 }
 145
 146 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
 147                                           u32 rx_alg)
 148 {
 149         void __iomem *ioaddr = hw->pcsr;
 150         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 151
 152         value &= ~MTL_OPERATION_RAA;
 153         switch (rx_alg) {
 154         case MTL_RX_ALGORITHM_SP:
 155                 value |= MTL_OPERATION_RAA_SP;
 156                 break;
 157         case MTL_RX_ALGORITHM_WSP:
 158                 value |= MTL_OPERATION_RAA_WSP;
 159                 break;
 160         default:
 161                 break;
 162         }
 163
 164         writel(value, ioaddr + MTL_OPERATION_MODE);
 165 }
 166
 167 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
 168                                           u32 tx_alg)
 169 {
 170         void __iomem *ioaddr = hw->pcsr;
 171         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 172
 173         value &= ~MTL_OPERATION_SCHALG_MASK;
 174         switch (tx_alg) {
 175         case MTL_TX_ALGORITHM_WRR:
 176                 value |= MTL_OPERATION_SCHALG_WRR;
 177                 break;
 178         case MTL_TX_ALGORITHM_WFQ:
 179                 value |= MTL_OPERATION_SCHALG_WFQ;
 180                 break;
 181         case MTL_TX_ALGORITHM_DWRR:
 182                 value |= MTL_OPERATION_SCHALG_DWRR;
 183                 break;
 184         case MTL_TX_ALGORITHM_SP:
 185                 value |= MTL_OPERATION_SCHALG_SP;
 186                 break;
 187         default:
 188                 break;
 189         }
 190
 191         writel(value, ioaddr + MTL_OPERATION_MODE);
 192 }
 193
 194 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
 195                                            u32 weight, u32 queue)
 196 {
 197         void __iomem *ioaddr = hw->pcsr;
 198         u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 199
 200         value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
 201         value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
 202         writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 203 }
 204
 205 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
 206 {
 207         void __iomem *ioaddr = hw->pcsr;
 208         u32 value;
 209
 210         if (queue < 4)
 211                 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
 212         else
 213                 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
 214
 215         if (queue == 0 || queue == 4) {
 216                 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
 217                 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
 218         } else {
 219                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
 220                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
 221         }
 222
 223         if (queue < 4)
 224                 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
 225         else
 226                 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
 227 }
 228
 229 static void dwmac4_config_cbs(struct mac_device_info *hw,
 230                               u32 send_slope, u32 idle_slope,
 231                               u32 high_credit, u32 low_credit, u32 queue)
 232 {
 233         void __iomem *ioaddr = hw->pcsr;
 234         u32 value;
 235
 236         pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
 237         pr_debug("\tsend_slope: 0x%08x\n", send_slope);
 238         pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
 239         pr_debug("\thigh_credit: 0x%08x\n", high_credit);
 240         pr_debug("\tlow_credit: 0x%08x\n", low_credit);
 241
 242         /* enable AV algorithm */
 243         value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 244         value |= MTL_ETS_CTRL_AVALG;
 245         value |= MTL_ETS_CTRL_CC;
 246         writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 247
 248         /* configure send slope */
 249         value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 250         value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
 251         value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
 252         writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 253
 254         /* configure idle slope (same register as tx weight) */
 255         dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
 256
 257         /* configure high credit */
 258         value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 259         value &= ~MTL_HIGH_CRED_HC_MASK;
 260         value |= high_credit & MTL_HIGH_CRED_HC_MASK;
 261         writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 262
 263         /* configure high credit */
 264         value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 265         value &= ~MTL_HIGH_CRED_LC_MASK;
 266         value |= low_credit & MTL_HIGH_CRED_LC_MASK;
 267         writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 268 }
 269
 270 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 271 {
 272         void __iomem *ioaddr = hw->pcsr;
 273         int i;
 274
 275         for (i = 0; i < GMAC_REG_NUM; i++)
 276                 reg_space[i] = readl(ioaddr + i * 4);
 277 }
 278
 279 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
 280 {
 281         void __iomem *ioaddr = hw->pcsr;
 282         u32 value = readl(ioaddr + GMAC_CONFIG);
 283
 284         if (hw->rx_csum)
 285                 value |= GMAC_CONFIG_IPC;
 286         else
 287                 value &= ~GMAC_CONFIG_IPC;
 288
 289         writel(value, ioaddr + GMAC_CONFIG);
 290
 291         value = readl(ioaddr + GMAC_CONFIG);
 292
 293         return !!(value & GMAC_CONFIG_IPC);
 294 }
 295
 296 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 297 {
 298         void __iomem *ioaddr = hw->pcsr;
 299         unsigned int pmt = 0;
 300         u32 config;
 301
 302         if (mode & WAKE_MAGIC) {
 303                 pr_debug("GMAC: WOL Magic frame\n");
 304                 pmt |= power_down | magic_pkt_en;
 305         }
 306         if (mode & WAKE_UCAST) {
 307                 pr_debug("GMAC: WOL on global unicast\n");
 308                 pmt |= power_down | global_unicast | wake_up_frame_en;
 309         }
 310
 311         if (pmt) {
 312                 /* The receiver must be enabled for WOL before powering down */
 313                 config = readl(ioaddr + GMAC_CONFIG);
 314                 config |= GMAC_CONFIG_RE;
 315                 writel(config, ioaddr + GMAC_CONFIG);
 316         }
 317         writel(pmt, ioaddr + GMAC_PMT);
 318 }
 319
 320 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 321                                  unsigned char *addr, unsigned int reg_n)
 322 {
 323         void __iomem *ioaddr = hw->pcsr;
 324
 325         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 326                                    GMAC_ADDR_LOW(reg_n));
 327 }
 328
 329 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 330                                  unsigned char *addr, unsigned int reg_n)
 331 {
 332         void __iomem *ioaddr = hw->pcsr;
 333
 334         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 335                                    GMAC_ADDR_LOW(reg_n));
 336 }
 337
 338 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 339                                 bool en_tx_lpi_clockgating)
 340 {
 341         void __iomem *ioaddr = hw->pcsr;
 342         u32 value;
 343
 344         /* Enable the link status receive on RGMII, SGMII ore SMII
 345          * receive path and instruct the transmit to enter in LPI
 346          * state.
 347          */
 348         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 349         value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 350
 351         if (en_tx_lpi_clockgating)
 352                 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 353
 354         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 355 }
 356
 357 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 358 {
 359         void __iomem *ioaddr = hw->pcsr;
 360         u32 value;
 361
 362         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 363         value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 364         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 365 }
 366
 367 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 368 {
 369         void __iomem *ioaddr = hw->pcsr;
 370         u32 value;
 371
 372         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 373
 374         if (link)
 375                 value |= GMAC4_LPI_CTRL_STATUS_PLS;
 376         else
 377                 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 378
 379         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 380 }
 381
 382 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 383 {
 384         void __iomem *ioaddr = hw->pcsr;
 385         int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 386
 387         /* Program the timers in the LPI timer control register:
 388          * LS: minimum time (ms) for which the link
 389          *  status from PHY should be ok before transmitting
 390          *  the LPI pattern.
 391          * TW: minimum time (us) for which the core waits
 392          *  after it has stopped transmitting the LPI pattern.
 393          */
 394         writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 395 }
 396
 397 static void dwmac4_set_filter(struct mac_device_info *hw,
 398                               struct net_device *dev)
 399 {
 400         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 401         int numhashregs = (hw->multicast_filter_bins >> 5);
 402         int mcbitslog2 = hw->mcast_bits_log2;
 403         unsigned int value;
 404         int i;
 405
 406         value = readl(ioaddr + GMAC_PACKET_FILTER);
 407         value &= ~GMAC_PACKET_FILTER_HMC;
 408         value &= ~GMAC_PACKET_FILTER_HPF;
 409         value &= ~GMAC_PACKET_FILTER_PCF;
 410         value &= ~GMAC_PACKET_FILTER_PM;
 411         value &= ~GMAC_PACKET_FILTER_PR;
 412         if (dev->flags & IFF_PROMISC) {
 413                 value = GMAC_PACKET_FILTER_PR | GMAC_PACKET_FILTER_PCF;
 414         } else if ((dev->flags & IFF_ALLMULTI) ||
 415                    (netdev_mc_count(dev) > hw->multicast_filter_bins)) {
 416                 /* Pass all multi */
 417                 value |= GMAC_PACKET_FILTER_PM;
 418                 /* Set all the bits of the HASH tab */
 419                 for (i = 0; i < numhashregs; i++)
 420                         writel(0xffffffff, ioaddr + GMAC_HASH_TAB(i));
 421         } else if (!netdev_mc_empty(dev)) {
 422                 struct netdev_hw_addr *ha;
 423                 u32 mc_filter[8];
 424
 425                 /* Hash filter for multicast */
 426                 value |= GMAC_PACKET_FILTER_HMC;
 427
 428                 memset(mc_filter, 0, sizeof(mc_filter));
 429                 netdev_for_each_mc_addr(ha, dev) {
 430                         /* The upper n bits of the calculated CRC are used to
 431                          * index the contents of the hash table. The number of
 432                          * bits used depends on the hardware configuration
 433                          * selected at core configuration time.
 434                          */
 435                         int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
 436                                         ETH_ALEN)) >> (32 - mcbitslog2);
 437                         /* The most significant bit determines the register to
 438                          * use (H/L) while the other 5 bits determine the bit
 439                          * within the register.
 440                          */
 441                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1f));
 442                 }
 443                 for (i = 0; i < numhashregs; i++)
 444                         writel(mc_filter[i], ioaddr + GMAC_HASH_TAB(i));
 445         }
 446
 447         value |= GMAC_PACKET_FILTER_HPF;
 448
 449         /* Handle multiple unicast addresses */
 450         if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
 451                 /* Switch to promiscuous mode if more than 128 addrs
 452                  * are required
 453                  */
 454                 value |= GMAC_PACKET_FILTER_PR;
 455         } else {
 456                 struct netdev_hw_addr *ha;
 457                 int reg = 1;
 458
 459                 netdev_for_each_uc_addr(ha, dev) {
 460                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 461                         reg++;
 462                 }
 463
 464                 while (reg < GMAC_MAX_PERFECT_ADDRESSES) {
 465                         writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
 466                         writel(0, ioaddr + GMAC_ADDR_LOW(reg));
 467                         reg++;
 468                 }
 469         }
 470
 471         writel(value, ioaddr + GMAC_PACKET_FILTER);
 472 }
 473
 474 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 475                              unsigned int fc, unsigned int pause_time,
 476                              u32 tx_cnt)
 477 {
 478         void __iomem *ioaddr = hw->pcsr;
 479         unsigned int flow = 0;
 480         u32 queue = 0;
 481
 482         pr_debug("GMAC Flow-Control:\n");
 483         if (fc & FLOW_RX) {
 484                 pr_debug("\tReceive Flow-Control ON\n");
 485                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 486         }
 487         writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 488
 489         if (fc & FLOW_TX) {
 490                 pr_debug("\tTransmit Flow-Control ON\n");
 491
 492                 if (duplex)
 493                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 494
 495                 for (queue = 0; queue < tx_cnt; queue++) {
 496                         flow = GMAC_TX_FLOW_CTRL_TFE;
 497
 498                         if (duplex)
 499                                 flow |=
 500                                 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 501
 502                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 503                 }
 504         } else {
 505                 for (queue = 0; queue < tx_cnt; queue++)
 506                         writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 507         }
 508 }
 509
 510 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 511                             bool loopback)
 512 {
 513         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 514 }
 515
 516 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
 517 {
 518         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 519 }
 520
 521 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 522 {
 523         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 524 }
 525
 526 /* RGMII or SMII interface */
 527 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 528 {
 529         u32 status;
 530
 531         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 532         x->irq_rgmii_n++;
 533
 534         /* Check the link status */
 535         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 536                 int speed_value;
 537
 538                 x->pcs_link = 1;
 539
 540                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 541                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 542                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 543                         x->pcs_speed = SPEED_1000;
 544                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 545                         x->pcs_speed = SPEED_100;
 546                 else
 547                         x->pcs_speed = SPEED_10;
 548
 549                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
 550
 551                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 552                         x->pcs_duplex ? "Full" : "Half");
 553         } else {
 554                 x->pcs_link = 0;
 555                 pr_info("Link is Down\n");
 556         }
 557 }
 558
 559 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
 560 {
 561         void __iomem *ioaddr = hw->pcsr;
 562         u32 mtl_int_qx_status;
 563         int ret = 0;
 564
 565         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 566
 567         /* Check MTL Interrupt */
 568         if (mtl_int_qx_status & MTL_INT_QX(chan)) {
 569                 /* read Queue x Interrupt status */
 570                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
 571
 572                 if (status & MTL_RX_OVERFLOW_INT) {
 573                         /*  clear Interrupt */
 574                         writel(status | MTL_RX_OVERFLOW_INT,
 575                                ioaddr + MTL_CHAN_INT_CTRL(chan));
 576                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 577                 }
 578         }
 579
 580         return ret;
 581 }
 582
 583 static int dwmac4_irq_status(struct mac_device_info *hw,
 584                              struct stmmac_extra_stats *x)
 585 {
 586         void __iomem *ioaddr = hw->pcsr;
 587         u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
 588         u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
 589         int ret = 0;
 590
 591         /* Discard disabled bits */
 592         intr_status &= intr_enable;
 593
 594         /* Not used events (e.g. MMC interrupts) are not handled. */
 595         if ((intr_status & mmc_tx_irq))
 596                 x->mmc_tx_irq_n++;
 597         if (unlikely(intr_status & mmc_rx_irq))
 598                 x->mmc_rx_irq_n++;
 599         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 600                 x->mmc_rx_csum_offload_irq_n++;
 601         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 602         if (unlikely(intr_status & pmt_irq)) {
 603                 readl(ioaddr + GMAC_PMT);
 604                 x->irq_receive_pmt_irq_n++;
 605         }
 606
 607         /* MAC tx/rx EEE LPI entry/exit interrupts */
 608         if (intr_status & lpi_irq) {
 609                 /* Clear LPI interrupt by reading MAC_LPI_Control_Status */
 610                 u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 611
 612                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
 613                         ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
 614                         x->irq_tx_path_in_lpi_mode_n++;
 615                 }
 616                 if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
 617                         ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
 618                         x->irq_tx_path_exit_lpi_mode_n++;
 619                 }
 620                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
 621                         x->irq_rx_path_in_lpi_mode_n++;
 622                 if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
 623                         x->irq_rx_path_exit_lpi_mode_n++;
 624         }
 625
 626         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 627         if (intr_status & PCS_RGSMIIIS_IRQ)
 628                 dwmac4_phystatus(ioaddr, x);
 629
 630         return ret;
 631 }
 632
 633 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 634                          u32 rx_queues, u32 tx_queues)
 635 {
 636         u32 value;
 637         u32 queue;
 638
 639         for (queue = 0; queue < tx_queues; queue++) {
 640                 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
 641
 642                 if (value & MTL_DEBUG_TXSTSFSTS)
 643                         x->mtl_tx_status_fifo_full++;
 644                 if (value & MTL_DEBUG_TXFSTS)
 645                         x->mtl_tx_fifo_not_empty++;
 646                 if (value & MTL_DEBUG_TWCSTS)
 647                         x->mmtl_fifo_ctrl++;
 648                 if (value & MTL_DEBUG_TRCSTS_MASK) {
 649                         u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 650                                      >> MTL_DEBUG_TRCSTS_SHIFT;
 651                         if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 652                                 x->mtl_tx_fifo_read_ctrl_write++;
 653                         else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 654                                 x->mtl_tx_fifo_read_ctrl_wait++;
 655                         else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 656                                 x->mtl_tx_fifo_read_ctrl_read++;
 657                         else
 658                                 x->mtl_tx_fifo_read_ctrl_idle++;
 659                 }
 660                 if (value & MTL_DEBUG_TXPAUSED)
 661                         x->mac_tx_in_pause++;
 662         }
 663
 664         for (queue = 0; queue < rx_queues; queue++) {
 665                 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
 666
 667                 if (value & MTL_DEBUG_RXFSTS_MASK) {
 668                         u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 669                                      >> MTL_DEBUG_RRCSTS_SHIFT;
 670
 671                         if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 672                                 x->mtl_rx_fifo_fill_level_full++;
 673                         else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 674                                 x->mtl_rx_fifo_fill_above_thresh++;
 675                         else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 676                                 x->mtl_rx_fifo_fill_below_thresh++;
 677                         else
 678                                 x->mtl_rx_fifo_fill_level_empty++;
 679                 }
 680                 if (value & MTL_DEBUG_RRCSTS_MASK) {
 681                         u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 682                                      MTL_DEBUG_RRCSTS_SHIFT;
 683
 684                         if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 685                                 x->mtl_rx_fifo_read_ctrl_flush++;
 686                         else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 687                                 x->mtl_rx_fifo_read_ctrl_read_data++;
 688                         else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 689                                 x->mtl_rx_fifo_read_ctrl_status++;
 690                         else
 691                                 x->mtl_rx_fifo_read_ctrl_idle++;
 692                 }
 693                 if (value & MTL_DEBUG_RWCSTS)
 694                         x->mtl_rx_fifo_ctrl_active++;
 695         }
 696
 697         /* GMAC debug */
 698         value = readl(ioaddr + GMAC_DEBUG);
 699
 700         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 701                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 702                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 703
 704                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 705                         x->mac_tx_frame_ctrl_xfer++;
 706                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 707                         x->mac_tx_frame_ctrl_pause++;
 708                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 709                         x->mac_tx_frame_ctrl_wait++;
 710                 else
 711                         x->mac_tx_frame_ctrl_idle++;
 712         }
 713         if (value & GMAC_DEBUG_TPESTS)
 714                 x->mac_gmii_tx_proto_engine++;
 715         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 716                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 717                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 718         if (value & GMAC_DEBUG_RPESTS)
 719                 x->mac_gmii_rx_proto_engine++;
 720 }
 721
 722 static void dwmac4_set_mac_loopback(void __iomem *ioaddr, bool enable)
 723 {
 724         u32 value = readl(ioaddr + GMAC_CONFIG);
 725
 726         if (enable)
 727                 value |= GMAC_CONFIG_LM;
 728         else
 729                 value &= ~GMAC_CONFIG_LM;
 730
 731         writel(value, ioaddr + GMAC_CONFIG);
 732 }
 733
 734 static void dwmac4_update_vlan_hash(struct mac_device_info *hw, u32 hash,
 735                                     bool is_double)
 736 {
 737         void __iomem *ioaddr = hw->pcsr;
 738
 739         writel(hash, ioaddr + GMAC_VLAN_HASH_TABLE);
 740
 741         if (hash) {
 742                 u32 value = GMAC_VLAN_VTHM | GMAC_VLAN_ETV;
 743                 if (is_double) {
 744                         value |= GMAC_VLAN_EDVLP;
 745                         value |= GMAC_VLAN_ESVL;
 746                         value |= GMAC_VLAN_DOVLTC;
 747                 }
 748
 749                 writel(value, ioaddr + GMAC_VLAN_TAG);
 750         } else {
 751                 u32 value = readl(ioaddr + GMAC_VLAN_TAG);
 752
 753                 value &= ~(GMAC_VLAN_VTHM | GMAC_VLAN_ETV);
 754                 value &= ~(GMAC_VLAN_EDVLP | GMAC_VLAN_ESVL);
 755                 value &= ~GMAC_VLAN_DOVLTC;
 756                 value &= ~GMAC_VLAN_VID;
 757
 758                 writel(value, ioaddr + GMAC_VLAN_TAG);
 759         }
 760 }
 761
 762 static void dwmac4_sarc_configure(void __iomem *ioaddr, int val)
 763 {
 764         u32 value = readl(ioaddr + GMAC_CONFIG);
 765
 766         value &= ~GMAC_CONFIG_SARC;
 767         value |= val << GMAC_CONFIG_SARC_SHIFT;
 768
 769         writel(value, ioaddr + GMAC_CONFIG);
 770 }
 771
 772 static void dwmac4_enable_vlan(struct mac_device_info *hw, u32 type)
 773 {
 774         void __iomem *ioaddr = hw->pcsr;
 775         u32 value;
 776
 777         value = readl(ioaddr + GMAC_VLAN_INCL);
 778         value |= GMAC_VLAN_VLTI;
 779         value |= GMAC_VLAN_CSVL; /* Only use SVLAN */
 780         value &= ~GMAC_VLAN_VLC;
 781         value |= (type << GMAC_VLAN_VLC_SHIFT) & GMAC_VLAN_VLC;
 782         writel(value, ioaddr + GMAC_VLAN_INCL);
 783 }
 784
 785 static void dwmac4_set_arp_offload(struct mac_device_info *hw, bool en,
 786                                    u32 addr)
 787 {
 788         void __iomem *ioaddr = hw->pcsr;
 789         u32 value;
 790
 791         writel(addr, ioaddr + GMAC_ARP_ADDR);
 792
 793         value = readl(ioaddr + GMAC_CONFIG);
 794         if (en)
 795                 value |= GMAC_CONFIG_ARPEN;
 796         else
 797                 value &= ~GMAC_CONFIG_ARPEN;
 798         writel(value, ioaddr + GMAC_CONFIG);
 799 }
 800
 801 const struct stmmac_ops dwmac4_ops = {
 802         .core_init = dwmac4_core_init,
 803         .set_mac = stmmac_set_mac,
 804         .rx_ipc = dwmac4_rx_ipc_enable,
 805         .rx_queue_enable = dwmac4_rx_queue_enable,
 806         .rx_queue_prio = dwmac4_rx_queue_priority,
 807         .tx_queue_prio = dwmac4_tx_queue_priority,
 808         .rx_queue_routing = dwmac4_rx_queue_routing,
 809         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 810         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 811         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 812         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 813         .config_cbs = dwmac4_config_cbs,
 814         .dump_regs = dwmac4_dump_regs,
 815         .host_irq_status = dwmac4_irq_status,
 816         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 817         .flow_ctrl = dwmac4_flow_ctrl,
 818         .pmt = dwmac4_pmt,
 819         .set_umac_addr = dwmac4_set_umac_addr,
 820         .get_umac_addr = dwmac4_get_umac_addr,
 821         .set_eee_mode = dwmac4_set_eee_mode,
 822         .reset_eee_mode = dwmac4_reset_eee_mode,
 823         .set_eee_timer = dwmac4_set_eee_timer,
 824         .set_eee_pls = dwmac4_set_eee_pls,
 825         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 826         .pcs_rane = dwmac4_rane,
 827         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 828         .debug = dwmac4_debug,
 829         .set_filter = dwmac4_set_filter,
 830         .set_mac_loopback = dwmac4_set_mac_loopback,
 831         .update_vlan_hash = dwmac4_update_vlan_hash,
 832         .sarc_configure = dwmac4_sarc_configure,
 833         .enable_vlan = dwmac4_enable_vlan,
 834         .set_arp_offload = dwmac4_set_arp_offload,
 835 };
 836
 837 const struct stmmac_ops dwmac410_ops = {
 838         .core_init = dwmac4_core_init,
 839         .set_mac = stmmac_dwmac4_set_mac,
 840         .rx_ipc = dwmac4_rx_ipc_enable,
 841         .rx_queue_enable = dwmac4_rx_queue_enable,
 842         .rx_queue_prio = dwmac4_rx_queue_priority,
 843         .tx_queue_prio = dwmac4_tx_queue_priority,
 844         .rx_queue_routing = dwmac4_rx_queue_routing,
 845         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 846         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 847         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 848         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 849         .config_cbs = dwmac4_config_cbs,
 850         .dump_regs = dwmac4_dump_regs,
 851         .host_irq_status = dwmac4_irq_status,
 852         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 853         .flow_ctrl = dwmac4_flow_ctrl,
 854         .pmt = dwmac4_pmt,
 855         .set_umac_addr = dwmac4_set_umac_addr,
 856         .get_umac_addr = dwmac4_get_umac_addr,
 857         .set_eee_mode = dwmac4_set_eee_mode,
 858         .reset_eee_mode = dwmac4_reset_eee_mode,
 859         .set_eee_timer = dwmac4_set_eee_timer,
 860         .set_eee_pls = dwmac4_set_eee_pls,
 861         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 862         .pcs_rane = dwmac4_rane,
 863         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 864         .debug = dwmac4_debug,
 865         .set_filter = dwmac4_set_filter,
 866         .set_mac_loopback = dwmac4_set_mac_loopback,
 867         .update_vlan_hash = dwmac4_update_vlan_hash,
 868         .sarc_configure = dwmac4_sarc_configure,
 869         .enable_vlan = dwmac4_enable_vlan,
 870         .set_arp_offload = dwmac4_set_arp_offload,
 871 };
 872
 873 const struct stmmac_ops dwmac510_ops = {
 874         .core_init = dwmac4_core_init,
 875         .set_mac = stmmac_dwmac4_set_mac,
 876         .rx_ipc = dwmac4_rx_ipc_enable,
 877         .rx_queue_enable = dwmac4_rx_queue_enable,
 878         .rx_queue_prio = dwmac4_rx_queue_priority,
 879         .tx_queue_prio = dwmac4_tx_queue_priority,
 880         .rx_queue_routing = dwmac4_rx_queue_routing,
 881         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 882         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 883         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 884         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 885         .config_cbs = dwmac4_config_cbs,
 886         .dump_regs = dwmac4_dump_regs,
 887         .host_irq_status = dwmac4_irq_status,
 888         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 889         .flow_ctrl = dwmac4_flow_ctrl,
 890         .pmt = dwmac4_pmt,
 891         .set_umac_addr = dwmac4_set_umac_addr,
 892         .get_umac_addr = dwmac4_get_umac_addr,
 893         .set_eee_mode = dwmac4_set_eee_mode,
 894         .reset_eee_mode = dwmac4_reset_eee_mode,
 895         .set_eee_timer = dwmac4_set_eee_timer,
 896         .set_eee_pls = dwmac4_set_eee_pls,
 897         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 898         .pcs_rane = dwmac4_rane,
 899         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 900         .debug = dwmac4_debug,
 901         .set_filter = dwmac4_set_filter,
 902         .safety_feat_config = dwmac5_safety_feat_config,
 903         .safety_feat_irq_status = dwmac5_safety_feat_irq_status,
 904         .safety_feat_dump = dwmac5_safety_feat_dump,
 905         .rxp_config = dwmac5_rxp_config,
 906         .flex_pps_config = dwmac5_flex_pps_config,
 907         .set_mac_loopback = dwmac4_set_mac_loopback,
 908         .update_vlan_hash = dwmac4_update_vlan_hash,
 909         .sarc_configure = dwmac4_sarc_configure,
 910         .enable_vlan = dwmac4_enable_vlan,
 911         .set_arp_offload = dwmac4_set_arp_offload,
 912 };
 913
 914 int dwmac4_setup(struct stmmac_priv *priv)
 915 {
 916         struct mac_device_info *mac = priv->hw;
 917
 918         dev_info(priv->device, "\tDWMAC4/5\n");
 919
 920         priv->dev->priv_flags |= IFF_UNICAST_FLT;
 921         mac->pcsr = priv->ioaddr;
 922         mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
 923         mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
 924         mac->mcast_bits_log2 = 0;
 925
 926         if (mac->multicast_filter_bins)
 927                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 928
 929         mac->link.duplex = GMAC_CONFIG_DM;
 930         mac->link.speed10 = GMAC_CONFIG_PS;
 931         mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
 932         mac->link.speed1000 = 0;
 933         mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
 934         mac->mii.addr = GMAC_MDIO_ADDR;
 935         mac->mii.data = GMAC_MDIO_DATA;
 936         mac->mii.addr_shift = 21;
 937         mac->mii.addr_mask = GENMASK(25, 21);
 938         mac->mii.reg_shift = 16;
 939         mac->mii.reg_mask = GENMASK(20, 16);
 940         mac->mii.clk_csr_shift = 8;
 941         mac->mii.clk_csr_mask = GENMASK(11, 8);
 942
 943         return 0;
 944 }