drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 /*
   2  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3  * DWC Ether MAC version 4.00  has been used for developing this code.
   4  *
   5  * This only implements the mac core functions for this chip.
   6  *
   7  * Copyright (C) 2015  STMicroelectronics Ltd
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms and conditions of the GNU General Public License,
  11  * version 2, as published by the Free Software Foundation.
  12  *
  13  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  14  */
  15
  16 #include <linux/crc32.h>
  17 #include <linux/slab.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/io.h>
  20 #include "stmmac_pcs.h"
  21 #include "dwmac4.h"
  22
  23 static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
  24 {
  25         void __iomem *ioaddr = hw->pcsr;
  26         u32 value = readl(ioaddr + GMAC_CONFIG);
  27
  28         value |= GMAC_CORE_INIT;
  29
  30         if (mtu > 1500)
  31                 value |= GMAC_CONFIG_2K;
  32         if (mtu > 2000)
  33                 value |= GMAC_CONFIG_JE;
  34
  35         if (hw->ps) {
  36                 value |= GMAC_CONFIG_TE;
  37
  38                 if (hw->ps == SPEED_1000) {
  39                         value &= ~GMAC_CONFIG_PS;
  40                 } else {
  41                         value |= GMAC_CONFIG_PS;
  42
  43                         if (hw->ps == SPEED_10)
  44                                 value &= ~GMAC_CONFIG_FES;
  45                         else
  46                                 value |= GMAC_CONFIG_FES;
  47                 }
  48         }
  49
  50         writel(value, ioaddr + GMAC_CONFIG);
  51
  52         /* Mask GMAC interrupts */
  53         value = GMAC_INT_DEFAULT_MASK;
  54         if (hw->pmt)
  55                 value |= GMAC_INT_PMT_EN;
  56         if (hw->pcs)
  57                 value |= GMAC_PCS_IRQ_DEFAULT;
  58
  59         writel(value, ioaddr + GMAC_INT_EN);
  60 }
  61
  62 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
  63                                    u8 mode, u32 queue)
  64 {
  65         void __iomem *ioaddr = hw->pcsr;
  66         u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
  67
  68         value &= GMAC_RX_QUEUE_CLEAR(queue);
  69         if (mode == MTL_RX_AVB)
  70                 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
  71         else if (mode == MTL_RX_DCB)
  72                 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
  73
  74         writel(value, ioaddr + GMAC_RXQ_CTRL0);
  75 }
  76
  77 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
  78                                           u32 rx_alg)
  79 {
  80         void __iomem *ioaddr = hw->pcsr;
  81         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
  82
  83         value &= ~MTL_OPERATION_RAA;
  84         switch (rx_alg) {
  85         case MTL_RX_ALGORITHM_SP:
  86                 value |= MTL_OPERATION_RAA_SP;
  87                 break;
  88         case MTL_RX_ALGORITHM_WSP:
  89                 value |= MTL_OPERATION_RAA_WSP;
  90                 break;
  91         default:
  92                 break;
  93         }
  94
  95         writel(value, ioaddr + MTL_OPERATION_MODE);
  96 }
  97
  98 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
  99                                           u32 tx_alg)
 100 {
 101         void __iomem *ioaddr = hw->pcsr;
 102         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 103
 104         value &= ~MTL_OPERATION_SCHALG_MASK;
 105         switch (tx_alg) {
 106         case MTL_TX_ALGORITHM_WRR:
 107                 value |= MTL_OPERATION_SCHALG_WRR;
 108                 break;
 109         case MTL_TX_ALGORITHM_WFQ:
 110                 value |= MTL_OPERATION_SCHALG_WFQ;
 111                 break;
 112         case MTL_TX_ALGORITHM_DWRR:
 113                 value |= MTL_OPERATION_SCHALG_DWRR;
 114                 break;
 115         case MTL_TX_ALGORITHM_SP:
 116                 value |= MTL_OPERATION_SCHALG_SP;
 117                 break;
 118         default:
 119                 break;
 120         }
 121 }
 122
 123 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
 124                                            u32 weight, u32 queue)
 125 {
 126         void __iomem *ioaddr = hw->pcsr;
 127         u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 128
 129         value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
 130         value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
 131         writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 132 }
 133
 134 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
 135 {
 136         void __iomem *ioaddr = hw->pcsr;
 137         u32 value;
 138
 139         if (queue < 4)
 140                 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
 141         else
 142                 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
 143
 144         if (queue == 0 || queue == 4) {
 145                 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
 146                 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
 147         } else {
 148                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
 149                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
 150         }
 151
 152         if (queue < 4)
 153                 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
 154         else
 155                 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
 156 }
 157
 158 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 159 {
 160         void __iomem *ioaddr = hw->pcsr;
 161         int i;
 162
 163         for (i = 0; i < GMAC_REG_NUM; i++)
 164                 reg_space[i] = readl(ioaddr + i * 4);
 165 }
 166
 167 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
 168 {
 169         void __iomem *ioaddr = hw->pcsr;
 170         u32 value = readl(ioaddr + GMAC_CONFIG);
 171
 172         if (hw->rx_csum)
 173                 value |= GMAC_CONFIG_IPC;
 174         else
 175                 value &= ~GMAC_CONFIG_IPC;
 176
 177         writel(value, ioaddr + GMAC_CONFIG);
 178
 179         value = readl(ioaddr + GMAC_CONFIG);
 180
 181         return !!(value & GMAC_CONFIG_IPC);
 182 }
 183
 184 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 185 {
 186         void __iomem *ioaddr = hw->pcsr;
 187         unsigned int pmt = 0;
 188
 189         if (mode & WAKE_MAGIC) {
 190                 pr_debug("GMAC: WOL Magic frame\n");
 191                 pmt |= power_down | magic_pkt_en;
 192         }
 193         if (mode & WAKE_UCAST) {
 194                 pr_debug("GMAC: WOL on global unicast\n");
 195                 pmt |= power_down | global_unicast | wake_up_frame_en;
 196         }
 197
 198         writel(pmt, ioaddr + GMAC_PMT);
 199 }
 200
 201 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 202                                  unsigned char *addr, unsigned int reg_n)
 203 {
 204         void __iomem *ioaddr = hw->pcsr;
 205
 206         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 207                                    GMAC_ADDR_LOW(reg_n));
 208 }
 209
 210 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 211                                  unsigned char *addr, unsigned int reg_n)
 212 {
 213         void __iomem *ioaddr = hw->pcsr;
 214
 215         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 216                                    GMAC_ADDR_LOW(reg_n));
 217 }
 218
 219 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 220                                 bool en_tx_lpi_clockgating)
 221 {
 222         void __iomem *ioaddr = hw->pcsr;
 223         u32 value;
 224
 225         /* Enable the link status receive on RGMII, SGMII ore SMII
 226          * receive path and instruct the transmit to enter in LPI
 227          * state.
 228          */
 229         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 230         value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 231
 232         if (en_tx_lpi_clockgating)
 233                 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 234
 235         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 236 }
 237
 238 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 239 {
 240         void __iomem *ioaddr = hw->pcsr;
 241         u32 value;
 242
 243         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 244         value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 245         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 246 }
 247
 248 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 249 {
 250         void __iomem *ioaddr = hw->pcsr;
 251         u32 value;
 252
 253         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 254
 255         if (link)
 256                 value |= GMAC4_LPI_CTRL_STATUS_PLS;
 257         else
 258                 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 259
 260         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 261 }
 262
 263 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 264 {
 265         void __iomem *ioaddr = hw->pcsr;
 266         int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 267
 268         /* Program the timers in the LPI timer control register:
 269          * LS: minimum time (ms) for which the link
 270          *  status from PHY should be ok before transmitting
 271          *  the LPI pattern.
 272          * TW: minimum time (us) for which the core waits
 273          *  after it has stopped transmitting the LPI pattern.
 274          */
 275         writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 276 }
 277
 278 static void dwmac4_set_filter(struct mac_device_info *hw,
 279                               struct net_device *dev)
 280 {
 281         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 282         unsigned int value = 0;
 283
 284         if (dev->flags & IFF_PROMISC) {
 285                 value = GMAC_PACKET_FILTER_PR;
 286         } else if ((dev->flags & IFF_ALLMULTI) ||
 287                         (netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
 288                 /* Pass all multi */
 289                 value = GMAC_PACKET_FILTER_PM;
 290                 /* Set the 64 bits of the HASH tab. To be updated if taller
 291                  * hash table is used
 292                  */
 293                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
 294                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
 295         } else if (!netdev_mc_empty(dev)) {
 296                 u32 mc_filter[2];
 297                 struct netdev_hw_addr *ha;
 298
 299                 /* Hash filter for multicast */
 300                 value = GMAC_PACKET_FILTER_HMC;
 301
 302                 memset(mc_filter, 0, sizeof(mc_filter));
 303                 netdev_for_each_mc_addr(ha, dev) {
 304                         /* The upper 6 bits of the calculated CRC are used to
 305                          * index the content of the Hash Table Reg 0 and 1.
 306                          */
 307                         int bit_nr =
 308                                 (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
 309                         /* The most significant bit determines the register
 310                          * to use while the other 5 bits determines the bit
 311                          * within the selected register
 312                          */
 313                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
 314                 }
 315                 writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
 316                 writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
 317         }
 318
 319         /* Handle multiple unicast addresses */
 320         if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
 321                 /* Switch to promiscuous mode if more than 128 addrs
 322                  * are required
 323                  */
 324                 value |= GMAC_PACKET_FILTER_PR;
 325         } else if (!netdev_uc_empty(dev)) {
 326                 int reg = 1;
 327                 struct netdev_hw_addr *ha;
 328
 329                 netdev_for_each_uc_addr(ha, dev) {
 330                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 331                         reg++;
 332                 }
 333         }
 334
 335         writel(value, ioaddr + GMAC_PACKET_FILTER);
 336 }
 337
 338 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 339                              unsigned int fc, unsigned int pause_time,
 340                              u32 tx_cnt)
 341 {
 342         void __iomem *ioaddr = hw->pcsr;
 343         unsigned int flow = 0;
 344         u32 queue = 0;
 345
 346         pr_debug("GMAC Flow-Control:\n");
 347         if (fc & FLOW_RX) {
 348                 pr_debug("\tReceive Flow-Control ON\n");
 349                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 350                 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 351         }
 352         if (fc & FLOW_TX) {
 353                 pr_debug("\tTransmit Flow-Control ON\n");
 354
 355                 if (duplex)
 356                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 357
 358                 for (queue = 0; queue < tx_cnt; queue++) {
 359                         flow |= GMAC_TX_FLOW_CTRL_TFE;
 360
 361                         if (duplex)
 362                                 flow |=
 363                                 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 364
 365                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 366                 }
 367         }
 368 }
 369
 370 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 371                             bool loopback)
 372 {
 373         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 374 }
 375
 376 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
 377 {
 378         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 379 }
 380
 381 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 382 {
 383         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 384 }
 385
 386 /* RGMII or SMII interface */
 387 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 388 {
 389         u32 status;
 390
 391         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 392         x->irq_rgmii_n++;
 393
 394         /* Check the link status */
 395         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 396                 int speed_value;
 397
 398                 x->pcs_link = 1;
 399
 400                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 401                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 402                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 403                         x->pcs_speed = SPEED_1000;
 404                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 405                         x->pcs_speed = SPEED_100;
 406                 else
 407                         x->pcs_speed = SPEED_10;
 408
 409                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
 410
 411                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 412                         x->pcs_duplex ? "Full" : "Half");
 413         } else {
 414                 x->pcs_link = 0;
 415                 pr_info("Link is Down\n");
 416         }
 417 }
 418
 419 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
 420 {
 421         void __iomem *ioaddr = hw->pcsr;
 422         u32 mtl_int_qx_status;
 423         int ret = 0;
 424
 425         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 426
 427         /* Check MTL Interrupt */
 428         if (mtl_int_qx_status & MTL_INT_QX(chan)) {
 429                 /* read Queue x Interrupt status */
 430                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
 431
 432                 if (status & MTL_RX_OVERFLOW_INT) {
 433                         /*  clear Interrupt */
 434                         writel(status | MTL_RX_OVERFLOW_INT,
 435                                ioaddr + MTL_CHAN_INT_CTRL(chan));
 436                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 437                 }
 438         }
 439
 440         return ret;
 441 }
 442
 443 static int dwmac4_irq_status(struct mac_device_info *hw,
 444                              struct stmmac_extra_stats *x)
 445 {
 446         void __iomem *ioaddr = hw->pcsr;
 447         u32 intr_status;
 448         int ret = 0;
 449
 450         intr_status = readl(ioaddr + GMAC_INT_STATUS);
 451
 452         /* Not used events (e.g. MMC interrupts) are not handled. */
 453         if ((intr_status & mmc_tx_irq))
 454                 x->mmc_tx_irq_n++;
 455         if (unlikely(intr_status & mmc_rx_irq))
 456                 x->mmc_rx_irq_n++;
 457         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 458                 x->mmc_rx_csum_offload_irq_n++;
 459         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 460         if (unlikely(intr_status & pmt_irq)) {
 461                 readl(ioaddr + GMAC_PMT);
 462                 x->irq_receive_pmt_irq_n++;
 463         }
 464
 465         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 466         if (intr_status & PCS_RGSMIIIS_IRQ)
 467                 dwmac4_phystatus(ioaddr, x);
 468
 469         return ret;
 470 }
 471
 472 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 473                          u32 rx_queues, u32 tx_queues)
 474 {
 475         u32 value;
 476         u32 queue;
 477
 478         for (queue = 0; queue < tx_queues; queue++) {
 479                 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
 480
 481                 if (value & MTL_DEBUG_TXSTSFSTS)
 482                         x->mtl_tx_status_fifo_full++;
 483                 if (value & MTL_DEBUG_TXFSTS)
 484                         x->mtl_tx_fifo_not_empty++;
 485                 if (value & MTL_DEBUG_TWCSTS)
 486                         x->mmtl_fifo_ctrl++;
 487                 if (value & MTL_DEBUG_TRCSTS_MASK) {
 488                         u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 489                                      >> MTL_DEBUG_TRCSTS_SHIFT;
 490                         if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 491                                 x->mtl_tx_fifo_read_ctrl_write++;
 492                         else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 493                                 x->mtl_tx_fifo_read_ctrl_wait++;
 494                         else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 495                                 x->mtl_tx_fifo_read_ctrl_read++;
 496                         else
 497                                 x->mtl_tx_fifo_read_ctrl_idle++;
 498                 }
 499                 if (value & MTL_DEBUG_TXPAUSED)
 500                         x->mac_tx_in_pause++;
 501         }
 502
 503         for (queue = 0; queue < rx_queues; queue++) {
 504                 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
 505
 506                 if (value & MTL_DEBUG_RXFSTS_MASK) {
 507                         u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 508                                      >> MTL_DEBUG_RRCSTS_SHIFT;
 509
 510                         if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 511                                 x->mtl_rx_fifo_fill_level_full++;
 512                         else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 513                                 x->mtl_rx_fifo_fill_above_thresh++;
 514                         else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 515                                 x->mtl_rx_fifo_fill_below_thresh++;
 516                         else
 517                                 x->mtl_rx_fifo_fill_level_empty++;
 518                 }
 519                 if (value & MTL_DEBUG_RRCSTS_MASK) {
 520                         u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 521                                      MTL_DEBUG_RRCSTS_SHIFT;
 522
 523                         if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 524                                 x->mtl_rx_fifo_read_ctrl_flush++;
 525                         else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 526                                 x->mtl_rx_fifo_read_ctrl_read_data++;
 527                         else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 528                                 x->mtl_rx_fifo_read_ctrl_status++;
 529                         else
 530                                 x->mtl_rx_fifo_read_ctrl_idle++;
 531                 }
 532                 if (value & MTL_DEBUG_RWCSTS)
 533                         x->mtl_rx_fifo_ctrl_active++;
 534         }
 535
 536         /* GMAC debug */
 537         value = readl(ioaddr + GMAC_DEBUG);
 538
 539         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 540                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 541                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 542
 543                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 544                         x->mac_tx_frame_ctrl_xfer++;
 545                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 546                         x->mac_tx_frame_ctrl_pause++;
 547                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 548                         x->mac_tx_frame_ctrl_wait++;
 549                 else
 550                         x->mac_tx_frame_ctrl_idle++;
 551         }
 552         if (value & GMAC_DEBUG_TPESTS)
 553                 x->mac_gmii_tx_proto_engine++;
 554         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 555                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 556                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 557         if (value & GMAC_DEBUG_RPESTS)
 558                 x->mac_gmii_rx_proto_engine++;
 559 }
 560
 561 static const struct stmmac_ops dwmac4_ops = {
 562         .core_init = dwmac4_core_init,
 563         .rx_ipc = dwmac4_rx_ipc_enable,
 564         .rx_queue_enable = dwmac4_rx_queue_enable,
 565         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 566         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 567         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 568         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 569         .dump_regs = dwmac4_dump_regs,
 570         .host_irq_status = dwmac4_irq_status,
 571         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 572         .flow_ctrl = dwmac4_flow_ctrl,
 573         .pmt = dwmac4_pmt,
 574         .set_umac_addr = dwmac4_set_umac_addr,
 575         .get_umac_addr = dwmac4_get_umac_addr,
 576         .set_eee_mode = dwmac4_set_eee_mode,
 577         .reset_eee_mode = dwmac4_reset_eee_mode,
 578         .set_eee_timer = dwmac4_set_eee_timer,
 579         .set_eee_pls = dwmac4_set_eee_pls,
 580         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 581         .pcs_rane = dwmac4_rane,
 582         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 583         .debug = dwmac4_debug,
 584         .set_filter = dwmac4_set_filter,
 585 };
 586
 587 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
 588                                      int perfect_uc_entries, int *synopsys_id)
 589 {
 590         struct mac_device_info *mac;
 591         u32 hwid = readl(ioaddr + GMAC_VERSION);
 592
 593         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 594         if (!mac)
 595                 return NULL;
 596
 597         mac->pcsr = ioaddr;
 598         mac->multicast_filter_bins = mcbins;
 599         mac->unicast_filter_entries = perfect_uc_entries;
 600         mac->mcast_bits_log2 = 0;
 601
 602         if (mac->multicast_filter_bins)
 603                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 604
 605         mac->mac = &dwmac4_ops;
 606
 607         mac->link.port = GMAC_CONFIG_PS;
 608         mac->link.duplex = GMAC_CONFIG_DM;
 609         mac->link.speed = GMAC_CONFIG_FES;
 610         mac->mii.addr = GMAC_MDIO_ADDR;
 611         mac->mii.data = GMAC_MDIO_DATA;
 612         mac->mii.addr_shift = 21;
 613         mac->mii.addr_mask = GENMASK(25, 21);
 614         mac->mii.reg_shift = 16;
 615         mac->mii.reg_mask = GENMASK(20, 16);
 616         mac->mii.clk_csr_shift = 8;
 617         mac->mii.clk_csr_mask = GENMASK(11, 8);
 618
 619         /* Get and dump the chip ID */
 620         *synopsys_id = stmmac_get_synopsys_id(hwid);
 621
 622         if (*synopsys_id > DWMAC_CORE_4_00)
 623                 mac->dma = &dwmac410_dma_ops;
 624         else
 625                 mac->dma = &dwmac4_dma_ops;
 626
 627         return mac;
 628 }