drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c

   1 /*
   2  * This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3  * DWC Ether MAC version 4.00  has been used for developing this code.
   4  *
   5  * This only implements the mac core functions for this chip.
   6  *
   7  * Copyright (C) 2015  STMicroelectronics Ltd
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms and conditions of the GNU General Public License,
  11  * version 2, as published by the Free Software Foundation.
  12  *
  13  * Author: Alexandre Torgue <alexandre.torgue@st.com>
  14  */
  15
  16 #include <linux/crc32.h>
  17 #include <linux/slab.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/io.h>
  20 #include "stmmac_pcs.h"
  21 #include "dwmac4.h"
  22
  23 static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
  24 {
  25         void __iomem *ioaddr = hw->pcsr;
  26         u32 value = readl(ioaddr + GMAC_CONFIG);
  27
  28         value |= GMAC_CORE_INIT;
  29
  30         if (mtu > 1500)
  31                 value |= GMAC_CONFIG_2K;
  32         if (mtu > 2000)
  33                 value |= GMAC_CONFIG_JE;
  34
  35         if (hw->ps) {
  36                 value |= GMAC_CONFIG_TE;
  37
  38                 if (hw->ps == SPEED_1000) {
  39                         value &= ~GMAC_CONFIG_PS;
  40                 } else {
  41                         value |= GMAC_CONFIG_PS;
  42
  43                         if (hw->ps == SPEED_10)
  44                                 value &= ~GMAC_CONFIG_FES;
  45                         else
  46                                 value |= GMAC_CONFIG_FES;
  47                 }
  48         }
  49
  50         writel(value, ioaddr + GMAC_CONFIG);
  51
  52         /* Mask GMAC interrupts */
  53         value = GMAC_INT_DEFAULT_MASK;
  54         if (hw->pmt)
  55                 value |= GMAC_INT_PMT_EN;
  56         if (hw->pcs)
  57                 value |= GMAC_PCS_IRQ_DEFAULT;
  58
  59         writel(value, ioaddr + GMAC_INT_EN);
  60 }
  61
  62 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
  63                                    u8 mode, u32 queue)
  64 {
  65         void __iomem *ioaddr = hw->pcsr;
  66         u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
  67
  68         value &= GMAC_RX_QUEUE_CLEAR(queue);
  69         if (mode == MTL_QUEUE_AVB)
  70                 value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
  71         else if (mode == MTL_QUEUE_DCB)
  72                 value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
  73
  74         writel(value, ioaddr + GMAC_RXQ_CTRL0);
  75 }
  76
  77 static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
  78                                           u32 rx_alg)
  79 {
  80         void __iomem *ioaddr = hw->pcsr;
  81         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
  82
  83         value &= ~MTL_OPERATION_RAA;
  84         switch (rx_alg) {
  85         case MTL_RX_ALGORITHM_SP:
  86                 value |= MTL_OPERATION_RAA_SP;
  87                 break;
  88         case MTL_RX_ALGORITHM_WSP:
  89                 value |= MTL_OPERATION_RAA_WSP;
  90                 break;
  91         default:
  92                 break;
  93         }
  94
  95         writel(value, ioaddr + MTL_OPERATION_MODE);
  96 }
  97
  98 static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
  99                                           u32 tx_alg)
 100 {
 101         void __iomem *ioaddr = hw->pcsr;
 102         u32 value = readl(ioaddr + MTL_OPERATION_MODE);
 103
 104         value &= ~MTL_OPERATION_SCHALG_MASK;
 105         switch (tx_alg) {
 106         case MTL_TX_ALGORITHM_WRR:
 107                 value |= MTL_OPERATION_SCHALG_WRR;
 108                 break;
 109         case MTL_TX_ALGORITHM_WFQ:
 110                 value |= MTL_OPERATION_SCHALG_WFQ;
 111                 break;
 112         case MTL_TX_ALGORITHM_DWRR:
 113                 value |= MTL_OPERATION_SCHALG_DWRR;
 114                 break;
 115         case MTL_TX_ALGORITHM_SP:
 116                 value |= MTL_OPERATION_SCHALG_SP;
 117                 break;
 118         default:
 119                 break;
 120         }
 121 }
 122
 123 static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
 124                                            u32 weight, u32 queue)
 125 {
 126         void __iomem *ioaddr = hw->pcsr;
 127         u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 128
 129         value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
 130         value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
 131         writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
 132 }
 133
 134 static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
 135 {
 136         void __iomem *ioaddr = hw->pcsr;
 137         u32 value;
 138
 139         if (queue < 4)
 140                 value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
 141         else
 142                 value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
 143
 144         if (queue == 0 || queue == 4) {
 145                 value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
 146                 value |= MTL_RXQ_DMA_Q04MDMACH(chan);
 147         } else {
 148                 value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
 149                 value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
 150         }
 151
 152         if (queue < 4)
 153                 writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
 154         else
 155                 writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
 156 }
 157
 158 static void dwmac4_config_cbs(struct mac_device_info *hw,
 159                               u32 send_slope, u32 idle_slope,
 160                               u32 high_credit, u32 low_credit, u32 queue)
 161 {
 162         void __iomem *ioaddr = hw->pcsr;
 163         u32 value;
 164
 165         pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
 166         pr_debug("\tsend_slope: 0x%08x\n", send_slope);
 167         pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
 168         pr_debug("\thigh_credit: 0x%08x\n", high_credit);
 169         pr_debug("\tlow_credit: 0x%08x\n", low_credit);
 170
 171         /* enable AV algorithm */
 172         value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 173         value |= MTL_ETS_CTRL_AVALG;
 174         value |= MTL_ETS_CTRL_CC;
 175         writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
 176
 177         /* configure send slope */
 178         value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 179         value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
 180         value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
 181         writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
 182
 183         /* configure idle slope (same register as tx weight) */
 184         dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
 185
 186         /* configure high credit */
 187         value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 188         value &= ~MTL_HIGH_CRED_HC_MASK;
 189         value |= high_credit & MTL_HIGH_CRED_HC_MASK;
 190         writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
 191
 192         /* configure high credit */
 193         value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 194         value &= ~MTL_HIGH_CRED_LC_MASK;
 195         value |= low_credit & MTL_HIGH_CRED_LC_MASK;
 196         writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
 197 }
 198
 199 static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 200 {
 201         void __iomem *ioaddr = hw->pcsr;
 202         int i;
 203
 204         for (i = 0; i < GMAC_REG_NUM; i++)
 205                 reg_space[i] = readl(ioaddr + i * 4);
 206 }
 207
 208 static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
 209 {
 210         void __iomem *ioaddr = hw->pcsr;
 211         u32 value = readl(ioaddr + GMAC_CONFIG);
 212
 213         if (hw->rx_csum)
 214                 value |= GMAC_CONFIG_IPC;
 215         else
 216                 value &= ~GMAC_CONFIG_IPC;
 217
 218         writel(value, ioaddr + GMAC_CONFIG);
 219
 220         value = readl(ioaddr + GMAC_CONFIG);
 221
 222         return !!(value & GMAC_CONFIG_IPC);
 223 }
 224
 225 static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
 226 {
 227         void __iomem *ioaddr = hw->pcsr;
 228         unsigned int pmt = 0;
 229
 230         if (mode & WAKE_MAGIC) {
 231                 pr_debug("GMAC: WOL Magic frame\n");
 232                 pmt |= power_down | magic_pkt_en;
 233         }
 234         if (mode & WAKE_UCAST) {
 235                 pr_debug("GMAC: WOL on global unicast\n");
 236                 pmt |= power_down | global_unicast | wake_up_frame_en;
 237         }
 238
 239         writel(pmt, ioaddr + GMAC_PMT);
 240 }
 241
 242 static void dwmac4_set_umac_addr(struct mac_device_info *hw,
 243                                  unsigned char *addr, unsigned int reg_n)
 244 {
 245         void __iomem *ioaddr = hw->pcsr;
 246
 247         stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 248                                    GMAC_ADDR_LOW(reg_n));
 249 }
 250
 251 static void dwmac4_get_umac_addr(struct mac_device_info *hw,
 252                                  unsigned char *addr, unsigned int reg_n)
 253 {
 254         void __iomem *ioaddr = hw->pcsr;
 255
 256         stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
 257                                    GMAC_ADDR_LOW(reg_n));
 258 }
 259
 260 static void dwmac4_set_eee_mode(struct mac_device_info *hw,
 261                                 bool en_tx_lpi_clockgating)
 262 {
 263         void __iomem *ioaddr = hw->pcsr;
 264         u32 value;
 265
 266         /* Enable the link status receive on RGMII, SGMII ore SMII
 267          * receive path and instruct the transmit to enter in LPI
 268          * state.
 269          */
 270         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 271         value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
 272
 273         if (en_tx_lpi_clockgating)
 274                 value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
 275
 276         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 277 }
 278
 279 static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
 280 {
 281         void __iomem *ioaddr = hw->pcsr;
 282         u32 value;
 283
 284         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 285         value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
 286         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 287 }
 288
 289 static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
 290 {
 291         void __iomem *ioaddr = hw->pcsr;
 292         u32 value;
 293
 294         value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
 295
 296         if (link)
 297                 value |= GMAC4_LPI_CTRL_STATUS_PLS;
 298         else
 299                 value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
 300
 301         writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
 302 }
 303
 304 static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
 305 {
 306         void __iomem *ioaddr = hw->pcsr;
 307         int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
 308
 309         /* Program the timers in the LPI timer control register:
 310          * LS: minimum time (ms) for which the link
 311          *  status from PHY should be ok before transmitting
 312          *  the LPI pattern.
 313          * TW: minimum time (us) for which the core waits
 314          *  after it has stopped transmitting the LPI pattern.
 315          */
 316         writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
 317 }
 318
 319 static void dwmac4_set_filter(struct mac_device_info *hw,
 320                               struct net_device *dev)
 321 {
 322         void __iomem *ioaddr = (void __iomem *)dev->base_addr;
 323         unsigned int value = 0;
 324
 325         if (dev->flags & IFF_PROMISC) {
 326                 value = GMAC_PACKET_FILTER_PR;
 327         } else if ((dev->flags & IFF_ALLMULTI) ||
 328                         (netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
 329                 /* Pass all multi */
 330                 value = GMAC_PACKET_FILTER_PM;
 331                 /* Set the 64 bits of the HASH tab. To be updated if taller
 332                  * hash table is used
 333                  */
 334                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
 335                 writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
 336         } else if (!netdev_mc_empty(dev)) {
 337                 u32 mc_filter[2];
 338                 struct netdev_hw_addr *ha;
 339
 340                 /* Hash filter for multicast */
 341                 value = GMAC_PACKET_FILTER_HMC;
 342
 343                 memset(mc_filter, 0, sizeof(mc_filter));
 344                 netdev_for_each_mc_addr(ha, dev) {
 345                         /* The upper 6 bits of the calculated CRC are used to
 346                          * index the content of the Hash Table Reg 0 and 1.
 347                          */
 348                         int bit_nr =
 349                                 (bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
 350                         /* The most significant bit determines the register
 351                          * to use while the other 5 bits determines the bit
 352                          * within the selected register
 353                          */
 354                         mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
 355                 }
 356                 writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
 357                 writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
 358         }
 359
 360         /* Handle multiple unicast addresses */
 361         if (netdev_uc_count(dev) > GMAC_MAX_PERFECT_ADDRESSES) {
 362                 /* Switch to promiscuous mode if more than 128 addrs
 363                  * are required
 364                  */
 365                 value |= GMAC_PACKET_FILTER_PR;
 366         } else if (!netdev_uc_empty(dev)) {
 367                 int reg = 1;
 368                 struct netdev_hw_addr *ha;
 369
 370                 netdev_for_each_uc_addr(ha, dev) {
 371                         dwmac4_set_umac_addr(hw, ha->addr, reg);
 372                         reg++;
 373                 }
 374         }
 375
 376         writel(value, ioaddr + GMAC_PACKET_FILTER);
 377 }
 378
 379 static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
 380                              unsigned int fc, unsigned int pause_time,
 381                              u32 tx_cnt)
 382 {
 383         void __iomem *ioaddr = hw->pcsr;
 384         unsigned int flow = 0;
 385         u32 queue = 0;
 386
 387         pr_debug("GMAC Flow-Control:\n");
 388         if (fc & FLOW_RX) {
 389                 pr_debug("\tReceive Flow-Control ON\n");
 390                 flow |= GMAC_RX_FLOW_CTRL_RFE;
 391                 writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
 392         }
 393         if (fc & FLOW_TX) {
 394                 pr_debug("\tTransmit Flow-Control ON\n");
 395
 396                 if (duplex)
 397                         pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
 398
 399                 for (queue = 0; queue < tx_cnt; queue++) {
 400                         flow |= GMAC_TX_FLOW_CTRL_TFE;
 401
 402                         if (duplex)
 403                                 flow |=
 404                                 (pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
 405
 406                         writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
 407                 }
 408         }
 409 }
 410
 411 static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
 412                             bool loopback)
 413 {
 414         dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
 415 }
 416
 417 static void dwmac4_rane(void __iomem *ioaddr, bool restart)
 418 {
 419         dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
 420 }
 421
 422 static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 423 {
 424         dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 425 }
 426
 427 /* RGMII or SMII interface */
 428 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 429 {
 430         u32 status;
 431
 432         status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
 433         x->irq_rgmii_n++;
 434
 435         /* Check the link status */
 436         if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
 437                 int speed_value;
 438
 439                 x->pcs_link = 1;
 440
 441                 speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
 442                                GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
 443                 if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
 444                         x->pcs_speed = SPEED_1000;
 445                 else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
 446                         x->pcs_speed = SPEED_100;
 447                 else
 448                         x->pcs_speed = SPEED_10;
 449
 450                 x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
 451
 452                 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
 453                         x->pcs_duplex ? "Full" : "Half");
 454         } else {
 455                 x->pcs_link = 0;
 456                 pr_info("Link is Down\n");
 457         }
 458 }
 459
 460 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
 461 {
 462         void __iomem *ioaddr = hw->pcsr;
 463         u32 mtl_int_qx_status;
 464         int ret = 0;
 465
 466         mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
 467
 468         /* Check MTL Interrupt */
 469         if (mtl_int_qx_status & MTL_INT_QX(chan)) {
 470                 /* read Queue x Interrupt status */
 471                 u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
 472
 473                 if (status & MTL_RX_OVERFLOW_INT) {
 474                         /*  clear Interrupt */
 475                         writel(status | MTL_RX_OVERFLOW_INT,
 476                                ioaddr + MTL_CHAN_INT_CTRL(chan));
 477                         ret = CORE_IRQ_MTL_RX_OVERFLOW;
 478                 }
 479         }
 480
 481         return ret;
 482 }
 483
 484 static int dwmac4_irq_status(struct mac_device_info *hw,
 485                              struct stmmac_extra_stats *x)
 486 {
 487         void __iomem *ioaddr = hw->pcsr;
 488         u32 intr_status;
 489         int ret = 0;
 490
 491         intr_status = readl(ioaddr + GMAC_INT_STATUS);
 492
 493         /* Not used events (e.g. MMC interrupts) are not handled. */
 494         if ((intr_status & mmc_tx_irq))
 495                 x->mmc_tx_irq_n++;
 496         if (unlikely(intr_status & mmc_rx_irq))
 497                 x->mmc_rx_irq_n++;
 498         if (unlikely(intr_status & mmc_rx_csum_offload_irq))
 499                 x->mmc_rx_csum_offload_irq_n++;
 500         /* Clear the PMT bits 5 and 6 by reading the PMT status reg */
 501         if (unlikely(intr_status & pmt_irq)) {
 502                 readl(ioaddr + GMAC_PMT);
 503                 x->irq_receive_pmt_irq_n++;
 504         }
 505
 506         dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
 507         if (intr_status & PCS_RGSMIIIS_IRQ)
 508                 dwmac4_phystatus(ioaddr, x);
 509
 510         return ret;
 511 }
 512
 513 static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 514                          u32 rx_queues, u32 tx_queues)
 515 {
 516         u32 value;
 517         u32 queue;
 518
 519         for (queue = 0; queue < tx_queues; queue++) {
 520                 value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
 521
 522                 if (value & MTL_DEBUG_TXSTSFSTS)
 523                         x->mtl_tx_status_fifo_full++;
 524                 if (value & MTL_DEBUG_TXFSTS)
 525                         x->mtl_tx_fifo_not_empty++;
 526                 if (value & MTL_DEBUG_TWCSTS)
 527                         x->mmtl_fifo_ctrl++;
 528                 if (value & MTL_DEBUG_TRCSTS_MASK) {
 529                         u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
 530                                      >> MTL_DEBUG_TRCSTS_SHIFT;
 531                         if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
 532                                 x->mtl_tx_fifo_read_ctrl_write++;
 533                         else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
 534                                 x->mtl_tx_fifo_read_ctrl_wait++;
 535                         else if (trcsts == MTL_DEBUG_TRCSTS_READ)
 536                                 x->mtl_tx_fifo_read_ctrl_read++;
 537                         else
 538                                 x->mtl_tx_fifo_read_ctrl_idle++;
 539                 }
 540                 if (value & MTL_DEBUG_TXPAUSED)
 541                         x->mac_tx_in_pause++;
 542         }
 543
 544         for (queue = 0; queue < rx_queues; queue++) {
 545                 value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
 546
 547                 if (value & MTL_DEBUG_RXFSTS_MASK) {
 548                         u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
 549                                      >> MTL_DEBUG_RRCSTS_SHIFT;
 550
 551                         if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
 552                                 x->mtl_rx_fifo_fill_level_full++;
 553                         else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
 554                                 x->mtl_rx_fifo_fill_above_thresh++;
 555                         else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
 556                                 x->mtl_rx_fifo_fill_below_thresh++;
 557                         else
 558                                 x->mtl_rx_fifo_fill_level_empty++;
 559                 }
 560                 if (value & MTL_DEBUG_RRCSTS_MASK) {
 561                         u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
 562                                      MTL_DEBUG_RRCSTS_SHIFT;
 563
 564                         if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
 565                                 x->mtl_rx_fifo_read_ctrl_flush++;
 566                         else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
 567                                 x->mtl_rx_fifo_read_ctrl_read_data++;
 568                         else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
 569                                 x->mtl_rx_fifo_read_ctrl_status++;
 570                         else
 571                                 x->mtl_rx_fifo_read_ctrl_idle++;
 572                 }
 573                 if (value & MTL_DEBUG_RWCSTS)
 574                         x->mtl_rx_fifo_ctrl_active++;
 575         }
 576
 577         /* GMAC debug */
 578         value = readl(ioaddr + GMAC_DEBUG);
 579
 580         if (value & GMAC_DEBUG_TFCSTS_MASK) {
 581                 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
 582                               >> GMAC_DEBUG_TFCSTS_SHIFT;
 583
 584                 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
 585                         x->mac_tx_frame_ctrl_xfer++;
 586                 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
 587                         x->mac_tx_frame_ctrl_pause++;
 588                 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
 589                         x->mac_tx_frame_ctrl_wait++;
 590                 else
 591                         x->mac_tx_frame_ctrl_idle++;
 592         }
 593         if (value & GMAC_DEBUG_TPESTS)
 594                 x->mac_gmii_tx_proto_engine++;
 595         if (value & GMAC_DEBUG_RFCFCSTS_MASK)
 596                 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
 597                                             >> GMAC_DEBUG_RFCFCSTS_SHIFT;
 598         if (value & GMAC_DEBUG_RPESTS)
 599                 x->mac_gmii_rx_proto_engine++;
 600 }
 601
 602 static const struct stmmac_ops dwmac4_ops = {
 603         .core_init = dwmac4_core_init,
 604         .rx_ipc = dwmac4_rx_ipc_enable,
 605         .rx_queue_enable = dwmac4_rx_queue_enable,
 606         .prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
 607         .prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
 608         .set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
 609         .map_mtl_to_dma = dwmac4_map_mtl_dma,
 610         .config_cbs = dwmac4_config_cbs,
 611         .dump_regs = dwmac4_dump_regs,
 612         .host_irq_status = dwmac4_irq_status,
 613         .host_mtl_irq_status = dwmac4_irq_mtl_status,
 614         .flow_ctrl = dwmac4_flow_ctrl,
 615         .pmt = dwmac4_pmt,
 616         .set_umac_addr = dwmac4_set_umac_addr,
 617         .get_umac_addr = dwmac4_get_umac_addr,
 618         .set_eee_mode = dwmac4_set_eee_mode,
 619         .reset_eee_mode = dwmac4_reset_eee_mode,
 620         .set_eee_timer = dwmac4_set_eee_timer,
 621         .set_eee_pls = dwmac4_set_eee_pls,
 622         .pcs_ctrl_ane = dwmac4_ctrl_ane,
 623         .pcs_rane = dwmac4_rane,
 624         .pcs_get_adv_lp = dwmac4_get_adv_lp,
 625         .debug = dwmac4_debug,
 626         .set_filter = dwmac4_set_filter,
 627 };
 628
 629 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
 630                                      int perfect_uc_entries, int *synopsys_id)
 631 {
 632         struct mac_device_info *mac;
 633         u32 hwid = readl(ioaddr + GMAC_VERSION);
 634
 635         mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
 636         if (!mac)
 637                 return NULL;
 638
 639         mac->pcsr = ioaddr;
 640         mac->multicast_filter_bins = mcbins;
 641         mac->unicast_filter_entries = perfect_uc_entries;
 642         mac->mcast_bits_log2 = 0;
 643
 644         if (mac->multicast_filter_bins)
 645                 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
 646
 647         mac->mac = &dwmac4_ops;
 648
 649         mac->link.port = GMAC_CONFIG_PS;
 650         mac->link.duplex = GMAC_CONFIG_DM;
 651         mac->link.speed = GMAC_CONFIG_FES;
 652         mac->mii.addr = GMAC_MDIO_ADDR;
 653         mac->mii.data = GMAC_MDIO_DATA;
 654         mac->mii.addr_shift = 21;
 655         mac->mii.addr_mask = GENMASK(25, 21);
 656         mac->mii.reg_shift = 16;
 657         mac->mii.reg_mask = GENMASK(20, 16);
 658         mac->mii.clk_csr_shift = 8;
 659         mac->mii.clk_csr_mask = GENMASK(11, 8);
 660
 661         /* Get and dump the chip ID */
 662         *synopsys_id = stmmac_get_synopsys_id(hwid);
 663
 664         if (*synopsys_id > DWMAC_CORE_4_00)
 665                 mac->dma = &dwmac410_dma_ops;
 666         else
 667                 mac->dma = &dwmac4_dma_ops;
 668
 669         return mac;
 670 }