4 * Copyright (C) 2015 STMicroelectronics Ltd
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * Author: Alexandre Torgue <alexandre.torgue@st.com>
19 #define GMAC_CONFIG 0x00000000
20 #define GMAC_PACKET_FILTER 0x00000008
21 #define GMAC_HASH_TAB_0_31 0x00000010
22 #define GMAC_HASH_TAB_32_63 0x00000014
23 #define GMAC_RX_FLOW_CTRL 0x00000090
24 #define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4)
25 #define GMAC_TXQ_PRTY_MAP0 0x98
26 #define GMAC_TXQ_PRTY_MAP1 0x9C
27 #define GMAC_RXQ_CTRL0 0x000000a0
28 #define GMAC_RXQ_CTRL1 0x000000a4
29 #define GMAC_RXQ_CTRL2 0x000000a8
30 #define GMAC_RXQ_CTRL3 0x000000ac
31 #define GMAC_INT_STATUS 0x000000b0
32 #define GMAC_INT_EN 0x000000b4
33 #define GMAC_1US_TIC_COUNTER 0x000000dc
34 #define GMAC_PCS_BASE 0x000000e0
35 #define GMAC_PHYIF_CONTROL_STATUS 0x000000f8
36 #define GMAC_PMT 0x000000c0
37 #define GMAC_VERSION 0x00000110
38 #define GMAC_DEBUG 0x00000114
39 #define GMAC_HW_FEATURE0 0x0000011c
40 #define GMAC_HW_FEATURE1 0x00000120
41 #define GMAC_HW_FEATURE2 0x00000124
42 #define GMAC_MDIO_ADDR 0x00000200
43 #define GMAC_MDIO_DATA 0x00000204
44 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8)
45 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8)
47 /* MAC Packet Filtering */
48 #define GMAC_PACKET_FILTER_PR BIT(0)
49 #define GMAC_PACKET_FILTER_HMC BIT(2)
50 #define GMAC_PACKET_FILTER_PM BIT(4)
52 #define GMAC_MAX_PERFECT_ADDRESSES 128
54 /* MAC RX Queue Enable */
55 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))
56 #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2)
57 #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1)
59 /* MAC Flow Control RX */
60 #define GMAC_RX_FLOW_CTRL_RFE BIT(0)
62 /* RX Queues Priorities */
63 #define GMAC_RXQCTRL_PSRQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
64 #define GMAC_RXQCTRL_PSRQX_SHIFT(x) ((x) * 8)
66 /* TX Queues Priorities */
67 #define GMAC_TXQCTRL_PSTQX_MASK(x) GENMASK(7 + ((x) * 8), 0 + ((x) * 8))
68 #define GMAC_TXQCTRL_PSTQX_SHIFT(x) ((x) * 8)
70 /* MAC Flow Control TX */
71 #define GMAC_TX_FLOW_CTRL_TFE BIT(1)
72 #define GMAC_TX_FLOW_CTRL_PT_SHIFT 16
74 /* MAC Interrupt bitmap*/
75 #define GMAC_INT_RGSMIIS BIT(0)
76 #define GMAC_INT_PCS_LINK BIT(1)
77 #define GMAC_INT_PCS_ANE BIT(2)
78 #define GMAC_INT_PCS_PHYIS BIT(3)
79 #define GMAC_INT_PMT_EN BIT(4)
80 #define GMAC_INT_LPI_EN BIT(5)
82 #define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \
85 #define GMAC_INT_DEFAULT_MASK GMAC_INT_PMT_EN
87 enum dwmac4_irq_status {
88 time_stamp_irq = 0x00001000,
89 mmc_rx_csum_offload_irq = 0x00000800,
90 mmc_tx_irq = 0x00000400,
91 mmc_rx_irq = 0x00000200,
98 pointer_reset = 0x80000000,
99 global_unicast = 0x00000200,
100 wake_up_rx_frame = 0x00000040,
101 magic_frame = 0x00000020,
102 wake_up_frame_en = 0x00000004,
103 magic_pkt_en = 0x00000002,
104 power_down = 0x00000001,
107 /* Energy Efficient Ethernet (EEE) for GMAC4
109 * LPI status, timer and control register offset
111 #define GMAC4_LPI_CTRL_STATUS 0xd0
112 #define GMAC4_LPI_TIMER_CTRL 0xd4
114 /* LPI control and status defines */
115 #define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */
116 #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
117 #define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */
118 #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
120 /* MAC Debug bitmap */
121 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
122 #define GMAC_DEBUG_TFCSTS_SHIFT 17
123 #define GMAC_DEBUG_TFCSTS_IDLE 0
124 #define GMAC_DEBUG_TFCSTS_WAIT 1
125 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
126 #define GMAC_DEBUG_TFCSTS_XFER 3
127 #define GMAC_DEBUG_TPESTS BIT(16)
128 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
129 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1
130 #define GMAC_DEBUG_RPESTS BIT(0)
133 #define GMAC_CONFIG_IPC BIT(27)
134 #define GMAC_CONFIG_2K BIT(22)
135 #define GMAC_CONFIG_ACS BIT(20)
136 #define GMAC_CONFIG_BE BIT(18)
137 #define GMAC_CONFIG_JD BIT(17)
138 #define GMAC_CONFIG_JE BIT(16)
139 #define GMAC_CONFIG_PS BIT(15)
140 #define GMAC_CONFIG_FES BIT(14)
141 #define GMAC_CONFIG_DM BIT(13)
142 #define GMAC_CONFIG_DCRS BIT(9)
143 #define GMAC_CONFIG_TE BIT(1)
144 #define GMAC_CONFIG_RE BIT(0)
146 /* MAC HW features0 bitmap */
147 #define GMAC_HW_FEAT_ADDMAC BIT(18)
148 #define GMAC_HW_FEAT_RXCOESEL BIT(16)
149 #define GMAC_HW_FEAT_TXCOSEL BIT(14)
150 #define GMAC_HW_FEAT_EEESEL BIT(13)
151 #define GMAC_HW_FEAT_TSSEL BIT(12)
152 #define GMAC_HW_FEAT_MMCSEL BIT(8)
153 #define GMAC_HW_FEAT_MGKSEL BIT(7)
154 #define GMAC_HW_FEAT_RWKSEL BIT(6)
155 #define GMAC_HW_FEAT_SMASEL BIT(5)
156 #define GMAC_HW_FEAT_VLHASH BIT(4)
157 #define GMAC_HW_FEAT_PCSSEL BIT(3)
158 #define GMAC_HW_FEAT_HDSEL BIT(2)
159 #define GMAC_HW_FEAT_GMIISEL BIT(1)
160 #define GMAC_HW_FEAT_MIISEL BIT(0)
162 /* MAC HW features1 bitmap */
163 #define GMAC_HW_FEAT_AVSEL BIT(20)
164 #define GMAC_HW_TSOEN BIT(18)
165 #define GMAC_HW_TXFIFOSIZE GENMASK(10, 6)
166 #define GMAC_HW_RXFIFOSIZE GENMASK(4, 0)
168 /* MAC HW features2 bitmap */
169 #define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18)
170 #define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12)
171 #define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6)
172 #define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0)
174 /* MAC HW ADDR regs */
175 #define GMAC_HI_DCS GENMASK(18, 16)
176 #define GMAC_HI_DCS_SHIFT 16
177 #define GMAC_HI_REG_AE BIT(31)
180 #define MTL_OPERATION_MODE 0x00000c00
181 #define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5)
182 #define MTL_OPERATION_SCHALG_WRR (0x0 << 5)
183 #define MTL_OPERATION_SCHALG_WFQ (0x1 << 5)
184 #define MTL_OPERATION_SCHALG_DWRR (0x2 << 5)
185 #define MTL_OPERATION_SCHALG_SP (0x3 << 5)
186 #define MTL_OPERATION_RAA BIT(2)
187 #define MTL_OPERATION_RAA_SP (0x0 << 2)
188 #define MTL_OPERATION_RAA_WSP (0x1 << 2)
190 #define MTL_INT_STATUS 0x00000c20
191 #define MTL_INT_QX(x) BIT(x)
193 #define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */
194 #define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */
195 #define MTL_RXQ_DMA_Q04MDMACH_MASK GENMASK(3, 0)
196 #define MTL_RXQ_DMA_Q04MDMACH(x) ((x) << 0)
197 #define MTL_RXQ_DMA_QXMDMACH_MASK(x) GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
198 #define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q)))
200 #define MTL_CHAN_BASE_ADDR 0x00000d00
201 #define MTL_CHAN_BASE_OFFSET 0x40
202 #define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \
203 (x * MTL_CHAN_BASE_OFFSET))
205 #define MTL_CHAN_TX_OP_MODE(x) MTL_CHANX_BASE_ADDR(x)
206 #define MTL_CHAN_TX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x8)
207 #define MTL_CHAN_INT_CTRL(x) (MTL_CHANX_BASE_ADDR(x) + 0x2c)
208 #define MTL_CHAN_RX_OP_MODE(x) (MTL_CHANX_BASE_ADDR(x) + 0x30)
209 #define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38)
211 #define MTL_OP_MODE_RSF BIT(5)
212 #define MTL_OP_MODE_TXQEN BIT(3)
213 #define MTL_OP_MODE_TSF BIT(1)
215 #define MTL_OP_MODE_TQS_MASK GENMASK(24, 16)
216 #define MTL_OP_MODE_TQS_SHIFT 16
218 #define MTL_OP_MODE_TTC_MASK 0x70
219 #define MTL_OP_MODE_TTC_SHIFT 4
221 #define MTL_OP_MODE_TTC_32 0
222 #define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT)
223 #define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT)
224 #define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT)
225 #define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT)
226 #define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT)
227 #define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT)
228 #define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT)
230 #define MTL_OP_MODE_RQS_MASK GENMASK(29, 20)
231 #define MTL_OP_MODE_RQS_SHIFT 20
233 #define MTL_OP_MODE_RFD_MASK GENMASK(19, 14)
234 #define MTL_OP_MODE_RFD_SHIFT 14
236 #define MTL_OP_MODE_RFA_MASK GENMASK(13, 8)
237 #define MTL_OP_MODE_RFA_SHIFT 8
239 #define MTL_OP_MODE_EHFC BIT(7)
241 #define MTL_OP_MODE_RTC_MASK 0x18
242 #define MTL_OP_MODE_RTC_SHIFT 3
244 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT)
245 #define MTL_OP_MODE_RTC_64 0
246 #define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT)
247 #define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT)
249 /* MTL ETS Control register */
250 #define MTL_ETS_CTRL_BASE_ADDR 0x00000d10
251 #define MTL_ETS_CTRL_BASE_OFFSET 0x40
252 #define MTL_ETSX_CTRL_BASE_ADDR(x) (MTL_ETS_CTRL_BASE_ADDR + \
253 ((x) * MTL_ETS_CTRL_BASE_OFFSET))
255 #define MTL_ETS_CTRL_CC BIT(3)
256 #define MTL_ETS_CTRL_AVALG BIT(2)
258 /* MTL Queue Quantum Weight */
259 #define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18
260 #define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40
261 #define MTL_TXQX_WEIGHT_BASE_ADDR(x) (MTL_TXQ_WEIGHT_BASE_ADDR + \
262 ((x) * MTL_TXQ_WEIGHT_BASE_OFFSET))
263 #define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0)
265 /* MTL sendSlopeCredit register */
266 #define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c
267 #define MTL_SEND_SLP_CRED_OFFSET 0x40
268 #define MTL_SEND_SLP_CREDX_BASE_ADDR(x) (MTL_SEND_SLP_CRED_BASE_ADDR + \
269 ((x) * MTL_SEND_SLP_CRED_OFFSET))
271 #define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0)
273 /* MTL hiCredit register */
274 #define MTL_HIGH_CRED_BASE_ADDR 0x00000d20
275 #define MTL_HIGH_CRED_OFFSET 0x40
276 #define MTL_HIGH_CREDX_BASE_ADDR(x) (MTL_HIGH_CRED_BASE_ADDR + \
277 ((x) * MTL_HIGH_CRED_OFFSET))
279 #define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0)
281 /* MTL loCredit register */
282 #define MTL_LOW_CRED_BASE_ADDR 0x00000d24
283 #define MTL_LOW_CRED_OFFSET 0x40
284 #define MTL_LOW_CREDX_BASE_ADDR(x) (MTL_LOW_CRED_BASE_ADDR + \
285 ((x) * MTL_LOW_CRED_OFFSET))
287 #define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0)
290 #define MTL_DEBUG_TXSTSFSTS BIT(5)
291 #define MTL_DEBUG_TXFSTS BIT(4)
292 #define MTL_DEBUG_TWCSTS BIT(3)
294 /* MTL debug: Tx FIFO Read Controller Status */
295 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
296 #define MTL_DEBUG_TRCSTS_SHIFT 1
297 #define MTL_DEBUG_TRCSTS_IDLE 0
298 #define MTL_DEBUG_TRCSTS_READ 1
299 #define MTL_DEBUG_TRCSTS_TXW 2
300 #define MTL_DEBUG_TRCSTS_WRITE 3
301 #define MTL_DEBUG_TXPAUSED BIT(0)
303 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
304 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
305 #define MTL_DEBUG_RXFSTS_SHIFT 4
306 #define MTL_DEBUG_RXFSTS_EMPTY 0
307 #define MTL_DEBUG_RXFSTS_BT 1
308 #define MTL_DEBUG_RXFSTS_AT 2
309 #define MTL_DEBUG_RXFSTS_FULL 3
310 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
311 #define MTL_DEBUG_RRCSTS_SHIFT 1
312 #define MTL_DEBUG_RRCSTS_IDLE 0
313 #define MTL_DEBUG_RRCSTS_RDATA 1
314 #define MTL_DEBUG_RRCSTS_RSTAT 2
315 #define MTL_DEBUG_RRCSTS_FLUSH 3
316 #define MTL_DEBUG_RWCSTS BIT(0)
319 #define MTL_RX_OVERFLOW_INT_EN BIT(24)
320 #define MTL_RX_OVERFLOW_INT BIT(16)
322 /* Default operating mode of the MAC */
323 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | GMAC_CONFIG_ACS | \
324 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS)
326 /* To dump the core regs excluding the Address Registers */
327 #define GMAC_REG_NUM 132
330 #define MTL_DEBUG_TXSTSFSTS BIT(5)
331 #define MTL_DEBUG_TXFSTS BIT(4)
332 #define MTL_DEBUG_TWCSTS BIT(3)
334 /* MTL debug: Tx FIFO Read Controller Status */
335 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
336 #define MTL_DEBUG_TRCSTS_SHIFT 1
337 #define MTL_DEBUG_TRCSTS_IDLE 0
338 #define MTL_DEBUG_TRCSTS_READ 1
339 #define MTL_DEBUG_TRCSTS_TXW 2
340 #define MTL_DEBUG_TRCSTS_WRITE 3
341 #define MTL_DEBUG_TXPAUSED BIT(0)
343 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
344 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
345 #define MTL_DEBUG_RXFSTS_SHIFT 4
346 #define MTL_DEBUG_RXFSTS_EMPTY 0
347 #define MTL_DEBUG_RXFSTS_BT 1
348 #define MTL_DEBUG_RXFSTS_AT 2
349 #define MTL_DEBUG_RXFSTS_FULL 3
350 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
351 #define MTL_DEBUG_RRCSTS_SHIFT 1
352 #define MTL_DEBUG_RRCSTS_IDLE 0
353 #define MTL_DEBUG_RRCSTS_RDATA 1
354 #define MTL_DEBUG_RRCSTS_RSTAT 2
355 #define MTL_DEBUG_RRCSTS_FLUSH 3
356 #define MTL_DEBUG_RWCSTS BIT(0)
358 /* SGMII/RGMII status register */
359 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
360 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
361 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
362 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
363 #define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17)
364 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17
365 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19)
366 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20)
367 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21)
369 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1
371 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2
372 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1
373 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0
375 extern const struct stmmac_dma_ops dwmac4_dma_ops;
376 extern const struct stmmac_dma_ops dwmac410_dma_ops;
377 #endif /* __DWMAC4_H__ */