4 * Copyright (C) 2015 STMicroelectronics Ltd
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * Author: Alexandre Torgue <alexandre.torgue@st.com>
19 #define GMAC_CONFIG 0x00000000
20 #define GMAC_PACKET_FILTER 0x00000008
21 #define GMAC_HASH_TAB_0_31 0x00000010
22 #define GMAC_HASH_TAB_32_63 0x00000014
23 #define GMAC_RX_FLOW_CTRL 0x00000090
24 #define GMAC_QX_TX_FLOW_CTRL(x) (0x70 + x * 4)
25 #define GMAC_RXQ_CTRL0 0x000000a0
26 #define GMAC_INT_STATUS 0x000000b0
27 #define GMAC_INT_EN 0x000000b4
28 #define GMAC_1US_TIC_COUNTER 0x000000dc
29 #define GMAC_PCS_BASE 0x000000e0
30 #define GMAC_PHYIF_CONTROL_STATUS 0x000000f8
31 #define GMAC_PMT 0x000000c0
32 #define GMAC_VERSION 0x00000110
33 #define GMAC_DEBUG 0x00000114
34 #define GMAC_HW_FEATURE0 0x0000011c
35 #define GMAC_HW_FEATURE1 0x00000120
36 #define GMAC_HW_FEATURE2 0x00000124
37 #define GMAC_MDIO_ADDR 0x00000200
38 #define GMAC_MDIO_DATA 0x00000204
39 #define GMAC_ADDR_HIGH(reg) (0x300 + reg * 8)
40 #define GMAC_ADDR_LOW(reg) (0x304 + reg * 8)
42 /* MAC Packet Filtering */
43 #define GMAC_PACKET_FILTER_PR BIT(0)
44 #define GMAC_PACKET_FILTER_HMC BIT(2)
45 #define GMAC_PACKET_FILTER_PM BIT(4)
47 #define GMAC_MAX_PERFECT_ADDRESSES 128
49 /* MAC RX Queue Enable */
50 #define GMAC_RX_QUEUE_CLEAR(queue) ~(GENMASK(1, 0) << ((queue) * 2))
51 #define GMAC_RX_AV_QUEUE_ENABLE(queue) BIT((queue) * 2)
52 #define GMAC_RX_DCB_QUEUE_ENABLE(queue) BIT(((queue) * 2) + 1)
54 /* MAC Flow Control RX */
55 #define GMAC_RX_FLOW_CTRL_RFE BIT(0)
57 /* MAC Flow Control TX */
58 #define GMAC_TX_FLOW_CTRL_TFE BIT(1)
59 #define GMAC_TX_FLOW_CTRL_PT_SHIFT 16
61 /* MAC Interrupt bitmap*/
62 #define GMAC_INT_RGSMIIS BIT(0)
63 #define GMAC_INT_PCS_LINK BIT(1)
64 #define GMAC_INT_PCS_ANE BIT(2)
65 #define GMAC_INT_PCS_PHYIS BIT(3)
66 #define GMAC_INT_PMT_EN BIT(4)
67 #define GMAC_INT_LPI_EN BIT(5)
69 #define GMAC_PCS_IRQ_DEFAULT (GMAC_INT_RGSMIIS | GMAC_INT_PCS_LINK | \
72 #define GMAC_INT_DEFAULT_MASK GMAC_INT_PMT_EN
74 enum dwmac4_irq_status {
75 time_stamp_irq = 0x00001000,
76 mmc_rx_csum_offload_irq = 0x00000800,
77 mmc_tx_irq = 0x00000400,
78 mmc_rx_irq = 0x00000200,
85 pointer_reset = 0x80000000,
86 global_unicast = 0x00000200,
87 wake_up_rx_frame = 0x00000040,
88 magic_frame = 0x00000020,
89 wake_up_frame_en = 0x00000004,
90 magic_pkt_en = 0x00000002,
91 power_down = 0x00000001,
94 /* Energy Efficient Ethernet (EEE) for GMAC4
96 * LPI status, timer and control register offset
98 #define GMAC4_LPI_CTRL_STATUS 0xd0
99 #define GMAC4_LPI_TIMER_CTRL 0xd4
101 /* LPI control and status defines */
102 #define GMAC4_LPI_CTRL_STATUS_LPITCSE BIT(21) /* LPI Tx Clock Stop Enable */
103 #define GMAC4_LPI_CTRL_STATUS_LPITXA BIT(19) /* Enable LPI TX Automate */
104 #define GMAC4_LPI_CTRL_STATUS_PLS BIT(17) /* PHY Link Status */
105 #define GMAC4_LPI_CTRL_STATUS_LPIEN BIT(16) /* LPI Enable */
107 /* MAC Debug bitmap */
108 #define GMAC_DEBUG_TFCSTS_MASK GENMASK(18, 17)
109 #define GMAC_DEBUG_TFCSTS_SHIFT 17
110 #define GMAC_DEBUG_TFCSTS_IDLE 0
111 #define GMAC_DEBUG_TFCSTS_WAIT 1
112 #define GMAC_DEBUG_TFCSTS_GEN_PAUSE 2
113 #define GMAC_DEBUG_TFCSTS_XFER 3
114 #define GMAC_DEBUG_TPESTS BIT(16)
115 #define GMAC_DEBUG_RFCFCSTS_MASK GENMASK(2, 1)
116 #define GMAC_DEBUG_RFCFCSTS_SHIFT 1
117 #define GMAC_DEBUG_RPESTS BIT(0)
120 #define GMAC_CONFIG_IPC BIT(27)
121 #define GMAC_CONFIG_2K BIT(22)
122 #define GMAC_CONFIG_ACS BIT(20)
123 #define GMAC_CONFIG_BE BIT(18)
124 #define GMAC_CONFIG_JD BIT(17)
125 #define GMAC_CONFIG_JE BIT(16)
126 #define GMAC_CONFIG_PS BIT(15)
127 #define GMAC_CONFIG_FES BIT(14)
128 #define GMAC_CONFIG_DM BIT(13)
129 #define GMAC_CONFIG_DCRS BIT(9)
130 #define GMAC_CONFIG_TE BIT(1)
131 #define GMAC_CONFIG_RE BIT(0)
133 /* MAC HW features0 bitmap */
134 #define GMAC_HW_FEAT_ADDMAC BIT(18)
135 #define GMAC_HW_FEAT_RXCOESEL BIT(16)
136 #define GMAC_HW_FEAT_TXCOSEL BIT(14)
137 #define GMAC_HW_FEAT_EEESEL BIT(13)
138 #define GMAC_HW_FEAT_TSSEL BIT(12)
139 #define GMAC_HW_FEAT_MMCSEL BIT(8)
140 #define GMAC_HW_FEAT_MGKSEL BIT(7)
141 #define GMAC_HW_FEAT_RWKSEL BIT(6)
142 #define GMAC_HW_FEAT_SMASEL BIT(5)
143 #define GMAC_HW_FEAT_VLHASH BIT(4)
144 #define GMAC_HW_FEAT_PCSSEL BIT(3)
145 #define GMAC_HW_FEAT_HDSEL BIT(2)
146 #define GMAC_HW_FEAT_GMIISEL BIT(1)
147 #define GMAC_HW_FEAT_MIISEL BIT(0)
149 /* MAC HW features1 bitmap */
150 #define GMAC_HW_FEAT_AVSEL BIT(20)
151 #define GMAC_HW_TSOEN BIT(18)
152 #define GMAC_HW_TXFIFOSIZE GENMASK(10, 6)
153 #define GMAC_HW_RXFIFOSIZE GENMASK(4, 0)
155 /* MAC HW features2 bitmap */
156 #define GMAC_HW_FEAT_TXCHCNT GENMASK(21, 18)
157 #define GMAC_HW_FEAT_RXCHCNT GENMASK(15, 12)
158 #define GMAC_HW_FEAT_TXQCNT GENMASK(9, 6)
159 #define GMAC_HW_FEAT_RXQCNT GENMASK(3, 0)
161 /* MAC HW ADDR regs */
162 #define GMAC_HI_DCS GENMASK(18, 16)
163 #define GMAC_HI_DCS_SHIFT 16
164 #define GMAC_HI_REG_AE BIT(31)
167 #define MTL_OPERATION_MODE 0x00000c00
168 #define MTL_OPERATION_SCHALG_MASK GENMASK(6, 5)
169 #define MTL_OPERATION_SCHALG_WRR (0x0 << 5)
170 #define MTL_OPERATION_SCHALG_WFQ (0x1 << 5)
171 #define MTL_OPERATION_SCHALG_DWRR (0x2 << 5)
172 #define MTL_OPERATION_SCHALG_SP (0x3 << 5)
173 #define MTL_OPERATION_RAA BIT(2)
174 #define MTL_OPERATION_RAA_SP (0x0 << 2)
175 #define MTL_OPERATION_RAA_WSP (0x1 << 2)
177 #define MTL_INT_STATUS 0x00000c20
178 #define MTL_INT_QX(x) BIT(x)
180 #define MTL_RXQ_DMA_MAP0 0x00000c30 /* queue 0 to 3 */
181 #define MTL_RXQ_DMA_MAP1 0x00000c34 /* queue 4 to 7 */
182 #define MTL_RXQ_DMA_Q04MDMACH_MASK GENMASK(3, 0)
183 #define MTL_RXQ_DMA_Q04MDMACH(x) ((x) << 0)
184 #define MTL_RXQ_DMA_QXMDMACH_MASK(x) GENMASK(11 + (8 * ((x) - 1)), 8 * (x))
185 #define MTL_RXQ_DMA_QXMDMACH(chan, q) ((chan) << (8 * (q)))
187 #define MTL_CHAN_BASE_ADDR 0x00000d00
188 #define MTL_CHAN_BASE_OFFSET 0x40
189 #define MTL_CHANX_BASE_ADDR(x) (MTL_CHAN_BASE_ADDR + \
190 (x * MTL_CHAN_BASE_OFFSET))
192 #define MTL_CHAN_TX_OP_MODE(x) MTL_CHANX_BASE_ADDR(x)
193 #define MTL_CHAN_TX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x8)
194 #define MTL_CHAN_INT_CTRL(x) (MTL_CHANX_BASE_ADDR(x) + 0x2c)
195 #define MTL_CHAN_RX_OP_MODE(x) (MTL_CHANX_BASE_ADDR(x) + 0x30)
196 #define MTL_CHAN_RX_DEBUG(x) (MTL_CHANX_BASE_ADDR(x) + 0x38)
198 #define MTL_OP_MODE_RSF BIT(5)
199 #define MTL_OP_MODE_TXQEN BIT(3)
200 #define MTL_OP_MODE_TSF BIT(1)
202 #define MTL_OP_MODE_TQS_MASK GENMASK(24, 16)
203 #define MTL_OP_MODE_TQS_SHIFT 16
205 #define MTL_OP_MODE_TTC_MASK 0x70
206 #define MTL_OP_MODE_TTC_SHIFT 4
208 #define MTL_OP_MODE_TTC_32 0
209 #define MTL_OP_MODE_TTC_64 (1 << MTL_OP_MODE_TTC_SHIFT)
210 #define MTL_OP_MODE_TTC_96 (2 << MTL_OP_MODE_TTC_SHIFT)
211 #define MTL_OP_MODE_TTC_128 (3 << MTL_OP_MODE_TTC_SHIFT)
212 #define MTL_OP_MODE_TTC_192 (4 << MTL_OP_MODE_TTC_SHIFT)
213 #define MTL_OP_MODE_TTC_256 (5 << MTL_OP_MODE_TTC_SHIFT)
214 #define MTL_OP_MODE_TTC_384 (6 << MTL_OP_MODE_TTC_SHIFT)
215 #define MTL_OP_MODE_TTC_512 (7 << MTL_OP_MODE_TTC_SHIFT)
217 #define MTL_OP_MODE_RQS_MASK GENMASK(29, 20)
218 #define MTL_OP_MODE_RQS_SHIFT 20
220 #define MTL_OP_MODE_RFD_MASK GENMASK(19, 14)
221 #define MTL_OP_MODE_RFD_SHIFT 14
223 #define MTL_OP_MODE_RFA_MASK GENMASK(13, 8)
224 #define MTL_OP_MODE_RFA_SHIFT 8
226 #define MTL_OP_MODE_EHFC BIT(7)
228 #define MTL_OP_MODE_RTC_MASK 0x18
229 #define MTL_OP_MODE_RTC_SHIFT 3
231 #define MTL_OP_MODE_RTC_32 (1 << MTL_OP_MODE_RTC_SHIFT)
232 #define MTL_OP_MODE_RTC_64 0
233 #define MTL_OP_MODE_RTC_96 (2 << MTL_OP_MODE_RTC_SHIFT)
234 #define MTL_OP_MODE_RTC_128 (3 << MTL_OP_MODE_RTC_SHIFT)
236 /* MTL ETS Control register */
237 #define MTL_ETS_CTRL_BASE_ADDR 0x00000d10
238 #define MTL_ETS_CTRL_BASE_OFFSET 0x40
239 #define MTL_ETSX_CTRL_BASE_ADDR(x) (MTL_ETS_CTRL_BASE_ADDR + \
240 ((x) * MTL_ETS_CTRL_BASE_OFFSET))
242 #define MTL_ETS_CTRL_CC BIT(3)
243 #define MTL_ETS_CTRL_AVALG BIT(2)
245 /* MTL Queue Quantum Weight */
246 #define MTL_TXQ_WEIGHT_BASE_ADDR 0x00000d18
247 #define MTL_TXQ_WEIGHT_BASE_OFFSET 0x40
248 #define MTL_TXQX_WEIGHT_BASE_ADDR(x) (MTL_TXQ_WEIGHT_BASE_ADDR + \
249 ((x) * MTL_TXQ_WEIGHT_BASE_OFFSET))
250 #define MTL_TXQ_WEIGHT_ISCQW_MASK GENMASK(20, 0)
252 /* MTL sendSlopeCredit register */
253 #define MTL_SEND_SLP_CRED_BASE_ADDR 0x00000d1c
254 #define MTL_SEND_SLP_CRED_OFFSET 0x40
255 #define MTL_SEND_SLP_CREDX_BASE_ADDR(x) (MTL_SEND_SLP_CRED_BASE_ADDR + \
256 ((x) * MTL_SEND_SLP_CRED_OFFSET))
258 #define MTL_SEND_SLP_CRED_SSC_MASK GENMASK(13, 0)
260 /* MTL hiCredit register */
261 #define MTL_HIGH_CRED_BASE_ADDR 0x00000d20
262 #define MTL_HIGH_CRED_OFFSET 0x40
263 #define MTL_HIGH_CREDX_BASE_ADDR(x) (MTL_HIGH_CRED_BASE_ADDR + \
264 ((x) * MTL_HIGH_CRED_OFFSET))
266 #define MTL_HIGH_CRED_HC_MASK GENMASK(28, 0)
268 /* MTL loCredit register */
269 #define MTL_LOW_CRED_BASE_ADDR 0x00000d24
270 #define MTL_LOW_CRED_OFFSET 0x40
271 #define MTL_LOW_CREDX_BASE_ADDR(x) (MTL_LOW_CRED_BASE_ADDR + \
272 ((x) * MTL_LOW_CRED_OFFSET))
274 #define MTL_HIGH_CRED_LC_MASK GENMASK(28, 0)
277 #define MTL_DEBUG_TXSTSFSTS BIT(5)
278 #define MTL_DEBUG_TXFSTS BIT(4)
279 #define MTL_DEBUG_TWCSTS BIT(3)
281 /* MTL debug: Tx FIFO Read Controller Status */
282 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
283 #define MTL_DEBUG_TRCSTS_SHIFT 1
284 #define MTL_DEBUG_TRCSTS_IDLE 0
285 #define MTL_DEBUG_TRCSTS_READ 1
286 #define MTL_DEBUG_TRCSTS_TXW 2
287 #define MTL_DEBUG_TRCSTS_WRITE 3
288 #define MTL_DEBUG_TXPAUSED BIT(0)
290 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
291 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
292 #define MTL_DEBUG_RXFSTS_SHIFT 4
293 #define MTL_DEBUG_RXFSTS_EMPTY 0
294 #define MTL_DEBUG_RXFSTS_BT 1
295 #define MTL_DEBUG_RXFSTS_AT 2
296 #define MTL_DEBUG_RXFSTS_FULL 3
297 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
298 #define MTL_DEBUG_RRCSTS_SHIFT 1
299 #define MTL_DEBUG_RRCSTS_IDLE 0
300 #define MTL_DEBUG_RRCSTS_RDATA 1
301 #define MTL_DEBUG_RRCSTS_RSTAT 2
302 #define MTL_DEBUG_RRCSTS_FLUSH 3
303 #define MTL_DEBUG_RWCSTS BIT(0)
306 #define MTL_RX_OVERFLOW_INT_EN BIT(24)
307 #define MTL_RX_OVERFLOW_INT BIT(16)
309 /* Default operating mode of the MAC */
310 #define GMAC_CORE_INIT (GMAC_CONFIG_JD | GMAC_CONFIG_PS | GMAC_CONFIG_ACS | \
311 GMAC_CONFIG_BE | GMAC_CONFIG_DCRS)
313 /* To dump the core regs excluding the Address Registers */
314 #define GMAC_REG_NUM 132
317 #define MTL_DEBUG_TXSTSFSTS BIT(5)
318 #define MTL_DEBUG_TXFSTS BIT(4)
319 #define MTL_DEBUG_TWCSTS BIT(3)
321 /* MTL debug: Tx FIFO Read Controller Status */
322 #define MTL_DEBUG_TRCSTS_MASK GENMASK(2, 1)
323 #define MTL_DEBUG_TRCSTS_SHIFT 1
324 #define MTL_DEBUG_TRCSTS_IDLE 0
325 #define MTL_DEBUG_TRCSTS_READ 1
326 #define MTL_DEBUG_TRCSTS_TXW 2
327 #define MTL_DEBUG_TRCSTS_WRITE 3
328 #define MTL_DEBUG_TXPAUSED BIT(0)
330 /* MAC debug: GMII or MII Transmit Protocol Engine Status */
331 #define MTL_DEBUG_RXFSTS_MASK GENMASK(5, 4)
332 #define MTL_DEBUG_RXFSTS_SHIFT 4
333 #define MTL_DEBUG_RXFSTS_EMPTY 0
334 #define MTL_DEBUG_RXFSTS_BT 1
335 #define MTL_DEBUG_RXFSTS_AT 2
336 #define MTL_DEBUG_RXFSTS_FULL 3
337 #define MTL_DEBUG_RRCSTS_MASK GENMASK(2, 1)
338 #define MTL_DEBUG_RRCSTS_SHIFT 1
339 #define MTL_DEBUG_RRCSTS_IDLE 0
340 #define MTL_DEBUG_RRCSTS_RDATA 1
341 #define MTL_DEBUG_RRCSTS_RSTAT 2
342 #define MTL_DEBUG_RRCSTS_FLUSH 3
343 #define MTL_DEBUG_RWCSTS BIT(0)
345 /* SGMII/RGMII status register */
346 #define GMAC_PHYIF_CTRLSTATUS_TC BIT(0)
347 #define GMAC_PHYIF_CTRLSTATUS_LUD BIT(1)
348 #define GMAC_PHYIF_CTRLSTATUS_SMIDRXS BIT(4)
349 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD BIT(16)
350 #define GMAC_PHYIF_CTRLSTATUS_SPEED GENMASK(18, 17)
351 #define GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT 17
352 #define GMAC_PHYIF_CTRLSTATUS_LNKSTS BIT(19)
353 #define GMAC_PHYIF_CTRLSTATUS_JABTO BIT(20)
354 #define GMAC_PHYIF_CTRLSTATUS_FALSECARDET BIT(21)
356 #define GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK 0x1
358 #define GMAC_PHYIF_CTRLSTATUS_SPEED_125 0x2
359 #define GMAC_PHYIF_CTRLSTATUS_SPEED_25 0x1
360 #define GMAC_PHYIF_CTRLSTATUS_SPEED_2_5 0x0
362 extern const struct stmmac_dma_ops dwmac4_dma_ops;
363 extern const struct stmmac_dma_ops dwmac410_dma_ops;
364 #endif /* __DWMAC4_H__ */