1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2020, Intel Corporation
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
11 #include "stmmac_ptp.h"
13 struct intel_priv_data {
14 int mdio_adhoc_addr; /* mdio address for serdes & etc */
15 unsigned long crossts_adj;
19 /* This struct is used to associate PCI Function of MAC controller on a board,
20 * discovered via DMI, with the address of PHY connected to the MAC. The
21 * negative value of the address means that MAC controller is not connected
24 struct stmmac_pci_func_data {
29 struct stmmac_pci_dmi_data {
30 const struct stmmac_pci_func_data *func;
34 struct stmmac_pci_info {
35 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
38 static int stmmac_pci_find_phy_addr(struct pci_dev *pdev,
39 const struct dmi_system_id *dmi_list)
41 const struct stmmac_pci_func_data *func_data;
42 const struct stmmac_pci_dmi_data *dmi_data;
43 const struct dmi_system_id *dmi_id;
44 int func = PCI_FUNC(pdev->devfn);
47 dmi_id = dmi_first_match(dmi_list);
51 dmi_data = dmi_id->driver_data;
52 func_data = dmi_data->func;
54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++)
55 if (func_data->func == func)
56 return func_data->phy_addr;
61 static int serdes_status_poll(struct stmmac_priv *priv, int phyaddr,
62 int phyreg, u32 mask, u32 val)
64 unsigned int retries = 10;
68 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg);
69 if ((val_rd & mask) == (val & mask))
71 udelay(POLL_DELAY_US);
77 static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
79 struct intel_priv_data *intel_priv = priv_data;
80 struct stmmac_priv *priv = netdev_priv(ndev);
81 int serdes_phy_addr = 0;
84 if (!intel_priv->mdio_adhoc_addr)
87 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
89 /* Set the serdes rate and the PCLK rate */
90 data = mdiobus_read(priv->mii, serdes_phy_addr,
93 data &= ~SERDES_RATE_MASK;
94 data &= ~SERDES_PCLK_MASK;
96 if (priv->plat->max_speed == 2500)
97 data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |
98 SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;
100 data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT |
101 SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT;
103 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
106 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
107 data |= SERDES_PLL_CLK;
108 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
110 /* check for clk_ack assertion */
111 data = serdes_status_poll(priv, serdes_phy_addr,
117 dev_err(priv->device, "Serdes PLL clk request timeout\n");
121 /* assert lane reset */
122 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
124 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
126 /* check for assert lane reset reflection */
127 data = serdes_status_poll(priv, serdes_phy_addr,
133 dev_err(priv->device, "Serdes assert lane reset timeout\n");
137 /* move power state to P0 */
138 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
140 data &= ~SERDES_PWR_ST_MASK;
141 data |= SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT;
143 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
145 /* Check for P0 state */
146 data = serdes_status_poll(priv, serdes_phy_addr,
149 SERDES_PWR_ST_P0 << SERDES_PWR_ST_SHIFT);
152 dev_err(priv->device, "Serdes power state P0 timeout.\n");
156 /* PSE only - ungate SGMII PHY Rx Clock */
157 if (intel_priv->is_pse)
158 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
159 0, SERDES_PHY_RX_CLK);
164 static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
166 struct intel_priv_data *intel_priv = intel_data;
167 struct stmmac_priv *priv = netdev_priv(ndev);
168 int serdes_phy_addr = 0;
171 if (!intel_priv->mdio_adhoc_addr)
174 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
176 /* PSE only - gate SGMII PHY Rx Clock */
177 if (intel_priv->is_pse)
178 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0,
179 SERDES_PHY_RX_CLK, 0);
181 /* move power state to P3 */
182 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
184 data &= ~SERDES_PWR_ST_MASK;
185 data |= SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT;
187 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
189 /* Check for P3 state */
190 data = serdes_status_poll(priv, serdes_phy_addr,
193 SERDES_PWR_ST_P3 << SERDES_PWR_ST_SHIFT);
196 dev_err(priv->device, "Serdes power state P3 timeout\n");
200 /* de-assert clk_req */
201 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
202 data &= ~SERDES_PLL_CLK;
203 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
205 /* check for clk_ack de-assert */
206 data = serdes_status_poll(priv, serdes_phy_addr,
209 (u32)~SERDES_PLL_CLK);
212 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n");
216 /* de-assert lane reset */
217 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
219 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
221 /* check for de-assert lane reset reflection */
222 data = serdes_status_poll(priv, serdes_phy_addr,
228 dev_err(priv->device, "Serdes de-assert lane reset timeout\n");
233 static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)
235 struct intel_priv_data *intel_priv = intel_data;
236 struct stmmac_priv *priv = netdev_priv(ndev);
237 int serdes_phy_addr = 0;
240 serdes_phy_addr = intel_priv->mdio_adhoc_addr;
242 /* Determine the link speed mode: 2.5Gbps/1Gbps */
243 data = mdiobus_read(priv->mii, serdes_phy_addr,
246 if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) ==
247 SERDES_LINK_MODE_2G5) {
248 dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n");
249 priv->plat->max_speed = 2500;
250 priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;
251 priv->plat->mdio_bus_data->xpcs_an_inband = false;
253 priv->plat->max_speed = 1000;
254 priv->plat->mdio_bus_data->xpcs_an_inband = true;
258 /* Program PTP Clock Frequency for different variant of
259 * Intel mGBE that has slightly different GPO mapping
261 static void intel_mgbe_ptp_clk_freq_config(void *npriv)
263 struct stmmac_priv *priv = (struct stmmac_priv *)npriv;
264 struct intel_priv_data *intel_priv;
267 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv;
269 gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS);
271 if (intel_priv->is_pse) {
272 /* For PSE GbE, use 200MHz */
273 gpio_value &= ~PSE_PTP_CLK_FREQ_MASK;
274 gpio_value |= PSE_PTP_CLK_FREQ_200MHZ;
276 /* For PCH GbE, use 200MHz */
277 gpio_value &= ~PCH_PTP_CLK_FREQ_MASK;
278 gpio_value |= PCH_PTP_CLK_FREQ_200MHZ;
281 writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS);
284 static void get_arttime(struct mii_bus *mii, int intel_adhoc_addr,
289 ns = mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE3);
290 ns <<= GMAC4_ART_TIME_SHIFT;
291 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE2);
292 ns <<= GMAC4_ART_TIME_SHIFT;
293 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE1);
294 ns <<= GMAC4_ART_TIME_SHIFT;
295 ns |= mdiobus_read(mii, intel_adhoc_addr, PMC_ART_VALUE0);
300 static int stmmac_cross_ts_isr(struct stmmac_priv *priv)
302 return (readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE);
305 static int intel_crosststamp(ktime_t *device,
306 struct system_counterval_t *system,
309 struct intel_priv_data *intel_priv;
311 struct stmmac_priv *priv = (struct stmmac_priv *)ctx;
312 void __iomem *ptpaddr = priv->ptpaddr;
313 void __iomem *ioaddr = priv->hw->pcsr;
322 if (!boot_cpu_has(X86_FEATURE_ART))
325 intel_priv = priv->plat->bsp_priv;
327 /* Both internal crosstimestamping and external triggered event
328 * timestamping cannot be run concurrently.
330 if (priv->plat->ext_snapshot_en)
333 priv->plat->int_snapshot_en = 1;
335 mutex_lock(&priv->aux_ts_lock);
336 /* Enable Internal snapshot trigger */
337 acr_value = readl(ptpaddr + PTP_ACR);
338 acr_value &= ~PTP_ACR_MASK;
339 switch (priv->plat->int_snapshot_num) {
341 acr_value |= PTP_ACR_ATSEN0;
344 acr_value |= PTP_ACR_ATSEN1;
347 acr_value |= PTP_ACR_ATSEN2;
350 acr_value |= PTP_ACR_ATSEN3;
353 mutex_unlock(&priv->aux_ts_lock);
354 priv->plat->int_snapshot_en = 0;
357 writel(acr_value, ptpaddr + PTP_ACR);
360 acr_value = readl(ptpaddr + PTP_ACR);
361 acr_value |= PTP_ACR_ATSFC;
362 writel(acr_value, ptpaddr + PTP_ACR);
363 /* Release the mutex */
364 mutex_unlock(&priv->aux_ts_lock);
366 /* Trigger Internal snapshot signal
367 * Create a rising edge by just toggle the GPO1 to low
370 gpio_value = readl(ioaddr + GMAC_GPIO_STATUS);
371 gpio_value &= ~GMAC_GPO1;
372 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
373 gpio_value |= GMAC_GPO1;
374 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS);
376 /* Time sync done Indication - Interrupt method */
377 if (!wait_event_interruptible_timeout(priv->tstamp_busy_wait,
378 stmmac_cross_ts_isr(priv),
380 priv->plat->int_snapshot_en = 0;
384 num_snapshot = (readl(ioaddr + GMAC_TIMESTAMP_STATUS) &
385 GMAC_TIMESTAMP_ATSNS_MASK) >>
386 GMAC_TIMESTAMP_ATSNS_SHIFT;
388 /* Repeat until the timestamps are from the FIFO last segment */
389 for (i = 0; i < num_snapshot; i++) {
390 read_lock_irqsave(&priv->ptp_lock, flags);
391 stmmac_get_ptptime(priv, ptpaddr, &ptp_time);
392 *device = ns_to_ktime(ptp_time);
393 read_unlock_irqrestore(&priv->ptp_lock, flags);
394 get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time);
395 *system = convert_art_to_tsc(art_time);
398 system->cycles *= intel_priv->crossts_adj;
399 priv->plat->int_snapshot_en = 0;
404 static void intel_mgbe_pse_crossts_adj(struct intel_priv_data *intel_priv,
407 if (boot_cpu_has(X86_FEATURE_ART)) {
408 unsigned int art_freq;
410 /* On systems that support ART, ART frequency can be obtained
411 * from ECX register of CPUID leaf (0x15).
413 art_freq = cpuid_ecx(ART_CPUID_LEAF);
414 do_div(art_freq, base);
415 intel_priv->crossts_adj = art_freq;
419 static void common_default_data(struct plat_stmmacenet_data *plat)
421 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
423 plat->force_sf_dma_mode = 1;
425 plat->mdio_bus_data->needs_reset = true;
427 /* Set default value for multicast hash bins */
428 plat->multicast_filter_bins = HASH_TABLE_SIZE;
430 /* Set default value for unicast filter entries */
431 plat->unicast_filter_entries = 1;
433 /* Set the maxmtu to a default of JUMBO_LEN */
434 plat->maxmtu = JUMBO_LEN;
436 /* Set default number of RX and TX queues to use */
437 plat->tx_queues_to_use = 1;
438 plat->rx_queues_to_use = 1;
440 /* Disable Priority config by default */
441 plat->tx_queues_cfg[0].use_prio = false;
442 plat->rx_queues_cfg[0].use_prio = false;
444 /* Disable RX queues routing by default */
445 plat->rx_queues_cfg[0].pkt_route = 0x0;
448 static int intel_mgbe_common_data(struct pci_dev *pdev,
449 struct plat_stmmacenet_data *plat)
451 struct fwnode_handle *fwnode;
461 plat->force_sf_dma_mode = 0;
463 plat->sph_disable = 1;
465 /* Multiplying factor to the clk_eee_i clock time
466 * period to make it closer to 100 ns. This value
467 * should be programmed such that the clk_eee_time_period *
468 * (MULT_FACT_100NS + 1) should be within 80 ns to 120 ns
469 * clk_eee frequency is 19.2Mhz
470 * clk_eee_time_period is 52ns
471 * 52ns * (1 + 1) = 104ns
472 * MULT_FACT_100NS = 1
474 plat->mult_fact_100ns = 1;
476 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
478 for (i = 0; i < plat->rx_queues_to_use; i++) {
479 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
480 plat->rx_queues_cfg[i].chan = i;
482 /* Disable Priority config by default */
483 plat->rx_queues_cfg[i].use_prio = false;
485 /* Disable RX queues routing by default */
486 plat->rx_queues_cfg[i].pkt_route = 0x0;
489 for (i = 0; i < plat->tx_queues_to_use; i++) {
490 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
492 /* Disable Priority config by default */
493 plat->tx_queues_cfg[i].use_prio = false;
494 /* Default TX Q0 to use TSO and rest TXQ for TBS */
496 plat->tx_queues_cfg[i].tbs_en = 1;
499 /* FIFO size is 4096 bytes for 1 tx/rx queue */
500 plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
501 plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
503 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
504 plat->tx_queues_cfg[0].weight = 0x09;
505 plat->tx_queues_cfg[1].weight = 0x0A;
506 plat->tx_queues_cfg[2].weight = 0x0B;
507 plat->tx_queues_cfg[3].weight = 0x0C;
508 plat->tx_queues_cfg[4].weight = 0x0D;
509 plat->tx_queues_cfg[5].weight = 0x0E;
510 plat->tx_queues_cfg[6].weight = 0x0F;
511 plat->tx_queues_cfg[7].weight = 0x10;
513 plat->dma_cfg->pbl = 32;
514 plat->dma_cfg->pblx8 = true;
515 plat->dma_cfg->fixed_burst = 0;
516 plat->dma_cfg->mixed_burst = 0;
517 plat->dma_cfg->aal = 0;
518 plat->dma_cfg->dche = true;
520 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
525 plat->axi->axi_lpi_en = 0;
526 plat->axi->axi_xit_frm = 0;
527 plat->axi->axi_wr_osr_lmt = 1;
528 plat->axi->axi_rd_osr_lmt = 1;
529 plat->axi->axi_blen[0] = 4;
530 plat->axi->axi_blen[1] = 8;
531 plat->axi->axi_blen[2] = 16;
533 plat->ptp_max_adj = plat->clk_ptp_rate;
534 plat->eee_usecs_rate = plat->clk_ptp_rate;
536 /* Set system clock */
537 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev));
539 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
543 if (IS_ERR(plat->stmmac_clk)) {
544 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n");
545 plat->stmmac_clk = NULL;
548 ret = clk_prepare_enable(plat->stmmac_clk);
550 clk_unregister_fixed_rate(plat->stmmac_clk);
554 plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config;
556 /* Set default value for multicast hash bins */
557 plat->multicast_filter_bins = HASH_TABLE_SIZE;
559 /* Set default value for unicast filter entries */
560 plat->unicast_filter_entries = 1;
562 /* Set the maxmtu to a default of JUMBO_LEN */
563 plat->maxmtu = JUMBO_LEN;
565 plat->vlan_fail_q_en = true;
567 /* Use the last Rx queue */
568 plat->vlan_fail_q = plat->rx_queues_to_use - 1;
570 /* For fixed-link setup, we allow phy-mode setting */
571 fwnode = dev_fwnode(&pdev->dev);
575 /* "phy-mode" setting is optional. If it is set,
576 * we allow either sgmii or 1000base-x for now.
578 phy_mode = fwnode_get_phy_mode(fwnode);
580 if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
581 phy_mode == PHY_INTERFACE_MODE_1000BASEX)
582 plat->phy_interface = phy_mode;
584 dev_warn(&pdev->dev, "Invalid phy-mode\n");
588 /* Intel mgbe SGMII interface uses pcs-xcps */
589 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
590 plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
591 plat->mdio_bus_data->has_xpcs = true;
592 plat->mdio_bus_data->xpcs_an_inband = true;
595 /* For fixed-link setup, we clear xpcs_an_inband */
597 struct fwnode_handle *fixed_node;
599 fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
601 plat->mdio_bus_data->xpcs_an_inband = false;
603 fwnode_handle_put(fixed_node);
606 /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */
607 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR;
608 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR;
610 plat->int_snapshot_num = AUX_SNAPSHOT1;
611 plat->ext_snapshot_num = AUX_SNAPSHOT0;
613 plat->crosststamp = intel_crosststamp;
614 plat->int_snapshot_en = 0;
616 /* Setup MSI vector offset specific to Intel mGbE controller */
617 plat->msi_mac_vec = 29;
618 plat->msi_lpi_vec = 28;
619 plat->msi_sfty_ce_vec = 27;
620 plat->msi_sfty_ue_vec = 26;
621 plat->msi_rx_base_vec = 0;
622 plat->msi_tx_base_vec = 1;
627 static int ehl_common_data(struct pci_dev *pdev,
628 struct plat_stmmacenet_data *plat)
630 plat->rx_queues_to_use = 8;
631 plat->tx_queues_to_use = 8;
632 plat->clk_ptp_rate = 200000000;
633 plat->use_phy_wol = 1;
635 plat->safety_feat_cfg->tsoee = 1;
636 plat->safety_feat_cfg->mrxpee = 1;
637 plat->safety_feat_cfg->mestee = 1;
638 plat->safety_feat_cfg->mrxee = 1;
639 plat->safety_feat_cfg->mtxee = 1;
640 plat->safety_feat_cfg->epsi = 0;
641 plat->safety_feat_cfg->edpp = 0;
642 plat->safety_feat_cfg->prtyen = 0;
643 plat->safety_feat_cfg->tmouten = 0;
645 return intel_mgbe_common_data(pdev, plat);
648 static int ehl_sgmii_data(struct pci_dev *pdev,
649 struct plat_stmmacenet_data *plat)
652 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
653 plat->speed_mode_2500 = intel_speed_mode_2500;
654 plat->serdes_powerup = intel_serdes_powerup;
655 plat->serdes_powerdown = intel_serdes_powerdown;
657 return ehl_common_data(pdev, plat);
660 static struct stmmac_pci_info ehl_sgmii1g_info = {
661 .setup = ehl_sgmii_data,
664 static int ehl_rgmii_data(struct pci_dev *pdev,
665 struct plat_stmmacenet_data *plat)
668 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
670 return ehl_common_data(pdev, plat);
673 static struct stmmac_pci_info ehl_rgmii1g_info = {
674 .setup = ehl_rgmii_data,
677 static int ehl_pse0_common_data(struct pci_dev *pdev,
678 struct plat_stmmacenet_data *plat)
680 struct intel_priv_data *intel_priv = plat->bsp_priv;
682 intel_priv->is_pse = true;
686 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
688 return ehl_common_data(pdev, plat);
691 static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
692 struct plat_stmmacenet_data *plat)
694 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
695 return ehl_pse0_common_data(pdev, plat);
698 static struct stmmac_pci_info ehl_pse0_rgmii1g_info = {
699 .setup = ehl_pse0_rgmii1g_data,
702 static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
703 struct plat_stmmacenet_data *plat)
705 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
706 plat->speed_mode_2500 = intel_speed_mode_2500;
707 plat->serdes_powerup = intel_serdes_powerup;
708 plat->serdes_powerdown = intel_serdes_powerdown;
709 return ehl_pse0_common_data(pdev, plat);
712 static struct stmmac_pci_info ehl_pse0_sgmii1g_info = {
713 .setup = ehl_pse0_sgmii1g_data,
716 static int ehl_pse1_common_data(struct pci_dev *pdev,
717 struct plat_stmmacenet_data *plat)
719 struct intel_priv_data *intel_priv = plat->bsp_priv;
721 intel_priv->is_pse = true;
725 intel_mgbe_pse_crossts_adj(intel_priv, EHL_PSE_ART_MHZ);
727 return ehl_common_data(pdev, plat);
730 static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
731 struct plat_stmmacenet_data *plat)
733 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
734 return ehl_pse1_common_data(pdev, plat);
737 static struct stmmac_pci_info ehl_pse1_rgmii1g_info = {
738 .setup = ehl_pse1_rgmii1g_data,
741 static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
742 struct plat_stmmacenet_data *plat)
744 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
745 plat->speed_mode_2500 = intel_speed_mode_2500;
746 plat->serdes_powerup = intel_serdes_powerup;
747 plat->serdes_powerdown = intel_serdes_powerdown;
748 return ehl_pse1_common_data(pdev, plat);
751 static struct stmmac_pci_info ehl_pse1_sgmii1g_info = {
752 .setup = ehl_pse1_sgmii1g_data,
755 static int tgl_common_data(struct pci_dev *pdev,
756 struct plat_stmmacenet_data *plat)
758 plat->rx_queues_to_use = 6;
759 plat->tx_queues_to_use = 4;
760 plat->clk_ptp_rate = 200000000;
761 plat->speed_mode_2500 = intel_speed_mode_2500;
763 plat->safety_feat_cfg->tsoee = 1;
764 plat->safety_feat_cfg->mrxpee = 0;
765 plat->safety_feat_cfg->mestee = 1;
766 plat->safety_feat_cfg->mrxee = 1;
767 plat->safety_feat_cfg->mtxee = 1;
768 plat->safety_feat_cfg->epsi = 0;
769 plat->safety_feat_cfg->edpp = 0;
770 plat->safety_feat_cfg->prtyen = 0;
771 plat->safety_feat_cfg->tmouten = 0;
773 return intel_mgbe_common_data(pdev, plat);
776 static int tgl_sgmii_phy0_data(struct pci_dev *pdev,
777 struct plat_stmmacenet_data *plat)
780 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
781 plat->serdes_powerup = intel_serdes_powerup;
782 plat->serdes_powerdown = intel_serdes_powerdown;
783 return tgl_common_data(pdev, plat);
786 static struct stmmac_pci_info tgl_sgmii1g_phy0_info = {
787 .setup = tgl_sgmii_phy0_data,
790 static int tgl_sgmii_phy1_data(struct pci_dev *pdev,
791 struct plat_stmmacenet_data *plat)
794 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
795 plat->serdes_powerup = intel_serdes_powerup;
796 plat->serdes_powerdown = intel_serdes_powerdown;
797 return tgl_common_data(pdev, plat);
800 static struct stmmac_pci_info tgl_sgmii1g_phy1_info = {
801 .setup = tgl_sgmii_phy1_data,
804 static int adls_sgmii_phy0_data(struct pci_dev *pdev,
805 struct plat_stmmacenet_data *plat)
808 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
810 /* SerDes power up and power down are done in BIOS for ADL */
812 return tgl_common_data(pdev, plat);
815 static struct stmmac_pci_info adls_sgmii1g_phy0_info = {
816 .setup = adls_sgmii_phy0_data,
819 static int adls_sgmii_phy1_data(struct pci_dev *pdev,
820 struct plat_stmmacenet_data *plat)
823 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
825 /* SerDes power up and power down are done in BIOS for ADL */
827 return tgl_common_data(pdev, plat);
830 static struct stmmac_pci_info adls_sgmii1g_phy1_info = {
831 .setup = adls_sgmii_phy1_data,
833 static const struct stmmac_pci_func_data galileo_stmmac_func_data[] = {
840 static const struct stmmac_pci_dmi_data galileo_stmmac_dmi_data = {
841 .func = galileo_stmmac_func_data,
842 .nfuncs = ARRAY_SIZE(galileo_stmmac_func_data),
845 static const struct stmmac_pci_func_data iot2040_stmmac_func_data[] = {
856 static const struct stmmac_pci_dmi_data iot2040_stmmac_dmi_data = {
857 .func = iot2040_stmmac_func_data,
858 .nfuncs = ARRAY_SIZE(iot2040_stmmac_func_data),
861 static const struct dmi_system_id quark_pci_dmi[] = {
864 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Galileo"),
866 .driver_data = (void *)&galileo_stmmac_dmi_data,
870 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"),
872 .driver_data = (void *)&galileo_stmmac_dmi_data,
874 /* There are 2 types of SIMATIC IOT2000: IOT2020 and IOT2040.
875 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
876 * has only one pci network device while other asset tags are
877 * for IOT2040 which has two.
881 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
882 DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
883 "6ES7647-0AA00-0YA2"),
885 .driver_data = (void *)&galileo_stmmac_dmi_data,
889 DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
891 .driver_data = (void *)&iot2040_stmmac_dmi_data,
896 static int quark_default_data(struct pci_dev *pdev,
897 struct plat_stmmacenet_data *plat)
901 /* Set common default data first */
902 common_default_data(plat);
904 /* Refuse to load the driver and register net device if MAC controller
905 * does not connect to any PHY interface.
907 ret = stmmac_pci_find_phy_addr(pdev, quark_pci_dmi);
909 /* Return error to the caller on DMI enabled boards. */
910 if (dmi_get_system_info(DMI_BOARD_NAME))
913 /* Galileo boards with old firmware don't support DMI. We always
914 * use 1 here as PHY address, so at least the first found MAC
915 * controller would be probed.
920 plat->bus_id = pci_dev_id(pdev);
921 plat->phy_addr = ret;
922 plat->phy_interface = PHY_INTERFACE_MODE_RMII;
924 plat->dma_cfg->pbl = 16;
925 plat->dma_cfg->pblx8 = true;
926 plat->dma_cfg->fixed_burst = 1;
932 static const struct stmmac_pci_info quark_info = {
933 .setup = quark_default_data,
936 static int stmmac_config_single_msi(struct pci_dev *pdev,
937 struct plat_stmmacenet_data *plat,
938 struct stmmac_resources *res)
942 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
944 dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n",
949 res->irq = pci_irq_vector(pdev, 0);
950 res->wol_irq = res->irq;
951 plat->multi_msi_en = 0;
952 dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n",
958 static int stmmac_config_multi_msi(struct pci_dev *pdev,
959 struct plat_stmmacenet_data *plat,
960 struct stmmac_resources *res)
965 if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX ||
966 plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) {
967 dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n",
972 ret = pci_alloc_irq_vectors(pdev, 2, STMMAC_MSI_VEC_MAX,
973 PCI_IRQ_MSI | PCI_IRQ_MSIX);
975 dev_info(&pdev->dev, "%s: multi MSI enablement failed\n",
981 for (i = 0; i < plat->rx_queues_to_use; i++) {
982 res->rx_irq[i] = pci_irq_vector(pdev,
983 plat->msi_rx_base_vec + i * 2);
987 for (i = 0; i < plat->tx_queues_to_use; i++) {
988 res->tx_irq[i] = pci_irq_vector(pdev,
989 plat->msi_tx_base_vec + i * 2);
992 if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX)
993 res->irq = pci_irq_vector(pdev, plat->msi_mac_vec);
994 if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX)
995 res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec);
996 if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX)
997 res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec);
998 if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX)
999 res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec);
1000 if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX)
1001 res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec);
1003 plat->multi_msi_en = 1;
1004 dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__);
1010 * intel_eth_pci_probe
1012 * @pdev: pci device pointer
1013 * @id: pointer to table of device id/id's.
1015 * Description: This probing function gets called for all PCI devices which
1016 * match the ID table and are not "owned" by other driver yet. This function
1017 * gets passed a "struct pci_dev *" for each device whose entry in the ID table
1018 * matches the device. The probe functions returns zero when the driver choose
1019 * to take "ownership" of the device or an error code(-ve no) otherwise.
1021 static int intel_eth_pci_probe(struct pci_dev *pdev,
1022 const struct pci_device_id *id)
1024 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data;
1025 struct intel_priv_data *intel_priv;
1026 struct plat_stmmacenet_data *plat;
1027 struct stmmac_resources res;
1030 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL);
1034 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
1038 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
1039 sizeof(*plat->mdio_bus_data),
1041 if (!plat->mdio_bus_data)
1044 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
1049 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev,
1050 sizeof(*plat->safety_feat_cfg),
1052 if (!plat->safety_feat_cfg)
1055 /* Enable pci device */
1056 ret = pcim_enable_device(pdev);
1058 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n",
1063 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
1067 pci_set_master(pdev);
1069 plat->bsp_priv = intel_priv;
1070 intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR;
1071 intel_priv->crossts_adj = 1;
1073 /* Initialize all MSI vectors to invalid so that it can be set
1074 * according to platform data settings below.
1075 * Note: MSI vector takes value from 0 upto 31 (STMMAC_MSI_VEC_MAX)
1077 plat->msi_mac_vec = STMMAC_MSI_VEC_MAX;
1078 plat->msi_wol_vec = STMMAC_MSI_VEC_MAX;
1079 plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX;
1080 plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX;
1081 plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX;
1082 plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX;
1083 plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX;
1085 ret = info->setup(pdev, plat);
1089 memset(&res, 0, sizeof(res));
1090 res.addr = pcim_iomap_table(pdev)[0];
1092 if (plat->eee_usecs_rate > 0) {
1095 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1;
1096 writel(tx_lpi_usec, res.addr + GMAC_1US_TIC_COUNTER);
1099 ret = stmmac_config_multi_msi(pdev, plat, &res);
1101 ret = stmmac_config_single_msi(pdev, plat, &res);
1103 dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n",
1109 ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
1117 clk_disable_unprepare(plat->stmmac_clk);
1118 clk_unregister_fixed_rate(plat->stmmac_clk);
1123 * intel_eth_pci_remove
1125 * @pdev: pci device pointer
1126 * Description: this function calls the main to free the net resources
1127 * and releases the PCI resources.
1129 static void intel_eth_pci_remove(struct pci_dev *pdev)
1131 struct net_device *ndev = dev_get_drvdata(&pdev->dev);
1132 struct stmmac_priv *priv = netdev_priv(ndev);
1134 stmmac_dvr_remove(&pdev->dev);
1136 clk_disable_unprepare(priv->plat->stmmac_clk);
1137 clk_unregister_fixed_rate(priv->plat->stmmac_clk);
1139 pcim_iounmap_regions(pdev, BIT(0));
1142 static int __maybe_unused intel_eth_pci_suspend(struct device *dev)
1144 struct pci_dev *pdev = to_pci_dev(dev);
1147 ret = stmmac_suspend(dev);
1151 ret = pci_save_state(pdev);
1155 pci_wake_from_d3(pdev, true);
1156 pci_set_power_state(pdev, PCI_D3hot);
1160 static int __maybe_unused intel_eth_pci_resume(struct device *dev)
1162 struct pci_dev *pdev = to_pci_dev(dev);
1165 pci_restore_state(pdev);
1166 pci_set_power_state(pdev, PCI_D0);
1168 ret = pcim_enable_device(pdev);
1172 pci_set_master(pdev);
1174 return stmmac_resume(dev);
1177 static SIMPLE_DEV_PM_OPS(intel_eth_pm_ops, intel_eth_pci_suspend,
1178 intel_eth_pci_resume);
1180 #define PCI_DEVICE_ID_INTEL_QUARK 0x0937
1181 #define PCI_DEVICE_ID_INTEL_EHL_RGMII1G 0x4b30
1182 #define PCI_DEVICE_ID_INTEL_EHL_SGMII1G 0x4b31
1183 #define PCI_DEVICE_ID_INTEL_EHL_SGMII2G5 0x4b32
1184 /* Intel(R) Programmable Services Engine (Intel(R) PSE) consist of 2 MAC
1185 * which are named PSE0 and PSE1
1187 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G 0x4ba0
1188 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G 0x4ba1
1189 #define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII2G5 0x4ba2
1190 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G 0x4bb0
1191 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G 0x4bb1
1192 #define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII2G5 0x4bb2
1193 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_0 0x43ac
1194 #define PCI_DEVICE_ID_INTEL_TGLH_SGMII1G_1 0x43a2
1195 #define PCI_DEVICE_ID_INTEL_TGL_SGMII1G 0xa0ac
1196 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_0 0x7aac
1197 #define PCI_DEVICE_ID_INTEL_ADLS_SGMII1G_1 0x7aad
1198 #define PCI_DEVICE_ID_INTEL_ADLN_SGMII1G 0x54ac
1199 #define PCI_DEVICE_ID_INTEL_RPLP_SGMII1G 0x51ac
1201 static const struct pci_device_id intel_eth_pci_id_table[] = {
1202 { PCI_DEVICE_DATA(INTEL, QUARK, &quark_info) },
1203 { PCI_DEVICE_DATA(INTEL, EHL_RGMII1G, &ehl_rgmii1g_info) },
1204 { PCI_DEVICE_DATA(INTEL, EHL_SGMII1G, &ehl_sgmii1g_info) },
1205 { PCI_DEVICE_DATA(INTEL, EHL_SGMII2G5, &ehl_sgmii1g_info) },
1206 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G, &ehl_pse0_rgmii1g_info) },
1207 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G, &ehl_pse0_sgmii1g_info) },
1208 { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII2G5, &ehl_pse0_sgmii1g_info) },
1209 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G, &ehl_pse1_rgmii1g_info) },
1210 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G, &ehl_pse1_sgmii1g_info) },
1211 { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII2G5, &ehl_pse1_sgmii1g_info) },
1212 { PCI_DEVICE_DATA(INTEL, TGL_SGMII1G, &tgl_sgmii1g_phy0_info) },
1213 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_0, &tgl_sgmii1g_phy0_info) },
1214 { PCI_DEVICE_DATA(INTEL, TGLH_SGMII1G_1, &tgl_sgmii1g_phy1_info) },
1215 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_0, &adls_sgmii1g_phy0_info) },
1216 { PCI_DEVICE_DATA(INTEL, ADLS_SGMII1G_1, &adls_sgmii1g_phy1_info) },
1217 { PCI_DEVICE_DATA(INTEL, ADLN_SGMII1G, &tgl_sgmii1g_phy0_info) },
1218 { PCI_DEVICE_DATA(INTEL, RPLP_SGMII1G, &tgl_sgmii1g_phy0_info) },
1221 MODULE_DEVICE_TABLE(pci, intel_eth_pci_id_table);
1223 static struct pci_driver intel_eth_pci_driver = {
1224 .name = "intel-eth-pci",
1225 .id_table = intel_eth_pci_id_table,
1226 .probe = intel_eth_pci_probe,
1227 .remove = intel_eth_pci_remove,
1229 .pm = &intel_eth_pm_ops,
1233 module_pci_driver(intel_eth_pci_driver);
1235 MODULE_DESCRIPTION("INTEL 10/100/1000 Ethernet PCI driver");
1236 MODULE_AUTHOR("Voon Weifeng <weifeng.voon@intel.com>");
1237 MODULE_LICENSE("GPL v2");