1 /*******************************************************************************
2 STMMAC Common Header File
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 The full GNU General Public License is included in this distribution in
16 the file called "COPYING".
18 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
19 *******************************************************************************/
24 #include <linux/etherdevice.h>
25 #include <linux/netdevice.h>
26 #include <linux/stmmac.h>
27 #include <linux/phy.h>
28 #include <linux/module.h>
29 #if IS_ENABLED(CONFIG_VLAN_8021Q)
30 #define STMMAC_VLAN_TAG_USED
31 #include <linux/if_vlan.h>
37 /* Synopsys Core versions */
38 #define DWMAC_CORE_3_40 0x34
39 #define DWMAC_CORE_3_50 0x35
40 #define DWMAC_CORE_4_00 0x40
41 #define STMMAC_CHAN0 0 /* Always supported and default for all chips */
43 /* These need to be power of two, and >= 4 */
44 #define DMA_TX_SIZE 512
45 #define DMA_RX_SIZE 512
46 #define STMMAC_GET_ENTRY(x, size) ((x + 1) & (size - 1))
48 #undef FRAME_FILTER_DEBUG
49 /* #define FRAME_FILTER_DEBUG */
51 /* Extra statistic and debug information exposed by ethtool */
52 struct stmmac_extra_stats {
54 unsigned long tx_underflow ____cacheline_aligned;
55 unsigned long tx_carrier;
56 unsigned long tx_losscarrier;
57 unsigned long vlan_tag;
58 unsigned long tx_deferred;
59 unsigned long tx_vlan;
60 unsigned long tx_jabber;
61 unsigned long tx_frame_flushed;
62 unsigned long tx_payload_error;
63 unsigned long tx_ip_header_error;
65 unsigned long rx_desc;
66 unsigned long sa_filter_fail;
67 unsigned long overflow_error;
68 unsigned long ipc_csum_error;
69 unsigned long rx_collision;
70 unsigned long rx_crc_errors;
71 unsigned long dribbling_bit;
72 unsigned long rx_length;
74 unsigned long rx_multicast;
75 unsigned long rx_gmac_overflow;
76 unsigned long rx_watchdog;
77 unsigned long da_rx_filter_fail;
78 unsigned long sa_rx_filter_fail;
79 unsigned long rx_missed_cntr;
80 unsigned long rx_overflow_cntr;
81 unsigned long rx_vlan;
82 /* Tx/Rx IRQ error info */
83 unsigned long tx_undeflow_irq;
84 unsigned long tx_process_stopped_irq;
85 unsigned long tx_jabber_irq;
86 unsigned long rx_overflow_irq;
87 unsigned long rx_buf_unav_irq;
88 unsigned long rx_process_stopped_irq;
89 unsigned long rx_watchdog_irq;
90 unsigned long tx_early_irq;
91 unsigned long fatal_bus_error_irq;
92 /* Tx/Rx IRQ Events */
93 unsigned long rx_early_irq;
94 unsigned long threshold;
95 unsigned long tx_pkt_n;
96 unsigned long rx_pkt_n;
97 unsigned long normal_irq_n;
98 unsigned long rx_normal_irq_n;
99 unsigned long napi_poll;
100 unsigned long tx_normal_irq_n;
101 unsigned long tx_clean;
102 unsigned long tx_set_ic_bit;
103 unsigned long irq_receive_pmt_irq_n;
105 unsigned long mmc_tx_irq_n;
106 unsigned long mmc_rx_irq_n;
107 unsigned long mmc_rx_csum_offload_irq_n;
109 unsigned long irq_tx_path_in_lpi_mode_n;
110 unsigned long irq_tx_path_exit_lpi_mode_n;
111 unsigned long irq_rx_path_in_lpi_mode_n;
112 unsigned long irq_rx_path_exit_lpi_mode_n;
113 unsigned long phy_eee_wakeup_error_n;
114 /* Extended RDES status */
115 unsigned long ip_hdr_err;
116 unsigned long ip_payload_err;
117 unsigned long ip_csum_bypassed;
118 unsigned long ipv4_pkt_rcvd;
119 unsigned long ipv6_pkt_rcvd;
120 unsigned long no_ptp_rx_msg_type_ext;
121 unsigned long ptp_rx_msg_type_sync;
122 unsigned long ptp_rx_msg_type_follow_up;
123 unsigned long ptp_rx_msg_type_delay_req;
124 unsigned long ptp_rx_msg_type_delay_resp;
125 unsigned long ptp_rx_msg_type_pdelay_req;
126 unsigned long ptp_rx_msg_type_pdelay_resp;
127 unsigned long ptp_rx_msg_type_pdelay_follow_up;
128 unsigned long ptp_rx_msg_type_announce;
129 unsigned long ptp_rx_msg_type_management;
130 unsigned long ptp_rx_msg_pkt_reserved_type;
131 unsigned long ptp_frame_type;
132 unsigned long ptp_ver;
133 unsigned long timestamp_dropped;
134 unsigned long av_pkt_rcvd;
135 unsigned long av_tagged_pkt_rcvd;
136 unsigned long vlan_tag_priority_val;
137 unsigned long l3_filter_match;
138 unsigned long l4_filter_match;
139 unsigned long l3_l4_filter_no_match;
141 unsigned long irq_pcs_ane_n;
142 unsigned long irq_pcs_link_n;
143 unsigned long irq_rgmii_n;
144 unsigned long pcs_link;
145 unsigned long pcs_duplex;
146 unsigned long pcs_speed;
148 unsigned long mtl_tx_status_fifo_full;
149 unsigned long mtl_tx_fifo_not_empty;
150 unsigned long mmtl_fifo_ctrl;
151 unsigned long mtl_tx_fifo_read_ctrl_write;
152 unsigned long mtl_tx_fifo_read_ctrl_wait;
153 unsigned long mtl_tx_fifo_read_ctrl_read;
154 unsigned long mtl_tx_fifo_read_ctrl_idle;
155 unsigned long mac_tx_in_pause;
156 unsigned long mac_tx_frame_ctrl_xfer;
157 unsigned long mac_tx_frame_ctrl_idle;
158 unsigned long mac_tx_frame_ctrl_wait;
159 unsigned long mac_tx_frame_ctrl_pause;
160 unsigned long mac_gmii_tx_proto_engine;
161 unsigned long mtl_rx_fifo_fill_level_full;
162 unsigned long mtl_rx_fifo_fill_above_thresh;
163 unsigned long mtl_rx_fifo_fill_below_thresh;
164 unsigned long mtl_rx_fifo_fill_level_empty;
165 unsigned long mtl_rx_fifo_read_ctrl_flush;
166 unsigned long mtl_rx_fifo_read_ctrl_read_data;
167 unsigned long mtl_rx_fifo_read_ctrl_status;
168 unsigned long mtl_rx_fifo_read_ctrl_idle;
169 unsigned long mtl_rx_fifo_ctrl_active;
170 unsigned long mac_rx_frame_ctrl_fifo;
171 unsigned long mac_gmii_rx_proto_engine;
173 unsigned long tx_tso_frames;
174 unsigned long tx_tso_nfrags;
177 /* CSR Frequency Access Defines*/
178 #define CSR_F_35M 35000000
179 #define CSR_F_60M 60000000
180 #define CSR_F_100M 100000000
181 #define CSR_F_150M 150000000
182 #define CSR_F_250M 250000000
183 #define CSR_F_300M 300000000
185 #define MAC_CSR_H_FRQ_MASK 0x20
187 #define HASH_TABLE_SIZE 64
188 #define PAUSE_TIME 0xffff
190 /* Flow Control defines */
194 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
197 #define STMMAC_PCS_RGMII (1 << 0)
198 #define STMMAC_PCS_SGMII (1 << 1)
199 #define STMMAC_PCS_TBI (1 << 2)
200 #define STMMAC_PCS_RTBI (1 << 3)
202 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
204 /* DAM HW feature register fields */
205 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
206 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
207 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
208 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
209 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
210 #define DMA_HW_FEAT_ADDMAC 0x00000020 /* Multiple MAC Addr Reg */
211 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
212 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
213 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
214 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
215 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
216 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
217 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 */
218 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 PTPv2 */
219 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
220 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
221 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
222 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP COE (Type 1) in Rx */
223 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP COE (Type 2) in Rx */
224 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
225 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. additional Rx Channels */
226 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. additional Tx Channels */
227 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate Descriptor */
228 /* Timestamping with Internal System Time */
229 #define DMA_HW_FEAT_INTTSEN 0x02000000
230 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
231 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN */
232 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY iface */
233 #define DEFAULT_DMA_PBL 8
235 /* PCS status and mask defines */
236 #define PCS_ANE_IRQ BIT(2) /* PCS Auto-Negotiation */
237 #define PCS_LINK_IRQ BIT(1) /* PCS Link */
238 #define PCS_RGSMIIIS_IRQ BIT(0) /* RGMII or SMII Interrupt */
240 /* Max/Min RI Watchdog Timer count value */
241 #define MAX_DMA_RIWT 0xff
242 #define MIN_DMA_RIWT 0x20
243 /* Tx coalesce parameters */
244 #define STMMAC_COAL_TX_TIMER 40000
245 #define STMMAC_MAX_COAL_TX_TICK 100000
246 #define STMMAC_TX_MAX_FRAMES 256
247 #define STMMAC_TX_FRAMES 64
250 enum rx_frame_status {
260 enum tx_frame_status {
267 enum dma_irq_status {
269 tx_hard_error_bump_tc = 0x2,
274 /* EEE and LPI defines */
275 #define CORE_IRQ_TX_PATH_IN_LPI_MODE (1 << 0)
276 #define CORE_IRQ_TX_PATH_EXIT_LPI_MODE (1 << 1)
277 #define CORE_IRQ_RX_PATH_IN_LPI_MODE (1 << 2)
278 #define CORE_IRQ_RX_PATH_EXIT_LPI_MODE (1 << 3)
280 #define CORE_IRQ_MTL_RX_OVERFLOW BIT(8)
282 /* Physical Coding Sublayer */
286 unsigned int lp_pause;
287 unsigned int lp_duplex;
290 #define STMMAC_PCS_PAUSE 1
291 #define STMMAC_PCS_ASYM_PAUSE 2
293 /* DMA HW capabilities */
294 struct dma_features {
295 unsigned int mbps_10_100;
296 unsigned int mbps_1000;
297 unsigned int half_duplex;
298 unsigned int hash_filter;
299 unsigned int multi_addr;
301 unsigned int sma_mdio;
302 unsigned int pmt_remote_wake_up;
303 unsigned int pmt_magic_frame;
306 unsigned int time_stamp;
308 unsigned int atime_stamp;
309 /* 802.3az - Energy-Efficient Ethernet (EEE) */
316 unsigned int rx_coe_type1;
317 unsigned int rx_coe_type2;
318 unsigned int rxfifo_over_2048;
319 /* TX and RX number of channels */
320 unsigned int number_rx_channel;
321 unsigned int number_tx_channel;
322 /* TX and RX number of queues */
323 unsigned int number_rx_queues;
324 unsigned int number_tx_queues;
325 /* Alternate (enhanced) DESC mode */
326 unsigned int enh_desc;
327 /* TX and RX FIFO sizes */
328 unsigned int tx_fifo_size;
329 unsigned int rx_fifo_size;
332 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
333 #define BUF_SIZE_16KiB 16384
334 #define BUF_SIZE_8KiB 8192
335 #define BUF_SIZE_4KiB 4096
336 #define BUF_SIZE_2KiB 2048
338 /* Power Down and WOL */
339 #define PMT_NOT_SUPPORTED 0
340 #define PMT_SUPPORTED 1
342 /* Common MAC defines */
343 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
344 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
345 #define MAC_ENABLE_RX 0x00000004 /* Receiver Enable */
347 /* Default LPI timers */
348 #define STMMAC_DEFAULT_LIT_LS 0x3E8
349 #define STMMAC_DEFAULT_TWT_LS 0x1E
351 #define STMMAC_CHAIN_MODE 0x1
352 #define STMMAC_RING_MODE 0x2
354 #define JUMBO_LEN 9000
356 /* Descriptors helpers */
357 struct stmmac_desc_ops {
358 /* DMA RX descriptor ring initialization */
359 void (*init_rx_desc) (struct dma_desc *p, int disable_rx_ic, int mode,
361 /* DMA TX descriptor ring initialization */
362 void (*init_tx_desc) (struct dma_desc *p, int mode, int end);
364 /* Invoked by the xmit function to prepare the tx descriptor */
365 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
366 bool csum_flag, int mode, bool tx_own,
368 void (*prepare_tso_tx_desc)(struct dma_desc *p, int is_fs, int len1,
369 int len2, bool tx_own, bool ls,
370 unsigned int tcphdrlen,
371 unsigned int tcppayloadlen);
372 /* Set/get the owner of the descriptor */
373 void (*set_tx_owner) (struct dma_desc *p);
374 int (*get_tx_owner) (struct dma_desc *p);
375 /* Clean the tx descriptor as soon as the tx irq is received */
376 void (*release_tx_desc) (struct dma_desc *p, int mode);
377 /* Clear interrupt on tx frame completion. When this bit is
378 * set an interrupt happens as soon as the frame is transmitted */
379 void (*set_tx_ic)(struct dma_desc *p);
380 /* Last tx segment reports the transmit status */
381 int (*get_tx_ls) (struct dma_desc *p);
382 /* Return the transmit status looking at the TDES1 */
383 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
384 struct dma_desc *p, void __iomem *ioaddr);
385 /* Get the buffer size from the descriptor */
386 int (*get_tx_len) (struct dma_desc *p);
387 /* Handle extra events on specific interrupts hw dependent */
388 void (*set_rx_owner) (struct dma_desc *p);
389 /* Get the receive frame size */
390 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
391 /* Return the reception status looking at the RDES1 */
392 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
394 void (*rx_extended_status) (void *data, struct stmmac_extra_stats *x,
395 struct dma_extended_desc *p);
396 /* Set tx timestamp enable bit */
397 void (*enable_tx_timestamp) (struct dma_desc *p);
398 /* get tx timestamp status */
399 int (*get_tx_timestamp_status) (struct dma_desc *p);
400 /* get timestamp value */
401 u64(*get_timestamp) (void *desc, u32 ats);
402 /* get rx timestamp status */
403 int (*get_rx_timestamp_status) (void *desc, u32 ats);
405 void (*display_ring)(void *head, unsigned int size, bool rx);
406 /* set MSS via context descriptor */
407 void (*set_mss)(struct dma_desc *p, unsigned int mss);
410 extern const struct stmmac_desc_ops enh_desc_ops;
411 extern const struct stmmac_desc_ops ndesc_ops;
413 /* Specific DMA helpers */
414 struct stmmac_dma_ops {
415 /* DMA core initialization */
416 int (*reset)(void __iomem *ioaddr);
417 void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
418 u32 dma_tx, u32 dma_rx, int atds);
419 /* Configure the AXI Bus Mode Register */
420 void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
421 /* Dump DMA registers */
422 void (*dump_regs)(void __iomem *ioaddr, u32 *reg_space);
423 /* Set tx/rx threshold in the csr6 register
424 * An invalid value enables the store-and-forward mode */
425 void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
427 /* To track extra statistic (if supported) */
428 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
429 void __iomem *ioaddr);
430 void (*enable_dma_transmission) (void __iomem *ioaddr);
431 void (*enable_dma_irq) (void __iomem *ioaddr);
432 void (*disable_dma_irq) (void __iomem *ioaddr);
433 void (*start_tx) (void __iomem *ioaddr);
434 void (*stop_tx) (void __iomem *ioaddr);
435 void (*start_rx) (void __iomem *ioaddr);
436 void (*stop_rx) (void __iomem *ioaddr);
437 int (*dma_interrupt) (void __iomem *ioaddr,
438 struct stmmac_extra_stats *x);
439 /* If supported then get the optional core features */
440 void (*get_hw_feature)(void __iomem *ioaddr,
441 struct dma_features *dma_cap);
442 /* Program the HW RX Watchdog */
443 void (*rx_watchdog) (void __iomem *ioaddr, u32 riwt);
444 void (*set_tx_ring_len)(void __iomem *ioaddr, u32 len);
445 void (*set_rx_ring_len)(void __iomem *ioaddr, u32 len);
446 void (*set_rx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
447 void (*set_tx_tail_ptr)(void __iomem *ioaddr, u32 tail_ptr, u32 chan);
448 void (*enable_tso)(void __iomem *ioaddr, bool en, u32 chan);
451 struct mac_device_info;
453 /* Helpers to program the MAC core */
455 /* MAC core initialization */
456 void (*core_init)(struct mac_device_info *hw, int mtu);
457 /* Enable and verify that the IPC module is supported */
458 int (*rx_ipc)(struct mac_device_info *hw);
459 /* Enable RX Queues */
460 void (*rx_queue_enable)(struct mac_device_info *hw, u8 mode, u32 queue);
461 /* Program RX Algorithms */
462 void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
463 /* Program TX Algorithms */
464 void (*prog_mtl_tx_algorithms)(struct mac_device_info *hw, u32 tx_alg);
465 /* Set MTL TX queues weight */
466 void (*set_mtl_tx_queue_weight)(struct mac_device_info *hw,
467 u32 weight, u32 queue);
468 /* RX MTL queue to RX dma mapping */
469 void (*map_mtl_to_dma)(struct mac_device_info *hw, u32 queue, u32 chan);
470 /* Dump MAC registers */
471 void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);
472 /* Handle extra events on specific interrupts hw dependent */
473 int (*host_irq_status)(struct mac_device_info *hw,
474 struct stmmac_extra_stats *x);
475 /* Handle MTL interrupts */
476 int (*host_mtl_irq_status)(struct mac_device_info *hw, u32 chan);
477 /* Multicast filter setting */
478 void (*set_filter)(struct mac_device_info *hw, struct net_device *dev);
479 /* Flow control setting */
480 void (*flow_ctrl)(struct mac_device_info *hw, unsigned int duplex,
481 unsigned int fc, unsigned int pause_time, u32 tx_cnt);
482 /* Set power management mode (e.g. magic frame) */
483 void (*pmt)(struct mac_device_info *hw, unsigned long mode);
484 /* Set/Get Unicast MAC addresses */
485 void (*set_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
487 void (*get_umac_addr)(struct mac_device_info *hw, unsigned char *addr,
489 void (*set_eee_mode)(struct mac_device_info *hw,
490 bool en_tx_lpi_clockgating);
491 void (*reset_eee_mode)(struct mac_device_info *hw);
492 void (*set_eee_timer)(struct mac_device_info *hw, int ls, int tw);
493 void (*set_eee_pls)(struct mac_device_info *hw, int link);
494 void (*debug)(void __iomem *ioaddr, struct stmmac_extra_stats *x,
495 u32 rx_queues, u32 tx_queues);
497 void (*pcs_ctrl_ane)(void __iomem *ioaddr, bool ane, bool srgmi_ral,
499 void (*pcs_rane)(void __iomem *ioaddr, bool restart);
500 void (*pcs_get_adv_lp)(void __iomem *ioaddr, struct rgmii_adv *adv);
503 /* PTP and HW Timer helpers */
504 struct stmmac_hwtimestamp {
505 void (*config_hw_tstamping) (void __iomem *ioaddr, u32 data);
506 u32 (*config_sub_second_increment)(void __iomem *ioaddr, u32 ptp_clock,
508 int (*init_systime) (void __iomem *ioaddr, u32 sec, u32 nsec);
509 int (*config_addend) (void __iomem *ioaddr, u32 addend);
510 int (*adjust_systime) (void __iomem *ioaddr, u32 sec, u32 nsec,
511 int add_sub, int gmac4);
512 u64(*get_systime) (void __iomem *ioaddr);
515 extern const struct stmmac_hwtimestamp stmmac_ptp;
516 extern const struct stmmac_mode_ops dwmac4_ring_mode_ops;
525 unsigned int addr; /* MII Address */
526 unsigned int data; /* MII Data */
527 unsigned int addr_shift; /* MII address shift */
528 unsigned int reg_shift; /* MII reg shift */
529 unsigned int addr_mask; /* MII address mask */
530 unsigned int reg_mask; /* MII reg mask */
531 unsigned int clk_csr_shift;
532 unsigned int clk_csr_mask;
535 /* Helpers to manage the descriptors for chain and ring modes */
536 struct stmmac_mode_ops {
537 void (*init) (void *des, dma_addr_t phy_addr, unsigned int size,
538 unsigned int extend_desc);
539 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
540 int (*jumbo_frm)(void *priv, struct sk_buff *skb, int csum);
541 int (*set_16kib_bfsize)(int mtu);
542 void (*init_desc3)(struct dma_desc *p);
543 void (*refill_desc3) (void *priv, struct dma_desc *p);
544 void (*clean_desc3) (void *priv, struct dma_desc *p);
547 struct mac_device_info {
548 const struct stmmac_ops *mac;
549 const struct stmmac_desc_ops *desc;
550 const struct stmmac_dma_ops *dma;
551 const struct stmmac_mode_ops *mode;
552 const struct stmmac_hwtimestamp *ptp;
553 struct mii_regs mii; /* MII register Addresses */
554 struct mac_link link;
555 void __iomem *pcsr; /* vpointer to device CSRs */
556 int multicast_filter_bins;
557 int unicast_filter_entries;
559 unsigned int rx_csum;
565 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr, int mcbins,
566 int perfect_uc_entries,
568 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr, int *synopsys_id);
569 struct mac_device_info *dwmac4_setup(void __iomem *ioaddr, int mcbins,
570 int perfect_uc_entries, int *synopsys_id);
572 void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
573 unsigned int high, unsigned int low);
574 void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
575 unsigned int high, unsigned int low);
576 void stmmac_set_mac(void __iomem *ioaddr, bool enable);
578 void stmmac_dwmac4_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
579 unsigned int high, unsigned int low);
580 void stmmac_dwmac4_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
581 unsigned int high, unsigned int low);
582 void stmmac_dwmac4_set_mac(void __iomem *ioaddr, bool enable);
584 void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
586 extern const struct stmmac_mode_ops ring_mode_ops;
587 extern const struct stmmac_mode_ops chain_mode_ops;
588 extern const struct stmmac_desc_ops dwmac4_desc_ops;
591 * stmmac_get_synopsys_id - return the SYINID.
592 * @priv: driver private structure
593 * Description: this simple function is to decode and return the SYINID
594 * starting from the HW core register.
596 static inline u32 stmmac_get_synopsys_id(u32 hwid)
598 /* Check Synopsys Id (not available on old chips) */
600 u32 uid = ((hwid & 0x0000ff00) >> 8);
601 u32 synid = (hwid & 0x000000ff);
603 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n",
610 #endif /* __COMMON_H__ */