1 /*******************************************************************************
2 STMMAC Common Header File
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23 *******************************************************************************/
25 #include <linux/etherdevice.h>
26 #include <linux/netdevice.h>
27 #include <linux/phy.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
31 #define STMMAC_VLAN_TAG_USED
32 #include <linux/if_vlan.h>
38 #undef CHIP_DEBUG_PRINT
39 /* Turn-on extra printk debug for MAC core, dma and descriptors */
40 /* #define CHIP_DEBUG_PRINT */
42 #ifdef CHIP_DEBUG_PRINT
43 #define CHIP_DBG(fmt, args...) printk(fmt, ## args)
45 #define CHIP_DBG(fmt, args...) do { } while (0)
48 #undef FRAME_FILTER_DEBUG
49 /* #define FRAME_FILTER_DEBUG */
51 struct stmmac_extra_stats {
53 unsigned long tx_underflow ____cacheline_aligned;
54 unsigned long tx_carrier;
55 unsigned long tx_losscarrier;
56 unsigned long vlan_tag;
57 unsigned long tx_deferred;
58 unsigned long tx_vlan;
59 unsigned long tx_jabber;
60 unsigned long tx_frame_flushed;
61 unsigned long tx_payload_error;
62 unsigned long tx_ip_header_error;
64 unsigned long rx_desc;
65 unsigned long sa_filter_fail;
66 unsigned long overflow_error;
67 unsigned long ipc_csum_error;
68 unsigned long rx_collision;
70 unsigned long dribbling_bit;
71 unsigned long rx_length;
73 unsigned long rx_multicast;
74 unsigned long rx_gmac_overflow;
75 unsigned long rx_watchdog;
76 unsigned long da_rx_filter_fail;
77 unsigned long sa_rx_filter_fail;
78 unsigned long rx_missed_cntr;
79 unsigned long rx_overflow_cntr;
80 unsigned long rx_vlan;
81 /* Tx/Rx IRQ errors */
82 unsigned long tx_undeflow_irq;
83 unsigned long tx_process_stopped_irq;
84 unsigned long tx_jabber_irq;
85 unsigned long rx_overflow_irq;
86 unsigned long rx_buf_unav_irq;
87 unsigned long rx_process_stopped_irq;
88 unsigned long rx_watchdog_irq;
89 unsigned long tx_early_irq;
90 unsigned long fatal_bus_error_irq;
92 unsigned long threshold;
93 unsigned long tx_pkt_n;
94 unsigned long rx_pkt_n;
96 unsigned long sched_timer_n;
97 unsigned long normal_irq_n;
100 /* CSR Frequency Access Defines*/
101 #define CSR_F_35M 35000000
102 #define CSR_F_60M 60000000
103 #define CSR_F_100M 100000000
104 #define CSR_F_150M 150000000
105 #define CSR_F_250M 250000000
106 #define CSR_F_300M 300000000
108 #define MAC_CSR_H_FRQ_MASK 0x20
110 #define HASH_TABLE_SIZE 64
111 #define PAUSE_TIME 0x200
113 /* Flow Control defines */
117 #define FLOW_AUTO (FLOW_TX | FLOW_RX)
119 #define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
121 /* DAM HW feature register fields */
122 #define DMA_HW_FEAT_MIISEL 0x00000001 /* 10/100 Mbps Support */
123 #define DMA_HW_FEAT_GMIISEL 0x00000002 /* 1000 Mbps Support */
124 #define DMA_HW_FEAT_HDSEL 0x00000004 /* Half-Duplex Support */
125 #define DMA_HW_FEAT_EXTHASHEN 0x00000008 /* Expanded DA Hash Filter */
126 #define DMA_HW_FEAT_HASHSEL 0x00000010 /* HASH Filter */
127 #define DMA_HW_FEAT_ADDMACADRSEL 0x00000020 /* Multiple MAC Addr Reg */
128 #define DMA_HW_FEAT_PCSSEL 0x00000040 /* PCS registers */
129 #define DMA_HW_FEAT_L3L4FLTREN 0x00000080 /* Layer 3 & Layer 4 Feature */
130 #define DMA_HW_FEAT_SMASEL 0x00000100 /* SMA(MDIO) Interface */
131 #define DMA_HW_FEAT_RWKSEL 0x00000200 /* PMT Remote Wakeup */
132 #define DMA_HW_FEAT_MGKSEL 0x00000400 /* PMT Magic Packet */
133 #define DMA_HW_FEAT_MMCSEL 0x00000800 /* RMON Module */
134 #define DMA_HW_FEAT_TSVER1SEL 0x00001000 /* Only IEEE 1588-2002 Timestamp */
135 #define DMA_HW_FEAT_TSVER2SEL 0x00002000 /* IEEE 1588-2008 Adv Timestamp */
136 #define DMA_HW_FEAT_EEESEL 0x00004000 /* Energy Efficient Ethernet */
137 #define DMA_HW_FEAT_AVSEL 0x00008000 /* AV Feature */
138 #define DMA_HW_FEAT_TXCOESEL 0x00010000 /* Checksum Offload in Tx */
139 #define DMA_HW_FEAT_RXTYP1COE 0x00020000 /* IP csum Offload(Type 1) in Rx */
140 #define DMA_HW_FEAT_RXTYP2COE 0x00040000 /* IP csum Offload(Type 2) in Rx */
141 #define DMA_HW_FEAT_RXFIFOSIZE 0x00080000 /* Rx FIFO > 2048 Bytes */
142 #define DMA_HW_FEAT_RXCHCNT 0x00300000 /* No. of additional Rx Channels */
143 #define DMA_HW_FEAT_TXCHCNT 0x00c00000 /* No. of additional Tx Channels */
144 #define DMA_HW_FEAT_ENHDESSEL 0x01000000 /* Alternate (Enhanced Descriptor) */
145 #define DMA_HW_FEAT_INTTSEN 0x02000000 /* Timestamping with Internal
147 #define DMA_HW_FEAT_FLEXIPPSEN 0x04000000 /* Flexible PPS Output */
148 #define DMA_HW_FEAT_SAVLANINS 0x08000000 /* Source Addr or VLAN Insertion */
149 #define DMA_HW_FEAT_ACTPHYIF 0x70000000 /* Active/selected PHY interface */
151 enum rx_frame_status { /* IPC status */
158 enum tx_dma_irq_status {
160 tx_hard_error_bump_tc = 2,
164 /* DMA HW capabilities */
165 struct dma_features {
166 unsigned int mbps_10_100;
167 unsigned int mbps_1000;
168 unsigned int half_duplex;
169 unsigned int hash_filter;
170 unsigned int multi_addr;
172 unsigned int sma_mdio;
173 unsigned int pmt_remote_wake_up;
174 unsigned int pmt_magic_frame;
177 unsigned int time_stamp;
179 unsigned int atime_stamp;
180 /* 802.3az - Energy-Efficient Ethernet (EEE) */
185 unsigned int rx_coe_type1;
186 unsigned int rx_coe_type2;
187 unsigned int rxfifo_over_2048;
188 /* TX and RX number of channels */
189 unsigned int number_rx_channel;
190 unsigned int number_tx_channel;
191 /* Alternate (enhanced) DESC mode*/
192 unsigned int enh_desc;
195 /* GMAC TX FIFO is 8K, Rx FIFO is 16K */
196 #define BUF_SIZE_16KiB 16384
197 #define BUF_SIZE_8KiB 8192
198 #define BUF_SIZE_4KiB 4096
199 #define BUF_SIZE_2KiB 2048
201 /* Power Down and WOL */
202 #define PMT_NOT_SUPPORTED 0
203 #define PMT_SUPPORTED 1
205 /* Common MAC defines */
206 #define MAC_CTRL_REG 0x00000000 /* MAC Control */
207 #define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
208 #define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
210 struct stmmac_desc_ops {
211 /* DMA RX descriptor ring initialization */
212 void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
214 /* DMA TX descriptor ring initialization */
215 void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);
217 /* Invoked by the xmit function to prepare the tx descriptor */
218 void (*prepare_tx_desc) (struct dma_desc *p, int is_fs, int len,
220 /* Set/get the owner of the descriptor */
221 void (*set_tx_owner) (struct dma_desc *p);
222 int (*get_tx_owner) (struct dma_desc *p);
223 /* Invoked by the xmit function to close the tx descriptor */
224 void (*close_tx_desc) (struct dma_desc *p);
225 /* Clean the tx descriptor as soon as the tx irq is received */
226 void (*release_tx_desc) (struct dma_desc *p);
227 /* Clear interrupt on tx frame completion. When this bit is
228 * set an interrupt happens as soon as the frame is transmitted */
229 void (*clear_tx_ic) (struct dma_desc *p);
230 /* Last tx segment reports the transmit status */
231 int (*get_tx_ls) (struct dma_desc *p);
232 /* Return the transmit status looking at the TDES1 */
233 int (*tx_status) (void *data, struct stmmac_extra_stats *x,
234 struct dma_desc *p, void __iomem *ioaddr);
235 /* Get the buffer size from the descriptor */
236 int (*get_tx_len) (struct dma_desc *p);
237 /* Handle extra events on specific interrupts hw dependent */
238 int (*get_rx_owner) (struct dma_desc *p);
239 void (*set_rx_owner) (struct dma_desc *p);
240 /* Get the receive frame size */
241 int (*get_rx_frame_len) (struct dma_desc *p, int rx_coe_type);
242 /* Return the reception status looking at the RDES1 */
243 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
247 struct stmmac_dma_ops {
248 /* DMA core initialization */
249 int (*init) (void __iomem *ioaddr, int pbl, int fb, int burst_len,
250 u32 dma_tx, u32 dma_rx);
251 /* Dump DMA registers */
252 void (*dump_regs) (void __iomem *ioaddr);
253 /* Set tx/rx threshold in the csr6 register
254 * An invalid value enables the store-and-forward mode */
255 void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode);
256 /* To track extra statistic (if supported) */
257 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
258 void __iomem *ioaddr);
259 void (*enable_dma_transmission) (void __iomem *ioaddr);
260 void (*enable_dma_irq) (void __iomem *ioaddr);
261 void (*disable_dma_irq) (void __iomem *ioaddr);
262 void (*start_tx) (void __iomem *ioaddr);
263 void (*stop_tx) (void __iomem *ioaddr);
264 void (*start_rx) (void __iomem *ioaddr);
265 void (*stop_rx) (void __iomem *ioaddr);
266 int (*dma_interrupt) (void __iomem *ioaddr,
267 struct stmmac_extra_stats *x);
268 /* If supported then get the optional core features */
269 unsigned int (*get_hw_feature) (void __iomem *ioaddr);
273 /* MAC core initialization */
274 void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned;
275 /* Enable and verify that the IPC module is supported */
276 int (*rx_ipc) (void __iomem *ioaddr);
277 /* Dump MAC registers */
278 void (*dump_regs) (void __iomem *ioaddr);
279 /* Handle extra events on specific interrupts hw dependent */
280 void (*host_irq_status) (void __iomem *ioaddr);
281 /* Multicast filter setting */
282 void (*set_filter) (struct net_device *dev);
283 /* Flow control setting */
284 void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex,
285 unsigned int fc, unsigned int pause_time);
286 /* Set power management mode (e.g. magic frame) */
287 void (*pmt) (void __iomem *ioaddr, unsigned long mode);
288 /* Set/Get Unicast MAC addresses */
289 void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
291 void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr,
302 unsigned int addr; /* MII Address */
303 unsigned int data; /* MII Data */
306 struct stmmac_ring_mode_ops {
307 unsigned int (*is_jumbo_frm) (int len, int ehn_desc);
308 unsigned int (*jumbo_frm) (void *priv, struct sk_buff *skb, int csum);
309 void (*refill_desc3) (int bfsize, struct dma_desc *p);
310 void (*init_desc3) (int des3_as_data_buf, struct dma_desc *p);
311 void (*init_dma_chain) (struct dma_desc *des, dma_addr_t phy_addr,
313 void (*clean_desc3) (struct dma_desc *p);
314 int (*set_16kib_bfsize) (int mtu);
317 struct mac_device_info {
318 const struct stmmac_ops *mac;
319 const struct stmmac_desc_ops *desc;
320 const struct stmmac_dma_ops *dma;
321 const struct stmmac_ring_mode_ops *ring;
322 struct mii_regs mii; /* MII register Addresses */
323 struct mac_link link;
324 unsigned int synopsys_uid;
327 struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr);
328 struct mac_device_info *dwmac100_setup(void __iomem *ioaddr);
330 extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
331 unsigned int high, unsigned int low);
332 extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
333 unsigned int high, unsigned int low);
335 extern void stmmac_set_mac(void __iomem *ioaddr, bool enable);
337 extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr);
338 extern const struct stmmac_ring_mode_ops ring_mode_ops;