1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
4 * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle
5 * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
8 * o IOC3 ASIC specification 4.51, 1996-04-18
9 * o IEEE 802.3 specification, 2000 edition
10 * o DP38840A Specification, National Semiconductor, March 1997
14 * o Use prefetching for large packets. What is a good lower limit for
16 * o Use hardware checksums.
17 * o Convert to using a IOC3 meta driver.
18 * o Which PHYs might possibly be attached to the IOC3 in real live,
19 * which workarounds are required for them? Do we ever have Lucent's?
20 * o For the 2.5 branch kill the mii-tool ioctls.
23 #define IOC3_NAME "ioc3-eth"
24 #define IOC3_VERSION "2.6.3-4"
26 #include <linux/delay.h>
27 #include <linux/kernel.h>
29 #include <linux/errno.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/crc32.h>
33 #include <linux/mii.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/gfp.h>
41 #ifdef CONFIG_SERIAL_8250
42 #include <linux/serial_core.h>
43 #include <linux/serial_8250.h>
44 #include <linux/serial_reg.h>
47 #include <linux/netdevice.h>
48 #include <linux/etherdevice.h>
49 #include <linux/ethtool.h>
50 #include <linux/skbuff.h>
51 #include <linux/dma-mapping.h>
55 #include <asm/byteorder.h>
56 #include <asm/pgtable.h>
57 #include <linux/uaccess.h>
58 #include <asm/sn/types.h>
59 #include <asm/sn/ioc3.h>
60 #include <asm/pci/bridge.h>
62 /* Number of RX buffers. This is tunable in the range of 16 <= x < 512.
63 * The value must be a power of two.
66 #define RX_RING_ENTRIES 512 /* fixed in hardware */
67 #define RX_RING_MASK (RX_RING_ENTRIES - 1)
68 #define RX_RING_SIZE (RX_RING_ENTRIES * sizeof(u64))
70 /* 128 TX buffers (not tunable) */
71 #define TX_RING_ENTRIES 128
72 #define TX_RING_MASK (TX_RING_ENTRIES - 1)
73 #define TX_RING_SIZE (TX_RING_ENTRIES * sizeof(struct ioc3_etxd))
75 /* IOC3 does dma transfers in 128 byte blocks */
76 #define IOC3_DMA_XFER_LEN 128UL
78 /* Every RX buffer starts with 8 byte descriptor data */
79 #define RX_OFFSET (sizeof(struct ioc3_erxbuf) + NET_IP_ALIGN)
80 #define RX_BUF_SIZE (13 * IOC3_DMA_XFER_LEN)
82 #define ETCSR_FD ((21 << ETCSR_IPGR2_SHIFT) | (21 << ETCSR_IPGR1_SHIFT) | 21)
83 #define ETCSR_HD ((17 << ETCSR_IPGR2_SHIFT) | (11 << ETCSR_IPGR1_SHIFT) | 21)
85 /* Private per NIC data of the driver. */
87 struct ioc3_ethregs *regs;
88 struct ioc3 *all_regs;
89 struct device *dma_dev;
91 unsigned long *rxr; /* pointer to receiver ring */
92 struct ioc3_etxd *txr;
95 struct sk_buff *rx_skbs[RX_RING_ENTRIES];
96 struct sk_buff *tx_skbs[TX_RING_ENTRIES];
97 int rx_ci; /* RX consumer index */
98 int rx_pi; /* RX producer index */
99 int tx_ci; /* TX consumer index */
100 int tx_pi; /* TX producer index */
102 u32 emcr, ehar_h, ehar_l;
103 spinlock_t ioc3_lock;
104 struct mii_if_info mii;
106 struct net_device *dev;
107 struct pci_dev *pdev;
109 /* Members used by autonegotiation */
110 struct timer_list ioc3_timer;
113 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
114 static void ioc3_set_multicast_list(struct net_device *dev);
115 static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev);
116 static void ioc3_timeout(struct net_device *dev);
117 static inline unsigned int ioc3_hash(const unsigned char *addr);
118 static void ioc3_start(struct ioc3_private *ip);
119 static inline void ioc3_stop(struct ioc3_private *ip);
120 static void ioc3_init(struct net_device *dev);
121 static int ioc3_alloc_rx_bufs(struct net_device *dev);
122 static void ioc3_free_rx_bufs(struct ioc3_private *ip);
123 static inline void ioc3_clean_tx_ring(struct ioc3_private *ip);
125 static const char ioc3_str[] = "IOC3 Ethernet";
126 static const struct ethtool_ops ioc3_ethtool_ops;
129 static inline unsigned long aligned_rx_skb_addr(unsigned long addr)
131 return (~addr + 1) & (IOC3_DMA_XFER_LEN - 1UL);
134 static inline int ioc3_alloc_skb(struct ioc3_private *ip, struct sk_buff **skb,
135 struct ioc3_erxbuf **rxb, dma_addr_t *rxb_dma)
137 struct sk_buff *new_skb;
141 new_skb = alloc_skb(RX_BUF_SIZE + IOC3_DMA_XFER_LEN - 1, GFP_ATOMIC);
145 /* ensure buffer is aligned to IOC3_DMA_XFER_LEN */
146 offset = aligned_rx_skb_addr((unsigned long)new_skb->data);
148 skb_reserve(new_skb, offset);
150 d = dma_map_single(ip->dma_dev, new_skb->data,
151 RX_BUF_SIZE, DMA_FROM_DEVICE);
153 if (dma_mapping_error(ip->dma_dev, d)) {
154 dev_kfree_skb_any(new_skb);
158 *rxb = (struct ioc3_erxbuf *)new_skb->data;
159 skb_reserve(new_skb, RX_OFFSET);
165 #ifdef CONFIG_PCI_XTALK_BRIDGE
166 static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr)
168 return (addr & ~PCI64_ATTR_BAR) | attr;
171 #define ERBAR_VAL (ERBAR_BARRIER_BIT << ERBAR_RXBARR_SHIFT)
173 static inline unsigned long ioc3_map(dma_addr_t addr, unsigned long attr)
181 #define IOC3_SIZE 0x100000
183 static inline u32 mcr_pack(u32 pulse, u32 sample)
185 return (pulse << 10) | (sample << 2);
188 static int nic_wait(u32 __iomem *mcr)
199 static int nic_reset(u32 __iomem *mcr)
203 writel(mcr_pack(500, 65), mcr);
204 presence = nic_wait(mcr);
206 writel(mcr_pack(0, 500), mcr);
212 static inline int nic_read_bit(u32 __iomem *mcr)
216 writel(mcr_pack(6, 13), mcr);
217 result = nic_wait(mcr);
218 writel(mcr_pack(0, 100), mcr);
224 static inline void nic_write_bit(u32 __iomem *mcr, int bit)
227 writel(mcr_pack(6, 110), mcr);
229 writel(mcr_pack(80, 30), mcr);
234 /* Read a byte from an iButton device
236 static u32 nic_read_byte(u32 __iomem *mcr)
241 for (i = 0; i < 8; i++)
242 result = (result >> 1) | (nic_read_bit(mcr) << 7);
247 /* Write a byte to an iButton device
249 static void nic_write_byte(u32 __iomem *mcr, int byte)
253 for (i = 8; i; i--) {
257 nic_write_bit(mcr, bit);
261 static u64 nic_find(u32 __iomem *mcr, int *last)
263 int a, b, index, disc;
268 nic_write_byte(mcr, 0xf0);
270 /* Algorithm from ``Book of iButton Standards''. */
271 for (index = 0, disc = 0; index < 64; index++) {
272 a = nic_read_bit(mcr);
273 b = nic_read_bit(mcr);
276 pr_warn("NIC search failed (not fatal).\n");
282 if (index == *last) {
283 address |= 1UL << index;
284 } else if (index > *last) {
285 address &= ~(1UL << index);
287 } else if ((address & (1UL << index)) == 0) {
290 nic_write_bit(mcr, address & (1UL << index));
294 address |= 1UL << index;
296 address &= ~(1UL << index);
297 nic_write_bit(mcr, a);
307 static int nic_init(u32 __iomem *mcr)
309 const char *unknown = "unknown";
310 const char *type = unknown;
318 reg = nic_find(mcr, &save);
320 switch (reg & 0xff) {
326 /* Let the caller try again. */
335 nic_write_byte(mcr, 0x55);
336 for (i = 0; i < 8; i++)
337 nic_write_byte(mcr, (reg >> (i << 3)) & 0xff);
339 reg >>= 8; /* Shift out type. */
340 for (i = 0; i < 6; i++) {
341 serial[i] = reg & 0xff;
348 pr_info("Found %s NIC", type);
350 pr_cont(" registration number %pM, CRC %02x", serial, crc);
356 /* Read the NIC (Number-In-a-Can) device used to store the MAC address on
357 * SN0 / SN00 nodeboards and PCI cards.
359 static void ioc3_get_eaddr_nic(struct ioc3_private *ip)
361 u32 __iomem *mcr = &ip->all_regs->mcr;
362 int tries = 2; /* There may be some problem with the battery? */
366 writel(1 << 21, &ip->all_regs->gpcr_s);
375 pr_err("Failed to read MAC address\n");
380 nic_write_byte(mcr, 0xf0);
381 nic_write_byte(mcr, 0x00);
382 nic_write_byte(mcr, 0x00);
384 for (i = 13; i >= 0; i--)
385 nic[i] = nic_read_byte(mcr);
387 for (i = 2; i < 8; i++)
388 ip->dev->dev_addr[i - 2] = nic[i];
391 /* Ok, this is hosed by design. It's necessary to know what machine the
392 * NIC is in in order to know how to read the NIC address. We also have
393 * to know if it's a PCI card or a NIC in on the node board ...
395 static void ioc3_get_eaddr(struct ioc3_private *ip)
397 ioc3_get_eaddr_nic(ip);
399 pr_info("Ethernet address is %pM.\n", ip->dev->dev_addr);
402 static void __ioc3_set_mac_address(struct net_device *dev)
404 struct ioc3_private *ip = netdev_priv(dev);
406 writel((dev->dev_addr[5] << 8) |
409 writel((dev->dev_addr[3] << 24) |
410 (dev->dev_addr[2] << 16) |
411 (dev->dev_addr[1] << 8) |
416 static int ioc3_set_mac_address(struct net_device *dev, void *addr)
418 struct ioc3_private *ip = netdev_priv(dev);
419 struct sockaddr *sa = addr;
421 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
423 spin_lock_irq(&ip->ioc3_lock);
424 __ioc3_set_mac_address(dev);
425 spin_unlock_irq(&ip->ioc3_lock);
430 /* Caller must hold the ioc3_lock ever for MII readers. This is also
431 * used to protect the transmitter side but it's low contention.
433 static int ioc3_mdio_read(struct net_device *dev, int phy, int reg)
435 struct ioc3_private *ip = netdev_priv(dev);
436 struct ioc3_ethregs *regs = ip->regs;
438 while (readl(®s->micr) & MICR_BUSY)
440 writel((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG,
442 while (readl(®s->micr) & MICR_BUSY)
445 return readl(®s->midr_r) & MIDR_DATA_MASK;
448 static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
450 struct ioc3_private *ip = netdev_priv(dev);
451 struct ioc3_ethregs *regs = ip->regs;
453 while (readl(®s->micr) & MICR_BUSY)
455 writel(data, ®s->midr_w);
456 writel((phy << MICR_PHYADDR_SHIFT) | reg, ®s->micr);
457 while (readl(®s->micr) & MICR_BUSY)
461 static int ioc3_mii_init(struct ioc3_private *ip);
463 static struct net_device_stats *ioc3_get_stats(struct net_device *dev)
465 struct ioc3_private *ip = netdev_priv(dev);
466 struct ioc3_ethregs *regs = ip->regs;
468 dev->stats.collisions += readl(®s->etcdc) & ETCDC_COLLCNT_MASK;
472 static void ioc3_tcpudp_checksum(struct sk_buff *skb, u32 hwsum, int len)
474 struct ethhdr *eh = eth_hdr(skb);
481 /* Did hardware handle the checksum at all? The cases we can handle
484 * - TCP and UDP checksums of IPv4 only.
485 * - IPv6 would be doable but we keep that for later ...
486 * - Only unfragmented packets. Did somebody already tell you
487 * fragmentation is evil?
488 * - don't care about packet size. Worst case when processing a
489 * malformed packet we'll try to access the packet at ip header +
490 * 64 bytes which is still inside the skb. Even in the unlikely
491 * case where the checksum is right the higher layers will still
492 * drop the packet as appropriate.
494 if (eh->h_proto != htons(ETH_P_IP))
497 ih = (struct iphdr *)((char *)eh + ETH_HLEN);
498 if (ip_is_fragment(ih))
501 proto = ih->protocol;
502 if (proto != IPPROTO_TCP && proto != IPPROTO_UDP)
505 /* Same as tx - compute csum of pseudo header */
507 (ih->tot_len - (ih->ihl << 2)) +
508 htons((u16)ih->protocol) +
509 (ih->saddr >> 16) + (ih->saddr & 0xffff) +
510 (ih->daddr >> 16) + (ih->daddr & 0xffff);
512 /* Sum up ethernet dest addr, src addr and protocol */
514 ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6];
516 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
517 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
519 csum += 0xffff ^ ehsum;
521 /* In the next step we also subtract the 1's complement
522 * checksum of the trailing ethernet CRC.
524 cp = (char *)eh + len; /* points at trailing CRC */
526 csum += 0xffff ^ (u16)((cp[1] << 8) | cp[0]);
527 csum += 0xffff ^ (u16)((cp[3] << 8) | cp[2]);
529 csum += 0xffff ^ (u16)((cp[0] << 8) | cp[1]);
530 csum += 0xffff ^ (u16)((cp[2] << 8) | cp[3]);
533 csum = (csum & 0xffff) + (csum >> 16);
534 csum = (csum & 0xffff) + (csum >> 16);
537 skb->ip_summed = CHECKSUM_UNNECESSARY;
540 static inline void ioc3_rx(struct net_device *dev)
542 struct ioc3_private *ip = netdev_priv(dev);
543 struct sk_buff *skb, *new_skb;
544 int rx_entry, n_entry, len;
545 struct ioc3_erxbuf *rxb;
550 rxr = ip->rxr; /* Ring base */
551 rx_entry = ip->rx_ci; /* RX consume index */
554 skb = ip->rx_skbs[rx_entry];
555 rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);
556 w0 = be32_to_cpu(rxb->w0);
558 while (w0 & ERXBUF_V) {
559 err = be32_to_cpu(rxb->err); /* It's valid ... */
560 if (err & ERXBUF_GOODPKT) {
561 len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
563 skb->protocol = eth_type_trans(skb, dev);
565 if (ioc3_alloc_skb(ip, &new_skb, &rxb, &d)) {
566 /* Ouch, drop packet and just recycle packet
567 * to keep the ring filled.
569 dev->stats.rx_dropped++;
575 if (likely(dev->features & NETIF_F_RXCSUM))
576 ioc3_tcpudp_checksum(skb,
577 w0 & ERXBUF_IPCKSUM_MASK,
580 dma_unmap_single(ip->dma_dev, rxr[rx_entry],
581 RX_BUF_SIZE, DMA_FROM_DEVICE);
585 ip->rx_skbs[rx_entry] = NULL; /* Poison */
587 dev->stats.rx_packets++; /* Statistics */
588 dev->stats.rx_bytes += len;
590 /* The frame is invalid and the skb never
591 * reached the network layer so we can just
596 dev->stats.rx_errors++;
598 if (err & ERXBUF_CRCERR) /* Statistics */
599 dev->stats.rx_crc_errors++;
600 if (err & ERXBUF_FRAMERR)
601 dev->stats.rx_frame_errors++;
604 ip->rx_skbs[n_entry] = new_skb;
605 rxr[n_entry] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR));
606 rxb->w0 = 0; /* Clear valid flag */
607 n_entry = (n_entry + 1) & RX_RING_MASK; /* Update erpir */
609 /* Now go on to the next ring entry. */
610 rx_entry = (rx_entry + 1) & RX_RING_MASK;
611 skb = ip->rx_skbs[rx_entry];
612 rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);
613 w0 = be32_to_cpu(rxb->w0);
615 writel((n_entry << 3) | ERPIR_ARM, &ip->regs->erpir);
617 ip->rx_ci = rx_entry;
620 static inline void ioc3_tx(struct net_device *dev)
622 struct ioc3_private *ip = netdev_priv(dev);
623 struct ioc3_ethregs *regs = ip->regs;
624 unsigned long packets, bytes;
625 int tx_entry, o_entry;
629 spin_lock(&ip->ioc3_lock);
630 etcir = readl(®s->etcir);
632 tx_entry = (etcir >> 7) & TX_RING_MASK;
637 while (o_entry != tx_entry) {
639 skb = ip->tx_skbs[o_entry];
641 dev_consume_skb_irq(skb);
642 ip->tx_skbs[o_entry] = NULL;
644 o_entry = (o_entry + 1) & TX_RING_MASK; /* Next */
646 etcir = readl(®s->etcir); /* More pkts sent? */
647 tx_entry = (etcir >> 7) & TX_RING_MASK;
650 dev->stats.tx_packets += packets;
651 dev->stats.tx_bytes += bytes;
652 ip->txqlen -= packets;
654 if (netif_queue_stopped(dev) && ip->txqlen < TX_RING_ENTRIES)
655 netif_wake_queue(dev);
658 spin_unlock(&ip->ioc3_lock);
661 /* Deal with fatal IOC3 errors. This condition might be caused by a hard or
662 * software problems, so we should try to recover
663 * more gracefully if this ever happens. In theory we might be flooded
664 * with such error interrupts if something really goes wrong, so we might
665 * also consider to take the interface down.
667 static void ioc3_error(struct net_device *dev, u32 eisr)
669 struct ioc3_private *ip = netdev_priv(dev);
671 spin_lock(&ip->ioc3_lock);
673 if (eisr & EISR_RXOFLO)
674 net_err_ratelimited("%s: RX overflow.\n", dev->name);
675 if (eisr & EISR_RXBUFOFLO)
676 net_err_ratelimited("%s: RX buffer overflow.\n", dev->name);
677 if (eisr & EISR_RXMEMERR)
678 net_err_ratelimited("%s: RX PCI error.\n", dev->name);
679 if (eisr & EISR_RXPARERR)
680 net_err_ratelimited("%s: RX SSRAM parity error.\n", dev->name);
681 if (eisr & EISR_TXBUFUFLO)
682 net_err_ratelimited("%s: TX buffer underflow.\n", dev->name);
683 if (eisr & EISR_TXMEMERR)
684 net_err_ratelimited("%s: TX PCI error.\n", dev->name);
687 ioc3_free_rx_bufs(ip);
688 ioc3_clean_tx_ring(ip);
691 if (ioc3_alloc_rx_bufs(dev)) {
692 netdev_err(dev, "%s: rx buffer allocation failed\n", __func__);
693 spin_unlock(&ip->ioc3_lock);
699 netif_wake_queue(dev);
701 spin_unlock(&ip->ioc3_lock);
704 /* The interrupt handler does all of the Rx thread work and cleans up
705 * after the Tx thread.
707 static irqreturn_t ioc3_interrupt(int irq, void *dev_id)
709 struct ioc3_private *ip = netdev_priv(dev_id);
710 struct ioc3_ethregs *regs = ip->regs;
713 eisr = readl(®s->eisr);
714 writel(eisr, ®s->eisr);
715 readl(®s->eisr); /* Flush */
717 if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR |
718 EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR))
719 ioc3_error(dev_id, eisr);
720 if (eisr & EISR_RXTIMERINT)
722 if (eisr & EISR_TXEXPLICIT)
728 static inline void ioc3_setup_duplex(struct ioc3_private *ip)
730 struct ioc3_ethregs *regs = ip->regs;
732 spin_lock_irq(&ip->ioc3_lock);
734 if (ip->mii.full_duplex) {
735 writel(ETCSR_FD, ®s->etcsr);
736 ip->emcr |= EMCR_DUPLEX;
738 writel(ETCSR_HD, ®s->etcsr);
739 ip->emcr &= ~EMCR_DUPLEX;
741 writel(ip->emcr, ®s->emcr);
743 spin_unlock_irq(&ip->ioc3_lock);
746 static void ioc3_timer(struct timer_list *t)
748 struct ioc3_private *ip = from_timer(ip, t, ioc3_timer);
750 /* Print the link status if it has changed */
751 mii_check_media(&ip->mii, 1, 0);
752 ioc3_setup_duplex(ip);
754 ip->ioc3_timer.expires = jiffies + ((12 * HZ) / 10); /* 1.2s */
755 add_timer(&ip->ioc3_timer);
758 /* Try to find a PHY. There is no apparent relation between the MII addresses
759 * in the SGI documentation and what we find in reality, so we simply probe
760 * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my
761 * onboard IOC3s has the special oddity that probing doesn't seem to find it
762 * yet the interface seems to work fine, so if probing fails we for now will
763 * simply default to PHY 31 instead of bailing out.
765 static int ioc3_mii_init(struct ioc3_private *ip)
767 int ioc3_phy_workaround = 1;
768 int i, found = 0, res = 0;
771 for (i = 0; i < 32; i++) {
772 word = ioc3_mdio_read(ip->dev, i, MII_PHYSID1);
774 if (word != 0xffff && word != 0x0000) {
776 break; /* Found a PHY */
781 if (ioc3_phy_workaround) {
796 static void ioc3_mii_start(struct ioc3_private *ip)
798 ip->ioc3_timer.expires = jiffies + (12 * HZ) / 10; /* 1.2 sec. */
799 add_timer(&ip->ioc3_timer);
802 static inline void ioc3_tx_unmap(struct ioc3_private *ip, int entry)
804 struct ioc3_etxd *desc;
805 u32 cmd, bufcnt, len;
807 desc = &ip->txr[entry];
808 cmd = be32_to_cpu(desc->cmd);
809 bufcnt = be32_to_cpu(desc->bufcnt);
810 if (cmd & ETXD_B1V) {
811 len = (bufcnt & ETXD_B1CNT_MASK) >> ETXD_B1CNT_SHIFT;
812 dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p1),
815 if (cmd & ETXD_B2V) {
816 len = (bufcnt & ETXD_B2CNT_MASK) >> ETXD_B2CNT_SHIFT;
817 dma_unmap_single(ip->dma_dev, be64_to_cpu(desc->p2),
822 static inline void ioc3_clean_tx_ring(struct ioc3_private *ip)
827 for (i = 0; i < TX_RING_ENTRIES; i++) {
828 skb = ip->tx_skbs[i];
830 ioc3_tx_unmap(ip, i);
831 ip->tx_skbs[i] = NULL;
832 dev_kfree_skb_any(skb);
840 static void ioc3_free_rx_bufs(struct ioc3_private *ip)
842 int rx_entry, n_entry;
846 rx_entry = ip->rx_pi;
848 while (n_entry != rx_entry) {
849 skb = ip->rx_skbs[n_entry];
851 dma_unmap_single(ip->dma_dev,
852 be64_to_cpu(ip->rxr[n_entry]),
853 RX_BUF_SIZE, DMA_FROM_DEVICE);
854 dev_kfree_skb_any(skb);
856 n_entry = (n_entry + 1) & RX_RING_MASK;
860 static int ioc3_alloc_rx_bufs(struct net_device *dev)
862 struct ioc3_private *ip = netdev_priv(dev);
863 struct ioc3_erxbuf *rxb;
867 /* Now the rx buffers. The RX ring may be larger but
868 * we only allocate 16 buffers for now. Need to tune
869 * this for performance and memory later.
871 for (i = 0; i < RX_BUFFS; i++) {
872 if (ioc3_alloc_skb(ip, &ip->rx_skbs[i], &rxb, &d))
875 rxb->w0 = 0; /* Clear valid flag */
876 ip->rxr[i] = cpu_to_be64(ioc3_map(d, PCI64_ATTR_BAR));
879 ip->rx_pi = RX_BUFFS;
884 static inline void ioc3_ssram_disc(struct ioc3_private *ip)
886 struct ioc3_ethregs *regs = ip->regs;
887 u32 *ssram0 = &ip->ssram[0x0000];
888 u32 *ssram1 = &ip->ssram[0x4000];
889 u32 pattern = 0x5555;
891 /* Assume the larger size SSRAM and enable parity checking */
892 writel(readl(®s->emcr) | (EMCR_BUFSIZ | EMCR_RAMPAR), ®s->emcr);
893 readl(®s->emcr); /* Flush */
895 writel(pattern, ssram0);
896 writel(~pattern & IOC3_SSRAM_DM, ssram1);
898 if ((readl(ssram0) & IOC3_SSRAM_DM) != pattern ||
899 (readl(ssram1) & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
900 /* set ssram size to 64 KB */
901 ip->emcr |= EMCR_RAMPAR;
902 writel(readl(®s->emcr) & ~EMCR_BUFSIZ, ®s->emcr);
904 ip->emcr |= EMCR_BUFSIZ | EMCR_RAMPAR;
908 static void ioc3_init(struct net_device *dev)
910 struct ioc3_private *ip = netdev_priv(dev);
911 struct ioc3_ethregs *regs = ip->regs;
913 del_timer_sync(&ip->ioc3_timer); /* Kill if running */
915 writel(EMCR_RST, ®s->emcr); /* Reset */
916 readl(®s->emcr); /* Flush WB */
917 udelay(4); /* Give it time ... */
918 writel(0, ®s->emcr);
922 writel(ERBAR_VAL, ®s->erbar);
923 readl(®s->etcdc); /* Clear on read */
924 writel(15, ®s->ercsr); /* RX low watermark */
925 writel(0, ®s->ertr); /* Interrupt immediately */
926 __ioc3_set_mac_address(dev);
927 writel(ip->ehar_h, ®s->ehar_h);
928 writel(ip->ehar_l, ®s->ehar_l);
929 writel(42, ®s->ersr); /* XXX should be random */
932 static void ioc3_start(struct ioc3_private *ip)
934 struct ioc3_ethregs *regs = ip->regs;
937 /* Now the rx ring base, consume & produce registers. */
938 ring = ioc3_map(ip->rxr_dma, PCI64_ATTR_PREC);
939 writel(ring >> 32, ®s->erbr_h);
940 writel(ring & 0xffffffff, ®s->erbr_l);
941 writel(ip->rx_ci << 3, ®s->ercir);
942 writel((ip->rx_pi << 3) | ERPIR_ARM, ®s->erpir);
944 ring = ioc3_map(ip->txr_dma, PCI64_ATTR_PREC);
946 ip->txqlen = 0; /* nothing queued */
948 /* Now the tx ring base, consume & produce registers. */
949 writel(ring >> 32, ®s->etbr_h);
950 writel(ring & 0xffffffff, ®s->etbr_l);
951 writel(ip->tx_pi << 7, ®s->etpir);
952 writel(ip->tx_ci << 7, ®s->etcir);
953 readl(®s->etcir); /* Flush */
955 ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |
956 EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN;
957 writel(ip->emcr, ®s->emcr);
958 writel(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
959 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
960 EISR_TXEXPLICIT | EISR_TXMEMERR, ®s->eier);
964 static inline void ioc3_stop(struct ioc3_private *ip)
966 struct ioc3_ethregs *regs = ip->regs;
968 writel(0, ®s->emcr); /* Shutup */
969 writel(0, ®s->eier); /* Disable interrupts */
970 readl(®s->eier); /* Flush */
973 static int ioc3_open(struct net_device *dev)
975 struct ioc3_private *ip = netdev_priv(dev);
977 if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) {
978 netdev_err(dev, "Can't get irq %d\n", dev->irq);
987 if (ioc3_alloc_rx_bufs(dev)) {
988 netdev_err(dev, "%s: rx buffer allocation failed\n", __func__);
994 netif_start_queue(dev);
998 static int ioc3_close(struct net_device *dev)
1000 struct ioc3_private *ip = netdev_priv(dev);
1002 del_timer_sync(&ip->ioc3_timer);
1004 netif_stop_queue(dev);
1007 free_irq(dev->irq, dev);
1009 ioc3_free_rx_bufs(ip);
1010 ioc3_clean_tx_ring(ip);
1015 /* MENET cards have four IOC3 chips, which are attached to two sets of
1016 * PCI slot resources each: the primary connections are on slots
1017 * 0..3 and the secondaries are on 4..7
1019 * All four ethernets are brought out to connectors; six serial ports
1020 * (a pair from each of the first three IOC3s) are brought out to
1021 * MiniDINs; all other subdevices are left swinging in the wind, leave
1025 static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int slot)
1027 struct pci_dev *dev = pci_get_slot(pdev->bus, PCI_DEVFN(slot, 0));
1031 if (dev->vendor == PCI_VENDOR_ID_SGI &&
1032 dev->device == PCI_DEVICE_ID_SGI_IOC3)
1040 static int ioc3_is_menet(struct pci_dev *pdev)
1042 return !pdev->bus->parent &&
1043 ioc3_adjacent_is_ioc3(pdev, 0) &&
1044 ioc3_adjacent_is_ioc3(pdev, 1) &&
1045 ioc3_adjacent_is_ioc3(pdev, 2);
1048 #ifdef CONFIG_SERIAL_8250
1049 /* Note about serial ports and consoles:
1050 * For console output, everyone uses the IOC3 UARTA (offset 0x178)
1051 * connected to the master node (look in ip27_setup_console() and
1052 * ip27prom_console_write()).
1054 * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port
1055 * addresses on a partitioned machine. Since we currently use the ioc3
1056 * serial ports, we use dynamic serial port discovery that the serial.c
1057 * driver uses for pci/pnp ports (there is an entry for the SGI ioc3
1058 * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater
1059 * than UARTB's, although UARTA on o200s has traditionally been known as
1060 * port 0. So, we just use one serial port from each ioc3 (since the
1061 * serial driver adds addresses to get to higher ports).
1063 * The first one to do a register_console becomes the preferred console
1064 * (if there is no kernel command line console= directive). /dev/console
1065 * (ie 5, 1) is then "aliased" into the device number returned by the
1066 * "device" routine referred to in this console structure
1067 * (ip27prom_console_dev).
1069 * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working
1070 * around ioc3 oddities in this respect.
1072 * The IOC3 serials use a 22MHz clock rate with an additional divider which
1073 * can be programmed in the SCR register if the DLAB bit is set.
1075 * Register to interrupt zero because we share the interrupt with
1076 * the serial driver which we don't properly support yet.
1078 * Can't use UPF_IOREMAP as the whole of IOC3 resources have already been
1081 static void ioc3_8250_register(struct ioc3_uartregs __iomem *uart)
1083 #define COSMISC_CONSTANT 6
1085 struct uart_8250_port port = {
1088 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
1091 .uartclk = (22000000 << 1) / COSMISC_CONSTANT,
1093 .membase = (unsigned char __iomem *)uart,
1094 .mapbase = (unsigned long)uart,
1099 lcr = readb(&uart->iu_lcr);
1100 writeb(lcr | UART_LCR_DLAB, &uart->iu_lcr);
1101 writeb(COSMISC_CONSTANT, &uart->iu_scr);
1102 writeb(lcr, &uart->iu_lcr);
1103 readb(&uart->iu_lcr);
1104 serial8250_register_8250_port(&port);
1107 static void ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3)
1111 /* We need to recognice and treat the fourth MENET serial as it
1112 * does not have an SuperIO chip attached to it, therefore attempting
1113 * to access it will result in bus errors. We call something an
1114 * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3
1115 * in it. This is paranoid but we want to avoid blowing up on a
1116 * showhorn PCI box that happens to have 4 IOC3 cards in it so it's
1117 * not paranoid enough ...
1119 if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3)
1122 /* Switch IOC3 to PIO mode. It probably already was but let's be
1125 writel(GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL, &ioc3->gpcr_s);
1126 readl(&ioc3->gpcr_s);
1127 writel(0, &ioc3->gppr[6]);
1128 readl(&ioc3->gppr[6]);
1129 writel(0, &ioc3->gppr[7]);
1130 readl(&ioc3->gppr[7]);
1131 writel(readl(&ioc3->port_a.sscr) & ~SSCR_DMA_EN, &ioc3->port_a.sscr);
1132 readl(&ioc3->port_a.sscr);
1133 writel(readl(&ioc3->port_b.sscr) & ~SSCR_DMA_EN, &ioc3->port_b.sscr);
1134 readl(&ioc3->port_b.sscr);
1135 /* Disable all SA/B interrupts except for SA/B_INT in SIO_IEC. */
1136 sio_iec = readl(&ioc3->sio_iec);
1137 sio_iec &= ~(SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL |
1138 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER |
1139 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS |
1140 SIO_IR_SA_TX_EXPLICIT | SIO_IR_SA_MEMERR);
1141 sio_iec |= SIO_IR_SA_INT;
1142 sio_iec &= ~(SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL |
1143 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER |
1144 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS |
1145 SIO_IR_SB_TX_EXPLICIT | SIO_IR_SB_MEMERR);
1146 sio_iec |= SIO_IR_SB_INT;
1147 writel(sio_iec, &ioc3->sio_iec);
1148 writel(0, &ioc3->port_a.sscr);
1149 writel(0, &ioc3->port_b.sscr);
1151 ioc3_8250_register(&ioc3->sregs.uarta);
1152 ioc3_8250_register(&ioc3->sregs.uartb);
1156 static const struct net_device_ops ioc3_netdev_ops = {
1157 .ndo_open = ioc3_open,
1158 .ndo_stop = ioc3_close,
1159 .ndo_start_xmit = ioc3_start_xmit,
1160 .ndo_tx_timeout = ioc3_timeout,
1161 .ndo_get_stats = ioc3_get_stats,
1162 .ndo_set_rx_mode = ioc3_set_multicast_list,
1163 .ndo_do_ioctl = ioc3_ioctl,
1164 .ndo_validate_addr = eth_validate_addr,
1165 .ndo_set_mac_address = ioc3_set_mac_address,
1168 static int ioc3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1170 unsigned int sw_physid1, sw_physid2;
1171 struct net_device *dev = NULL;
1172 struct ioc3_private *ip;
1174 unsigned long ioc3_base, ioc3_size;
1175 u32 vendor, model, rev;
1176 int err, pci_using_dac;
1178 /* Configure DMA attributes. */
1179 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1182 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1184 pr_err("%s: Unable to obtain 64 bit DMA for consistent allocations\n",
1189 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1191 pr_err("%s: No usable DMA configuration, aborting.\n",
1198 if (pci_enable_device(pdev))
1201 dev = alloc_etherdev(sizeof(struct ioc3_private));
1208 dev->features |= NETIF_F_HIGHDMA;
1210 err = pci_request_regions(pdev, "ioc3");
1214 SET_NETDEV_DEV(dev, &pdev->dev);
1216 ip = netdev_priv(dev);
1218 ip->dma_dev = &pdev->dev;
1220 dev->irq = pdev->irq;
1222 ioc3_base = pci_resource_start(pdev, 0);
1223 ioc3_size = pci_resource_len(pdev, 0);
1224 ioc3 = (struct ioc3 *)ioremap(ioc3_base, ioc3_size);
1226 pr_err("ioc3eth(%s): ioremap failed, goodbye.\n",
1231 ip->regs = &ioc3->eth;
1232 ip->ssram = ioc3->ssram;
1233 ip->all_regs = ioc3;
1235 #ifdef CONFIG_SERIAL_8250
1236 ioc3_serial_probe(pdev, ioc3);
1239 spin_lock_init(&ip->ioc3_lock);
1240 timer_setup(&ip->ioc3_timer, ioc3_timer, 0);
1244 /* Allocate rx ring. 4kb = 512 entries, must be 4kb aligned */
1245 ip->rxr = dma_alloc_coherent(ip->dma_dev, RX_RING_SIZE, &ip->rxr_dma,
1248 pr_err("ioc3-eth: rx ring allocation failed\n");
1253 /* Allocate tx rings. 16kb = 128 bufs, must be 16kb aligned */
1254 ip->txr = dma_alloc_coherent(ip->dma_dev, TX_RING_SIZE, &ip->txr_dma,
1257 pr_err("ioc3-eth: tx ring allocation failed\n");
1266 ip->mii.phy_id_mask = 0x1f;
1267 ip->mii.reg_num_mask = 0x1f;
1269 ip->mii.mdio_read = ioc3_mdio_read;
1270 ip->mii.mdio_write = ioc3_mdio_write;
1274 if (ip->mii.phy_id == -1) {
1275 pr_err("ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
1282 ioc3_ssram_disc(ip);
1285 /* The IOC3-specific entries in the device structure. */
1286 dev->watchdog_timeo = 5 * HZ;
1287 dev->netdev_ops = &ioc3_netdev_ops;
1288 dev->ethtool_ops = &ioc3_ethtool_ops;
1289 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
1290 dev->features = NETIF_F_IP_CSUM;
1292 sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
1293 sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
1295 err = register_netdev(dev);
1299 mii_check_media(&ip->mii, 1, 1);
1300 ioc3_setup_duplex(ip);
1302 vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
1303 model = (sw_physid2 >> 4) & 0x3f;
1304 rev = sw_physid2 & 0xf;
1305 netdev_info(dev, "Using PHY %d, vendor 0x%x, model %d, rev %d.\n",
1306 ip->mii.phy_id, vendor, model, rev);
1307 netdev_info(dev, "IOC3 SSRAM has %d kbyte.\n",
1308 ip->emcr & EMCR_BUFSIZ ? 128 : 64);
1313 del_timer_sync(&ip->ioc3_timer);
1315 dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr,
1318 dma_free_coherent(ip->dma_dev, TX_RING_SIZE, ip->txr,
1321 pci_release_regions(pdev);
1325 /* We should call pci_disable_device(pdev); here if the IOC3 wasn't
1326 * such a weird device ...
1332 static void ioc3_remove_one(struct pci_dev *pdev)
1334 struct net_device *dev = pci_get_drvdata(pdev);
1335 struct ioc3_private *ip = netdev_priv(dev);
1337 dma_free_coherent(ip->dma_dev, RX_RING_SIZE, ip->rxr, ip->rxr_dma);
1338 dma_free_coherent(ip->dma_dev, TX_RING_SIZE, ip->txr, ip->txr_dma);
1340 unregister_netdev(dev);
1341 del_timer_sync(&ip->ioc3_timer);
1343 iounmap(ip->all_regs);
1344 pci_release_regions(pdev);
1346 /* We should call pci_disable_device(pdev); here if the IOC3 wasn't
1347 * such a weird device ...
1351 static const struct pci_device_id ioc3_pci_tbl[] = {
1352 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
1355 MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl);
1357 static struct pci_driver ioc3_driver = {
1359 .id_table = ioc3_pci_tbl,
1360 .probe = ioc3_probe,
1361 .remove = ioc3_remove_one,
1364 static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1366 struct ioc3_private *ip = netdev_priv(dev);
1367 struct ioc3_etxd *desc;
1373 /* IOC3 has a fairly simple minded checksumming hardware which simply
1374 * adds up the 1's complement checksum for the entire packet and
1375 * inserts it at an offset which can be specified in the descriptor
1376 * into the transmit packet. This means we have to compensate for the
1377 * MAC header which should not be summed and the TCP/UDP pseudo headers
1380 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1381 const struct iphdr *ih = ip_hdr(skb);
1382 const int proto = ntohs(ih->protocol);
1387 /* The MAC header. skb->mac seem the logic approach
1388 * to find the MAC header - except it's a NULL pointer ...
1390 eh = (u16 *)skb->data;
1392 /* Sum up dest addr, src addr and protocol */
1393 ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6];
1395 /* Skip IP header; it's sum is always zero and was
1396 * already filled in by ip_output.c
1398 csum = csum_tcpudp_nofold(ih->saddr, ih->daddr,
1399 ih->tot_len - (ih->ihl << 2),
1400 proto, csum_fold(ehsum));
1402 csum = (csum & 0xffff) + (csum >> 16); /* Fold again */
1403 csum = (csum & 0xffff) + (csum >> 16);
1405 csoff = ETH_HLEN + (ih->ihl << 2);
1406 if (proto == IPPROTO_UDP) {
1407 csoff += offsetof(struct udphdr, check);
1408 udp_hdr(skb)->check = csum;
1410 if (proto == IPPROTO_TCP) {
1411 csoff += offsetof(struct tcphdr, check);
1412 tcp_hdr(skb)->check = csum;
1415 w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT);
1418 spin_lock_irq(&ip->ioc3_lock);
1420 data = (unsigned long)skb->data;
1423 produce = ip->tx_pi;
1424 desc = &ip->txr[produce];
1427 /* Short packet, let's copy it directly into the ring. */
1428 skb_copy_from_linear_data(skb, desc->data, skb->len);
1429 if (len < ETH_ZLEN) {
1430 /* Very short packet, pad with zeros at the end. */
1431 memset(desc->data + len, 0, ETH_ZLEN - len);
1434 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0);
1435 desc->bufcnt = cpu_to_be32(len);
1436 } else if ((data ^ (data + len - 1)) & 0x4000) {
1437 unsigned long b2 = (data | 0x3fffUL) + 1UL;
1438 unsigned long s1 = b2 - data;
1439 unsigned long s2 = data + len - b2;
1442 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE |
1443 ETXD_B1V | ETXD_B2V | w0);
1444 desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) |
1445 (s2 << ETXD_B2CNT_SHIFT));
1446 d1 = dma_map_single(ip->dma_dev, skb->data, s1, DMA_TO_DEVICE);
1447 if (dma_mapping_error(ip->dma_dev, d1))
1449 d2 = dma_map_single(ip->dma_dev, (void *)b2, s1, DMA_TO_DEVICE);
1450 if (dma_mapping_error(ip->dma_dev, d2)) {
1451 dma_unmap_single(ip->dma_dev, d1, len, DMA_TO_DEVICE);
1454 desc->p1 = cpu_to_be64(ioc3_map(d1, PCI64_ATTR_PREF));
1455 desc->p2 = cpu_to_be64(ioc3_map(d2, PCI64_ATTR_PREF));
1459 /* Normal sized packet that doesn't cross a page boundary. */
1460 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0);
1461 desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
1462 d = dma_map_single(ip->dma_dev, skb->data, len, DMA_TO_DEVICE);
1463 if (dma_mapping_error(ip->dma_dev, d))
1465 desc->p1 = cpu_to_be64(ioc3_map(d, PCI64_ATTR_PREF));
1468 mb(); /* make sure all descriptor changes are visible */
1470 ip->tx_skbs[produce] = skb; /* Remember skb */
1471 produce = (produce + 1) & TX_RING_MASK;
1472 ip->tx_pi = produce;
1473 writel(produce << 7, &ip->regs->etpir); /* Fire ... */
1477 if (ip->txqlen >= (TX_RING_ENTRIES - 1))
1478 netif_stop_queue(dev);
1480 spin_unlock_irq(&ip->ioc3_lock);
1482 return NETDEV_TX_OK;
1485 dev_kfree_skb_any(skb);
1486 dev->stats.tx_dropped++;
1488 spin_unlock_irq(&ip->ioc3_lock);
1490 return NETDEV_TX_OK;
1493 static void ioc3_timeout(struct net_device *dev)
1495 struct ioc3_private *ip = netdev_priv(dev);
1497 netdev_err(dev, "transmit timed out, resetting\n");
1499 spin_lock_irq(&ip->ioc3_lock);
1502 ioc3_free_rx_bufs(ip);
1503 ioc3_clean_tx_ring(ip);
1506 if (ioc3_alloc_rx_bufs(dev)) {
1507 netdev_err(dev, "%s: rx buffer allocation failed\n", __func__);
1508 spin_unlock_irq(&ip->ioc3_lock);
1515 spin_unlock_irq(&ip->ioc3_lock);
1517 netif_wake_queue(dev);
1520 /* Given a multicast ethernet address, this routine calculates the
1521 * address's bit index in the logical address filter mask
1523 static inline unsigned int ioc3_hash(const unsigned char *addr)
1525 unsigned int temp = 0;
1529 crc = ether_crc_le(ETH_ALEN, addr);
1531 crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */
1532 for (bits = 6; --bits >= 0; ) {
1534 temp |= (crc & 0x1);
1541 static void ioc3_get_drvinfo(struct net_device *dev,
1542 struct ethtool_drvinfo *info)
1544 struct ioc3_private *ip = netdev_priv(dev);
1546 strlcpy(info->driver, IOC3_NAME, sizeof(info->driver));
1547 strlcpy(info->version, IOC3_VERSION, sizeof(info->version));
1548 strlcpy(info->bus_info, pci_name(ip->pdev), sizeof(info->bus_info));
1551 static int ioc3_get_link_ksettings(struct net_device *dev,
1552 struct ethtool_link_ksettings *cmd)
1554 struct ioc3_private *ip = netdev_priv(dev);
1556 spin_lock_irq(&ip->ioc3_lock);
1557 mii_ethtool_get_link_ksettings(&ip->mii, cmd);
1558 spin_unlock_irq(&ip->ioc3_lock);
1563 static int ioc3_set_link_ksettings(struct net_device *dev,
1564 const struct ethtool_link_ksettings *cmd)
1566 struct ioc3_private *ip = netdev_priv(dev);
1569 spin_lock_irq(&ip->ioc3_lock);
1570 rc = mii_ethtool_set_link_ksettings(&ip->mii, cmd);
1571 spin_unlock_irq(&ip->ioc3_lock);
1576 static int ioc3_nway_reset(struct net_device *dev)
1578 struct ioc3_private *ip = netdev_priv(dev);
1581 spin_lock_irq(&ip->ioc3_lock);
1582 rc = mii_nway_restart(&ip->mii);
1583 spin_unlock_irq(&ip->ioc3_lock);
1588 static u32 ioc3_get_link(struct net_device *dev)
1590 struct ioc3_private *ip = netdev_priv(dev);
1593 spin_lock_irq(&ip->ioc3_lock);
1594 rc = mii_link_ok(&ip->mii);
1595 spin_unlock_irq(&ip->ioc3_lock);
1600 static const struct ethtool_ops ioc3_ethtool_ops = {
1601 .get_drvinfo = ioc3_get_drvinfo,
1602 .nway_reset = ioc3_nway_reset,
1603 .get_link = ioc3_get_link,
1604 .get_link_ksettings = ioc3_get_link_ksettings,
1605 .set_link_ksettings = ioc3_set_link_ksettings,
1608 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1610 struct ioc3_private *ip = netdev_priv(dev);
1613 spin_lock_irq(&ip->ioc3_lock);
1614 rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL);
1615 spin_unlock_irq(&ip->ioc3_lock);
1620 static void ioc3_set_multicast_list(struct net_device *dev)
1622 struct ioc3_private *ip = netdev_priv(dev);
1623 struct ioc3_ethregs *regs = ip->regs;
1624 struct netdev_hw_addr *ha;
1627 spin_lock_irq(&ip->ioc3_lock);
1629 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1630 ip->emcr |= EMCR_PROMISC;
1631 writel(ip->emcr, ®s->emcr);
1634 ip->emcr &= ~EMCR_PROMISC;
1635 writel(ip->emcr, ®s->emcr); /* Clear promiscuous. */
1638 if ((dev->flags & IFF_ALLMULTI) ||
1639 (netdev_mc_count(dev) > 64)) {
1640 /* Too many for hashing to make sense or we want all
1641 * multicast packets anyway, so skip computing all the
1642 * hashes and just accept all packets.
1644 ip->ehar_h = 0xffffffff;
1645 ip->ehar_l = 0xffffffff;
1647 netdev_for_each_mc_addr(ha, dev) {
1648 ehar |= (1UL << ioc3_hash(ha->addr));
1650 ip->ehar_h = ehar >> 32;
1651 ip->ehar_l = ehar & 0xffffffff;
1653 writel(ip->ehar_h, ®s->ehar_h);
1654 writel(ip->ehar_l, ®s->ehar_l);
1657 spin_unlock_irq(&ip->ioc3_lock);
1660 module_pci_driver(ioc3_driver);
1661 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1662 MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
1663 MODULE_LICENSE("GPL");