1 // SPDX-License-Identifier: GPL-2.0
2 /* Driver for SGI's IOC3 based Ethernet cards as found in the PCI card.
4 * Copyright (C) 1999, 2000, 01, 03, 06 Ralf Baechle
5 * Copyright (C) 1995, 1999, 2000, 2001 by Silicon Graphics, Inc.
8 * o IOC3 ASIC specification 4.51, 1996-04-18
9 * o IEEE 802.3 specification, 2000 edition
10 * o DP38840A Specification, National Semiconductor, March 1997
14 * o Handle allocation failures in ioc3_alloc_skb() more gracefully.
15 * o Handle allocation failures in ioc3_init_rings().
16 * o Use prefetching for large packets. What is a good lower limit for
18 * o We're probably allocating a bit too much memory.
19 * o Use hardware checksums.
20 * o Convert to using a IOC3 meta driver.
21 * o Which PHYs might possibly be attached to the IOC3 in real live,
22 * which workarounds are required for them? Do we ever have Lucent's?
23 * o For the 2.5 branch kill the mii-tool ioctls.
26 #define IOC3_NAME "ioc3-eth"
27 #define IOC3_VERSION "2.6.3-4"
29 #include <linux/delay.h>
30 #include <linux/kernel.h>
32 #include <linux/errno.h>
33 #include <linux/module.h>
34 #include <linux/pci.h>
35 #include <linux/crc32.h>
36 #include <linux/mii.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/gfp.h>
45 #ifdef CONFIG_SERIAL_8250
46 #include <linux/serial_core.h>
47 #include <linux/serial_8250.h>
48 #include <linux/serial_reg.h>
51 #include <linux/netdevice.h>
52 #include <linux/etherdevice.h>
53 #include <linux/ethtool.h>
54 #include <linux/skbuff.h>
57 #include <asm/byteorder.h>
58 #include <asm/pgtable.h>
59 #include <linux/uaccess.h>
60 #include <asm/sn/types.h>
61 #include <asm/sn/ioc3.h>
62 #include <asm/pci/bridge.h>
64 /* Number of RX buffers. This is tunable in the range of 16 <= x < 512.
65 * The value must be a power of two.
68 #define RX_RING_ENTRIES 512 /* fixed in hardware */
69 #define RX_RING_MASK (RX_RING_ENTRIES - 1)
71 /* 128 TX buffers (not tunable) */
72 #define TX_RING_ENTRIES 128
73 #define TX_RING_MASK (TX_RING_ENTRIES - 1)
75 #define ETCSR_FD ((17 << ETCSR_IPGR2_SHIFT) | (11 << ETCSR_IPGR1_SHIFT) | 21)
76 #define ETCSR_HD ((21 << ETCSR_IPGR2_SHIFT) | (21 << ETCSR_IPGR1_SHIFT) | 21)
78 /* Private per NIC data of the driver. */
80 struct ioc3_ethregs *regs;
81 struct ioc3 *all_regs;
83 unsigned long *rxr; /* pointer to receiver ring */
84 struct ioc3_etxd *txr;
85 struct sk_buff *rx_skbs[RX_RING_ENTRIES];
86 struct sk_buff *tx_skbs[TX_RING_ENTRIES];
87 int rx_ci; /* RX consumer index */
88 int rx_pi; /* RX producer index */
89 int tx_ci; /* TX consumer index */
90 int tx_pi; /* TX producer index */
92 u32 emcr, ehar_h, ehar_l;
94 struct mii_if_info mii;
96 struct net_device *dev;
99 /* Members used by autonegotiation */
100 struct timer_list ioc3_timer;
103 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
104 static void ioc3_set_multicast_list(struct net_device *dev);
105 static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev);
106 static void ioc3_timeout(struct net_device *dev);
107 static inline unsigned int ioc3_hash(const unsigned char *addr);
108 static inline void ioc3_stop(struct ioc3_private *ip);
109 static void ioc3_init(struct net_device *dev);
111 static const char ioc3_str[] = "IOC3 Ethernet";
112 static const struct ethtool_ops ioc3_ethtool_ops;
114 /* We use this to acquire receive skb's that we can DMA directly into. */
116 #define IOC3_CACHELINE 128UL
118 static inline unsigned long aligned_rx_skb_addr(unsigned long addr)
120 return (~addr + 1) & (IOC3_CACHELINE - 1UL);
123 static inline struct sk_buff *ioc3_alloc_skb(unsigned long length,
124 unsigned int gfp_mask)
128 skb = alloc_skb(length + IOC3_CACHELINE - 1, gfp_mask);
130 int offset = aligned_rx_skb_addr((unsigned long)skb->data);
133 skb_reserve(skb, offset);
139 static inline unsigned long ioc3_map(void *ptr, unsigned long vdev)
141 #ifdef CONFIG_SGI_IP27
142 vdev <<= 57; /* Shift to PCI64_ATTR_VIRTUAL */
144 return vdev | (0xaUL << PCI64_ATTR_TARG_SHFT) | PCI64_ATTR_PREF |
145 ((unsigned long)ptr & TO_PHYS_MASK);
147 return virt_to_bus(ptr);
151 /* BEWARE: The IOC3 documentation documents the size of rx buffers as
152 * 1644 while it's actually 1664. This one was nasty to track down ...
155 #define RX_BUF_ALLOC_SIZE (1664 + RX_OFFSET + IOC3_CACHELINE)
157 #define IOC3_SIZE 0x100000
159 static inline u32 mcr_pack(u32 pulse, u32 sample)
161 return (pulse << 10) | (sample << 2);
164 static int nic_wait(u32 __iomem *mcr)
175 static int nic_reset(u32 __iomem *mcr)
179 writel(mcr_pack(500, 65), mcr);
180 presence = nic_wait(mcr);
182 writel(mcr_pack(0, 500), mcr);
188 static inline int nic_read_bit(u32 __iomem *mcr)
192 writel(mcr_pack(6, 13), mcr);
193 result = nic_wait(mcr);
194 writel(mcr_pack(0, 100), mcr);
200 static inline void nic_write_bit(u32 __iomem *mcr, int bit)
203 writel(mcr_pack(6, 110), mcr);
205 writel(mcr_pack(80, 30), mcr);
210 /* Read a byte from an iButton device
212 static u32 nic_read_byte(u32 __iomem *mcr)
217 for (i = 0; i < 8; i++)
218 result = (result >> 1) | (nic_read_bit(mcr) << 7);
223 /* Write a byte to an iButton device
225 static void nic_write_byte(u32 __iomem *mcr, int byte)
229 for (i = 8; i; i--) {
233 nic_write_bit(mcr, bit);
237 static u64 nic_find(u32 __iomem *mcr, int *last)
239 int a, b, index, disc;
244 nic_write_byte(mcr, 0xf0);
246 /* Algorithm from ``Book of iButton Standards''. */
247 for (index = 0, disc = 0; index < 64; index++) {
248 a = nic_read_bit(mcr);
249 b = nic_read_bit(mcr);
252 pr_warn("NIC search failed (not fatal).\n");
258 if (index == *last) {
259 address |= 1UL << index;
260 } else if (index > *last) {
261 address &= ~(1UL << index);
263 } else if ((address & (1UL << index)) == 0) {
266 nic_write_bit(mcr, address & (1UL << index));
270 address |= 1UL << index;
272 address &= ~(1UL << index);
273 nic_write_bit(mcr, a);
283 static int nic_init(u32 __iomem *mcr)
285 const char *unknown = "unknown";
286 const char *type = unknown;
294 reg = nic_find(mcr, &save);
296 switch (reg & 0xff) {
302 /* Let the caller try again. */
311 nic_write_byte(mcr, 0x55);
312 for (i = 0; i < 8; i++)
313 nic_write_byte(mcr, (reg >> (i << 3)) & 0xff);
315 reg >>= 8; /* Shift out type. */
316 for (i = 0; i < 6; i++) {
317 serial[i] = reg & 0xff;
324 pr_info("Found %s NIC", type);
326 pr_cont(" registration number %pM, CRC %02x", serial, crc);
332 /* Read the NIC (Number-In-a-Can) device used to store the MAC address on
333 * SN0 / SN00 nodeboards and PCI cards.
335 static void ioc3_get_eaddr_nic(struct ioc3_private *ip)
337 u32 __iomem *mcr = &ip->all_regs->mcr;
338 int tries = 2; /* There may be some problem with the battery? */
342 writel(1 << 21, &ip->all_regs->gpcr_s);
351 pr_err("Failed to read MAC address\n");
356 nic_write_byte(mcr, 0xf0);
357 nic_write_byte(mcr, 0x00);
358 nic_write_byte(mcr, 0x00);
360 for (i = 13; i >= 0; i--)
361 nic[i] = nic_read_byte(mcr);
363 for (i = 2; i < 8; i++)
364 ip->dev->dev_addr[i - 2] = nic[i];
367 /* Ok, this is hosed by design. It's necessary to know what machine the
368 * NIC is in in order to know how to read the NIC address. We also have
369 * to know if it's a PCI card or a NIC in on the node board ...
371 static void ioc3_get_eaddr(struct ioc3_private *ip)
373 ioc3_get_eaddr_nic(ip);
375 pr_info("Ethernet address is %pM.\n", ip->dev->dev_addr);
378 static void __ioc3_set_mac_address(struct net_device *dev)
380 struct ioc3_private *ip = netdev_priv(dev);
382 writel((dev->dev_addr[5] << 8) |
385 writel((dev->dev_addr[3] << 24) |
386 (dev->dev_addr[2] << 16) |
387 (dev->dev_addr[1] << 8) |
392 static int ioc3_set_mac_address(struct net_device *dev, void *addr)
394 struct ioc3_private *ip = netdev_priv(dev);
395 struct sockaddr *sa = addr;
397 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
399 spin_lock_irq(&ip->ioc3_lock);
400 __ioc3_set_mac_address(dev);
401 spin_unlock_irq(&ip->ioc3_lock);
406 /* Caller must hold the ioc3_lock ever for MII readers. This is also
407 * used to protect the transmitter side but it's low contention.
409 static int ioc3_mdio_read(struct net_device *dev, int phy, int reg)
411 struct ioc3_private *ip = netdev_priv(dev);
412 struct ioc3_ethregs *regs = ip->regs;
414 while (readl(®s->micr) & MICR_BUSY)
416 writel((phy << MICR_PHYADDR_SHIFT) | reg | MICR_READTRIG,
418 while (readl(®s->micr) & MICR_BUSY)
421 return readl(®s->midr_r) & MIDR_DATA_MASK;
424 static void ioc3_mdio_write(struct net_device *dev, int phy, int reg, int data)
426 struct ioc3_private *ip = netdev_priv(dev);
427 struct ioc3_ethregs *regs = ip->regs;
429 while (readl(®s->micr) & MICR_BUSY)
431 writel(data, ®s->midr_w);
432 writel((phy << MICR_PHYADDR_SHIFT) | reg, ®s->micr);
433 while (readl(®s->micr) & MICR_BUSY)
437 static int ioc3_mii_init(struct ioc3_private *ip);
439 static struct net_device_stats *ioc3_get_stats(struct net_device *dev)
441 struct ioc3_private *ip = netdev_priv(dev);
442 struct ioc3_ethregs *regs = ip->regs;
444 dev->stats.collisions += readl(®s->etcdc) & ETCDC_COLLCNT_MASK;
448 static void ioc3_tcpudp_checksum(struct sk_buff *skb, u32 hwsum, int len)
450 struct ethhdr *eh = eth_hdr(skb);
457 /* Did hardware handle the checksum at all? The cases we can handle
460 * - TCP and UDP checksums of IPv4 only.
461 * - IPv6 would be doable but we keep that for later ...
462 * - Only unfragmented packets. Did somebody already tell you
463 * fragmentation is evil?
464 * - don't care about packet size. Worst case when processing a
465 * malformed packet we'll try to access the packet at ip header +
466 * 64 bytes which is still inside the skb. Even in the unlikely
467 * case where the checksum is right the higher layers will still
468 * drop the packet as appropriate.
470 if (eh->h_proto != htons(ETH_P_IP))
473 ih = (struct iphdr *)((char *)eh + ETH_HLEN);
474 if (ip_is_fragment(ih))
477 proto = ih->protocol;
478 if (proto != IPPROTO_TCP && proto != IPPROTO_UDP)
481 /* Same as tx - compute csum of pseudo header */
483 (ih->tot_len - (ih->ihl << 2)) +
484 htons((u16)ih->protocol) +
485 (ih->saddr >> 16) + (ih->saddr & 0xffff) +
486 (ih->daddr >> 16) + (ih->daddr & 0xffff);
488 /* Sum up ethernet dest addr, src addr and protocol */
490 ehsum = ew[0] + ew[1] + ew[2] + ew[3] + ew[4] + ew[5] + ew[6];
492 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
493 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
495 csum += 0xffff ^ ehsum;
497 /* In the next step we also subtract the 1's complement
498 * checksum of the trailing ethernet CRC.
500 cp = (char *)eh + len; /* points at trailing CRC */
502 csum += 0xffff ^ (u16)((cp[1] << 8) | cp[0]);
503 csum += 0xffff ^ (u16)((cp[3] << 8) | cp[2]);
505 csum += 0xffff ^ (u16)((cp[0] << 8) | cp[1]);
506 csum += 0xffff ^ (u16)((cp[2] << 8) | cp[3]);
509 csum = (csum & 0xffff) + (csum >> 16);
510 csum = (csum & 0xffff) + (csum >> 16);
513 skb->ip_summed = CHECKSUM_UNNECESSARY;
516 static inline void ioc3_rx(struct net_device *dev)
518 struct ioc3_private *ip = netdev_priv(dev);
519 struct sk_buff *skb, *new_skb;
520 int rx_entry, n_entry, len;
521 struct ioc3_erxbuf *rxb;
525 rxr = ip->rxr; /* Ring base */
526 rx_entry = ip->rx_ci; /* RX consume index */
529 skb = ip->rx_skbs[rx_entry];
530 rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);
531 w0 = be32_to_cpu(rxb->w0);
533 while (w0 & ERXBUF_V) {
534 err = be32_to_cpu(rxb->err); /* It's valid ... */
535 if (err & ERXBUF_GOODPKT) {
536 len = ((w0 >> ERXBUF_BYTECNT_SHIFT) & 0x7ff) - 4;
538 skb->protocol = eth_type_trans(skb, dev);
540 new_skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
542 /* Ouch, drop packet and just recycle packet
543 * to keep the ring filled.
545 dev->stats.rx_dropped++;
550 if (likely(dev->features & NETIF_F_RXCSUM))
551 ioc3_tcpudp_checksum(skb,
552 w0 & ERXBUF_IPCKSUM_MASK,
557 ip->rx_skbs[rx_entry] = NULL; /* Poison */
559 /* Because we reserve afterwards. */
560 skb_put(new_skb, (1664 + RX_OFFSET));
561 rxb = (struct ioc3_erxbuf *)new_skb->data;
562 skb_reserve(new_skb, RX_OFFSET);
564 dev->stats.rx_packets++; /* Statistics */
565 dev->stats.rx_bytes += len;
567 /* The frame is invalid and the skb never
568 * reached the network layer so we can just
572 dev->stats.rx_errors++;
574 if (err & ERXBUF_CRCERR) /* Statistics */
575 dev->stats.rx_crc_errors++;
576 if (err & ERXBUF_FRAMERR)
577 dev->stats.rx_frame_errors++;
579 ip->rx_skbs[n_entry] = new_skb;
580 rxr[n_entry] = cpu_to_be64(ioc3_map(rxb, 1));
581 rxb->w0 = 0; /* Clear valid flag */
582 n_entry = (n_entry + 1) & RX_RING_MASK; /* Update erpir */
584 /* Now go on to the next ring entry. */
585 rx_entry = (rx_entry + 1) & RX_RING_MASK;
586 skb = ip->rx_skbs[rx_entry];
587 rxb = (struct ioc3_erxbuf *)(skb->data - RX_OFFSET);
588 w0 = be32_to_cpu(rxb->w0);
590 writel((n_entry << 3) | ERPIR_ARM, &ip->regs->erpir);
592 ip->rx_ci = rx_entry;
595 static inline void ioc3_tx(struct net_device *dev)
597 struct ioc3_private *ip = netdev_priv(dev);
598 struct ioc3_ethregs *regs = ip->regs;
599 unsigned long packets, bytes;
600 int tx_entry, o_entry;
604 spin_lock(&ip->ioc3_lock);
605 etcir = readl(®s->etcir);
607 tx_entry = (etcir >> 7) & TX_RING_MASK;
612 while (o_entry != tx_entry) {
614 skb = ip->tx_skbs[o_entry];
616 dev_consume_skb_irq(skb);
617 ip->tx_skbs[o_entry] = NULL;
619 o_entry = (o_entry + 1) & TX_RING_MASK; /* Next */
621 etcir = readl(®s->etcir); /* More pkts sent? */
622 tx_entry = (etcir >> 7) & TX_RING_MASK;
625 dev->stats.tx_packets += packets;
626 dev->stats.tx_bytes += bytes;
627 ip->txqlen -= packets;
629 if (netif_queue_stopped(dev) && ip->txqlen < TX_RING_ENTRIES)
630 netif_wake_queue(dev);
633 spin_unlock(&ip->ioc3_lock);
636 /* Deal with fatal IOC3 errors. This condition might be caused by a hard or
637 * software problems, so we should try to recover
638 * more gracefully if this ever happens. In theory we might be flooded
639 * with such error interrupts if something really goes wrong, so we might
640 * also consider to take the interface down.
642 static void ioc3_error(struct net_device *dev, u32 eisr)
644 struct ioc3_private *ip = netdev_priv(dev);
646 spin_lock(&ip->ioc3_lock);
648 if (eisr & EISR_RXOFLO)
649 net_err_ratelimited("%s: RX overflow.\n", dev->name);
650 if (eisr & EISR_RXBUFOFLO)
651 net_err_ratelimited("%s: RX buffer overflow.\n", dev->name);
652 if (eisr & EISR_RXMEMERR)
653 net_err_ratelimited("%s: RX PCI error.\n", dev->name);
654 if (eisr & EISR_RXPARERR)
655 net_err_ratelimited("%s: RX SSRAM parity error.\n", dev->name);
656 if (eisr & EISR_TXBUFUFLO)
657 net_err_ratelimited("%s: TX buffer underflow.\n", dev->name);
658 if (eisr & EISR_TXMEMERR)
659 net_err_ratelimited("%s: TX PCI error.\n", dev->name);
665 netif_wake_queue(dev);
667 spin_unlock(&ip->ioc3_lock);
670 /* The interrupt handler does all of the Rx thread work and cleans up
671 * after the Tx thread.
673 static irqreturn_t ioc3_interrupt(int irq, void *dev_id)
675 struct ioc3_private *ip = netdev_priv(dev_id);
676 struct ioc3_ethregs *regs = ip->regs;
679 eisr = readl(®s->eisr);
680 writel(eisr, ®s->eisr);
681 readl(®s->eisr); /* Flush */
683 if (eisr & (EISR_RXOFLO | EISR_RXBUFOFLO | EISR_RXMEMERR |
684 EISR_RXPARERR | EISR_TXBUFUFLO | EISR_TXMEMERR))
685 ioc3_error(dev_id, eisr);
686 if (eisr & EISR_RXTIMERINT)
688 if (eisr & EISR_TXEXPLICIT)
694 static inline void ioc3_setup_duplex(struct ioc3_private *ip)
696 struct ioc3_ethregs *regs = ip->regs;
698 if (ip->mii.full_duplex) {
699 writel(ETCSR_FD, ®s->etcsr);
700 ip->emcr |= EMCR_DUPLEX;
702 writel(ETCSR_HD, ®s->etcsr);
703 ip->emcr &= ~EMCR_DUPLEX;
705 writel(ip->emcr, ®s->emcr);
708 static void ioc3_timer(struct timer_list *t)
710 struct ioc3_private *ip = from_timer(ip, t, ioc3_timer);
712 /* Print the link status if it has changed */
713 mii_check_media(&ip->mii, 1, 0);
714 ioc3_setup_duplex(ip);
716 ip->ioc3_timer.expires = jiffies + ((12 * HZ) / 10); /* 1.2s */
717 add_timer(&ip->ioc3_timer);
720 /* Try to find a PHY. There is no apparent relation between the MII addresses
721 * in the SGI documentation and what we find in reality, so we simply probe
722 * for the PHY. It seems IOC3 PHYs usually live on address 31. One of my
723 * onboard IOC3s has the special oddity that probing doesn't seem to find it
724 * yet the interface seems to work fine, so if probing fails we for now will
725 * simply default to PHY 31 instead of bailing out.
727 static int ioc3_mii_init(struct ioc3_private *ip)
729 int ioc3_phy_workaround = 1;
730 int i, found = 0, res = 0;
733 for (i = 0; i < 32; i++) {
734 word = ioc3_mdio_read(ip->dev, i, MII_PHYSID1);
736 if (word != 0xffff && word != 0x0000) {
738 break; /* Found a PHY */
743 if (ioc3_phy_workaround) {
758 static void ioc3_mii_start(struct ioc3_private *ip)
760 ip->ioc3_timer.expires = jiffies + (12 * HZ) / 10; /* 1.2 sec. */
761 add_timer(&ip->ioc3_timer);
764 static inline void ioc3_clean_tx_ring(struct ioc3_private *ip)
769 for (i = 0; i < TX_RING_ENTRIES; i++) {
770 skb = ip->tx_skbs[i];
772 ip->tx_skbs[i] = NULL;
773 dev_kfree_skb_any(skb);
781 static void ioc3_free_rx_bufs(struct ioc3_private *ip)
783 int rx_entry, n_entry;
786 rx_entry = ip->rx_pi;
788 while (n_entry != rx_entry) {
789 dev_kfree_skb_any(ip->rx_skbs[n_entry]);
791 n_entry = (n_entry + 1) & RX_RING_MASK;
795 static void ioc3_alloc_rx_bufs(struct net_device *dev)
797 struct ioc3_private *ip = netdev_priv(dev);
798 struct ioc3_erxbuf *rxb;
801 /* Now the rx buffers. The RX ring may be larger but
802 * we only allocate 16 buffers for now. Need to tune
803 * this for performance and memory later.
805 for (i = 0; i < RX_BUFFS; i++) {
808 skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
810 show_free_areas(0, NULL);
814 ip->rx_skbs[i] = skb;
816 /* Because we reserve afterwards. */
817 skb_put(skb, (1664 + RX_OFFSET));
818 rxb = (struct ioc3_erxbuf *)skb->data;
819 rxb->w0 = 0; /* Clear valid flag */
820 ip->rxr[i] = cpu_to_be64(ioc3_map(rxb, 1));
821 skb_reserve(skb, RX_OFFSET);
824 ip->rx_pi = RX_BUFFS;
827 static void ioc3_init_rings(struct net_device *dev)
829 struct ioc3_private *ip = netdev_priv(dev);
830 struct ioc3_ethregs *regs = ip->regs;
833 ioc3_free_rx_bufs(ip);
834 ioc3_alloc_rx_bufs(dev);
836 ioc3_clean_tx_ring(ip);
838 /* Now the rx ring base, consume & produce registers. */
839 ring = ioc3_map(ip->rxr, 0);
840 writel(ring >> 32, ®s->erbr_h);
841 writel(ring & 0xffffffff, ®s->erbr_l);
842 writel(ip->rx_ci << 3, ®s->ercir);
843 writel((ip->rx_pi << 3) | ERPIR_ARM, ®s->erpir);
845 ring = ioc3_map(ip->txr, 0);
847 ip->txqlen = 0; /* nothing queued */
849 /* Now the tx ring base, consume & produce registers. */
850 writel(ring >> 32, ®s->etbr_h);
851 writel(ring & 0xffffffff, ®s->etbr_l);
852 writel(ip->tx_pi << 7, ®s->etpir);
853 writel(ip->tx_ci << 7, ®s->etcir);
854 readl(®s->etcir); /* Flush */
857 static inline void ioc3_ssram_disc(struct ioc3_private *ip)
859 struct ioc3_ethregs *regs = ip->regs;
860 u32 *ssram0 = &ip->ssram[0x0000];
861 u32 *ssram1 = &ip->ssram[0x4000];
862 u32 pattern = 0x5555;
864 /* Assume the larger size SSRAM and enable parity checking */
865 writel(readl(®s->emcr) | (EMCR_BUFSIZ | EMCR_RAMPAR), ®s->emcr);
866 readl(®s->emcr); /* Flush */
868 writel(pattern, ssram0);
869 writel(~pattern & IOC3_SSRAM_DM, ssram1);
871 if ((readl(ssram0) & IOC3_SSRAM_DM) != pattern ||
872 (readl(ssram1) & IOC3_SSRAM_DM) != (~pattern & IOC3_SSRAM_DM)) {
873 /* set ssram size to 64 KB */
874 ip->emcr |= EMCR_RAMPAR;
875 writel(readl(®s->emcr) & ~EMCR_BUFSIZ, ®s->emcr);
877 ip->emcr |= EMCR_BUFSIZ | EMCR_RAMPAR;
881 static void ioc3_init(struct net_device *dev)
883 struct ioc3_private *ip = netdev_priv(dev);
884 struct ioc3_ethregs *regs = ip->regs;
886 del_timer_sync(&ip->ioc3_timer); /* Kill if running */
888 writel(EMCR_RST, ®s->emcr); /* Reset */
889 readl(®s->emcr); /* Flush WB */
890 udelay(4); /* Give it time ... */
891 writel(0, ®s->emcr);
895 #ifdef CONFIG_SGI_IP27
896 /* Barrier on last store */
897 writel(PCI64_ATTR_BAR >> 32, ®s->erbar);
899 /* Let PCI API get it right */
900 writel(0, ®s->erbar);
902 readl(®s->etcdc); /* Clear on read */
903 writel(15, ®s->ercsr); /* RX low watermark */
904 writel(0, ®s->ertr); /* Interrupt immediately */
905 __ioc3_set_mac_address(dev);
906 writel(ip->ehar_h, ®s->ehar_h);
907 writel(ip->ehar_l, ®s->ehar_l);
908 writel(42, ®s->ersr); /* XXX should be random */
910 ioc3_init_rings(dev);
912 ip->emcr |= ((RX_OFFSET / 2) << EMCR_RXOFF_SHIFT) | EMCR_TXDMAEN |
913 EMCR_TXEN | EMCR_RXDMAEN | EMCR_RXEN | EMCR_PADEN;
914 writel(ip->emcr, ®s->emcr);
915 writel(EISR_RXTIMERINT | EISR_RXOFLO | EISR_RXBUFOFLO |
916 EISR_RXMEMERR | EISR_RXPARERR | EISR_TXBUFUFLO |
917 EISR_TXEXPLICIT | EISR_TXMEMERR, ®s->eier);
921 static inline void ioc3_stop(struct ioc3_private *ip)
923 struct ioc3_ethregs *regs = ip->regs;
925 writel(0, ®s->emcr); /* Shutup */
926 writel(0, ®s->eier); /* Disable interrupts */
927 readl(®s->eier); /* Flush */
930 static int ioc3_open(struct net_device *dev)
932 struct ioc3_private *ip = netdev_priv(dev);
934 if (request_irq(dev->irq, ioc3_interrupt, IRQF_SHARED, ioc3_str, dev)) {
935 netdev_err(dev, "Can't get irq %d\n", dev->irq);
945 netif_start_queue(dev);
949 static int ioc3_close(struct net_device *dev)
951 struct ioc3_private *ip = netdev_priv(dev);
953 del_timer_sync(&ip->ioc3_timer);
955 netif_stop_queue(dev);
958 free_irq(dev->irq, dev);
960 ioc3_free_rx_bufs(ip);
961 ioc3_clean_tx_ring(ip);
966 /* MENET cards have four IOC3 chips, which are attached to two sets of
967 * PCI slot resources each: the primary connections are on slots
968 * 0..3 and the secondaries are on 4..7
970 * All four ethernets are brought out to connectors; six serial ports
971 * (a pair from each of the first three IOC3s) are brought out to
972 * MiniDINs; all other subdevices are left swinging in the wind, leave
976 static int ioc3_adjacent_is_ioc3(struct pci_dev *pdev, int slot)
978 struct pci_dev *dev = pci_get_slot(pdev->bus, PCI_DEVFN(slot, 0));
982 if (dev->vendor == PCI_VENDOR_ID_SGI &&
983 dev->device == PCI_DEVICE_ID_SGI_IOC3)
991 static int ioc3_is_menet(struct pci_dev *pdev)
993 return !pdev->bus->parent &&
994 ioc3_adjacent_is_ioc3(pdev, 0) &&
995 ioc3_adjacent_is_ioc3(pdev, 1) &&
996 ioc3_adjacent_is_ioc3(pdev, 2);
999 #ifdef CONFIG_SERIAL_8250
1000 /* Note about serial ports and consoles:
1001 * For console output, everyone uses the IOC3 UARTA (offset 0x178)
1002 * connected to the master node (look in ip27_setup_console() and
1003 * ip27prom_console_write()).
1005 * For serial (/dev/ttyS0 etc), we can not have hardcoded serial port
1006 * addresses on a partitioned machine. Since we currently use the ioc3
1007 * serial ports, we use dynamic serial port discovery that the serial.c
1008 * driver uses for pci/pnp ports (there is an entry for the SGI ioc3
1009 * boards in pci_boards[]). Unfortunately, UARTA's pio address is greater
1010 * than UARTB's, although UARTA on o200s has traditionally been known as
1011 * port 0. So, we just use one serial port from each ioc3 (since the
1012 * serial driver adds addresses to get to higher ports).
1014 * The first one to do a register_console becomes the preferred console
1015 * (if there is no kernel command line console= directive). /dev/console
1016 * (ie 5, 1) is then "aliased" into the device number returned by the
1017 * "device" routine referred to in this console structure
1018 * (ip27prom_console_dev).
1020 * Also look in ip27-pci.c:pci_fixup_ioc3() for some comments on working
1021 * around ioc3 oddities in this respect.
1023 * The IOC3 serials use a 22MHz clock rate with an additional divider which
1024 * can be programmed in the SCR register if the DLAB bit is set.
1026 * Register to interrupt zero because we share the interrupt with
1027 * the serial driver which we don't properly support yet.
1029 * Can't use UPF_IOREMAP as the whole of IOC3 resources have already been
1032 static void ioc3_8250_register(struct ioc3_uartregs __iomem *uart)
1034 #define COSMISC_CONSTANT 6
1036 struct uart_8250_port port = {
1039 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
1042 .uartclk = (22000000 << 1) / COSMISC_CONSTANT,
1044 .membase = (unsigned char __iomem *)uart,
1045 .mapbase = (unsigned long)uart,
1050 lcr = readb(&uart->iu_lcr);
1051 writeb(lcr | UART_LCR_DLAB, &uart->iu_lcr);
1052 writeb(COSMISC_CONSTANT, &uart->iu_scr);
1053 writeb(lcr, &uart->iu_lcr);
1054 readb(&uart->iu_lcr);
1055 serial8250_register_8250_port(&port);
1058 static void ioc3_serial_probe(struct pci_dev *pdev, struct ioc3 *ioc3)
1062 /* We need to recognice and treat the fourth MENET serial as it
1063 * does not have an SuperIO chip attached to it, therefore attempting
1064 * to access it will result in bus errors. We call something an
1065 * MENET if PCI slot 0, 1, 2 and 3 of a master PCI bus all have an IOC3
1066 * in it. This is paranoid but we want to avoid blowing up on a
1067 * showhorn PCI box that happens to have 4 IOC3 cards in it so it's
1068 * not paranoid enough ...
1070 if (ioc3_is_menet(pdev) && PCI_SLOT(pdev->devfn) == 3)
1073 /* Switch IOC3 to PIO mode. It probably already was but let's be
1076 writel(GPCR_UARTA_MODESEL | GPCR_UARTB_MODESEL, &ioc3->gpcr_s);
1077 readl(&ioc3->gpcr_s);
1078 writel(0, &ioc3->gppr[6]);
1079 readl(&ioc3->gppr[6]);
1080 writel(0, &ioc3->gppr[7]);
1081 readl(&ioc3->gppr[7]);
1082 writel(readl(&ioc3->port_a.sscr) & ~SSCR_DMA_EN, &ioc3->port_a.sscr);
1083 readl(&ioc3->port_a.sscr);
1084 writel(readl(&ioc3->port_b.sscr) & ~SSCR_DMA_EN, &ioc3->port_b.sscr);
1085 readl(&ioc3->port_b.sscr);
1086 /* Disable all SA/B interrupts except for SA/B_INT in SIO_IEC. */
1087 sio_iec = readl(&ioc3->sio_iec);
1088 sio_iec &= ~(SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL |
1089 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER |
1090 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS |
1091 SIO_IR_SA_TX_EXPLICIT | SIO_IR_SA_MEMERR);
1092 sio_iec |= SIO_IR_SA_INT;
1093 sio_iec &= ~(SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL |
1094 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER |
1095 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS |
1096 SIO_IR_SB_TX_EXPLICIT | SIO_IR_SB_MEMERR);
1097 sio_iec |= SIO_IR_SB_INT;
1098 writel(sio_iec, &ioc3->sio_iec);
1099 writel(0, &ioc3->port_a.sscr);
1100 writel(0, &ioc3->port_b.sscr);
1102 ioc3_8250_register(&ioc3->sregs.uarta);
1103 ioc3_8250_register(&ioc3->sregs.uartb);
1107 static const struct net_device_ops ioc3_netdev_ops = {
1108 .ndo_open = ioc3_open,
1109 .ndo_stop = ioc3_close,
1110 .ndo_start_xmit = ioc3_start_xmit,
1111 .ndo_tx_timeout = ioc3_timeout,
1112 .ndo_get_stats = ioc3_get_stats,
1113 .ndo_set_rx_mode = ioc3_set_multicast_list,
1114 .ndo_do_ioctl = ioc3_ioctl,
1115 .ndo_validate_addr = eth_validate_addr,
1116 .ndo_set_mac_address = ioc3_set_mac_address,
1119 static int ioc3_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1121 unsigned int sw_physid1, sw_physid2;
1122 struct net_device *dev = NULL;
1123 struct ioc3_private *ip;
1125 unsigned long ioc3_base, ioc3_size;
1126 u32 vendor, model, rev;
1127 int err, pci_using_dac;
1129 /* Configure DMA attributes. */
1130 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1133 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1135 pr_err("%s: Unable to obtain 64 bit DMA for consistent allocations\n",
1140 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1142 pr_err("%s: No usable DMA configuration, aborting.\n",
1149 if (pci_enable_device(pdev))
1152 dev = alloc_etherdev(sizeof(struct ioc3_private));
1159 dev->features |= NETIF_F_HIGHDMA;
1161 err = pci_request_regions(pdev, "ioc3");
1165 SET_NETDEV_DEV(dev, &pdev->dev);
1167 ip = netdev_priv(dev);
1170 dev->irq = pdev->irq;
1172 ioc3_base = pci_resource_start(pdev, 0);
1173 ioc3_size = pci_resource_len(pdev, 0);
1174 ioc3 = (struct ioc3 *)ioremap(ioc3_base, ioc3_size);
1176 pr_err("ioc3eth(%s): ioremap failed, goodbye.\n",
1181 ip->regs = &ioc3->eth;
1182 ip->ssram = ioc3->ssram;
1183 ip->all_regs = ioc3;
1185 #ifdef CONFIG_SERIAL_8250
1186 ioc3_serial_probe(pdev, ioc3);
1189 spin_lock_init(&ip->ioc3_lock);
1190 timer_setup(&ip->ioc3_timer, ioc3_timer, 0);
1194 /* Allocate rx ring. 4kb = 512 entries, must be 4kb aligned */
1195 ip->rxr = (unsigned long *)get_zeroed_page(GFP_KERNEL);
1197 pr_err("ioc3-eth: rx ring allocation failed\n");
1202 /* Allocate tx rings. 16kb = 128 bufs, must be 16kb aligned */
1203 ip->txr = (struct ioc3_etxd *)__get_free_pages(GFP_KERNEL, 2);
1205 pr_err("ioc3-eth: tx ring allocation failed\n");
1214 ip->mii.phy_id_mask = 0x1f;
1215 ip->mii.reg_num_mask = 0x1f;
1217 ip->mii.mdio_read = ioc3_mdio_read;
1218 ip->mii.mdio_write = ioc3_mdio_write;
1222 if (ip->mii.phy_id == -1) {
1223 pr_err("ioc3-eth(%s): Didn't find a PHY, goodbye.\n",
1230 ioc3_ssram_disc(ip);
1233 /* The IOC3-specific entries in the device structure. */
1234 dev->watchdog_timeo = 5 * HZ;
1235 dev->netdev_ops = &ioc3_netdev_ops;
1236 dev->ethtool_ops = &ioc3_ethtool_ops;
1237 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
1238 dev->features = NETIF_F_IP_CSUM;
1240 sw_physid1 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID1);
1241 sw_physid2 = ioc3_mdio_read(dev, ip->mii.phy_id, MII_PHYSID2);
1243 err = register_netdev(dev);
1247 mii_check_media(&ip->mii, 1, 1);
1248 ioc3_setup_duplex(ip);
1250 vendor = (sw_physid1 << 12) | (sw_physid2 >> 4);
1251 model = (sw_physid2 >> 4) & 0x3f;
1252 rev = sw_physid2 & 0xf;
1253 netdev_info(dev, "Using PHY %d, vendor 0x%x, model %d, rev %d.\n",
1254 ip->mii.phy_id, vendor, model, rev);
1255 netdev_info(dev, "IOC3 SSRAM has %d kbyte.\n",
1256 ip->emcr & EMCR_BUFSIZ ? 128 : 64);
1262 del_timer_sync(&ip->ioc3_timer);
1263 ioc3_free_rx_bufs(ip);
1265 free_page((unsigned long)ip->rxr);
1267 free_pages((unsigned long)ip->txr, 2);
1269 pci_release_regions(pdev);
1273 /* We should call pci_disable_device(pdev); here if the IOC3 wasn't
1274 * such a weird device ...
1280 static void ioc3_remove_one(struct pci_dev *pdev)
1282 struct net_device *dev = pci_get_drvdata(pdev);
1283 struct ioc3_private *ip = netdev_priv(dev);
1285 free_page((unsigned long)ip->rxr);
1286 free_pages((unsigned long)ip->txr, 2);
1288 unregister_netdev(dev);
1289 del_timer_sync(&ip->ioc3_timer);
1291 iounmap(ip->all_regs);
1292 pci_release_regions(pdev);
1294 /* We should call pci_disable_device(pdev); here if the IOC3 wasn't
1295 * such a weird device ...
1299 static const struct pci_device_id ioc3_pci_tbl[] = {
1300 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3, PCI_ANY_ID, PCI_ANY_ID },
1303 MODULE_DEVICE_TABLE(pci, ioc3_pci_tbl);
1305 static struct pci_driver ioc3_driver = {
1307 .id_table = ioc3_pci_tbl,
1308 .probe = ioc3_probe,
1309 .remove = ioc3_remove_one,
1312 static netdev_tx_t ioc3_start_xmit(struct sk_buff *skb, struct net_device *dev)
1314 struct ioc3_private *ip = netdev_priv(dev);
1315 struct ioc3_etxd *desc;
1321 /* IOC3 has a fairly simple minded checksumming hardware which simply
1322 * adds up the 1's complement checksum for the entire packet and
1323 * inserts it at an offset which can be specified in the descriptor
1324 * into the transmit packet. This means we have to compensate for the
1325 * MAC header which should not be summed and the TCP/UDP pseudo headers
1328 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1329 const struct iphdr *ih = ip_hdr(skb);
1330 const int proto = ntohs(ih->protocol);
1335 /* The MAC header. skb->mac seem the logic approach
1336 * to find the MAC header - except it's a NULL pointer ...
1338 eh = (u16 *)skb->data;
1340 /* Sum up dest addr, src addr and protocol */
1341 ehsum = eh[0] + eh[1] + eh[2] + eh[3] + eh[4] + eh[5] + eh[6];
1343 /* Fold ehsum. can't use csum_fold which negates also ... */
1344 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1345 ehsum = (ehsum & 0xffff) + (ehsum >> 16);
1347 /* Skip IP header; it's sum is always zero and was
1348 * already filled in by ip_output.c
1350 csum = csum_tcpudp_nofold(ih->saddr, ih->daddr,
1351 ih->tot_len - (ih->ihl << 2),
1352 proto, 0xffff ^ ehsum);
1354 csum = (csum & 0xffff) + (csum >> 16); /* Fold again */
1355 csum = (csum & 0xffff) + (csum >> 16);
1357 csoff = ETH_HLEN + (ih->ihl << 2);
1358 if (proto == IPPROTO_UDP) {
1359 csoff += offsetof(struct udphdr, check);
1360 udp_hdr(skb)->check = csum;
1362 if (proto == IPPROTO_TCP) {
1363 csoff += offsetof(struct tcphdr, check);
1364 tcp_hdr(skb)->check = csum;
1367 w0 = ETXD_DOCHECKSUM | (csoff << ETXD_CHKOFF_SHIFT);
1370 spin_lock_irq(&ip->ioc3_lock);
1372 data = (unsigned long)skb->data;
1375 produce = ip->tx_pi;
1376 desc = &ip->txr[produce];
1379 /* Short packet, let's copy it directly into the ring. */
1380 skb_copy_from_linear_data(skb, desc->data, skb->len);
1381 if (len < ETH_ZLEN) {
1382 /* Very short packet, pad with zeros at the end. */
1383 memset(desc->data + len, 0, ETH_ZLEN - len);
1386 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_D0V | w0);
1387 desc->bufcnt = cpu_to_be32(len);
1388 } else if ((data ^ (data + len - 1)) & 0x4000) {
1389 unsigned long b2 = (data | 0x3fffUL) + 1UL;
1390 unsigned long s1 = b2 - data;
1391 unsigned long s2 = data + len - b2;
1393 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE |
1394 ETXD_B1V | ETXD_B2V | w0);
1395 desc->bufcnt = cpu_to_be32((s1 << ETXD_B1CNT_SHIFT) |
1396 (s2 << ETXD_B2CNT_SHIFT));
1397 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1398 desc->p2 = cpu_to_be64(ioc3_map((void *)b2, 1));
1400 /* Normal sized packet that doesn't cross a page boundary. */
1401 desc->cmd = cpu_to_be32(len | ETXD_INTWHENDONE | ETXD_B1V | w0);
1402 desc->bufcnt = cpu_to_be32(len << ETXD_B1CNT_SHIFT);
1403 desc->p1 = cpu_to_be64(ioc3_map(skb->data, 1));
1406 mb(); /* make sure all descriptor changes are visible */
1408 ip->tx_skbs[produce] = skb; /* Remember skb */
1409 produce = (produce + 1) & TX_RING_MASK;
1410 ip->tx_pi = produce;
1411 writel(produce << 7, &ip->regs->etpir); /* Fire ... */
1415 if (ip->txqlen >= (TX_RING_ENTRIES - 1))
1416 netif_stop_queue(dev);
1418 spin_unlock_irq(&ip->ioc3_lock);
1420 return NETDEV_TX_OK;
1423 static void ioc3_timeout(struct net_device *dev)
1425 struct ioc3_private *ip = netdev_priv(dev);
1427 netdev_err(dev, "transmit timed out, resetting\n");
1429 spin_lock_irq(&ip->ioc3_lock);
1436 spin_unlock_irq(&ip->ioc3_lock);
1438 netif_wake_queue(dev);
1441 /* Given a multicast ethernet address, this routine calculates the
1442 * address's bit index in the logical address filter mask
1444 static inline unsigned int ioc3_hash(const unsigned char *addr)
1446 unsigned int temp = 0;
1450 crc = ether_crc_le(ETH_ALEN, addr);
1452 crc &= 0x3f; /* bit reverse lowest 6 bits for hash index */
1453 for (bits = 6; --bits >= 0; ) {
1455 temp |= (crc & 0x1);
1462 static void ioc3_get_drvinfo(struct net_device *dev,
1463 struct ethtool_drvinfo *info)
1465 struct ioc3_private *ip = netdev_priv(dev);
1467 strlcpy(info->driver, IOC3_NAME, sizeof(info->driver));
1468 strlcpy(info->version, IOC3_VERSION, sizeof(info->version));
1469 strlcpy(info->bus_info, pci_name(ip->pdev), sizeof(info->bus_info));
1472 static int ioc3_get_link_ksettings(struct net_device *dev,
1473 struct ethtool_link_ksettings *cmd)
1475 struct ioc3_private *ip = netdev_priv(dev);
1477 spin_lock_irq(&ip->ioc3_lock);
1478 mii_ethtool_get_link_ksettings(&ip->mii, cmd);
1479 spin_unlock_irq(&ip->ioc3_lock);
1484 static int ioc3_set_link_ksettings(struct net_device *dev,
1485 const struct ethtool_link_ksettings *cmd)
1487 struct ioc3_private *ip = netdev_priv(dev);
1490 spin_lock_irq(&ip->ioc3_lock);
1491 rc = mii_ethtool_set_link_ksettings(&ip->mii, cmd);
1492 spin_unlock_irq(&ip->ioc3_lock);
1497 static int ioc3_nway_reset(struct net_device *dev)
1499 struct ioc3_private *ip = netdev_priv(dev);
1502 spin_lock_irq(&ip->ioc3_lock);
1503 rc = mii_nway_restart(&ip->mii);
1504 spin_unlock_irq(&ip->ioc3_lock);
1509 static u32 ioc3_get_link(struct net_device *dev)
1511 struct ioc3_private *ip = netdev_priv(dev);
1514 spin_lock_irq(&ip->ioc3_lock);
1515 rc = mii_link_ok(&ip->mii);
1516 spin_unlock_irq(&ip->ioc3_lock);
1521 static const struct ethtool_ops ioc3_ethtool_ops = {
1522 .get_drvinfo = ioc3_get_drvinfo,
1523 .nway_reset = ioc3_nway_reset,
1524 .get_link = ioc3_get_link,
1525 .get_link_ksettings = ioc3_get_link_ksettings,
1526 .set_link_ksettings = ioc3_set_link_ksettings,
1529 static int ioc3_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1531 struct ioc3_private *ip = netdev_priv(dev);
1534 spin_lock_irq(&ip->ioc3_lock);
1535 rc = generic_mii_ioctl(&ip->mii, if_mii(rq), cmd, NULL);
1536 spin_unlock_irq(&ip->ioc3_lock);
1541 static void ioc3_set_multicast_list(struct net_device *dev)
1543 struct ioc3_private *ip = netdev_priv(dev);
1544 struct ioc3_ethregs *regs = ip->regs;
1545 struct netdev_hw_addr *ha;
1548 netif_stop_queue(dev); /* Lock out others. */
1550 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1551 ip->emcr |= EMCR_PROMISC;
1552 writel(ip->emcr, ®s->emcr);
1555 ip->emcr &= ~EMCR_PROMISC;
1556 writel(ip->emcr, ®s->emcr); /* Clear promiscuous. */
1559 if ((dev->flags & IFF_ALLMULTI) ||
1560 (netdev_mc_count(dev) > 64)) {
1561 /* Too many for hashing to make sense or we want all
1562 * multicast packets anyway, so skip computing all the
1563 * hashes and just accept all packets.
1565 ip->ehar_h = 0xffffffff;
1566 ip->ehar_l = 0xffffffff;
1568 netdev_for_each_mc_addr(ha, dev) {
1569 ehar |= (1UL << ioc3_hash(ha->addr));
1571 ip->ehar_h = ehar >> 32;
1572 ip->ehar_l = ehar & 0xffffffff;
1574 writel(ip->ehar_h, ®s->ehar_h);
1575 writel(ip->ehar_l, ®s->ehar_l);
1578 netif_wake_queue(dev); /* Let us get going again. */
1581 module_pci_driver(ioc3_driver);
1582 MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
1583 MODULE_DESCRIPTION("SGI IOC3 Ethernet driver");
1584 MODULE_LICENSE("GPL");