1 // SPDX-License-Identifier: GPL-2.0-only
2 /****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2018 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include "net_driver.h"
13 #include "nic_common.h"
14 #include "tx_common.h"
16 static unsigned int efx_tx_cb_page_count(struct efx_tx_queue *tx_queue)
18 return DIV_ROUND_UP(tx_queue->ptr_mask + 1,
19 PAGE_SIZE >> EFX_TX_CB_ORDER);
22 int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
24 struct efx_nic *efx = tx_queue->efx;
28 /* Create the smallest power-of-two aligned ring */
29 entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
30 EFX_WARN_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
31 tx_queue->ptr_mask = entries - 1;
33 netif_dbg(efx, probe, efx->net_dev,
34 "creating TX queue %d size %#x mask %#x\n",
35 tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
37 /* Allocate software ring */
38 tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer),
40 if (!tx_queue->buffer)
43 tx_queue->cb_page = kcalloc(efx_tx_cb_page_count(tx_queue),
44 sizeof(tx_queue->cb_page[0]), GFP_KERNEL);
45 if (!tx_queue->cb_page) {
50 /* Allocate hardware ring, determine TXQ type */
51 rc = efx_nic_probe_tx(tx_queue);
55 tx_queue->channel->tx_queue_by_type[tx_queue->type] = tx_queue;
59 kfree(tx_queue->cb_page);
60 tx_queue->cb_page = NULL;
62 kfree(tx_queue->buffer);
63 tx_queue->buffer = NULL;
67 void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
69 struct efx_nic *efx = tx_queue->efx;
71 netif_dbg(efx, drv, efx->net_dev,
72 "initialising TX queue %d\n", tx_queue->queue);
74 tx_queue->insert_count = 0;
75 tx_queue->notify_count = 0;
76 tx_queue->write_count = 0;
77 tx_queue->packet_write_count = 0;
78 tx_queue->old_write_count = 0;
79 tx_queue->read_count = 0;
80 tx_queue->old_read_count = 0;
81 tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
82 tx_queue->xmit_pending = false;
83 tx_queue->timestamping = (efx_ptp_use_mac_tx_timestamps(efx) &&
84 tx_queue->channel == efx_ptp_channel(efx));
85 tx_queue->completed_timestamp_major = 0;
86 tx_queue->completed_timestamp_minor = 0;
88 tx_queue->xdp_tx = efx_channel_is_xdp_tx(tx_queue->channel);
89 tx_queue->tso_version = 0;
91 /* Set up TX descriptor ring */
92 efx_nic_init_tx(tx_queue);
94 tx_queue->initialised = true;
97 void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
99 struct efx_tx_buffer *buffer;
101 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
102 "shutting down TX queue %d\n", tx_queue->queue);
104 tx_queue->initialised = false;
106 if (!tx_queue->buffer)
109 /* Free any buffers left in the ring */
110 while (tx_queue->read_count != tx_queue->write_count) {
111 unsigned int pkts_compl = 0, bytes_compl = 0;
112 unsigned int efv_pkts_compl = 0;
114 buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
115 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl,
118 ++tx_queue->read_count;
120 tx_queue->xmit_pending = false;
121 netdev_tx_reset_queue(tx_queue->core_txq);
124 void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
128 if (!tx_queue->buffer)
131 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
132 "destroying TX queue %d\n", tx_queue->queue);
133 efx_nic_remove_tx(tx_queue);
135 if (tx_queue->cb_page) {
136 for (i = 0; i < efx_tx_cb_page_count(tx_queue); i++)
137 efx_nic_free_buffer(tx_queue->efx,
138 &tx_queue->cb_page[i]);
139 kfree(tx_queue->cb_page);
140 tx_queue->cb_page = NULL;
143 kfree(tx_queue->buffer);
144 tx_queue->buffer = NULL;
145 tx_queue->channel->tx_queue_by_type[tx_queue->type] = NULL;
148 void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
149 struct efx_tx_buffer *buffer,
150 unsigned int *pkts_compl,
151 unsigned int *bytes_compl,
152 unsigned int *efv_pkts_compl)
154 if (buffer->unmap_len) {
155 struct device *dma_dev = &tx_queue->efx->pci_dev->dev;
156 dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset;
158 if (buffer->flags & EFX_TX_BUF_MAP_SINGLE)
159 dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len,
162 dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len,
164 buffer->unmap_len = 0;
167 if (buffer->flags & EFX_TX_BUF_SKB) {
168 struct sk_buff *skb = (struct sk_buff *)buffer->skb;
170 if (unlikely(buffer->flags & EFX_TX_BUF_EFV)) {
171 EFX_WARN_ON_PARANOID(!efv_pkts_compl);
174 EFX_WARN_ON_PARANOID(!pkts_compl || !bytes_compl);
176 (*bytes_compl) += skb->len;
179 if (tx_queue->timestamping &&
180 (tx_queue->completed_timestamp_major ||
181 tx_queue->completed_timestamp_minor)) {
182 struct skb_shared_hwtstamps hwtstamp;
185 efx_ptp_nic_to_kernel_time(tx_queue);
186 skb_tstamp_tx(skb, &hwtstamp);
188 tx_queue->completed_timestamp_major = 0;
189 tx_queue->completed_timestamp_minor = 0;
191 dev_consume_skb_any((struct sk_buff *)buffer->skb);
192 netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
193 "TX queue %d transmission id %x complete\n",
194 tx_queue->queue, tx_queue->read_count);
195 } else if (buffer->flags & EFX_TX_BUF_XDP) {
196 xdp_return_frame_rx_napi(buffer->xdpf);
203 /* Remove packets from the TX queue
205 * This removes packets from the TX queue, up to and including the
208 static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
210 unsigned int *pkts_compl,
211 unsigned int *bytes_compl,
212 unsigned int *efv_pkts_compl)
214 struct efx_nic *efx = tx_queue->efx;
215 unsigned int stop_index, read_ptr;
217 stop_index = (index + 1) & tx_queue->ptr_mask;
218 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
220 while (read_ptr != stop_index) {
221 struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
223 if (!efx_tx_buffer_in_use(buffer)) {
224 netif_err(efx, tx_err, efx->net_dev,
225 "TX queue %d spurious TX completion id %d\n",
226 tx_queue->queue, read_ptr);
227 efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
231 efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl,
234 ++tx_queue->read_count;
235 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
239 void efx_xmit_done_check_empty(struct efx_tx_queue *tx_queue)
241 if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
242 tx_queue->old_write_count = READ_ONCE(tx_queue->write_count);
243 if (tx_queue->read_count == tx_queue->old_write_count) {
244 /* Ensure that read_count is flushed. */
246 tx_queue->empty_read_count =
247 tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
252 int efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
254 unsigned int fill_level, pkts_compl = 0, bytes_compl = 0;
255 unsigned int efv_pkts_compl = 0;
256 struct efx_nic *efx = tx_queue->efx;
258 EFX_WARN_ON_ONCE_PARANOID(index > tx_queue->ptr_mask);
260 efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl,
262 tx_queue->pkts_compl += pkts_compl;
263 tx_queue->bytes_compl += bytes_compl;
265 if (pkts_compl + efv_pkts_compl > 1)
266 ++tx_queue->merge_events;
268 /* See if we need to restart the netif queue. This memory
269 * barrier ensures that we write read_count (inside
270 * efx_dequeue_buffers()) before reading the queue status.
273 if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) &&
274 likely(efx->port_enabled) &&
275 likely(netif_device_present(efx->net_dev))) {
276 fill_level = efx_channel_tx_fill_level(tx_queue->channel);
277 if (fill_level <= efx->txq_wake_thresh)
278 netif_tx_wake_queue(tx_queue->core_txq);
281 efx_xmit_done_check_empty(tx_queue);
283 return pkts_compl + efv_pkts_compl;
286 /* Remove buffers put into a tx_queue for the current packet.
287 * None of the buffers must have an skb attached.
289 void efx_enqueue_unwind(struct efx_tx_queue *tx_queue,
290 unsigned int insert_count)
292 unsigned int efv_pkts_compl = 0;
293 struct efx_tx_buffer *buffer;
294 unsigned int bytes_compl = 0;
295 unsigned int pkts_compl = 0;
297 /* Work backwards until we hit the original insert pointer value */
298 while (tx_queue->insert_count != insert_count) {
299 --tx_queue->insert_count;
300 buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
301 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl,
306 struct efx_tx_buffer *efx_tx_map_chunk(struct efx_tx_queue *tx_queue,
307 dma_addr_t dma_addr, size_t len)
309 const struct efx_nic_type *nic_type = tx_queue->efx->type;
310 struct efx_tx_buffer *buffer;
311 unsigned int dma_len;
313 /* Map the fragment taking account of NIC-dependent DMA limits. */
315 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
317 if (nic_type->tx_limit_len)
318 dma_len = nic_type->tx_limit_len(tx_queue, dma_addr, len);
322 buffer->len = dma_len;
323 buffer->dma_addr = dma_addr;
324 buffer->flags = EFX_TX_BUF_CONT;
327 ++tx_queue->insert_count;
333 int efx_tx_tso_header_length(struct sk_buff *skb)
337 if (skb->encapsulation)
338 header_len = skb_inner_transport_header(skb) -
340 (inner_tcp_hdr(skb)->doff << 2u);
342 header_len = skb_transport_header(skb) - skb->data +
343 (tcp_hdr(skb)->doff << 2u);
347 /* Map all data from an SKB for DMA and create descriptors on the queue. */
348 int efx_tx_map_data(struct efx_tx_queue *tx_queue, struct sk_buff *skb,
349 unsigned int segment_count)
351 struct efx_nic *efx = tx_queue->efx;
352 struct device *dma_dev = &efx->pci_dev->dev;
353 unsigned int frag_index, nr_frags;
354 dma_addr_t dma_addr, unmap_addr;
355 unsigned short dma_flags;
356 size_t len, unmap_len;
358 nr_frags = skb_shinfo(skb)->nr_frags;
361 /* Map header data. */
362 len = skb_headlen(skb);
363 dma_addr = dma_map_single(dma_dev, skb->data, len, DMA_TO_DEVICE);
364 dma_flags = EFX_TX_BUF_MAP_SINGLE;
366 unmap_addr = dma_addr;
368 if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
372 /* For TSO we need to put the header in to a separate
373 * descriptor. Map this separately if necessary.
375 size_t header_len = efx_tx_tso_header_length(skb);
377 if (header_len != len) {
378 tx_queue->tso_long_headers++;
379 efx_tx_map_chunk(tx_queue, dma_addr, header_len);
381 dma_addr += header_len;
385 /* Add descriptors for each fragment. */
387 struct efx_tx_buffer *buffer;
388 skb_frag_t *fragment;
390 buffer = efx_tx_map_chunk(tx_queue, dma_addr, len);
392 /* The final descriptor for a fragment is responsible for
393 * unmapping the whole fragment.
395 buffer->flags = EFX_TX_BUF_CONT | dma_flags;
396 buffer->unmap_len = unmap_len;
397 buffer->dma_offset = buffer->dma_addr - unmap_addr;
399 if (frag_index >= nr_frags) {
400 /* Store SKB details with the final buffer for
404 buffer->flags = EFX_TX_BUF_SKB | dma_flags;
408 /* Move on to the next fragment. */
409 fragment = &skb_shinfo(skb)->frags[frag_index++];
410 len = skb_frag_size(fragment);
411 dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len,
415 unmap_addr = dma_addr;
417 if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
422 unsigned int efx_tx_max_skb_descs(struct efx_nic *efx)
424 /* Header and payload descriptor for each output segment, plus
425 * one for every input fragment boundary within a segment
427 unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS;
429 /* Possibly one more per segment for option descriptors */
430 if (efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
431 max_descs += EFX_TSO_MAX_SEGS;
433 /* Possibly more for PCIe page boundaries within input fragments */
434 if (PAGE_SIZE > EFX_PAGE_SIZE)
435 max_descs += max_t(unsigned int, MAX_SKB_FRAGS,
436 DIV_ROUND_UP(GSO_LEGACY_MAX_SIZE,
443 * Fallback to software TSO.
445 * This is used if we are unable to send a GSO packet through hardware TSO.
446 * This should only ever happen due to per-queue restrictions - unsupported
447 * packets should first be filtered by the feature flags.
449 * Returns 0 on success, error code otherwise.
451 int efx_tx_tso_fallback(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
453 struct sk_buff *segments, *next;
455 segments = skb_gso_segment(skb, 0);
456 if (IS_ERR(segments))
457 return PTR_ERR(segments);
459 dev_consume_skb_any(skb);
461 skb_list_walk_safe(segments, skb, next) {
462 skb_mark_not_on_list(skb);
463 efx_enqueue_skb(tx_queue, skb);