1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2013 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/pci.h>
12 #include <linux/tcp.h>
15 #include <linux/ipv6.h>
16 #include <linux/slab.h>
18 #include <linux/if_ether.h>
19 #include <linux/highmem.h>
20 #include <linux/cache.h>
21 #include "net_driver.h"
25 #include "workarounds.h"
26 #include "ef10_regs.h"
30 #define EFX_PIOBUF_SIZE_MAX ER_DZ_TX_PIOBUF_SIZE
31 #define EFX_PIOBUF_SIZE_DEF ALIGN(256, L1_CACHE_BYTES)
32 unsigned int efx_piobuf_size __read_mostly = EFX_PIOBUF_SIZE_DEF;
34 #endif /* EFX_USE_PIO */
36 static inline unsigned int
37 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue)
39 return tx_queue->insert_count & tx_queue->ptr_mask;
42 static inline struct efx_tx_buffer *
43 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
45 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
48 static inline struct efx_tx_buffer *
49 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
51 struct efx_tx_buffer *buffer =
52 __efx_tx_queue_get_insert_buffer(tx_queue);
54 EFX_BUG_ON_PARANOID(buffer->len);
55 EFX_BUG_ON_PARANOID(buffer->flags);
56 EFX_BUG_ON_PARANOID(buffer->unmap_len);
61 static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
62 struct efx_tx_buffer *buffer,
63 unsigned int *pkts_compl,
64 unsigned int *bytes_compl)
66 if (buffer->unmap_len) {
67 struct device *dma_dev = &tx_queue->efx->pci_dev->dev;
68 dma_addr_t unmap_addr = buffer->dma_addr - buffer->dma_offset;
69 if (buffer->flags & EFX_TX_BUF_MAP_SINGLE)
70 dma_unmap_single(dma_dev, unmap_addr, buffer->unmap_len,
73 dma_unmap_page(dma_dev, unmap_addr, buffer->unmap_len,
75 buffer->unmap_len = 0;
78 if (buffer->flags & EFX_TX_BUF_SKB) {
80 (*bytes_compl) += buffer->skb->len;
81 dev_kfree_skb_any((struct sk_buff *) buffer->skb);
82 netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev,
83 "TX queue %d transmission id %x complete\n",
84 tx_queue->queue, tx_queue->read_count);
85 } else if (buffer->flags & EFX_TX_BUF_HEAP) {
86 kfree(buffer->heap_buf);
93 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
96 static inline unsigned
97 efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr)
99 /* Depending on the NIC revision, we can use descriptor
100 * lengths up to 8K or 8K-1. However, since PCI Express
101 * devices must split read requests at 4K boundaries, there is
102 * little benefit from using descriptors that cross those
103 * boundaries and we keep things simple by not doing so.
105 unsigned len = (~dma_addr & (EFX_PAGE_SIZE - 1)) + 1;
107 /* Work around hardware bug for unaligned buffers. */
108 if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf))
109 len = min_t(unsigned, len, 512 - (dma_addr & 0xf));
114 unsigned int efx_tx_max_skb_descs(struct efx_nic *efx)
116 /* Header and payload descriptor for each output segment, plus
117 * one for every input fragment boundary within a segment
119 unsigned int max_descs = EFX_TSO_MAX_SEGS * 2 + MAX_SKB_FRAGS;
121 /* Possibly one more per segment for the alignment workaround,
122 * or for option descriptors
124 if (EFX_WORKAROUND_5391(efx) || efx_nic_rev(efx) >= EFX_REV_HUNT_A0)
125 max_descs += EFX_TSO_MAX_SEGS;
127 /* Possibly more for PCIe page boundaries within input fragments */
128 if (PAGE_SIZE > EFX_PAGE_SIZE)
129 max_descs += max_t(unsigned int, MAX_SKB_FRAGS,
130 DIV_ROUND_UP(GSO_MAX_SIZE, EFX_PAGE_SIZE));
135 /* Get partner of a TX queue, seen as part of the same net core queue */
136 static struct efx_tx_queue *efx_tx_queue_partner(struct efx_tx_queue *tx_queue)
138 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD)
139 return tx_queue - EFX_TXQ_TYPE_OFFLOAD;
141 return tx_queue + EFX_TXQ_TYPE_OFFLOAD;
144 static void efx_tx_maybe_stop_queue(struct efx_tx_queue *txq1)
146 /* We need to consider both queues that the net core sees as one */
147 struct efx_tx_queue *txq2 = efx_tx_queue_partner(txq1);
148 struct efx_nic *efx = txq1->efx;
149 unsigned int fill_level;
151 fill_level = max(txq1->insert_count - txq1->old_read_count,
152 txq2->insert_count - txq2->old_read_count);
153 if (likely(fill_level < efx->txq_stop_thresh))
156 /* We used the stale old_read_count above, which gives us a
157 * pessimistic estimate of the fill level (which may even
158 * validly be >= efx->txq_entries). Now try again using
159 * read_count (more likely to be a cache miss).
161 * If we read read_count and then conditionally stop the
162 * queue, it is possible for the completion path to race with
163 * us and complete all outstanding descriptors in the middle,
164 * after which there will be no more completions to wake it.
165 * Therefore we stop the queue first, then read read_count
166 * (with a memory barrier to ensure the ordering), then
167 * restart the queue if the fill level turns out to be low
170 netif_tx_stop_queue(txq1->core_txq);
172 txq1->old_read_count = ACCESS_ONCE(txq1->read_count);
173 txq2->old_read_count = ACCESS_ONCE(txq2->read_count);
175 fill_level = max(txq1->insert_count - txq1->old_read_count,
176 txq2->insert_count - txq2->old_read_count);
177 EFX_BUG_ON_PARANOID(fill_level >= efx->txq_entries);
178 if (likely(fill_level < efx->txq_stop_thresh)) {
180 if (likely(!efx->loopback_selftest))
181 netif_tx_start_queue(txq1->core_txq);
187 struct efx_short_copy_buffer {
189 u8 buf[L1_CACHE_BYTES];
192 /* Copy to PIO, respecting that writes to PIO buffers must be dword aligned.
193 * Advances piobuf pointer. Leaves additional data in the copy buffer.
195 static void efx_memcpy_toio_aligned(struct efx_nic *efx, u8 __iomem **piobuf,
197 struct efx_short_copy_buffer *copy_buf)
199 int block_len = len & ~(sizeof(copy_buf->buf) - 1);
201 __iowrite64_copy(*piobuf, data, block_len >> 3);
202 *piobuf += block_len;
207 BUG_ON(copy_buf->used);
208 BUG_ON(len > sizeof(copy_buf->buf));
209 memcpy(copy_buf->buf, data, len);
210 copy_buf->used = len;
214 /* Copy to PIO, respecting dword alignment, popping data from copy buffer first.
215 * Advances piobuf pointer. Leaves additional data in the copy buffer.
217 static void efx_memcpy_toio_aligned_cb(struct efx_nic *efx, u8 __iomem **piobuf,
219 struct efx_short_copy_buffer *copy_buf)
221 if (copy_buf->used) {
222 /* if the copy buffer is partially full, fill it up and write */
224 min_t(int, sizeof(copy_buf->buf) - copy_buf->used, len);
226 memcpy(copy_buf->buf + copy_buf->used, data, copy_to_buf);
227 copy_buf->used += copy_to_buf;
229 /* if we didn't fill it up then we're done for now */
230 if (copy_buf->used < sizeof(copy_buf->buf))
233 __iowrite64_copy(*piobuf, copy_buf->buf,
234 sizeof(copy_buf->buf) >> 3);
235 *piobuf += sizeof(copy_buf->buf);
241 efx_memcpy_toio_aligned(efx, piobuf, data, len, copy_buf);
244 static void efx_flush_copy_buffer(struct efx_nic *efx, u8 __iomem *piobuf,
245 struct efx_short_copy_buffer *copy_buf)
247 /* if there's anything in it, write the whole buffer, including junk */
249 __iowrite64_copy(piobuf, copy_buf->buf,
250 sizeof(copy_buf->buf) >> 3);
253 /* Traverse skb structure and copy fragments in to PIO buffer.
254 * Advances piobuf pointer.
256 static void efx_skb_copy_bits_to_pio(struct efx_nic *efx, struct sk_buff *skb,
258 struct efx_short_copy_buffer *copy_buf)
262 efx_memcpy_toio_aligned(efx, piobuf, skb->data, skb_headlen(skb),
265 for (i = 0; i < skb_shinfo(skb)->nr_frags; ++i) {
266 skb_frag_t *f = &skb_shinfo(skb)->frags[i];
269 vaddr = kmap_atomic(skb_frag_page(f));
271 efx_memcpy_toio_aligned_cb(efx, piobuf, vaddr + f->page_offset,
272 skb_frag_size(f), copy_buf);
273 kunmap_atomic(vaddr);
276 EFX_BUG_ON_PARANOID(skb_shinfo(skb)->frag_list);
279 static struct efx_tx_buffer *
280 efx_enqueue_skb_pio(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
282 struct efx_tx_buffer *buffer =
283 efx_tx_queue_get_insert_buffer(tx_queue);
284 u8 __iomem *piobuf = tx_queue->piobuf;
286 /* Copy to PIO buffer. Ensure the writes are padded to the end
287 * of a cache line, as this is required for write-combining to be
288 * effective on at least x86.
291 if (skb_shinfo(skb)->nr_frags) {
292 /* The size of the copy buffer will ensure all writes
293 * are the size of a cache line.
295 struct efx_short_copy_buffer copy_buf;
299 efx_skb_copy_bits_to_pio(tx_queue->efx, skb,
301 efx_flush_copy_buffer(tx_queue->efx, piobuf, ©_buf);
303 /* Pad the write to the size of a cache line.
304 * We can do this because we know the skb_shared_info sruct is
305 * after the source, and the destination buffer is big enough.
307 BUILD_BUG_ON(L1_CACHE_BYTES >
308 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)));
309 __iowrite64_copy(tx_queue->piobuf, skb->data,
310 ALIGN(skb->len, L1_CACHE_BYTES) >> 3);
313 EFX_POPULATE_QWORD_5(buffer->option,
314 ESF_DZ_TX_DESC_IS_OPT, 1,
315 ESF_DZ_TX_OPTION_TYPE, ESE_DZ_TX_OPTION_DESC_PIO,
316 ESF_DZ_TX_PIO_CONT, 0,
317 ESF_DZ_TX_PIO_BYTE_CNT, skb->len,
318 ESF_DZ_TX_PIO_BUF_ADDR,
319 tx_queue->piobuf_offset);
320 ++tx_queue->pio_packets;
321 ++tx_queue->insert_count;
324 #endif /* EFX_USE_PIO */
327 * Add a socket buffer to a TX queue
329 * This maps all fragments of a socket buffer for DMA and adds them to
330 * the TX queue. The queue's insert pointer will be incremented by
331 * the number of fragments in the socket buffer.
333 * If any DMA mapping fails, any mapped fragments will be unmapped,
334 * the queue's insert pointer will be restored to its original value.
336 * This function is split out from efx_hard_start_xmit to allow the
337 * loopback test to direct packets via specific TX queues.
339 * Returns NETDEV_TX_OK.
340 * You must hold netif_tx_lock() to call this function.
342 netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
344 struct efx_nic *efx = tx_queue->efx;
345 struct device *dma_dev = &efx->pci_dev->dev;
346 struct efx_tx_buffer *buffer;
347 skb_frag_t *fragment;
348 unsigned int len, unmap_len = 0;
349 dma_addr_t dma_addr, unmap_addr = 0;
350 unsigned int dma_len;
351 unsigned short dma_flags;
354 EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
356 if (skb_shinfo(skb)->gso_size)
357 return efx_enqueue_skb_tso(tx_queue, skb);
359 /* Get size of the initial fragment */
360 len = skb_headlen(skb);
362 /* Pad if necessary */
363 if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) {
364 EFX_BUG_ON_PARANOID(skb->data_len);
366 if (skb_pad(skb, len - skb->len))
370 /* Consider using PIO for short packets */
372 if (skb->len <= efx_piobuf_size && tx_queue->piobuf &&
373 efx_nic_tx_is_empty(tx_queue) &&
374 efx_nic_tx_is_empty(efx_tx_queue_partner(tx_queue))) {
375 buffer = efx_enqueue_skb_pio(tx_queue, skb);
376 dma_flags = EFX_TX_BUF_OPTION;
381 /* Map for DMA. Use dma_map_single rather than dma_map_page
382 * since this is more efficient on machines with sparse
385 dma_flags = EFX_TX_BUF_MAP_SINGLE;
386 dma_addr = dma_map_single(dma_dev, skb->data, len, PCI_DMA_TODEVICE);
388 /* Process all fragments */
390 if (unlikely(dma_mapping_error(dma_dev, dma_addr)))
393 /* Store fields for marking in the per-fragment final
396 unmap_addr = dma_addr;
398 /* Add to TX queue, splitting across DMA boundaries */
400 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
402 dma_len = efx_max_tx_len(efx, dma_addr);
403 if (likely(dma_len >= len))
406 /* Fill out per descriptor fields */
407 buffer->len = dma_len;
408 buffer->dma_addr = dma_addr;
409 buffer->flags = EFX_TX_BUF_CONT;
412 ++tx_queue->insert_count;
415 /* Transfer ownership of the unmapping to the final buffer */
416 buffer->flags = EFX_TX_BUF_CONT | dma_flags;
417 buffer->unmap_len = unmap_len;
418 buffer->dma_offset = buffer->dma_addr - unmap_addr;
421 /* Get address and size of next fragment */
422 if (i >= skb_shinfo(skb)->nr_frags)
424 fragment = &skb_shinfo(skb)->frags[i];
425 len = skb_frag_size(fragment);
429 dma_addr = skb_frag_dma_map(dma_dev, fragment, 0, len,
433 /* Transfer ownership of the skb to the final buffer */
438 buffer->flags = EFX_TX_BUF_SKB | dma_flags;
440 netdev_tx_sent_queue(tx_queue->core_txq, skb->len);
442 /* Pass off to hardware */
443 efx_nic_push_buffers(tx_queue);
445 tx_queue->tx_packets++;
447 efx_tx_maybe_stop_queue(tx_queue);
452 netif_err(efx, tx_err, efx->net_dev,
453 " TX queue %d could not map skb with %d bytes %d "
454 "fragments for DMA\n", tx_queue->queue, skb->len,
455 skb_shinfo(skb)->nr_frags + 1);
457 /* Mark the packet as transmitted, and free the SKB ourselves */
458 dev_kfree_skb_any(skb);
460 /* Work backwards until we hit the original insert pointer value */
461 while (tx_queue->insert_count != tx_queue->write_count) {
462 unsigned int pkts_compl = 0, bytes_compl = 0;
463 --tx_queue->insert_count;
464 buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
465 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
468 /* Free the fragment we were mid-way through pushing */
470 if (dma_flags & EFX_TX_BUF_MAP_SINGLE)
471 dma_unmap_single(dma_dev, unmap_addr, unmap_len,
474 dma_unmap_page(dma_dev, unmap_addr, unmap_len,
481 /* Remove packets from the TX queue
483 * This removes packets from the TX queue, up to and including the
486 static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
488 unsigned int *pkts_compl,
489 unsigned int *bytes_compl)
491 struct efx_nic *efx = tx_queue->efx;
492 unsigned int stop_index, read_ptr;
494 stop_index = (index + 1) & tx_queue->ptr_mask;
495 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
497 while (read_ptr != stop_index) {
498 struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
500 if (!(buffer->flags & EFX_TX_BUF_OPTION) &&
501 unlikely(buffer->len == 0)) {
502 netif_err(efx, tx_err, efx->net_dev,
503 "TX queue %d spurious TX completion id %x\n",
504 tx_queue->queue, read_ptr);
505 efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
509 efx_dequeue_buffer(tx_queue, buffer, pkts_compl, bytes_compl);
511 ++tx_queue->read_count;
512 read_ptr = tx_queue->read_count & tx_queue->ptr_mask;
516 /* Initiate a packet transmission. We use one channel per CPU
517 * (sharing when we have more CPUs than channels). On Falcon, the TX
518 * completion events will be directed back to the CPU that transmitted
519 * the packet, which should be cache-efficient.
521 * Context: non-blocking.
522 * Note that returning anything other than NETDEV_TX_OK will cause the
523 * OS to free the skb.
525 netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
526 struct net_device *net_dev)
528 struct efx_nic *efx = netdev_priv(net_dev);
529 struct efx_tx_queue *tx_queue;
530 unsigned index, type;
532 EFX_WARN_ON_PARANOID(!netif_device_present(net_dev));
534 /* PTP "event" packet */
535 if (unlikely(efx_xmit_with_hwtstamp(skb)) &&
536 unlikely(efx_ptp_is_ptp_tx(efx, skb))) {
537 return efx_ptp_tx(efx, skb);
540 index = skb_get_queue_mapping(skb);
541 type = skb->ip_summed == CHECKSUM_PARTIAL ? EFX_TXQ_TYPE_OFFLOAD : 0;
542 if (index >= efx->n_tx_channels) {
543 index -= efx->n_tx_channels;
544 type |= EFX_TXQ_TYPE_HIGHPRI;
546 tx_queue = efx_get_tx_queue(efx, index, type);
548 return efx_enqueue_skb(tx_queue, skb);
551 void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue)
553 struct efx_nic *efx = tx_queue->efx;
555 /* Must be inverse of queue lookup in efx_hard_start_xmit() */
557 netdev_get_tx_queue(efx->net_dev,
558 tx_queue->queue / EFX_TXQ_TYPES +
559 ((tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI) ?
560 efx->n_tx_channels : 0));
563 int efx_setup_tc(struct net_device *net_dev, u8 num_tc)
565 struct efx_nic *efx = netdev_priv(net_dev);
566 struct efx_channel *channel;
567 struct efx_tx_queue *tx_queue;
571 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0 || num_tc > EFX_MAX_TX_TC)
574 if (num_tc == net_dev->num_tc)
577 for (tc = 0; tc < num_tc; tc++) {
578 net_dev->tc_to_txq[tc].offset = tc * efx->n_tx_channels;
579 net_dev->tc_to_txq[tc].count = efx->n_tx_channels;
582 if (num_tc > net_dev->num_tc) {
583 /* Initialise high-priority queues as necessary */
584 efx_for_each_channel(channel, efx) {
585 efx_for_each_possible_channel_tx_queue(tx_queue,
587 if (!(tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI))
589 if (!tx_queue->buffer) {
590 rc = efx_probe_tx_queue(tx_queue);
594 if (!tx_queue->initialised)
595 efx_init_tx_queue(tx_queue);
596 efx_init_tx_queue_core_txq(tx_queue);
600 /* Reduce number of classes before number of queues */
601 net_dev->num_tc = num_tc;
604 rc = netif_set_real_num_tx_queues(net_dev,
605 max_t(int, num_tc, 1) *
610 /* Do not destroy high-priority queues when they become
611 * unused. We would have to flush them first, and it is
612 * fairly difficult to flush a subset of TX queues. Leave
613 * it to efx_fini_channels().
616 net_dev->num_tc = num_tc;
620 void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
623 struct efx_nic *efx = tx_queue->efx;
624 struct efx_tx_queue *txq2;
625 unsigned int pkts_compl = 0, bytes_compl = 0;
627 EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask);
629 efx_dequeue_buffers(tx_queue, index, &pkts_compl, &bytes_compl);
630 netdev_tx_completed_queue(tx_queue->core_txq, pkts_compl, bytes_compl);
633 ++tx_queue->merge_events;
635 /* See if we need to restart the netif queue. This memory
636 * barrier ensures that we write read_count (inside
637 * efx_dequeue_buffers()) before reading the queue status.
640 if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) &&
641 likely(efx->port_enabled) &&
642 likely(netif_device_present(efx->net_dev))) {
643 txq2 = efx_tx_queue_partner(tx_queue);
644 fill_level = max(tx_queue->insert_count - tx_queue->read_count,
645 txq2->insert_count - txq2->read_count);
646 if (fill_level <= efx->txq_wake_thresh)
647 netif_tx_wake_queue(tx_queue->core_txq);
650 /* Check whether the hardware queue is now empty */
651 if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) {
652 tx_queue->old_write_count = ACCESS_ONCE(tx_queue->write_count);
653 if (tx_queue->read_count == tx_queue->old_write_count) {
655 tx_queue->empty_read_count =
656 tx_queue->read_count | EFX_EMPTY_COUNT_VALID;
661 /* Size of page-based TSO header buffers. Larger blocks must be
662 * allocated from the heap.
664 #define TSOH_STD_SIZE 128
665 #define TSOH_PER_PAGE (PAGE_SIZE / TSOH_STD_SIZE)
667 /* At most half the descriptors in the queue at any time will refer to
668 * a TSO header buffer, since they must always be followed by a
669 * payload descriptor referring to an skb.
671 static unsigned int efx_tsoh_page_count(struct efx_tx_queue *tx_queue)
673 return DIV_ROUND_UP(tx_queue->ptr_mask + 1, 2 * TSOH_PER_PAGE);
676 int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
678 struct efx_nic *efx = tx_queue->efx;
679 unsigned int entries;
682 /* Create the smallest power-of-two aligned ring */
683 entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE);
684 EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
685 tx_queue->ptr_mask = entries - 1;
687 netif_dbg(efx, probe, efx->net_dev,
688 "creating TX queue %d size %#x mask %#x\n",
689 tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask);
691 /* Allocate software ring */
692 tx_queue->buffer = kcalloc(entries, sizeof(*tx_queue->buffer),
694 if (!tx_queue->buffer)
697 if (tx_queue->queue & EFX_TXQ_TYPE_OFFLOAD) {
698 tx_queue->tsoh_page =
699 kcalloc(efx_tsoh_page_count(tx_queue),
700 sizeof(tx_queue->tsoh_page[0]), GFP_KERNEL);
701 if (!tx_queue->tsoh_page) {
707 /* Allocate hardware ring */
708 rc = efx_nic_probe_tx(tx_queue);
715 kfree(tx_queue->tsoh_page);
716 tx_queue->tsoh_page = NULL;
718 kfree(tx_queue->buffer);
719 tx_queue->buffer = NULL;
723 void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
725 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
726 "initialising TX queue %d\n", tx_queue->queue);
728 tx_queue->insert_count = 0;
729 tx_queue->write_count = 0;
730 tx_queue->old_write_count = 0;
731 tx_queue->read_count = 0;
732 tx_queue->old_read_count = 0;
733 tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID;
735 /* Set up TX descriptor ring */
736 efx_nic_init_tx(tx_queue);
738 tx_queue->initialised = true;
741 void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
743 struct efx_tx_buffer *buffer;
745 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
746 "shutting down TX queue %d\n", tx_queue->queue);
748 if (!tx_queue->buffer)
751 /* Free any buffers left in the ring */
752 while (tx_queue->read_count != tx_queue->write_count) {
753 unsigned int pkts_compl = 0, bytes_compl = 0;
754 buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask];
755 efx_dequeue_buffer(tx_queue, buffer, &pkts_compl, &bytes_compl);
757 ++tx_queue->read_count;
759 netdev_tx_reset_queue(tx_queue->core_txq);
762 void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
766 if (!tx_queue->buffer)
769 netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev,
770 "destroying TX queue %d\n", tx_queue->queue);
771 efx_nic_remove_tx(tx_queue);
773 if (tx_queue->tsoh_page) {
774 for (i = 0; i < efx_tsoh_page_count(tx_queue); i++)
775 efx_nic_free_buffer(tx_queue->efx,
776 &tx_queue->tsoh_page[i]);
777 kfree(tx_queue->tsoh_page);
778 tx_queue->tsoh_page = NULL;
781 kfree(tx_queue->buffer);
782 tx_queue->buffer = NULL;
786 /* Efx TCP segmentation acceleration.
788 * Why? Because by doing it here in the driver we can go significantly
789 * faster than the GSO.
791 * Requires TX checksum offload support.
794 #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
797 * struct tso_state - TSO state for an SKB
798 * @out_len: Remaining length in current segment
799 * @seqnum: Current sequence number
800 * @ipv4_id: Current IPv4 ID, host endian
801 * @packet_space: Remaining space in current packet
802 * @dma_addr: DMA address of current position
803 * @in_len: Remaining length in current SKB fragment
804 * @unmap_len: Length of SKB fragment
805 * @unmap_addr: DMA address of SKB fragment
806 * @dma_flags: TX buffer flags for DMA mapping - %EFX_TX_BUF_MAP_SINGLE or 0
807 * @protocol: Network protocol (after any VLAN header)
808 * @ip_off: Offset of IP header
809 * @tcp_off: Offset of TCP header
810 * @header_len: Number of bytes of header
811 * @ip_base_len: IPv4 tot_len or IPv6 payload_len, before TCP payload
812 * @header_dma_addr: Header DMA address, when using option descriptors
813 * @header_unmap_len: Header DMA mapped length, or 0 if not using option
816 * The state used during segmentation. It is put into this data structure
817 * just to make it easy to pass into inline functions.
820 /* Output position */
824 unsigned packet_space;
830 dma_addr_t unmap_addr;
831 unsigned short dma_flags;
835 unsigned int tcp_off;
837 unsigned int ip_base_len;
838 dma_addr_t header_dma_addr;
839 unsigned int header_unmap_len;
844 * Verify that our various assumptions about sk_buffs and the conditions
845 * under which TSO will be attempted hold true. Return the protocol number.
847 static __be16 efx_tso_check_protocol(struct sk_buff *skb)
849 __be16 protocol = skb->protocol;
851 EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
853 if (protocol == htons(ETH_P_8021Q)) {
854 struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
855 protocol = veh->h_vlan_encapsulated_proto;
858 if (protocol == htons(ETH_P_IP)) {
859 EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
861 EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6));
862 EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP);
864 EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
865 + (tcp_hdr(skb)->doff << 2u)) >
871 static u8 *efx_tsoh_get_buffer(struct efx_tx_queue *tx_queue,
872 struct efx_tx_buffer *buffer, unsigned int len)
876 EFX_BUG_ON_PARANOID(buffer->len);
877 EFX_BUG_ON_PARANOID(buffer->flags);
878 EFX_BUG_ON_PARANOID(buffer->unmap_len);
880 if (likely(len <= TSOH_STD_SIZE - NET_IP_ALIGN)) {
882 (tx_queue->insert_count & tx_queue->ptr_mask) / 2;
883 struct efx_buffer *page_buf =
884 &tx_queue->tsoh_page[index / TSOH_PER_PAGE];
886 TSOH_STD_SIZE * (index % TSOH_PER_PAGE) + NET_IP_ALIGN;
888 if (unlikely(!page_buf->addr) &&
889 efx_nic_alloc_buffer(tx_queue->efx, page_buf, PAGE_SIZE,
893 result = (u8 *)page_buf->addr + offset;
894 buffer->dma_addr = page_buf->dma_addr + offset;
895 buffer->flags = EFX_TX_BUF_CONT;
897 tx_queue->tso_long_headers++;
899 buffer->heap_buf = kmalloc(NET_IP_ALIGN + len, GFP_ATOMIC);
900 if (unlikely(!buffer->heap_buf))
902 result = (u8 *)buffer->heap_buf + NET_IP_ALIGN;
903 buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_HEAP;
912 * efx_tx_queue_insert - push descriptors onto the TX queue
913 * @tx_queue: Efx TX queue
914 * @dma_addr: DMA address of fragment
915 * @len: Length of fragment
916 * @final_buffer: The final buffer inserted into the queue
918 * Push descriptors onto the TX queue.
920 static void efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
921 dma_addr_t dma_addr, unsigned len,
922 struct efx_tx_buffer **final_buffer)
924 struct efx_tx_buffer *buffer;
925 struct efx_nic *efx = tx_queue->efx;
928 EFX_BUG_ON_PARANOID(len <= 0);
931 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
932 ++tx_queue->insert_count;
934 EFX_BUG_ON_PARANOID(tx_queue->insert_count -
935 tx_queue->read_count >=
938 buffer->dma_addr = dma_addr;
940 dma_len = efx_max_tx_len(efx, dma_addr);
942 /* If there is enough space to send then do so */
946 buffer->len = dma_len;
947 buffer->flags = EFX_TX_BUF_CONT;
952 EFX_BUG_ON_PARANOID(!len);
954 *final_buffer = buffer;
959 * Put a TSO header into the TX queue.
961 * This is special-cased because we know that it is small enough to fit in
962 * a single fragment, and we know it doesn't cross a page boundary. It
963 * also allows us to not worry about end-of-packet etc.
965 static int efx_tso_put_header(struct efx_tx_queue *tx_queue,
966 struct efx_tx_buffer *buffer, u8 *header)
968 if (unlikely(buffer->flags & EFX_TX_BUF_HEAP)) {
969 buffer->dma_addr = dma_map_single(&tx_queue->efx->pci_dev->dev,
972 if (unlikely(dma_mapping_error(&tx_queue->efx->pci_dev->dev,
973 buffer->dma_addr))) {
974 kfree(buffer->heap_buf);
979 buffer->unmap_len = buffer->len;
980 buffer->dma_offset = 0;
981 buffer->flags |= EFX_TX_BUF_MAP_SINGLE;
984 ++tx_queue->insert_count;
989 /* Remove buffers put into a tx_queue. None of the buffers must have
992 static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
994 struct efx_tx_buffer *buffer;
996 /* Work backwards until we hit the original insert pointer value */
997 while (tx_queue->insert_count != tx_queue->write_count) {
998 --tx_queue->insert_count;
999 buffer = __efx_tx_queue_get_insert_buffer(tx_queue);
1000 efx_dequeue_buffer(tx_queue, buffer, NULL, NULL);
1005 /* Parse the SKB header and initialise state. */
1006 static int tso_start(struct tso_state *st, struct efx_nic *efx,
1007 const struct sk_buff *skb)
1009 bool use_opt_desc = efx_nic_rev(efx) >= EFX_REV_HUNT_A0;
1010 struct device *dma_dev = &efx->pci_dev->dev;
1011 unsigned int header_len, in_len;
1012 dma_addr_t dma_addr;
1014 st->ip_off = skb_network_header(skb) - skb->data;
1015 st->tcp_off = skb_transport_header(skb) - skb->data;
1016 header_len = st->tcp_off + (tcp_hdr(skb)->doff << 2u);
1017 in_len = skb_headlen(skb) - header_len;
1018 st->header_len = header_len;
1019 st->in_len = in_len;
1020 if (st->protocol == htons(ETH_P_IP)) {
1021 st->ip_base_len = st->header_len - st->ip_off;
1022 st->ipv4_id = ntohs(ip_hdr(skb)->id);
1024 st->ip_base_len = st->header_len - st->tcp_off;
1027 st->seqnum = ntohl(tcp_hdr(skb)->seq);
1029 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
1030 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
1031 EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
1033 st->out_len = skb->len - header_len;
1035 if (!use_opt_desc) {
1036 st->header_unmap_len = 0;
1038 if (likely(in_len == 0)) {
1044 dma_addr = dma_map_single(dma_dev, skb->data + header_len,
1045 in_len, DMA_TO_DEVICE);
1046 st->dma_flags = EFX_TX_BUF_MAP_SINGLE;
1047 st->dma_addr = dma_addr;
1048 st->unmap_addr = dma_addr;
1049 st->unmap_len = in_len;
1051 dma_addr = dma_map_single(dma_dev, skb->data,
1052 skb_headlen(skb), DMA_TO_DEVICE);
1053 st->header_dma_addr = dma_addr;
1054 st->header_unmap_len = skb_headlen(skb);
1056 st->dma_addr = dma_addr + header_len;
1060 return unlikely(dma_mapping_error(dma_dev, dma_addr)) ? -ENOMEM : 0;
1063 static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
1066 st->unmap_addr = skb_frag_dma_map(&efx->pci_dev->dev, frag, 0,
1067 skb_frag_size(frag), DMA_TO_DEVICE);
1068 if (likely(!dma_mapping_error(&efx->pci_dev->dev, st->unmap_addr))) {
1070 st->unmap_len = skb_frag_size(frag);
1071 st->in_len = skb_frag_size(frag);
1072 st->dma_addr = st->unmap_addr;
1080 * tso_fill_packet_with_fragment - form descriptors for the current fragment
1081 * @tx_queue: Efx TX queue
1082 * @skb: Socket buffer
1085 * Form descriptors for the current fragment, until we reach the end
1086 * of fragment or end-of-packet.
1088 static void tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
1089 const struct sk_buff *skb,
1090 struct tso_state *st)
1092 struct efx_tx_buffer *buffer;
1095 if (st->in_len == 0)
1097 if (st->packet_space == 0)
1100 EFX_BUG_ON_PARANOID(st->in_len <= 0);
1101 EFX_BUG_ON_PARANOID(st->packet_space <= 0);
1103 n = min(st->in_len, st->packet_space);
1105 st->packet_space -= n;
1109 efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
1111 if (st->out_len == 0) {
1112 /* Transfer ownership of the skb */
1114 buffer->flags = EFX_TX_BUF_SKB;
1115 } else if (st->packet_space != 0) {
1116 buffer->flags = EFX_TX_BUF_CONT;
1119 if (st->in_len == 0) {
1120 /* Transfer ownership of the DMA mapping */
1121 buffer->unmap_len = st->unmap_len;
1122 buffer->dma_offset = buffer->unmap_len - buffer->len;
1123 buffer->flags |= st->dma_flags;
1132 * tso_start_new_packet - generate a new header and prepare for the new packet
1133 * @tx_queue: Efx TX queue
1134 * @skb: Socket buffer
1137 * Generate a new header and prepare for the new packet. Return 0 on
1138 * success, or -%ENOMEM if failed to alloc header.
1140 static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
1141 const struct sk_buff *skb,
1142 struct tso_state *st)
1144 struct efx_tx_buffer *buffer =
1145 efx_tx_queue_get_insert_buffer(tx_queue);
1146 bool is_last = st->out_len <= skb_shinfo(skb)->gso_size;
1150 st->packet_space = skb_shinfo(skb)->gso_size;
1151 tcp_flags_clear = 0x09; /* mask out FIN and PSH */
1153 st->packet_space = st->out_len;
1154 tcp_flags_clear = 0x00;
1157 if (!st->header_unmap_len) {
1158 /* Allocate and insert a DMA-mapped header buffer. */
1159 struct tcphdr *tsoh_th;
1164 header = efx_tsoh_get_buffer(tx_queue, buffer, st->header_len);
1168 tsoh_th = (struct tcphdr *)(header + st->tcp_off);
1170 /* Copy and update the headers. */
1171 memcpy(header, skb->data, st->header_len);
1173 tsoh_th->seq = htonl(st->seqnum);
1174 ((u8 *)tsoh_th)[13] &= ~tcp_flags_clear;
1176 ip_length = st->ip_base_len + st->packet_space;
1178 if (st->protocol == htons(ETH_P_IP)) {
1179 struct iphdr *tsoh_iph =
1180 (struct iphdr *)(header + st->ip_off);
1182 tsoh_iph->tot_len = htons(ip_length);
1183 tsoh_iph->id = htons(st->ipv4_id);
1185 struct ipv6hdr *tsoh_iph =
1186 (struct ipv6hdr *)(header + st->ip_off);
1188 tsoh_iph->payload_len = htons(ip_length);
1191 rc = efx_tso_put_header(tx_queue, buffer, header);
1195 /* Send the original headers with a TSO option descriptor
1198 u8 tcp_flags = ((u8 *)tcp_hdr(skb))[13] & ~tcp_flags_clear;
1200 buffer->flags = EFX_TX_BUF_OPTION;
1202 buffer->unmap_len = 0;
1203 EFX_POPULATE_QWORD_5(buffer->option,
1204 ESF_DZ_TX_DESC_IS_OPT, 1,
1205 ESF_DZ_TX_OPTION_TYPE,
1206 ESE_DZ_TX_OPTION_DESC_TSO,
1207 ESF_DZ_TX_TSO_TCP_FLAGS, tcp_flags,
1208 ESF_DZ_TX_TSO_IP_ID, st->ipv4_id,
1209 ESF_DZ_TX_TSO_TCP_SEQNO, st->seqnum);
1210 ++tx_queue->insert_count;
1212 /* We mapped the headers in tso_start(). Unmap them
1213 * when the last segment is completed.
1215 buffer = efx_tx_queue_get_insert_buffer(tx_queue);
1216 buffer->dma_addr = st->header_dma_addr;
1217 buffer->len = st->header_len;
1219 buffer->flags = EFX_TX_BUF_CONT | EFX_TX_BUF_MAP_SINGLE;
1220 buffer->unmap_len = st->header_unmap_len;
1221 buffer->dma_offset = 0;
1222 /* Ensure we only unmap them once in case of a
1223 * later DMA mapping error and rollback
1225 st->header_unmap_len = 0;
1227 buffer->flags = EFX_TX_BUF_CONT;
1228 buffer->unmap_len = 0;
1230 ++tx_queue->insert_count;
1233 st->seqnum += skb_shinfo(skb)->gso_size;
1235 /* Linux leaves suitable gaps in the IP ID space for us to fill. */
1238 ++tx_queue->tso_packets;
1240 ++tx_queue->tx_packets;
1247 * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
1248 * @tx_queue: Efx TX queue
1249 * @skb: Socket buffer
1251 * Context: You must hold netif_tx_lock() to call this function.
1253 * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
1254 * @skb was not enqueued. In all cases @skb is consumed. Return
1257 static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
1258 struct sk_buff *skb)
1260 struct efx_nic *efx = tx_queue->efx;
1262 struct tso_state state;
1264 /* Find the packet protocol and sanity-check it */
1265 state.protocol = efx_tso_check_protocol(skb);
1267 EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
1269 rc = tso_start(&state, efx, skb);
1273 if (likely(state.in_len == 0)) {
1274 /* Grab the first payload fragment. */
1275 EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
1277 rc = tso_get_fragment(&state, efx,
1278 skb_shinfo(skb)->frags + frag_i);
1282 /* Payload starts in the header area. */
1286 if (tso_start_new_packet(tx_queue, skb, &state) < 0)
1290 tso_fill_packet_with_fragment(tx_queue, skb, &state);
1292 /* Move onto the next fragment? */
1293 if (state.in_len == 0) {
1294 if (++frag_i >= skb_shinfo(skb)->nr_frags)
1295 /* End of payload reached. */
1297 rc = tso_get_fragment(&state, efx,
1298 skb_shinfo(skb)->frags + frag_i);
1303 /* Start at new packet? */
1304 if (state.packet_space == 0 &&
1305 tso_start_new_packet(tx_queue, skb, &state) < 0)
1309 netdev_tx_sent_queue(tx_queue->core_txq, skb->len);
1311 /* Pass off to hardware */
1312 efx_nic_push_buffers(tx_queue);
1314 efx_tx_maybe_stop_queue(tx_queue);
1316 tx_queue->tso_bursts++;
1317 return NETDEV_TX_OK;
1320 netif_err(efx, tx_err, efx->net_dev,
1321 "Out of memory for TSO headers, or DMA mapping error\n");
1322 dev_kfree_skb_any(skb);
1324 /* Free the DMA mapping we were in the process of writing out */
1325 if (state.unmap_len) {
1326 if (state.dma_flags & EFX_TX_BUF_MAP_SINGLE)
1327 dma_unmap_single(&efx->pci_dev->dev, state.unmap_addr,
1328 state.unmap_len, DMA_TO_DEVICE);
1330 dma_unmap_page(&efx->pci_dev->dev, state.unmap_addr,
1331 state.unmap_len, DMA_TO_DEVICE);
1334 /* Free the header DMA mapping, if using option descriptors */
1335 if (state.header_unmap_len)
1336 dma_unmap_single(&efx->pci_dev->dev, state.header_dma_addr,
1337 state.header_unmap_len, DMA_TO_DEVICE);
1339 efx_enqueue_unwind(tx_queue);
1340 return NETDEV_TX_OK;