1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2013 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ethtool.h>
19 #include <linux/if_vlan.h>
20 #include <linux/timer.h>
21 #include <linux/mdio.h>
22 #include <linux/list.h>
23 #include <linux/pci.h>
24 #include <linux/device.h>
25 #include <linux/highmem.h>
26 #include <linux/workqueue.h>
27 #include <linux/mutex.h>
28 #include <linux/rwsem.h>
29 #include <linux/vmalloc.h>
30 #include <linux/i2c.h>
31 #include <linux/mtd/mtd.h>
32 #include <net/busy_poll.h>
38 /**************************************************************************
42 **************************************************************************/
44 #define EFX_DRIVER_VERSION "4.1"
47 #define EFX_WARN_ON_ONCE_PARANOID(x) WARN_ON_ONCE(x)
48 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
50 #define EFX_WARN_ON_ONCE_PARANOID(x) do {} while (0)
51 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
54 /**************************************************************************
58 **************************************************************************/
60 #define EFX_MAX_CHANNELS 32U
61 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
62 #define EFX_EXTRA_CHANNEL_IOV 0
63 #define EFX_EXTRA_CHANNEL_PTP 1
64 #define EFX_MAX_EXTRA_CHANNELS 2U
66 /* Checksum generation is a per-queue option in hardware, so each
67 * queue visible to the networking core is backed by two hardware TX
69 #define EFX_MAX_TX_TC 2
70 #define EFX_MAX_CORE_TX_QUEUES (EFX_MAX_TX_TC * EFX_MAX_CHANNELS)
71 #define EFX_TXQ_TYPE_OFFLOAD 1 /* flag */
72 #define EFX_TXQ_TYPE_HIGHPRI 2 /* flag */
73 #define EFX_TXQ_TYPES 4
74 #define EFX_MAX_TX_QUEUES (EFX_TXQ_TYPES * EFX_MAX_CHANNELS)
76 /* Maximum possible MTU the driver supports */
77 #define EFX_MAX_MTU (9 * 1024)
79 /* Minimum MTU, from RFC791 (IP) */
80 #define EFX_MIN_MTU 68
82 /* Size of an RX scatter buffer. Small enough to pack 2 into a 4K page,
83 * and should be a multiple of the cache line size.
85 #define EFX_RX_USR_BUF_SIZE (2048 - 256)
87 /* If possible, we should ensure cache line alignment at start and end
88 * of every buffer. Otherwise, we just need to ensure 4-byte
89 * alignment of the network header.
92 #define EFX_RX_BUF_ALIGNMENT L1_CACHE_BYTES
94 #define EFX_RX_BUF_ALIGNMENT 4
97 /* Forward declare Precision Time Protocol (PTP) support structure. */
99 struct hwtstamp_config;
101 struct efx_self_tests;
104 * struct efx_buffer - A general-purpose DMA buffer
105 * @addr: host base address of the buffer
106 * @dma_addr: DMA base address of the buffer
107 * @len: Buffer length, in bytes
109 * The NIC uses these buffers for its interrupt status registers and
119 * struct efx_special_buffer - DMA buffer entered into buffer table
120 * @buf: Standard &struct efx_buffer
121 * @index: Buffer index within controller;s buffer table
122 * @entries: Number of buffer table entries
124 * The NIC has a buffer table that maps buffers of size %EFX_BUF_SIZE.
125 * Event and descriptor rings are addressed via one or more buffer
126 * table entries (and so can be physically non-contiguous, although we
127 * currently do not take advantage of that). On Falcon and Siena we
128 * have to take care of allocating and initialising the entries
129 * ourselves. On later hardware this is managed by the firmware and
130 * @index and @entries are left as 0.
132 struct efx_special_buffer {
133 struct efx_buffer buf;
135 unsigned int entries;
139 * struct efx_tx_buffer - buffer state for a TX descriptor
140 * @skb: When @flags & %EFX_TX_BUF_SKB, the associated socket buffer to be
141 * freed when descriptor completes
142 * @option: When @flags & %EFX_TX_BUF_OPTION, a NIC-specific option descriptor.
143 * @dma_addr: DMA address of the fragment.
144 * @flags: Flags for allocation and DMA mapping type
145 * @len: Length of this fragment.
146 * This field is zero when the queue slot is empty.
147 * @unmap_len: Length of this fragment to unmap
148 * @dma_offset: Offset of @dma_addr from the address of the backing DMA mapping.
149 * Only valid if @unmap_len != 0.
151 struct efx_tx_buffer {
152 const struct sk_buff *skb;
157 unsigned short flags;
159 unsigned short unmap_len;
160 unsigned short dma_offset;
162 #define EFX_TX_BUF_CONT 1 /* not last descriptor of packet */
163 #define EFX_TX_BUF_SKB 2 /* buffer is last part of skb */
164 #define EFX_TX_BUF_MAP_SINGLE 8 /* buffer was mapped with dma_map_single() */
165 #define EFX_TX_BUF_OPTION 0x10 /* empty buffer for option descriptor */
168 * struct efx_tx_queue - An Efx TX queue
170 * This is a ring buffer of TX fragments.
171 * Since the TX completion path always executes on the same
172 * CPU and the xmit path can operate on different CPUs,
173 * performance is increased by ensuring that the completion
174 * path and the xmit path operate on different cache lines.
175 * This is particularly important if the xmit path is always
176 * executing on one CPU which is different from the completion
177 * path. There is also a cache line for members which are
178 * read but not written on the fast path.
180 * @efx: The associated Efx NIC
181 * @queue: DMA queue number
182 * @tso_version: Version of TSO in use for this queue.
183 * @channel: The associated channel
184 * @core_txq: The networking core TX queue structure
185 * @buffer: The software buffer ring
186 * @cb_page: Array of pages of copy buffers. Carved up according to
187 * %EFX_TX_CB_ORDER into %EFX_TX_CB_SIZE-sized chunks.
188 * @txd: The hardware descriptor ring
189 * @ptr_mask: The size of the ring minus 1.
190 * @piobuf: PIO buffer region for this TX queue (shared with its partner).
191 * Size of the region is efx_piobuf_size.
192 * @piobuf_offset: Buffer offset to be specified in PIO descriptors
193 * @initialised: Has hardware queue been initialised?
194 * @handle_tso: TSO xmit preparation handler. Sets up the TSO metadata and
195 * may also map tx data, depending on the nature of the TSO implementation.
196 * @read_count: Current read pointer.
197 * This is the number of buffers that have been removed from both rings.
198 * @old_write_count: The value of @write_count when last checked.
199 * This is here for performance reasons. The xmit path will
200 * only get the up-to-date value of @write_count if this
201 * variable indicates that the queue is empty. This is to
202 * avoid cache-line ping-pong between the xmit path and the
204 * @merge_events: Number of TX merged completion events
205 * @insert_count: Current insert pointer
206 * This is the number of buffers that have been added to the
208 * @write_count: Current write pointer
209 * This is the number of buffers that have been added to the
211 * @packet_write_count: Completable write pointer
212 * This is the write pointer of the last packet written.
213 * Normally this will equal @write_count, but as option descriptors
214 * don't produce completion events, they won't update this.
215 * Filled in iff @efx->type->option_descriptors; only used for PIO.
216 * Thus, this is written and used on EF10, and neither on farch.
217 * @old_read_count: The value of read_count when last checked.
218 * This is here for performance reasons. The xmit path will
219 * only get the up-to-date value of read_count if this
220 * variable indicates that the queue is full. This is to
221 * avoid cache-line ping-pong between the xmit path and the
223 * @tso_bursts: Number of times TSO xmit invoked by kernel
224 * @tso_long_headers: Number of packets with headers too long for standard
226 * @tso_packets: Number of packets via the TSO xmit path
227 * @tso_fallbacks: Number of times TSO fallback used
228 * @pushes: Number of times the TX push feature has been used
229 * @pio_packets: Number of times the TX PIO feature has been used
230 * @xmit_more_available: Are any packets waiting to be pushed to the NIC
231 * @cb_packets: Number of times the TX copybreak feature has been used
232 * @empty_read_count: If the completion path has seen the queue as empty
233 * and the transmission path has not yet checked this, the value of
234 * @read_count bitwise-added to %EFX_EMPTY_COUNT_VALID; otherwise 0.
236 struct efx_tx_queue {
237 /* Members which don't change on the fast path */
238 struct efx_nic *efx ____cacheline_aligned_in_smp;
240 unsigned int tso_version;
241 struct efx_channel *channel;
242 struct netdev_queue *core_txq;
243 struct efx_tx_buffer *buffer;
244 struct efx_buffer *cb_page;
245 struct efx_special_buffer txd;
246 unsigned int ptr_mask;
247 void __iomem *piobuf;
248 unsigned int piobuf_offset;
251 /* Function pointers used in the fast path. */
252 int (*handle_tso)(struct efx_tx_queue*, struct sk_buff*, bool *);
254 /* Members used mainly on the completion path */
255 unsigned int read_count ____cacheline_aligned_in_smp;
256 unsigned int old_write_count;
257 unsigned int merge_events;
258 unsigned int bytes_compl;
259 unsigned int pkts_compl;
261 /* Members used only on the xmit path */
262 unsigned int insert_count ____cacheline_aligned_in_smp;
263 unsigned int write_count;
264 unsigned int packet_write_count;
265 unsigned int old_read_count;
266 unsigned int tso_bursts;
267 unsigned int tso_long_headers;
268 unsigned int tso_packets;
269 unsigned int tso_fallbacks;
271 unsigned int pio_packets;
272 bool xmit_more_available;
273 unsigned int cb_packets;
274 /* Statistics to supplement MAC stats */
275 unsigned long tx_packets;
277 /* Members shared between paths and sometimes updated */
278 unsigned int empty_read_count ____cacheline_aligned_in_smp;
279 #define EFX_EMPTY_COUNT_VALID 0x80000000
280 atomic_t flush_outstanding;
283 #define EFX_TX_CB_ORDER 7
284 #define EFX_TX_CB_SIZE (1 << EFX_TX_CB_ORDER) - NET_IP_ALIGN
287 * struct efx_rx_buffer - An Efx RX data buffer
288 * @dma_addr: DMA base address of the buffer
289 * @page: The associated page buffer.
290 * Will be %NULL if the buffer slot is currently free.
291 * @page_offset: If pending: offset in @page of DMA base address.
292 * If completed: offset in @page of Ethernet header.
293 * @len: If pending: length for DMA descriptor.
294 * If completed: received length, excluding hash prefix.
295 * @flags: Flags for buffer and packet state. These are only set on the
296 * first buffer of a scattered packet.
298 struct efx_rx_buffer {
305 #define EFX_RX_BUF_LAST_IN_PAGE 0x0001
306 #define EFX_RX_PKT_CSUMMED 0x0002
307 #define EFX_RX_PKT_DISCARD 0x0004
308 #define EFX_RX_PKT_TCP 0x0040
309 #define EFX_RX_PKT_PREFIX_LEN 0x0080 /* length is in prefix only */
310 #define EFX_RX_PKT_CSUM_LEVEL 0x0200
313 * struct efx_rx_page_state - Page-based rx buffer state
315 * Inserted at the start of every page allocated for receive buffers.
316 * Used to facilitate sharing dma mappings between recycled rx buffers
317 * and those passed up to the kernel.
319 * @dma_addr: The dma address of this page.
321 struct efx_rx_page_state {
324 unsigned int __pad[0] ____cacheline_aligned;
328 * struct efx_rx_queue - An Efx RX queue
329 * @efx: The associated Efx NIC
330 * @core_index: Index of network core RX queue. Will be >= 0 iff this
331 * is associated with a real RX queue.
332 * @buffer: The software buffer ring
333 * @rxd: The hardware descriptor ring
334 * @ptr_mask: The size of the ring minus 1.
335 * @refill_enabled: Enable refill whenever fill level is low
336 * @flush_pending: Set when a RX flush is pending. Has the same lifetime as
337 * @rxq_flush_pending.
338 * @added_count: Number of buffers added to the receive queue.
339 * @notified_count: Number of buffers given to NIC (<= @added_count).
340 * @removed_count: Number of buffers removed from the receive queue.
341 * @scatter_n: Used by NIC specific receive code.
342 * @scatter_len: Used by NIC specific receive code.
343 * @page_ring: The ring to store DMA mapped pages for reuse.
344 * @page_add: Counter to calculate the write pointer for the recycle ring.
345 * @page_remove: Counter to calculate the read pointer for the recycle ring.
346 * @page_recycle_count: The number of pages that have been recycled.
347 * @page_recycle_failed: The number of pages that couldn't be recycled because
348 * the kernel still held a reference to them.
349 * @page_recycle_full: The number of pages that were released because the
350 * recycle ring was full.
351 * @page_ptr_mask: The number of pages in the RX recycle ring minus 1.
352 * @max_fill: RX descriptor maximum fill level (<= ring size)
353 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
355 * @min_fill: RX descriptor minimum non-zero fill level.
356 * This records the minimum fill level observed when a ring
357 * refill was triggered.
358 * @recycle_count: RX buffer recycle counter.
359 * @slow_fill: Timer used to defer efx_nic_generate_fill_event().
361 struct efx_rx_queue {
364 struct efx_rx_buffer *buffer;
365 struct efx_special_buffer rxd;
366 unsigned int ptr_mask;
370 unsigned int added_count;
371 unsigned int notified_count;
372 unsigned int removed_count;
373 unsigned int scatter_n;
374 unsigned int scatter_len;
375 struct page **page_ring;
376 unsigned int page_add;
377 unsigned int page_remove;
378 unsigned int page_recycle_count;
379 unsigned int page_recycle_failed;
380 unsigned int page_recycle_full;
381 unsigned int page_ptr_mask;
382 unsigned int max_fill;
383 unsigned int fast_fill_trigger;
384 unsigned int min_fill;
385 unsigned int min_overfill;
386 unsigned int recycle_count;
387 struct timer_list slow_fill;
388 unsigned int slow_fill_count;
389 /* Statistics to supplement MAC stats */
390 unsigned long rx_packets;
393 enum efx_sync_events_state {
394 SYNC_EVENTS_DISABLED = 0,
395 SYNC_EVENTS_QUIESCENT,
396 SYNC_EVENTS_REQUESTED,
401 * struct efx_channel - An Efx channel
403 * A channel comprises an event queue, at least one TX queue, at least
404 * one RX queue, and an associated tasklet for processing the event
407 * @efx: Associated Efx NIC
408 * @channel: Channel instance number
409 * @type: Channel type definition
410 * @eventq_init: Event queue initialised flag
411 * @enabled: Channel enabled indicator
412 * @irq: IRQ number (MSI and MSI-X only)
413 * @irq_moderation_us: IRQ moderation value (in microseconds)
414 * @napi_dev: Net device used with NAPI
415 * @napi_str: NAPI control structure
416 * @state: state for NAPI vs busy polling
417 * @state_lock: lock protecting @state
418 * @eventq: Event queue buffer
419 * @eventq_mask: Event queue pointer mask
420 * @eventq_read_ptr: Event queue read pointer
421 * @event_test_cpu: Last CPU to handle interrupt or test event for this channel
422 * @irq_count: Number of IRQs since last adaptive moderation decision
423 * @irq_mod_score: IRQ moderation score
424 * @rps_flow_id: Flow IDs of filters allocated for accelerated RFS,
425 * indexed by filter ID
426 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
427 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
428 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
429 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
430 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
431 * @n_rx_overlength: Count of RX_OVERLENGTH errors
432 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
433 * @n_rx_nodesc_trunc: Number of RX packets truncated and then dropped due to
434 * lack of descriptors
435 * @n_rx_merge_events: Number of RX merged completion events
436 * @n_rx_merge_packets: Number of RX packets completed by merged events
437 * @rx_pkt_n_frags: Number of fragments in next packet to be delivered by
438 * __efx_rx_packet(), or zero if there is none
439 * @rx_pkt_index: Ring index of first buffer for next packet to be delivered
440 * by __efx_rx_packet(), if @rx_pkt_n_frags != 0
441 * @rx_queue: RX queue for this channel
442 * @tx_queue: TX queues for this channel
443 * @sync_events_state: Current state of sync events on this channel
444 * @sync_timestamp_major: Major part of the last ptp sync event
445 * @sync_timestamp_minor: Minor part of the last ptp sync event
450 const struct efx_channel_type *type;
454 unsigned int irq_moderation_us;
455 struct net_device *napi_dev;
456 struct napi_struct napi_str;
457 #ifdef CONFIG_NET_RX_BUSY_POLL
458 unsigned long busy_poll_state;
460 struct efx_special_buffer eventq;
461 unsigned int eventq_mask;
462 unsigned int eventq_read_ptr;
465 unsigned int irq_count;
466 unsigned int irq_mod_score;
467 #ifdef CONFIG_RFS_ACCEL
468 unsigned int rfs_filters_added;
469 #define RPS_FLOW_ID_INVALID 0xFFFFFFFF
473 unsigned int n_rx_tobe_disc;
474 unsigned int n_rx_ip_hdr_chksum_err;
475 unsigned int n_rx_tcp_udp_chksum_err;
476 unsigned int n_rx_outer_ip_hdr_chksum_err;
477 unsigned int n_rx_outer_tcp_udp_chksum_err;
478 unsigned int n_rx_inner_ip_hdr_chksum_err;
479 unsigned int n_rx_inner_tcp_udp_chksum_err;
480 unsigned int n_rx_eth_crc_err;
481 unsigned int n_rx_mcast_mismatch;
482 unsigned int n_rx_frm_trunc;
483 unsigned int n_rx_overlength;
484 unsigned int n_skbuff_leaks;
485 unsigned int n_rx_nodesc_trunc;
486 unsigned int n_rx_merge_events;
487 unsigned int n_rx_merge_packets;
489 unsigned int rx_pkt_n_frags;
490 unsigned int rx_pkt_index;
492 struct efx_rx_queue rx_queue;
493 struct efx_tx_queue tx_queue[EFX_TXQ_TYPES];
495 enum efx_sync_events_state sync_events_state;
496 u32 sync_timestamp_major;
497 u32 sync_timestamp_minor;
501 * struct efx_msi_context - Context for each MSI
502 * @efx: The associated NIC
503 * @index: Index of the channel/IRQ
504 * @name: Name of the channel/IRQ
506 * Unlike &struct efx_channel, this is never reallocated and is always
507 * safe for the IRQ handler to access.
509 struct efx_msi_context {
512 char name[IFNAMSIZ + 6];
516 * struct efx_channel_type - distinguishes traffic and extra channels
517 * @handle_no_channel: Handle failure to allocate an extra channel
518 * @pre_probe: Set up extra state prior to initialisation
519 * @post_remove: Tear down extra state after finalisation, if allocated.
520 * May be called on channels that have not been probed.
521 * @get_name: Generate the channel's name (used for its IRQ handler)
522 * @copy: Copy the channel state prior to reallocation. May be %NULL if
523 * reallocation is not supported.
524 * @receive_skb: Handle an skb ready to be passed to netif_receive_skb()
525 * @keep_eventq: Flag for whether event queue should be kept initialised
526 * while the device is stopped
528 struct efx_channel_type {
529 void (*handle_no_channel)(struct efx_nic *);
530 int (*pre_probe)(struct efx_channel *);
531 void (*post_remove)(struct efx_channel *);
532 void (*get_name)(struct efx_channel *, char *buf, size_t len);
533 struct efx_channel *(*copy)(const struct efx_channel *);
534 bool (*receive_skb)(struct efx_channel *, struct sk_buff *);
544 #define STRING_TABLE_LOOKUP(val, member) \
545 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
547 extern const char *const efx_loopback_mode_names[];
548 extern const unsigned int efx_loopback_mode_max;
549 #define LOOPBACK_MODE(efx) \
550 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
552 extern const char *const efx_reset_type_names[];
553 extern const unsigned int efx_reset_type_max;
554 #define RESET_TYPE(type) \
555 STRING_TABLE_LOOKUP(type, efx_reset_type)
557 void efx_get_udp_tunnel_type_name(u16 type, char *buf, size_t buflen);
560 /* Be careful if altering to correct macro below */
561 EFX_INT_MODE_MSIX = 0,
562 EFX_INT_MODE_MSI = 1,
563 EFX_INT_MODE_LEGACY = 2,
564 EFX_INT_MODE_MAX /* Insert any new items before this */
566 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
569 STATE_UNINIT = 0, /* device being probed/removed or is frozen */
570 STATE_READY = 1, /* hardware ready and netdev registered */
571 STATE_DISABLED = 2, /* device disabled due to hardware errors */
572 STATE_RECOVERY = 3, /* device recovering from PCI error */
575 /* Forward declaration */
578 /* Pseudo bit-mask flow control field */
579 #define EFX_FC_RX FLOW_CTRL_RX
580 #define EFX_FC_TX FLOW_CTRL_TX
581 #define EFX_FC_AUTO 4
584 * struct efx_link_state - Current state of the link
586 * @fd: Link is full-duplex
587 * @fc: Actual flow control flags
588 * @speed: Link speed (Mbps)
590 struct efx_link_state {
597 static inline bool efx_link_state_equal(const struct efx_link_state *left,
598 const struct efx_link_state *right)
600 return left->up == right->up && left->fd == right->fd &&
601 left->fc == right->fc && left->speed == right->speed;
605 * struct efx_phy_operations - Efx PHY operations table
606 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
607 * efx->loopback_modes.
608 * @init: Initialise PHY
609 * @fini: Shut down PHY
610 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
611 * @poll: Update @link_state and report whether it changed.
612 * Serialised by the mac_lock.
613 * @get_link_ksettings: Get ethtool settings. Serialised by the mac_lock.
614 * @set_link_ksettings: Set ethtool settings. Serialised by the mac_lock.
615 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
616 * (only needed where AN bit is set in mmds)
617 * @test_alive: Test that PHY is 'alive' (online)
618 * @test_name: Get the name of a PHY-specific test/result
619 * @run_tests: Run tests and record results as appropriate (offline).
620 * Flags are the ethtool tests flags.
622 struct efx_phy_operations {
623 int (*probe) (struct efx_nic *efx);
624 int (*init) (struct efx_nic *efx);
625 void (*fini) (struct efx_nic *efx);
626 void (*remove) (struct efx_nic *efx);
627 int (*reconfigure) (struct efx_nic *efx);
628 bool (*poll) (struct efx_nic *efx);
629 void (*get_link_ksettings)(struct efx_nic *efx,
630 struct ethtool_link_ksettings *cmd);
631 int (*set_link_ksettings)(struct efx_nic *efx,
632 const struct ethtool_link_ksettings *cmd);
633 void (*set_npage_adv) (struct efx_nic *efx, u32);
634 int (*test_alive) (struct efx_nic *efx);
635 const char *(*test_name) (struct efx_nic *efx, unsigned int index);
636 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
637 int (*get_module_eeprom) (struct efx_nic *efx,
638 struct ethtool_eeprom *ee,
640 int (*get_module_info) (struct efx_nic *efx,
641 struct ethtool_modinfo *modinfo);
645 * enum efx_phy_mode - PHY operating mode flags
646 * @PHY_MODE_NORMAL: on and should pass traffic
647 * @PHY_MODE_TX_DISABLED: on with TX disabled
648 * @PHY_MODE_LOW_POWER: set to low power through MDIO
649 * @PHY_MODE_OFF: switched off through external control
650 * @PHY_MODE_SPECIAL: on but will not pass traffic
654 PHY_MODE_TX_DISABLED = 1,
655 PHY_MODE_LOW_POWER = 2,
657 PHY_MODE_SPECIAL = 8,
660 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
662 return !!(mode & ~PHY_MODE_TX_DISABLED);
666 * struct efx_hw_stat_desc - Description of a hardware statistic
667 * @name: Name of the statistic as visible through ethtool, or %NULL if
668 * it should not be exposed
669 * @dma_width: Width in bits (0 for non-DMA statistics)
670 * @offset: Offset within stats (ignored for non-DMA statistics)
672 struct efx_hw_stat_desc {
678 /* Number of bits used in a multicast filter hash address */
679 #define EFX_MCAST_HASH_BITS 8
681 /* Number of (single-bit) entries in a multicast filter hash */
682 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
684 /* An Efx multicast filter hash */
685 union efx_multicast_hash {
686 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
687 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
693 * struct efx_nic - an Efx NIC
694 * @name: Device name (net device name or bus id before net device registered)
695 * @pci_dev: The PCI device
696 * @node: List node for maintaning primary/secondary function lists
697 * @primary: &struct efx_nic instance for the primary function of this
698 * controller. May be the same structure, and may be %NULL if no
699 * primary function is bound. Serialised by rtnl_lock.
700 * @secondary_list: List of &struct efx_nic instances for the secondary PCI
701 * functions of the controller, if this is for the primary function.
702 * Serialised by rtnl_lock.
703 * @type: Controller type attributes
704 * @legacy_irq: IRQ number
705 * @workqueue: Workqueue for port reconfigures and the HW monitor.
706 * Work items do not hold and must not acquire RTNL.
707 * @workqueue_name: Name of workqueue
708 * @reset_work: Scheduled reset workitem
709 * @membase_phys: Memory BAR value as physical address
710 * @membase: Memory BAR value
711 * @interrupt_mode: Interrupt mode
712 * @timer_quantum_ns: Interrupt timer quantum, in nanoseconds
713 * @timer_max_ns: Interrupt timer maximum value, in nanoseconds
714 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
715 * @irq_rx_mod_step_us: Step size for IRQ moderation for RX event queues
716 * @irq_rx_moderation_us: IRQ moderation time for RX event queues
717 * @msg_enable: Log message enable flags
718 * @state: Device state number (%STATE_*). Serialised by the rtnl_lock.
719 * @reset_pending: Bitmask for pending resets
720 * @tx_queue: TX DMA queues
721 * @rx_queue: RX DMA queues
723 * @msi_context: Context for each MSI
724 * @extra_channel_types: Types of extra (non-traffic) channels that
725 * should be allocated for this NIC
726 * @rxq_entries: Size of receive queues requested by user.
727 * @txq_entries: Size of transmit queues requested by user.
728 * @txq_stop_thresh: TX queue fill level at or above which we stop it.
729 * @txq_wake_thresh: TX queue fill level at or below which we wake it.
730 * @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
731 * @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
732 * @sram_lim_qw: Qword address limit of SRAM
733 * @next_buffer_table: First available buffer table id
734 * @n_channels: Number of channels in use
735 * @n_rx_channels: Number of channels used for RX (= number of RX queues)
736 * @n_tx_channels: Number of channels used for TX
737 * @rx_ip_align: RX DMA address offset to have IP header aligned in
738 * in accordance with NET_IP_ALIGN
739 * @rx_dma_len: Current maximum RX DMA length
740 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
741 * @rx_buffer_truesize: Amortised allocation size of an RX buffer,
742 * for use in sk_buff::truesize
743 * @rx_prefix_size: Size of RX prefix before packet data
744 * @rx_packet_hash_offset: Offset of RX flow hash from start of packet data
745 * (valid only if @rx_prefix_size != 0; always negative)
746 * @rx_packet_len_offset: Offset of RX packet length from start of packet data
747 * (valid only for NICs that set %EFX_RX_PKT_PREFIX_LEN; always negative)
748 * @rx_packet_ts_offset: Offset of timestamp from start of packet data
749 * (valid only if channel->sync_timestamps_enabled; always negative)
750 * @rx_hash_key: Toeplitz hash key for RSS
751 * @rx_indir_table: Indirection table for RSS
752 * @rx_scatter: Scatter mode enabled for receives
753 * @rss_active: RSS enabled on hardware
754 * @rx_hash_udp_4tuple: UDP 4-tuple hashing enabled
755 * @int_error_count: Number of internal errors seen recently
756 * @int_error_expire: Time at which error count will be expired
757 * @irq_soft_enabled: Are IRQs soft-enabled? If not, IRQ handler will
758 * acknowledge but do nothing else.
759 * @irq_status: Interrupt status buffer
760 * @irq_zero_count: Number of legacy IRQs seen with queue flags == 0
761 * @irq_level: IRQ level/index for IRQs not triggered by an event queue
762 * @selftest_work: Work item for asynchronous self-test
763 * @mtd_list: List of MTDs attached to the NIC
764 * @nic_data: Hardware dependent state
765 * @mcdi: Management-Controller-to-Driver Interface state
766 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
767 * efx_monitor() and efx_reconfigure_port()
768 * @port_enabled: Port enabled indicator.
769 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
770 * efx_mac_work() with kernel interfaces. Safe to read under any
771 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
772 * be held to modify it.
773 * @port_initialized: Port initialized?
774 * @net_dev: Operating system network device. Consider holding the rtnl lock
775 * @fixed_features: Features which cannot be turned off
776 * @stats_buffer: DMA buffer for statistics
777 * @phy_type: PHY type
778 * @phy_op: PHY interface
779 * @phy_data: PHY private data (including PHY-specific stats)
780 * @mdio: PHY MDIO interface
781 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
782 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
783 * @link_advertising: Autonegotiation advertising flags
784 * @link_state: Current state of the link
785 * @n_link_state_changes: Number of times the link has changed state
786 * @unicast_filter: Flag for Falcon-arch simple unicast filter.
787 * Protected by @mac_lock.
788 * @multicast_hash: Multicast hash table for Falcon-arch.
789 * Protected by @mac_lock.
790 * @wanted_fc: Wanted flow control flags
791 * @fc_disable: When non-zero flow control is disabled. Typically used to
792 * ensure that network back pressure doesn't delay dma queue flushes.
793 * Serialised by the rtnl lock.
794 * @mac_work: Work item for changing MAC promiscuity and multicast hash
795 * @loopback_mode: Loopback status
796 * @loopback_modes: Supported loopback mode bitmask
797 * @loopback_selftest: Offline self-test private state
798 * @filter_sem: Filter table rw_semaphore, for freeing the table
799 * @filter_lock: Filter table lock, for mere content changes
800 * @filter_state: Architecture-dependent filter table state
801 * @rps_expire_channel: Next channel to check for expiry
802 * @rps_expire_index: Next index to check for expiry in
803 * @rps_expire_channel's @rps_flow_id
804 * @active_queues: Count of RX and TX queues that haven't been flushed and drained.
805 * @rxq_flush_pending: Count of number of receive queues that need to be flushed.
806 * Decremented when the efx_flush_rx_queue() is called.
807 * @rxq_flush_outstanding: Count of number of RX flushes started but not yet
808 * completed (either success or failure). Not used when MCDI is used to
809 * flush receive queues.
810 * @flush_wq: wait queue used by efx_nic_flush_queues() to wait for flush completions.
811 * @vf_count: Number of VFs intended to be enabled.
812 * @vf_init_count: Number of VFs that have been fully initialised.
813 * @vi_scale: log2 number of vnics per VF.
814 * @ptp_data: PTP state data
815 * @vpd_sn: Serial number read from VPD
816 * @monitor_work: Hardware monitor workitem
817 * @biu_lock: BIU (bus interface unit) lock
818 * @last_irq_cpu: Last CPU to handle a possible test interrupt. This
819 * field is used by efx_test_interrupts() to verify that an
820 * interrupt has occurred.
821 * @stats_lock: Statistics update lock. Must be held when calling
822 * efx_nic_type::{update,start,stop}_stats.
823 * @n_rx_noskb_drops: Count of RX packets dropped due to failure to allocate an skb
825 * This is stored in the private area of the &struct net_device.
828 /* The following fields should be written very rarely */
831 struct list_head node;
832 struct efx_nic *primary;
833 struct list_head secondary_list;
834 struct pci_dev *pci_dev;
835 unsigned int port_num;
836 const struct efx_nic_type *type;
838 bool eeh_disabled_legacy_irq;
839 struct workqueue_struct *workqueue;
840 char workqueue_name[16];
841 struct work_struct reset_work;
842 resource_size_t membase_phys;
843 void __iomem *membase;
845 enum efx_int_mode interrupt_mode;
846 unsigned int timer_quantum_ns;
847 unsigned int timer_max_ns;
848 bool irq_rx_adaptive;
849 unsigned int irq_mod_step_us;
850 unsigned int irq_rx_moderation_us;
853 enum nic_state state;
854 unsigned long reset_pending;
856 struct efx_channel *channel[EFX_MAX_CHANNELS];
857 struct efx_msi_context msi_context[EFX_MAX_CHANNELS];
858 const struct efx_channel_type *
859 extra_channel_type[EFX_MAX_EXTRA_CHANNELS];
861 unsigned rxq_entries;
862 unsigned txq_entries;
863 unsigned int txq_stop_thresh;
864 unsigned int txq_wake_thresh;
868 unsigned sram_lim_qw;
869 unsigned next_buffer_table;
871 unsigned int max_channels;
872 unsigned int max_tx_channels;
874 unsigned n_rx_channels;
876 unsigned tx_channel_offset;
877 unsigned n_tx_channels;
878 unsigned int rx_ip_align;
879 unsigned int rx_dma_len;
880 unsigned int rx_buffer_order;
881 unsigned int rx_buffer_truesize;
882 unsigned int rx_page_buf_step;
883 unsigned int rx_bufs_per_page;
884 unsigned int rx_pages_per_batch;
885 unsigned int rx_prefix_size;
886 int rx_packet_hash_offset;
887 int rx_packet_len_offset;
888 int rx_packet_ts_offset;
890 u32 rx_indir_table[128];
893 bool rx_hash_udp_4tuple;
895 unsigned int_error_count;
896 unsigned long int_error_expire;
898 bool irq_soft_enabled;
899 struct efx_buffer irq_status;
900 unsigned irq_zero_count;
902 struct delayed_work selftest_work;
904 #ifdef CONFIG_SFC_MTD
905 struct list_head mtd_list;
909 struct efx_mcdi_data *mcdi;
911 struct mutex mac_lock;
912 struct work_struct mac_work;
915 bool mc_bist_for_other_fn;
916 bool port_initialized;
917 struct net_device *net_dev;
919 netdev_features_t fixed_features;
921 struct efx_buffer stats_buffer;
922 u64 rx_nodesc_drops_total;
923 u64 rx_nodesc_drops_while_down;
924 bool rx_nodesc_drops_prev_state;
926 unsigned int phy_type;
927 const struct efx_phy_operations *phy_op;
929 struct mdio_if_info mdio;
930 unsigned int mdio_bus;
931 enum efx_phy_mode phy_mode;
933 u32 link_advertising;
934 struct efx_link_state link_state;
935 unsigned int n_link_state_changes;
938 union efx_multicast_hash multicast_hash;
943 enum efx_loopback_mode loopback_mode;
946 void *loopback_selftest;
948 struct rw_semaphore filter_sem;
949 spinlock_t filter_lock;
951 #ifdef CONFIG_RFS_ACCEL
952 unsigned int rps_expire_channel;
953 unsigned int rps_expire_index;
956 atomic_t active_queues;
957 atomic_t rxq_flush_pending;
958 atomic_t rxq_flush_outstanding;
959 wait_queue_head_t flush_wq;
961 #ifdef CONFIG_SFC_SRIOV
963 unsigned vf_init_count;
967 struct efx_ptp_data *ptp_data;
971 /* The following fields may be written more often */
973 struct delayed_work monitor_work ____cacheline_aligned_in_smp;
976 spinlock_t stats_lock;
977 atomic_t n_rx_noskb_drops;
980 static inline int efx_dev_registered(struct efx_nic *efx)
982 return efx->net_dev->reg_state == NETREG_REGISTERED;
985 static inline unsigned int efx_port_num(struct efx_nic *efx)
987 return efx->port_num;
990 struct efx_mtd_partition {
991 struct list_head node;
993 const char *dev_type_name;
994 const char *type_name;
995 char name[IFNAMSIZ + 20];
998 struct efx_udp_tunnel {
999 u16 type; /* TUNNEL_ENCAP_UDP_PORT_ENTRY_foo, see mcdi_pcol.h */
1001 /* Count of repeated adds of the same port. Used only inside the list,
1002 * not in request arguments.
1008 * struct efx_nic_type - Efx device type definition
1009 * @mem_bar: Get the memory BAR
1010 * @mem_map_size: Get memory BAR mapped size
1011 * @probe: Probe the controller
1012 * @remove: Free resources allocated by probe()
1013 * @init: Initialise the controller
1014 * @dimension_resources: Dimension controller resources (buffer table,
1015 * and VIs once the available interrupt resources are clear)
1016 * @fini: Shut down the controller
1017 * @monitor: Periodic function for polling link state and hardware monitor
1018 * @map_reset_reason: Map ethtool reset reason to a reset method
1019 * @map_reset_flags: Map ethtool reset flags to a reset method, if possible
1020 * @reset: Reset the controller hardware and possibly the PHY. This will
1021 * be called while the controller is uninitialised.
1022 * @probe_port: Probe the MAC and PHY
1023 * @remove_port: Free resources allocated by probe_port()
1024 * @handle_global_event: Handle a "global" event (may be %NULL)
1025 * @fini_dmaq: Flush and finalise DMA queues (RX and TX queues)
1026 * @prepare_flush: Prepare the hardware for flushing the DMA queues
1027 * (for Falcon architecture)
1028 * @finish_flush: Clean up after flushing the DMA queues (for Falcon
1030 * @prepare_flr: Prepare for an FLR
1031 * @finish_flr: Clean up after an FLR
1032 * @describe_stats: Describe statistics for ethtool
1033 * @update_stats: Update statistics not provided by event handling.
1034 * Either argument may be %NULL.
1035 * @start_stats: Start the regular fetching of statistics
1036 * @pull_stats: Pull stats from the NIC and wait until they arrive.
1037 * @stop_stats: Stop the regular fetching of statistics
1038 * @set_id_led: Set state of identifying LED or revert to automatic function
1039 * @push_irq_moderation: Apply interrupt moderation value
1040 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
1041 * @prepare_enable_fc_tx: Prepare MAC to enable pause frame TX (may be %NULL)
1042 * @reconfigure_mac: Push MAC address, MTU, flow control and filter settings
1043 * to the hardware. Serialised by the mac_lock.
1044 * @check_mac_fault: Check MAC fault state. True if fault present.
1045 * @get_wol: Get WoL configuration from driver state
1046 * @set_wol: Push WoL configuration to the NIC
1047 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
1048 * @test_chip: Test registers. May use efx_farch_test_registers(), and is
1049 * expected to reset the NIC.
1050 * @test_nvram: Test validity of NVRAM contents
1051 * @mcdi_request: Send an MCDI request with the given header and SDU.
1052 * The SDU length may be any value from 0 up to the protocol-
1053 * defined maximum, but its buffer will be padded to a multiple
1055 * @mcdi_poll_response: Test whether an MCDI response is available.
1056 * @mcdi_read_response: Read the MCDI response PDU. The offset will
1057 * be a multiple of 4. The length may not be, but the buffer
1058 * will be padded so it is safe to round up.
1059 * @mcdi_poll_reboot: Test whether the MCDI has rebooted. If so,
1060 * return an appropriate error code for aborting any current
1061 * request; otherwise return 0.
1062 * @irq_enable_master: Enable IRQs on the NIC. Each event queue must
1063 * be separately enabled after this.
1064 * @irq_test_generate: Generate a test IRQ
1065 * @irq_disable_non_ev: Disable non-event IRQs on the NIC. Each event
1066 * queue must be separately disabled before this.
1067 * @irq_handle_msi: Handle MSI for a channel. The @dev_id argument is
1068 * a pointer to the &struct efx_msi_context for the channel.
1069 * @irq_handle_legacy: Handle legacy interrupt. The @dev_id argument
1070 * is a pointer to the &struct efx_nic.
1071 * @tx_probe: Allocate resources for TX queue
1072 * @tx_init: Initialise TX queue on the NIC
1073 * @tx_remove: Free resources for TX queue
1074 * @tx_write: Write TX descriptors and doorbell
1075 * @rx_push_rss_config: Write RSS hash key and indirection table to the NIC
1076 * @rx_pull_rss_config: Read RSS hash key and indirection table back from the NIC
1077 * @rx_probe: Allocate resources for RX queue
1078 * @rx_init: Initialise RX queue on the NIC
1079 * @rx_remove: Free resources for RX queue
1080 * @rx_write: Write RX descriptors and doorbell
1081 * @rx_defer_refill: Generate a refill reminder event
1082 * @ev_probe: Allocate resources for event queue
1083 * @ev_init: Initialise event queue on the NIC
1084 * @ev_fini: Deinitialise event queue on the NIC
1085 * @ev_remove: Free resources for event queue
1086 * @ev_process: Process events for a queue, up to the given NAPI quota
1087 * @ev_read_ack: Acknowledge read events on a queue, rearming its IRQ
1088 * @ev_test_generate: Generate a test event
1089 * @filter_table_probe: Probe filter capabilities and set up filter software state
1090 * @filter_table_restore: Restore filters removed from hardware
1091 * @filter_table_remove: Remove filters from hardware and tear down software state
1092 * @filter_update_rx_scatter: Update filters after change to rx scatter setting
1093 * @filter_insert: add or replace a filter
1094 * @filter_remove_safe: remove a filter by ID, carefully
1095 * @filter_get_safe: retrieve a filter by ID, carefully
1096 * @filter_clear_rx: Remove all RX filters whose priority is less than or
1097 * equal to the given priority and is not %EFX_FILTER_PRI_AUTO
1098 * @filter_count_rx_used: Get the number of filters in use at a given priority
1099 * @filter_get_rx_id_limit: Get maximum value of a filter id, plus 1
1100 * @filter_get_rx_ids: Get list of RX filters at a given priority
1101 * @filter_rfs_insert: Add or replace a filter for RFS. This must be
1102 * atomic. The hardware change may be asynchronous but should
1103 * not be delayed for long. It may fail if this can't be done
1105 * @filter_rfs_expire_one: Consider expiring a filter inserted for RFS.
1106 * This must check whether the specified table entry is used by RFS
1107 * and that rps_may_expire_flow() returns true for it.
1108 * @mtd_probe: Probe and add MTD partitions associated with this net device,
1109 * using efx_mtd_add()
1110 * @mtd_rename: Set an MTD partition name using the net device name
1111 * @mtd_read: Read from an MTD partition
1112 * @mtd_erase: Erase part of an MTD partition
1113 * @mtd_write: Write to an MTD partition
1114 * @mtd_sync: Wait for write-back to complete on MTD partition. This
1115 * also notifies the driver that a writer has finished using this
1117 * @ptp_write_host_time: Send host time to MC as part of sync protocol
1118 * @ptp_set_ts_sync_events: Enable or disable sync events for inline RX
1119 * timestamping, possibly only temporarily for the purposes of a reset.
1120 * @ptp_set_ts_config: Set hardware timestamp configuration. The flags
1121 * and tx_type will already have been validated but this operation
1122 * must validate and update rx_filter.
1123 * @get_phys_port_id: Get the underlying physical port id.
1124 * @set_mac_address: Set the MAC address of the device
1125 * @tso_versions: Returns mask of firmware-assisted TSO versions supported.
1126 * If %NULL, then device does not support any TSO version.
1127 * @udp_tnl_push_ports: Push the list of UDP tunnel ports to the NIC if required.
1128 * @udp_tnl_add_port: Add a UDP tunnel port
1129 * @udp_tnl_has_port: Check if a port has been added as UDP tunnel
1130 * @udp_tnl_del_port: Remove a UDP tunnel port
1131 * @revision: Hardware architecture revision
1132 * @txd_ptr_tbl_base: TX descriptor ring base address
1133 * @rxd_ptr_tbl_base: RX descriptor ring base address
1134 * @buf_tbl_base: Buffer table base address
1135 * @evq_ptr_tbl_base: Event queue pointer table base address
1136 * @evq_rptr_tbl_base: Event queue read-pointer table base address
1137 * @max_dma_mask: Maximum possible DMA mask
1138 * @rx_prefix_size: Size of RX prefix before packet data
1139 * @rx_hash_offset: Offset of RX flow hash within prefix
1140 * @rx_ts_offset: Offset of timestamp within prefix
1141 * @rx_buffer_padding: Size of padding at end of RX packet
1142 * @can_rx_scatter: NIC is able to scatter packets to multiple buffers
1143 * @always_rx_scatter: NIC will always scatter packets to multiple buffers
1144 * @option_descriptors: NIC supports TX option descriptors
1145 * @min_interrupt_mode: Lowest capability interrupt mode supported
1146 * from &enum efx_int_mode.
1147 * @max_interrupt_mode: Highest capability interrupt mode supported
1148 * from &enum efx_int_mode.
1149 * @timer_period_max: Maximum period of interrupt timer (in ticks)
1150 * @offload_features: net_device feature flags for protocol offload
1151 * features implemented in hardware
1152 * @mcdi_max_ver: Maximum MCDI version supported
1153 * @hwtstamp_filters: Mask of hardware timestamp filter types supported
1155 struct efx_nic_type {
1157 unsigned int mem_bar;
1158 unsigned int (*mem_map_size)(struct efx_nic *efx);
1159 int (*probe)(struct efx_nic *efx);
1160 void (*remove)(struct efx_nic *efx);
1161 int (*init)(struct efx_nic *efx);
1162 int (*dimension_resources)(struct efx_nic *efx);
1163 void (*fini)(struct efx_nic *efx);
1164 void (*monitor)(struct efx_nic *efx);
1165 enum reset_type (*map_reset_reason)(enum reset_type reason);
1166 int (*map_reset_flags)(u32 *flags);
1167 int (*reset)(struct efx_nic *efx, enum reset_type method);
1168 int (*probe_port)(struct efx_nic *efx);
1169 void (*remove_port)(struct efx_nic *efx);
1170 bool (*handle_global_event)(struct efx_channel *channel, efx_qword_t *);
1171 int (*fini_dmaq)(struct efx_nic *efx);
1172 void (*prepare_flush)(struct efx_nic *efx);
1173 void (*finish_flush)(struct efx_nic *efx);
1174 void (*prepare_flr)(struct efx_nic *efx);
1175 void (*finish_flr)(struct efx_nic *efx);
1176 size_t (*describe_stats)(struct efx_nic *efx, u8 *names);
1177 size_t (*update_stats)(struct efx_nic *efx, u64 *full_stats,
1178 struct rtnl_link_stats64 *core_stats);
1179 void (*start_stats)(struct efx_nic *efx);
1180 void (*pull_stats)(struct efx_nic *efx);
1181 void (*stop_stats)(struct efx_nic *efx);
1182 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
1183 void (*push_irq_moderation)(struct efx_channel *channel);
1184 int (*reconfigure_port)(struct efx_nic *efx);
1185 void (*prepare_enable_fc_tx)(struct efx_nic *efx);
1186 int (*reconfigure_mac)(struct efx_nic *efx);
1187 bool (*check_mac_fault)(struct efx_nic *efx);
1188 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
1189 int (*set_wol)(struct efx_nic *efx, u32 type);
1190 void (*resume_wol)(struct efx_nic *efx);
1191 int (*test_chip)(struct efx_nic *efx, struct efx_self_tests *tests);
1192 int (*test_nvram)(struct efx_nic *efx);
1193 void (*mcdi_request)(struct efx_nic *efx,
1194 const efx_dword_t *hdr, size_t hdr_len,
1195 const efx_dword_t *sdu, size_t sdu_len);
1196 bool (*mcdi_poll_response)(struct efx_nic *efx);
1197 void (*mcdi_read_response)(struct efx_nic *efx, efx_dword_t *pdu,
1198 size_t pdu_offset, size_t pdu_len);
1199 int (*mcdi_poll_reboot)(struct efx_nic *efx);
1200 void (*mcdi_reboot_detected)(struct efx_nic *efx);
1201 void (*irq_enable_master)(struct efx_nic *efx);
1202 int (*irq_test_generate)(struct efx_nic *efx);
1203 void (*irq_disable_non_ev)(struct efx_nic *efx);
1204 irqreturn_t (*irq_handle_msi)(int irq, void *dev_id);
1205 irqreturn_t (*irq_handle_legacy)(int irq, void *dev_id);
1206 int (*tx_probe)(struct efx_tx_queue *tx_queue);
1207 void (*tx_init)(struct efx_tx_queue *tx_queue);
1208 void (*tx_remove)(struct efx_tx_queue *tx_queue);
1209 void (*tx_write)(struct efx_tx_queue *tx_queue);
1210 unsigned int (*tx_limit_len)(struct efx_tx_queue *tx_queue,
1211 dma_addr_t dma_addr, unsigned int len);
1212 int (*rx_push_rss_config)(struct efx_nic *efx, bool user,
1213 const u32 *rx_indir_table, const u8 *key);
1214 int (*rx_pull_rss_config)(struct efx_nic *efx);
1215 int (*rx_probe)(struct efx_rx_queue *rx_queue);
1216 void (*rx_init)(struct efx_rx_queue *rx_queue);
1217 void (*rx_remove)(struct efx_rx_queue *rx_queue);
1218 void (*rx_write)(struct efx_rx_queue *rx_queue);
1219 void (*rx_defer_refill)(struct efx_rx_queue *rx_queue);
1220 int (*ev_probe)(struct efx_channel *channel);
1221 int (*ev_init)(struct efx_channel *channel);
1222 void (*ev_fini)(struct efx_channel *channel);
1223 void (*ev_remove)(struct efx_channel *channel);
1224 int (*ev_process)(struct efx_channel *channel, int quota);
1225 void (*ev_read_ack)(struct efx_channel *channel);
1226 void (*ev_test_generate)(struct efx_channel *channel);
1227 int (*filter_table_probe)(struct efx_nic *efx);
1228 void (*filter_table_restore)(struct efx_nic *efx);
1229 void (*filter_table_remove)(struct efx_nic *efx);
1230 void (*filter_update_rx_scatter)(struct efx_nic *efx);
1231 s32 (*filter_insert)(struct efx_nic *efx,
1232 struct efx_filter_spec *spec, bool replace);
1233 int (*filter_remove_safe)(struct efx_nic *efx,
1234 enum efx_filter_priority priority,
1236 int (*filter_get_safe)(struct efx_nic *efx,
1237 enum efx_filter_priority priority,
1238 u32 filter_id, struct efx_filter_spec *);
1239 int (*filter_clear_rx)(struct efx_nic *efx,
1240 enum efx_filter_priority priority);
1241 u32 (*filter_count_rx_used)(struct efx_nic *efx,
1242 enum efx_filter_priority priority);
1243 u32 (*filter_get_rx_id_limit)(struct efx_nic *efx);
1244 s32 (*filter_get_rx_ids)(struct efx_nic *efx,
1245 enum efx_filter_priority priority,
1246 u32 *buf, u32 size);
1247 #ifdef CONFIG_RFS_ACCEL
1248 s32 (*filter_rfs_insert)(struct efx_nic *efx,
1249 struct efx_filter_spec *spec);
1250 bool (*filter_rfs_expire_one)(struct efx_nic *efx, u32 flow_id,
1251 unsigned int index);
1253 #ifdef CONFIG_SFC_MTD
1254 int (*mtd_probe)(struct efx_nic *efx);
1255 void (*mtd_rename)(struct efx_mtd_partition *part);
1256 int (*mtd_read)(struct mtd_info *mtd, loff_t start, size_t len,
1257 size_t *retlen, u8 *buffer);
1258 int (*mtd_erase)(struct mtd_info *mtd, loff_t start, size_t len);
1259 int (*mtd_write)(struct mtd_info *mtd, loff_t start, size_t len,
1260 size_t *retlen, const u8 *buffer);
1261 int (*mtd_sync)(struct mtd_info *mtd);
1263 void (*ptp_write_host_time)(struct efx_nic *efx, u32 host_time);
1264 int (*ptp_set_ts_sync_events)(struct efx_nic *efx, bool en, bool temp);
1265 int (*ptp_set_ts_config)(struct efx_nic *efx,
1266 struct hwtstamp_config *init);
1267 int (*sriov_configure)(struct efx_nic *efx, int num_vfs);
1268 int (*vlan_rx_add_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1269 int (*vlan_rx_kill_vid)(struct efx_nic *efx, __be16 proto, u16 vid);
1270 int (*get_phys_port_id)(struct efx_nic *efx,
1271 struct netdev_phys_item_id *ppid);
1272 int (*sriov_init)(struct efx_nic *efx);
1273 void (*sriov_fini)(struct efx_nic *efx);
1274 bool (*sriov_wanted)(struct efx_nic *efx);
1275 void (*sriov_reset)(struct efx_nic *efx);
1276 void (*sriov_flr)(struct efx_nic *efx, unsigned vf_i);
1277 int (*sriov_set_vf_mac)(struct efx_nic *efx, int vf_i, u8 *mac);
1278 int (*sriov_set_vf_vlan)(struct efx_nic *efx, int vf_i, u16 vlan,
1280 int (*sriov_set_vf_spoofchk)(struct efx_nic *efx, int vf_i,
1282 int (*sriov_get_vf_config)(struct efx_nic *efx, int vf_i,
1283 struct ifla_vf_info *ivi);
1284 int (*sriov_set_vf_link_state)(struct efx_nic *efx, int vf_i,
1286 int (*vswitching_probe)(struct efx_nic *efx);
1287 int (*vswitching_restore)(struct efx_nic *efx);
1288 void (*vswitching_remove)(struct efx_nic *efx);
1289 int (*get_mac_address)(struct efx_nic *efx, unsigned char *perm_addr);
1290 int (*set_mac_address)(struct efx_nic *efx);
1291 u32 (*tso_versions)(struct efx_nic *efx);
1292 int (*udp_tnl_push_ports)(struct efx_nic *efx);
1293 int (*udp_tnl_add_port)(struct efx_nic *efx, struct efx_udp_tunnel tnl);
1294 bool (*udp_tnl_has_port)(struct efx_nic *efx, __be16 port);
1295 int (*udp_tnl_del_port)(struct efx_nic *efx, struct efx_udp_tunnel tnl);
1298 unsigned int txd_ptr_tbl_base;
1299 unsigned int rxd_ptr_tbl_base;
1300 unsigned int buf_tbl_base;
1301 unsigned int evq_ptr_tbl_base;
1302 unsigned int evq_rptr_tbl_base;
1304 unsigned int rx_prefix_size;
1305 unsigned int rx_hash_offset;
1306 unsigned int rx_ts_offset;
1307 unsigned int rx_buffer_padding;
1308 bool can_rx_scatter;
1309 bool always_rx_scatter;
1310 bool option_descriptors;
1311 unsigned int min_interrupt_mode;
1312 unsigned int max_interrupt_mode;
1313 unsigned int timer_period_max;
1314 netdev_features_t offload_features;
1316 unsigned int max_rx_ip_filters;
1317 u32 hwtstamp_filters;
1318 unsigned int rx_hash_key_size;
1321 /**************************************************************************
1323 * Prototypes and inline functions
1325 *************************************************************************/
1327 static inline struct efx_channel *
1328 efx_get_channel(struct efx_nic *efx, unsigned index)
1330 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_channels);
1331 return efx->channel[index];
1334 /* Iterate over all used channels */
1335 #define efx_for_each_channel(_channel, _efx) \
1336 for (_channel = (_efx)->channel[0]; \
1338 _channel = (_channel->channel + 1 < (_efx)->n_channels) ? \
1339 (_efx)->channel[_channel->channel + 1] : NULL)
1341 /* Iterate over all used channels in reverse */
1342 #define efx_for_each_channel_rev(_channel, _efx) \
1343 for (_channel = (_efx)->channel[(_efx)->n_channels - 1]; \
1345 _channel = _channel->channel ? \
1346 (_efx)->channel[_channel->channel - 1] : NULL)
1348 static inline struct efx_tx_queue *
1349 efx_get_tx_queue(struct efx_nic *efx, unsigned index, unsigned type)
1351 EFX_WARN_ON_ONCE_PARANOID(index >= efx->n_tx_channels ||
1352 type >= EFX_TXQ_TYPES);
1353 return &efx->channel[efx->tx_channel_offset + index]->tx_queue[type];
1356 static inline bool efx_channel_has_tx_queues(struct efx_channel *channel)
1358 return channel->channel - channel->efx->tx_channel_offset <
1359 channel->efx->n_tx_channels;
1362 static inline struct efx_tx_queue *
1363 efx_channel_get_tx_queue(struct efx_channel *channel, unsigned type)
1365 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_tx_queues(channel) ||
1366 type >= EFX_TXQ_TYPES);
1367 return &channel->tx_queue[type];
1370 static inline bool efx_tx_queue_used(struct efx_tx_queue *tx_queue)
1372 return !(tx_queue->efx->net_dev->num_tc < 2 &&
1373 tx_queue->queue & EFX_TXQ_TYPE_HIGHPRI);
1376 /* Iterate over all TX queues belonging to a channel */
1377 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
1378 if (!efx_channel_has_tx_queues(_channel)) \
1381 for (_tx_queue = (_channel)->tx_queue; \
1382 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES && \
1383 efx_tx_queue_used(_tx_queue); \
1386 /* Iterate over all possible TX queues belonging to a channel */
1387 #define efx_for_each_possible_channel_tx_queue(_tx_queue, _channel) \
1388 if (!efx_channel_has_tx_queues(_channel)) \
1391 for (_tx_queue = (_channel)->tx_queue; \
1392 _tx_queue < (_channel)->tx_queue + EFX_TXQ_TYPES; \
1395 static inline bool efx_channel_has_rx_queue(struct efx_channel *channel)
1397 return channel->rx_queue.core_index >= 0;
1400 static inline struct efx_rx_queue *
1401 efx_channel_get_rx_queue(struct efx_channel *channel)
1403 EFX_WARN_ON_ONCE_PARANOID(!efx_channel_has_rx_queue(channel));
1404 return &channel->rx_queue;
1407 /* Iterate over all RX queues belonging to a channel */
1408 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
1409 if (!efx_channel_has_rx_queue(_channel)) \
1412 for (_rx_queue = &(_channel)->rx_queue; \
1416 static inline struct efx_channel *
1417 efx_rx_queue_channel(struct efx_rx_queue *rx_queue)
1419 return container_of(rx_queue, struct efx_channel, rx_queue);
1422 static inline int efx_rx_queue_index(struct efx_rx_queue *rx_queue)
1424 return efx_rx_queue_channel(rx_queue)->channel;
1427 /* Returns a pointer to the specified receive buffer in the RX
1430 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
1433 return &rx_queue->buffer[index];
1437 * EFX_MAX_FRAME_LEN - calculate maximum frame length
1439 * This calculates the maximum frame length that will be used for a
1440 * given MTU. The frame length will be equal to the MTU plus a
1441 * constant amount of header space and padding. This is the quantity
1442 * that the net driver will program into the MAC as the maximum frame
1445 * The 10G MAC requires 8-byte alignment on the frame
1446 * length, so we round up to the nearest 8.
1448 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
1449 * XGMII cycle). If the frame length reaches the maximum value in the
1450 * same cycle, the XMAC can miss the IPG altogether. We work around
1451 * this by adding a further 16 bytes.
1453 #define EFX_FRAME_PAD 16
1454 #define EFX_MAX_FRAME_LEN(mtu) \
1455 (ALIGN(((mtu) + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN + EFX_FRAME_PAD), 8))
1457 static inline bool efx_xmit_with_hwtstamp(struct sk_buff *skb)
1459 return skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP;
1461 static inline void efx_xmit_hwtstamp_pending(struct sk_buff *skb)
1463 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1466 /* Get all supported features.
1467 * If a feature is not fixed, it is present in hw_features.
1468 * If a feature is fixed, it does not present in hw_features, but
1469 * always in features.
1471 static inline netdev_features_t efx_supported_features(const struct efx_nic *efx)
1473 const struct net_device *net_dev = efx->net_dev;
1475 return net_dev->features | net_dev->hw_features;
1478 /* Get the current TX queue insert index. */
1479 static inline unsigned int
1480 efx_tx_queue_get_insert_index(const struct efx_tx_queue *tx_queue)
1482 return tx_queue->insert_count & tx_queue->ptr_mask;
1485 /* Get a TX buffer. */
1486 static inline struct efx_tx_buffer *
1487 __efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1489 return &tx_queue->buffer[efx_tx_queue_get_insert_index(tx_queue)];
1492 /* Get a TX buffer, checking it's not currently in use. */
1493 static inline struct efx_tx_buffer *
1494 efx_tx_queue_get_insert_buffer(const struct efx_tx_queue *tx_queue)
1496 struct efx_tx_buffer *buffer =
1497 __efx_tx_queue_get_insert_buffer(tx_queue);
1499 EFX_WARN_ON_ONCE_PARANOID(buffer->len);
1500 EFX_WARN_ON_ONCE_PARANOID(buffer->flags);
1501 EFX_WARN_ON_ONCE_PARANOID(buffer->unmap_len);
1506 #endif /* EFX_NET_DRIVER_H */