1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2009-2013 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
14 /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */
15 /* Power-on reset state */
16 #define MC_FW_STATE_POR (1)
17 /* If this is set in MC_RESET_STATE_REG then it should be
18 * possible to jump into IMEM without loading code from flash. */
19 #define MC_FW_WARM_BOOT_OK (2)
20 /* The MC main image has started to boot. */
21 #define MC_FW_STATE_BOOTING (4)
22 /* The Scheduler has started. */
23 #define MC_FW_STATE_SCHED (8)
24 /* If this is set in MC_RESET_STATE_REG then it should be
25 * possible to jump into IMEM without loading code from flash.
26 * Unlike a warm boot, assume DMEM has been reloaded, so that
27 * the MC persistent data must be reinitialised. */
28 #define MC_FW_TEPID_BOOT_OK (16)
29 /* BIST state has been initialized */
30 #define MC_FW_BIST_INIT_OK (128)
32 /* Siena MC shared memmory offsets */
33 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
34 #define MC_SMEM_P0_DOORBELL_OFST 0x000
35 #define MC_SMEM_P1_DOORBELL_OFST 0x004
36 /* The rest of these are firmware-defined */
37 #define MC_SMEM_P0_PDU_OFST 0x008
38 #define MC_SMEM_P1_PDU_OFST 0x108
39 #define MC_SMEM_PDU_LEN 0x100
40 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
41 #define MC_SMEM_P0_STATUS_OFST 0x7f8
42 #define MC_SMEM_P1_STATUS_OFST 0x7fc
44 /* Values to be written to the per-port status dword in shared
45 * memory on reboot and assert */
46 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
47 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
49 /* Check whether an mcfw version (in host order) belongs to a bootloader */
50 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
52 /* The current version of the MCDI protocol.
54 * Note that the ROM burnt into the card only talks V0, so at the very
55 * least every driver must support version 0 and MCDI_PCOL_VERSION
57 #define MCDI_PCOL_VERSION 2
59 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
63 * Each MCDI request starts with an MCDI_HEADER, which is a 32bit
64 * structure, filled in by the client.
66 * 0 7 8 16 20 22 23 24 31
67 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS |
71 * \------------------------------ Resync (always set)
73 * The client writes it's request into MC shared memory, and rings the
74 * doorbell. Each request is completed by either by the MC writting
75 * back into shared memory, or by writting out an event.
77 * All MCDI commands support completion by shared memory response. Each
78 * request may also contain additional data (accounted for by HEADER.LEN),
79 * and some response's may also contain additional data (again, accounted
82 * Some MCDI commands support completion by event, in which any associated
83 * response data is included in the event.
85 * The protocol requires one response to be delivered for every request, a
86 * request should not be sent unless the response for the previous request
87 * has been received (either by polling shared memory, or by receiving
91 /** Request/Response structure */
92 #define MCDI_HEADER_OFST 0
93 #define MCDI_HEADER_CODE_LBN 0
94 #define MCDI_HEADER_CODE_WIDTH 7
95 #define MCDI_HEADER_RESYNC_LBN 7
96 #define MCDI_HEADER_RESYNC_WIDTH 1
97 #define MCDI_HEADER_DATALEN_LBN 8
98 #define MCDI_HEADER_DATALEN_WIDTH 8
99 #define MCDI_HEADER_SEQ_LBN 16
100 #define MCDI_HEADER_SEQ_WIDTH 4
101 #define MCDI_HEADER_RSVD_LBN 20
102 #define MCDI_HEADER_RSVD_WIDTH 1
103 #define MCDI_HEADER_NOT_EPOCH_LBN 21
104 #define MCDI_HEADER_NOT_EPOCH_WIDTH 1
105 #define MCDI_HEADER_ERROR_LBN 22
106 #define MCDI_HEADER_ERROR_WIDTH 1
107 #define MCDI_HEADER_RESPONSE_LBN 23
108 #define MCDI_HEADER_RESPONSE_WIDTH 1
109 #define MCDI_HEADER_XFLAGS_LBN 24
110 #define MCDI_HEADER_XFLAGS_WIDTH 8
111 /* Request response using event */
112 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
114 /* Maximum number of payload bytes */
115 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
116 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400
118 #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2
121 /* The MC can generate events for two reasons:
122 * - To complete a shared memory request if XFLAGS_EVREQ was set
123 * - As a notification (link state, i2c event), controlled
124 * via MC_CMD_LOG_CTRL
126 * Both events share a common structure:
128 * 0 32 33 36 44 52 60
129 * | Data | Cont | Level | Src | Code | Rsvd |
131 * \ There is another event pending in this notification
133 * If Code==CMDDONE, then the fields are further interpreted as:
135 * - LEVEL==INFO Command succeeded
136 * - LEVEL==ERR Command failed
139 * | Seq | Datalen | Errno | Rsvd |
141 * These fields are taken directly out of the standard MCDI header, i.e.,
142 * LEVEL==ERR, Datalen == 0 => Reboot
144 * Events can be squirted out of the UART (using LOG_CTRL) without a
145 * MCDI header. An event can be distinguished from a MCDI response by
146 * examining the first byte which is 0xc0. This corresponds to the
147 * non-existent MCDI command MC_CMD_DEBUG_LOG.
150 * | command | Resync | = 0xc0
152 * Since the event is written in big-endian byte order, this works
153 * providing bits 56-63 of the event are 0xc0.
156 * | Rsvd | Code | = 0xc0
158 * Which means for convenience the event code is 0xc for all MC
161 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
164 /* Operation not permitted. */
165 #define MC_CMD_ERR_EPERM 1
166 /* Non-existent command target */
167 #define MC_CMD_ERR_ENOENT 2
168 /* assert() has killed the MC */
169 #define MC_CMD_ERR_EINTR 4
171 #define MC_CMD_ERR_EIO 5
173 #define MC_CMD_ERR_EAGAIN 11
175 #define MC_CMD_ERR_ENOMEM 12
176 /* Caller does not hold required locks */
177 #define MC_CMD_ERR_EACCES 13
178 /* Resource is currently unavailable (e.g. lock contention) */
179 #define MC_CMD_ERR_EBUSY 16
181 #define MC_CMD_ERR_ENODEV 19
182 /* Invalid argument to target */
183 #define MC_CMD_ERR_EINVAL 22
185 #define MC_CMD_ERR_ERANGE 34
186 /* Non-recursive resource is already acquired */
187 #define MC_CMD_ERR_EDEADLK 35
188 /* Operation not implemented */
189 #define MC_CMD_ERR_ENOSYS 38
190 /* Operation timed out */
191 #define MC_CMD_ERR_ETIME 62
192 /* Link has been severed */
193 #define MC_CMD_ERR_ENOLINK 67
195 #define MC_CMD_ERR_EPROTO 71
196 /* Operation not supported */
197 #define MC_CMD_ERR_ENOTSUP 95
198 /* Address not available */
199 #define MC_CMD_ERR_EADDRNOTAVAIL 99
201 #define MC_CMD_ERR_ENOTCONN 107
202 /* Operation already in progress */
203 #define MC_CMD_ERR_EALREADY 114
205 /* Resource allocation failed. */
206 #define MC_CMD_ERR_ALLOC_FAIL 0x1000
207 /* V-adaptor not found. */
208 #define MC_CMD_ERR_NO_VADAPTOR 0x1001
209 /* EVB port not found. */
210 #define MC_CMD_ERR_NO_EVB_PORT 0x1002
211 /* V-switch not found. */
212 #define MC_CMD_ERR_NO_VSWITCH 0x1003
213 /* Too many VLAN tags. */
214 #define MC_CMD_ERR_VLAN_LIMIT 0x1004
215 /* Bad PCI function number. */
216 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
217 /* Invalid VLAN mode. */
218 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
219 /* Invalid v-switch type. */
220 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
221 /* Invalid v-port type. */
222 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
223 /* MAC address exists. */
224 #define MC_CMD_ERR_MAC_EXIST 0x1009
225 /* Slave core not present */
226 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
228 #define MC_CMD_ERR_CODE_OFST 0
230 /* We define 8 "escape" commands to allow
231 for command number space extension */
233 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
234 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
235 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
236 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
237 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
238 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
239 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
240 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
242 /* Vectors in the boot ROM */
243 /* Point to the copycode entry point. */
244 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
245 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
246 /* Points to the recovery mode entry point. */
247 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
248 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
250 /* The command set exported by the boot ROM (MCDI v0) */
251 #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \
252 (1 << MC_CMD_READ32) | \
253 (1 << MC_CMD_WRITE32) | \
254 (1 << MC_CMD_COPYCODE) | \
255 (1 << MC_CMD_GET_VERSION), \
258 #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \
259 (MC_CMD_SENSOR_ENTRY_OFST + (_x))
261 #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \
262 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
263 MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \
264 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
266 #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \
267 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
268 MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \
269 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
271 #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \
272 (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \
273 MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \
274 (n) * MC_CMD_DBIWROP_TYPEDEF_LEN)
277 /* Version 2 adds an optional argument to error returns: the errno value
278 * may be followed by the (0-based) number of the first argument that
279 * could not be processed.
281 #define MC_CMD_ERR_ARG_OFST 4
284 #define MC_CMD_ERR_ENOSPC 28
286 /* MCDI_EVENT structuredef */
287 #define MCDI_EVENT_LEN 8
288 #define MCDI_EVENT_CONT_LBN 32
289 #define MCDI_EVENT_CONT_WIDTH 1
290 #define MCDI_EVENT_LEVEL_LBN 33
291 #define MCDI_EVENT_LEVEL_WIDTH 3
293 #define MCDI_EVENT_LEVEL_INFO 0x0
295 #define MCDI_EVENT_LEVEL_WARN 0x1
297 #define MCDI_EVENT_LEVEL_ERR 0x2
299 #define MCDI_EVENT_LEVEL_FATAL 0x3
300 #define MCDI_EVENT_DATA_OFST 0
301 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0
302 #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8
303 #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8
304 #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8
305 #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16
306 #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8
307 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
308 #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16
309 #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16
310 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
312 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
314 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
316 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
318 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
319 #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20
320 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
321 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24
322 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8
323 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
324 #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8
325 #define MCDI_EVENT_SENSOREVT_STATE_LBN 8
326 #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8
327 #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16
328 #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16
329 #define MCDI_EVENT_FWALERT_DATA_LBN 8
330 #define MCDI_EVENT_FWALERT_DATA_WIDTH 24
331 #define MCDI_EVENT_FWALERT_REASON_LBN 0
332 #define MCDI_EVENT_FWALERT_REASON_WIDTH 8
333 /* enum: SRAM Access. */
334 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
335 #define MCDI_EVENT_FLR_VF_LBN 0
336 #define MCDI_EVENT_FLR_VF_WIDTH 8
337 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0
338 #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12
339 #define MCDI_EVENT_TX_ERR_TYPE_LBN 12
340 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
341 /* enum: Descriptor loader reported failure */
342 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
343 /* enum: Descriptor ring empty and no EOP seen for packet */
344 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2
345 /* enum: Overlength packet */
346 #define MCDI_EVENT_TX_ERR_2BIG 0x3
347 /* enum: Malformed option descriptor */
348 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5
349 /* enum: Option descriptor part way through a packet */
350 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8
351 /* enum: DMA or PIO data access error */
352 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
353 #define MCDI_EVENT_TX_ERR_INFO_LBN 16
354 #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16
355 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12
356 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1
357 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
358 #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12
359 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
360 #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8
361 /* enum: PLL lost lock */
362 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
363 /* enum: Filter overflow (PDMA) */
364 #define MCDI_EVENT_PTP_ERR_FILTER 0x2
365 /* enum: FIFO overflow (FPGA) */
366 #define MCDI_EVENT_PTP_ERR_FIFO 0x3
367 /* enum: Merge queue overflow */
368 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4
369 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0
370 #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8
371 /* enum: AOE failed to load - no valid image? */
372 #define MCDI_EVENT_AOE_NO_LOAD 0x1
373 /* enum: AOE FC reported an exception */
374 #define MCDI_EVENT_AOE_FC_ASSERT 0x2
375 /* enum: AOE FC watchdogged */
376 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3
377 /* enum: AOE FC failed to start */
378 #define MCDI_EVENT_AOE_FC_NO_START 0x4
379 /* enum: Generic AOE fault - likely to have been reported via other means too
380 * but intended for use by aoex driver.
382 #define MCDI_EVENT_AOE_FAULT 0x5
383 /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */
384 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
385 /* enum: AOE loaded successfully */
386 #define MCDI_EVENT_AOE_LOAD 0x7
387 /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */
388 #define MCDI_EVENT_AOE_DMA 0x8
389 /* enum: AOE byteblaster connected/disconnected (Connection status in
392 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9
393 #define MCDI_EVENT_AOE_ERR_DATA_LBN 8
394 #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8
395 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0
396 #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12
397 #define MCDI_EVENT_RX_ERR_TYPE_LBN 12
398 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
399 #define MCDI_EVENT_RX_ERR_INFO_LBN 16
400 #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16
401 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12
402 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1
403 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
404 #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12
405 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
406 #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16
407 #define MCDI_EVENT_DATA_LBN 0
408 #define MCDI_EVENT_DATA_WIDTH 32
409 #define MCDI_EVENT_SRC_LBN 36
410 #define MCDI_EVENT_SRC_WIDTH 8
411 #define MCDI_EVENT_EV_CODE_LBN 60
412 #define MCDI_EVENT_EV_CODE_WIDTH 4
413 #define MCDI_EVENT_CODE_LBN 44
414 #define MCDI_EVENT_CODE_WIDTH 8
415 /* enum: Bad assert. */
416 #define MCDI_EVENT_CODE_BADSSERT 0x1
417 /* enum: PM Notice. */
418 #define MCDI_EVENT_CODE_PMNOTICE 0x2
419 /* enum: Command done. */
420 #define MCDI_EVENT_CODE_CMDDONE 0x3
421 /* enum: Link change. */
422 #define MCDI_EVENT_CODE_LINKCHANGE 0x4
423 /* enum: Sensor Event. */
424 #define MCDI_EVENT_CODE_SENSOREVT 0x5
425 /* enum: Schedule error. */
426 #define MCDI_EVENT_CODE_SCHEDERR 0x6
428 #define MCDI_EVENT_CODE_REBOOT 0x7
429 /* enum: Mac stats DMA. */
430 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
431 /* enum: Firmware alert. */
432 #define MCDI_EVENT_CODE_FWALERT 0x9
433 /* enum: Function level reset. */
434 #define MCDI_EVENT_CODE_FLR 0xa
435 /* enum: Transmit error */
436 #define MCDI_EVENT_CODE_TX_ERR 0xb
437 /* enum: Tx flush has completed */
438 #define MCDI_EVENT_CODE_TX_FLUSH 0xc
439 /* enum: PTP packet received timestamp */
440 #define MCDI_EVENT_CODE_PTP_RX 0xd
441 /* enum: PTP NIC failure */
442 #define MCDI_EVENT_CODE_PTP_FAULT 0xe
443 /* enum: PTP PPS event */
444 #define MCDI_EVENT_CODE_PTP_PPS 0xf
445 /* enum: Rx flush has completed */
446 #define MCDI_EVENT_CODE_RX_FLUSH 0x10
447 /* enum: Receive error */
448 #define MCDI_EVENT_CODE_RX_ERR 0x11
449 /* enum: AOE fault */
450 #define MCDI_EVENT_CODE_AOE 0x12
451 /* enum: Network port calibration failed (VCAL). */
452 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13
453 /* enum: HW PPS event */
454 #define MCDI_EVENT_CODE_HW_PPS 0x14
455 /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and
456 * a different format)
458 #define MCDI_EVENT_CODE_MC_REBOOT 0x15
459 /* enum: the MC has detected a parity error */
460 #define MCDI_EVENT_CODE_PAR_ERR 0x16
461 /* enum: the MC has detected a correctable error */
462 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
463 /* enum: the MC has detected an uncorrectable error */
464 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
465 /* enum: Artificial event generated by host and posted via MC for test
468 #define MCDI_EVENT_CODE_TESTGEN 0xfa
469 #define MCDI_EVENT_CMDDONE_DATA_OFST 0
470 #define MCDI_EVENT_CMDDONE_DATA_LBN 0
471 #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32
472 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
473 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
474 #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32
475 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0
476 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0
477 #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32
478 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
479 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
480 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32
481 #define MCDI_EVENT_TX_ERR_DATA_OFST 0
482 #define MCDI_EVENT_TX_ERR_DATA_LBN 0
483 #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32
484 /* Seconds field of timestamp */
485 #define MCDI_EVENT_PTP_SECONDS_OFST 0
486 #define MCDI_EVENT_PTP_SECONDS_LBN 0
487 #define MCDI_EVENT_PTP_SECONDS_WIDTH 32
488 /* Nanoseconds field of timestamp */
489 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
490 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
491 #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32
492 /* Lowest four bytes of sourceUUID from PTP packet */
493 #define MCDI_EVENT_PTP_UUID_OFST 0
494 #define MCDI_EVENT_PTP_UUID_LBN 0
495 #define MCDI_EVENT_PTP_UUID_WIDTH 32
496 #define MCDI_EVENT_RX_ERR_DATA_OFST 0
497 #define MCDI_EVENT_RX_ERR_DATA_LBN 0
498 #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32
499 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0
500 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0
501 #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32
502 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
503 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
504 #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32
505 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
506 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
507 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32
509 /* FCDI_EVENT structuredef */
510 #define FCDI_EVENT_LEN 8
511 #define FCDI_EVENT_CONT_LBN 32
512 #define FCDI_EVENT_CONT_WIDTH 1
513 #define FCDI_EVENT_LEVEL_LBN 33
514 #define FCDI_EVENT_LEVEL_WIDTH 3
516 #define FCDI_EVENT_LEVEL_INFO 0x0
518 #define FCDI_EVENT_LEVEL_WARN 0x1
520 #define FCDI_EVENT_LEVEL_ERR 0x2
522 #define FCDI_EVENT_LEVEL_FATAL 0x3
523 #define FCDI_EVENT_DATA_OFST 0
524 #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0
525 #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1
526 #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */
527 #define FCDI_EVENT_LINK_UP 0x1 /* enum */
528 #define FCDI_EVENT_DATA_LBN 0
529 #define FCDI_EVENT_DATA_WIDTH 32
530 #define FCDI_EVENT_SRC_LBN 36
531 #define FCDI_EVENT_SRC_WIDTH 8
532 #define FCDI_EVENT_EV_CODE_LBN 60
533 #define FCDI_EVENT_EV_CODE_WIDTH 4
534 #define FCDI_EVENT_CODE_LBN 44
535 #define FCDI_EVENT_CODE_WIDTH 8
536 /* enum: The FC was rebooted. */
537 #define FCDI_EVENT_CODE_REBOOT 0x1
538 /* enum: Bad assert. */
539 #define FCDI_EVENT_CODE_ASSERT 0x2
540 /* enum: DDR3 test result. */
541 #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3
542 /* enum: Link status. */
543 #define FCDI_EVENT_CODE_LINK_STATE 0x4
544 /* enum: A timed read is ready to be serviced. */
545 #define FCDI_EVENT_CODE_TIMED_READ 0x5
546 /* enum: One or more PPS IN events */
547 #define FCDI_EVENT_CODE_PPS_IN 0x6
548 /* enum: One or more PPS OUT events */
549 #define FCDI_EVENT_CODE_PPS_OUT 0x7
550 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0
551 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0
552 #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32
553 #define FCDI_EVENT_ASSERT_TYPE_LBN 36
554 #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8
555 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36
556 #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8
557 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0
558 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0
559 #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32
560 #define FCDI_EVENT_LINK_STATE_DATA_OFST 0
561 #define FCDI_EVENT_LINK_STATE_DATA_LBN 0
562 #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32
563 #define FCDI_EVENT_PPS_COUNT_OFST 0
564 #define FCDI_EVENT_PPS_COUNT_LBN 0
565 #define FCDI_EVENT_PPS_COUNT_WIDTH 32
567 /* FCDI_EXTENDED_EVENT structuredef */
568 #define FCDI_EXTENDED_EVENT_LENMIN 16
569 #define FCDI_EXTENDED_EVENT_LENMAX 248
570 #define FCDI_EXTENDED_EVENT_LEN(num) (8+8*(num))
571 /* Number of timestamps following */
572 #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0
573 #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0
574 #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32
575 /* Seconds field of a timestamp record */
576 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8
577 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64
578 #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32
579 /* Nanoseconds field of a timestamp record */
580 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12
581 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96
582 #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32
583 /* Timestamp records comprising the event */
584 #define FCDI_EXTENDED_EVENT_PPS_TIME_OFST 8
585 #define FCDI_EXTENDED_EVENT_PPS_TIME_LEN 8
586 #define FCDI_EXTENDED_EVENT_PPS_TIME_LO_OFST 8
587 #define FCDI_EXTENDED_EVENT_PPS_TIME_HI_OFST 12
588 #define FCDI_EXTENDED_EVENT_PPS_TIME_MINNUM 1
589 #define FCDI_EXTENDED_EVENT_PPS_TIME_MAXNUM 30
590 #define FCDI_EXTENDED_EVENT_PPS_TIME_LBN 64
591 #define FCDI_EXTENDED_EVENT_PPS_TIME_WIDTH 64
594 /***********************************/
596 * Read multiple 32byte words from MC memory.
598 #define MC_CMD_READ32 0x1
600 /* MC_CMD_READ32_IN msgrequest */
601 #define MC_CMD_READ32_IN_LEN 8
602 #define MC_CMD_READ32_IN_ADDR_OFST 0
603 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4
605 /* MC_CMD_READ32_OUT msgresponse */
606 #define MC_CMD_READ32_OUT_LENMIN 4
607 #define MC_CMD_READ32_OUT_LENMAX 252
608 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
609 #define MC_CMD_READ32_OUT_BUFFER_OFST 0
610 #define MC_CMD_READ32_OUT_BUFFER_LEN 4
611 #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1
612 #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63
615 /***********************************/
617 * Write multiple 32byte words to MC memory.
619 #define MC_CMD_WRITE32 0x2
621 /* MC_CMD_WRITE32_IN msgrequest */
622 #define MC_CMD_WRITE32_IN_LENMIN 8
623 #define MC_CMD_WRITE32_IN_LENMAX 252
624 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
625 #define MC_CMD_WRITE32_IN_ADDR_OFST 0
626 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4
627 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4
628 #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1
629 #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62
631 /* MC_CMD_WRITE32_OUT msgresponse */
632 #define MC_CMD_WRITE32_OUT_LEN 0
635 /***********************************/
637 * Copy MC code between two locations and jump.
639 #define MC_CMD_COPYCODE 0x3
641 /* MC_CMD_COPYCODE_IN msgrequest */
642 #define MC_CMD_COPYCODE_IN_LEN 16
644 #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0
645 /* enum: Entering the main image via a copy of a single word from and to this
646 * address indicates that it should not attempt to start the datapath CPUs.
647 * This is useful for certain soft rebooting scenarios. (Huntington only)
649 #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0
650 /* enum: Entering the main image via a copy of a single word from and to this
651 * address indicates that it should not attempt to parse any configuration from
652 * flash. (In addition, the datapath CPUs will not be started, as for
653 * MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR above.) This is useful for
654 * certain soft rebooting scenarios. (Huntington only)
656 #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc
657 /* Destination address */
658 #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4
659 #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8
660 /* Address of where to jump after copy. */
661 #define MC_CMD_COPYCODE_IN_JUMP_OFST 12
662 /* enum: Control should return to the caller rather than jumping */
663 #define MC_CMD_COPYCODE_JUMP_NONE 0x1
665 /* MC_CMD_COPYCODE_OUT msgresponse */
666 #define MC_CMD_COPYCODE_OUT_LEN 0
669 /***********************************/
671 * Select function for function-specific commands.
673 #define MC_CMD_SET_FUNC 0x4
675 /* MC_CMD_SET_FUNC_IN msgrequest */
676 #define MC_CMD_SET_FUNC_IN_LEN 4
678 #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0
680 /* MC_CMD_SET_FUNC_OUT msgresponse */
681 #define MC_CMD_SET_FUNC_OUT_LEN 0
684 /***********************************/
685 /* MC_CMD_GET_BOOT_STATUS
686 * Get the instruction address from which the MC booted.
688 #define MC_CMD_GET_BOOT_STATUS 0x5
690 /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */
691 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
693 /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */
694 #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8
696 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
697 /* enum: indicates that the MC wasn't flash booted */
698 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
699 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
700 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
701 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1
702 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1
703 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1
704 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2
705 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1
708 /***********************************/
709 /* MC_CMD_GET_ASSERTS
710 * Get (and optionally clear) the current assertion status. Only
711 * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other
712 * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS
714 #define MC_CMD_GET_ASSERTS 0x6
716 /* MC_CMD_GET_ASSERTS_IN msgrequest */
717 #define MC_CMD_GET_ASSERTS_IN_LEN 4
718 /* Set to clear assertion */
719 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
721 /* MC_CMD_GET_ASSERTS_OUT msgresponse */
722 #define MC_CMD_GET_ASSERTS_OUT_LEN 140
723 /* Assertion status flag. */
724 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
725 /* enum: No assertions have failed. */
726 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
727 /* enum: A system-level assertion has failed. */
728 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
729 /* enum: A thread-level assertion has failed. */
730 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
731 /* enum: The system was reset by the watchdog. */
732 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
733 /* enum: An illegal address trap stopped the system (huntington and later) */
734 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
735 /* Failing PC value */
736 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
738 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8
739 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
740 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31
741 /* Failing thread address */
742 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132
743 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136
746 /***********************************/
748 * Configure the output stream for various events and messages.
750 #define MC_CMD_LOG_CTRL 0x7
752 /* MC_CMD_LOG_CTRL_IN msgrequest */
753 #define MC_CMD_LOG_CTRL_IN_LEN 8
754 /* Log destination */
755 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
757 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
758 /* enum: Event queue. */
759 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
760 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
762 /* MC_CMD_LOG_CTRL_OUT msgresponse */
763 #define MC_CMD_LOG_CTRL_OUT_LEN 0
766 /***********************************/
767 /* MC_CMD_GET_VERSION
768 * Get version information about the MC firmware.
770 #define MC_CMD_GET_VERSION 0x8
772 /* MC_CMD_GET_VERSION_IN msgrequest */
773 #define MC_CMD_GET_VERSION_IN_LEN 0
775 /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */
776 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4
777 /* placeholder, set to 0 */
778 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
780 /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */
781 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4
782 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
783 /* enum: Reserved version number to indicate "any" version. */
784 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
785 /* enum: Bootrom version value for Siena. */
786 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
787 /* enum: Bootrom version value for Huntington. */
788 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
790 /* MC_CMD_GET_VERSION_OUT msgresponse */
791 #define MC_CMD_GET_VERSION_OUT_LEN 32
792 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
793 /* Enum values, see field(s): */
794 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
795 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
796 /* 128bit mask of functions supported by the current firmware */
797 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8
798 #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16
799 #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24
800 #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8
801 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24
802 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28
804 /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */
805 #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48
806 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
807 /* Enum values, see field(s): */
808 /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */
809 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
810 /* 128bit mask of functions supported by the current firmware */
811 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8
812 #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16
813 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24
814 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8
815 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24
816 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28
818 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32
819 #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16
822 /***********************************/
824 * Perform PTP operation
826 #define MC_CMD_PTP 0xb
828 /* MC_CMD_PTP_IN msgrequest */
829 #define MC_CMD_PTP_IN_LEN 1
830 /* PTP operation code */
831 #define MC_CMD_PTP_IN_OP_OFST 0
832 #define MC_CMD_PTP_IN_OP_LEN 1
833 /* enum: Enable PTP packet timestamping operation. */
834 #define MC_CMD_PTP_OP_ENABLE 0x1
835 /* enum: Disable PTP packet timestamping operation. */
836 #define MC_CMD_PTP_OP_DISABLE 0x2
837 /* enum: Send a PTP packet. */
838 #define MC_CMD_PTP_OP_TRANSMIT 0x3
839 /* enum: Read the current NIC time. */
840 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4
841 /* enum: Get the current PTP status. */
842 #define MC_CMD_PTP_OP_STATUS 0x5
843 /* enum: Adjust the PTP NIC's time. */
844 #define MC_CMD_PTP_OP_ADJUST 0x6
845 /* enum: Synchronize host and NIC time. */
846 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7
847 /* enum: Basic manufacturing tests. */
848 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
849 /* enum: Packet based manufacturing tests. */
850 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
851 /* enum: Reset some of the PTP related statistics */
852 #define MC_CMD_PTP_OP_RESET_STATS 0xa
853 /* enum: Debug operations to MC. */
854 #define MC_CMD_PTP_OP_DEBUG 0xb
855 /* enum: Read an FPGA register */
856 #define MC_CMD_PTP_OP_FPGAREAD 0xc
857 /* enum: Write an FPGA register */
858 #define MC_CMD_PTP_OP_FPGAWRITE 0xd
859 /* enum: Apply an offset to the NIC clock */
860 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
861 /* enum: Change Apply an offset to the NIC clock */
862 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
863 /* enum: Set the MC packet filter VLAN tags for received PTP packets */
864 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
865 /* enum: Set the MC packet filter UUID for received PTP packets */
866 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
867 /* enum: Set the MC packet filter Domain for received PTP packets */
868 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
869 /* enum: Set the clock source */
870 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13
871 /* enum: Reset value of Timer Reg. */
872 #define MC_CMD_PTP_OP_RST_CLK 0x14
873 /* enum: Enable the forwarding of PPS events to the host */
874 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15
875 /* enum: Above this for future use. */
876 #define MC_CMD_PTP_OP_MAX 0x16
878 /* MC_CMD_PTP_IN_ENABLE msgrequest */
879 #define MC_CMD_PTP_IN_ENABLE_LEN 16
880 #define MC_CMD_PTP_IN_CMD_OFST 0
881 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
882 /* Event queue for PTP events */
883 #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8
884 /* PTP timestamping mode */
885 #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12
886 /* enum: PTP, version 1 */
887 #define MC_CMD_PTP_MODE_V1 0x0
888 /* enum: PTP, version 1, with VLAN headers - deprecated */
889 #define MC_CMD_PTP_MODE_V1_VLAN 0x1
890 /* enum: PTP, version 2 */
891 #define MC_CMD_PTP_MODE_V2 0x2
892 /* enum: PTP, version 2, with VLAN headers - deprecated */
893 #define MC_CMD_PTP_MODE_V2_VLAN 0x3
894 /* enum: PTP, version 2, with improved UUID filtering */
895 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4
896 /* enum: FCoE (seconds and microseconds) */
897 #define MC_CMD_PTP_MODE_FCOE 0x5
899 /* MC_CMD_PTP_IN_DISABLE msgrequest */
900 #define MC_CMD_PTP_IN_DISABLE_LEN 8
901 /* MC_CMD_PTP_IN_CMD_OFST 0 */
902 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
904 /* MC_CMD_PTP_IN_TRANSMIT msgrequest */
905 #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13
906 #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252
907 #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num))
908 /* MC_CMD_PTP_IN_CMD_OFST 0 */
909 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
910 /* Transmit packet length */
911 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8
912 /* Transmit packet data */
913 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12
914 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1
915 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1
916 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240
918 /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */
919 #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8
920 /* MC_CMD_PTP_IN_CMD_OFST 0 */
921 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
923 /* MC_CMD_PTP_IN_STATUS msgrequest */
924 #define MC_CMD_PTP_IN_STATUS_LEN 8
925 /* MC_CMD_PTP_IN_CMD_OFST 0 */
926 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
928 /* MC_CMD_PTP_IN_ADJUST msgrequest */
929 #define MC_CMD_PTP_IN_ADJUST_LEN 24
930 /* MC_CMD_PTP_IN_CMD_OFST 0 */
931 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
932 /* Frequency adjustment 40 bit fixed point ns */
933 #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8
934 #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8
935 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8
936 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12
937 /* enum: Number of fractional bits in frequency adjustment */
938 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28
939 /* Time adjustment in seconds */
940 #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16
941 /* Time adjustment in nanoseconds */
942 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20
944 /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */
945 #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20
946 /* MC_CMD_PTP_IN_CMD_OFST 0 */
947 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
948 /* Number of time readings to capture */
949 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8
950 /* Host address in which to write "synchronization started" indication (64
953 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12
954 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8
955 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12
956 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16
958 /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */
959 #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8
960 /* MC_CMD_PTP_IN_CMD_OFST 0 */
961 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
963 /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */
964 #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12
965 /* MC_CMD_PTP_IN_CMD_OFST 0 */
966 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
967 /* Enable or disable packet testing */
968 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8
970 /* MC_CMD_PTP_IN_RESET_STATS msgrequest */
971 #define MC_CMD_PTP_IN_RESET_STATS_LEN 8
972 /* MC_CMD_PTP_IN_CMD_OFST 0 */
973 /* Reset PTP statistics */
974 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
976 /* MC_CMD_PTP_IN_DEBUG msgrequest */
977 #define MC_CMD_PTP_IN_DEBUG_LEN 12
978 /* MC_CMD_PTP_IN_CMD_OFST 0 */
979 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
980 /* Debug operations */
981 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8
983 /* MC_CMD_PTP_IN_FPGAREAD msgrequest */
984 #define MC_CMD_PTP_IN_FPGAREAD_LEN 16
985 /* MC_CMD_PTP_IN_CMD_OFST 0 */
986 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
987 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8
988 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12
990 /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */
991 #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13
992 #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252
993 #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num))
994 /* MC_CMD_PTP_IN_CMD_OFST 0 */
995 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
996 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8
997 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12
998 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1
999 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1
1000 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240
1002 /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */
1003 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16
1004 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1005 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1006 /* Time adjustment in seconds */
1007 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8
1008 /* Time adjustment in nanoseconds */
1009 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12
1011 /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */
1012 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16
1013 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1014 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1015 /* Frequency adjustment 40 bit fixed point ns */
1016 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8
1017 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8
1018 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8
1019 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12
1020 /* enum: Number of fractional bits in frequency adjustment */
1021 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
1023 /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */
1024 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24
1025 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1026 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1027 /* Number of VLAN tags, 0 if not VLAN */
1028 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8
1029 /* Set of VLAN tags to filter against */
1030 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12
1031 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
1032 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3
1034 /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */
1035 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20
1036 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1037 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1038 /* 1 to enable UUID filtering, 0 to disable */
1039 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8
1040 /* UUID to filter against */
1041 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12
1042 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8
1043 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12
1044 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16
1046 /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */
1047 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16
1048 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1049 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1050 /* 1 to enable Domain filtering, 0 to disable */
1051 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8
1052 /* Domain number to filter against */
1053 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12
1055 /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */
1056 #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12
1057 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1058 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1059 /* Set the clock source. */
1060 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8
1061 /* enum: Internal. */
1062 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
1063 /* enum: External. */
1064 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
1066 /* MC_CMD_PTP_IN_RST_CLK msgrequest */
1067 #define MC_CMD_PTP_IN_RST_CLK_LEN 8
1068 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1069 /* Reset value of Timer Reg. */
1070 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
1072 /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */
1073 #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12
1074 /* MC_CMD_PTP_IN_CMD_OFST 0 */
1075 /* Enable or disable */
1076 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
1078 #define MC_CMD_PTP_ENABLE_PPS 0x0
1080 #define MC_CMD_PTP_DISABLE_PPS 0x1
1081 /* Queueid to send events back */
1082 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8
1084 /* MC_CMD_PTP_OUT msgresponse */
1085 #define MC_CMD_PTP_OUT_LEN 0
1087 /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */
1088 #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8
1089 /* Value of seconds timestamp */
1090 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
1091 /* Value of nanoseconds timestamp */
1092 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
1094 /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */
1095 #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8
1096 /* Value of seconds timestamp */
1097 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
1098 /* Value of nanoseconds timestamp */
1099 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
1101 /* MC_CMD_PTP_OUT_STATUS msgresponse */
1102 #define MC_CMD_PTP_OUT_STATUS_LEN 64
1103 /* Frequency of NIC's hardware clock */
1104 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
1105 /* Number of packets transmitted and timestamped */
1106 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
1107 /* Number of packets received and timestamped */
1108 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8
1109 /* Number of packets timestamped by the FPGA */
1110 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12
1111 /* Number of packets filter matched */
1112 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16
1113 /* Number of packets not filter matched */
1114 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20
1115 /* Number of PPS overflows (noise on input?) */
1116 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24
1117 /* Number of PPS bad periods */
1118 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28
1119 /* Minimum period of PPS pulse */
1120 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32
1121 /* Maximum period of PPS pulse */
1122 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36
1123 /* Last period of PPS pulse */
1124 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40
1125 /* Mean period of PPS pulse */
1126 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44
1127 /* Minimum offset of PPS pulse (signed) */
1128 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48
1129 /* Maximum offset of PPS pulse (signed) */
1130 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52
1131 /* Last offset of PPS pulse (signed) */
1132 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56
1133 /* Mean offset of PPS pulse (signed) */
1134 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60
1136 /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */
1137 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20
1138 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240
1139 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
1140 /* A set of host and NIC times */
1141 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
1142 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20
1143 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1
1144 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12
1145 /* Host time immediately before NIC's hardware clock read */
1146 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
1147 /* Value of seconds timestamp */
1148 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
1149 /* Value of nanoseconds timestamp */
1150 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8
1151 /* Host time immediately after NIC's hardware clock read */
1152 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12
1153 /* Number of nanoseconds waited after reading NIC's hardware clock */
1154 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16
1156 /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */
1157 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8
1158 /* Results of testing */
1159 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
1160 /* enum: Successful test */
1161 #define MC_CMD_PTP_MANF_SUCCESS 0x0
1162 /* enum: FPGA load failed */
1163 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1
1164 /* enum: FPGA version invalid */
1165 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2
1166 /* enum: FPGA registers incorrect */
1167 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
1168 /* enum: Oscillator possibly not working? */
1169 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4
1170 /* enum: Timestamps not increasing */
1171 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5
1172 /* enum: Mismatched packet count */
1173 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6
1174 /* enum: Mismatched packet count (Siena filter and FPGA) */
1175 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7
1176 /* enum: Not enough packets to perform timestamp check */
1177 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
1178 /* enum: Timestamp trigger GPIO not working */
1179 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
1180 /* Presence of external oscillator */
1181 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
1183 /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */
1184 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12
1185 /* Results of testing */
1186 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
1187 /* Number of packets received by FPGA */
1188 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
1189 /* Number of packets received by Siena filters */
1190 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8
1192 /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */
1193 #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1
1194 #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252
1195 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
1196 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
1197 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1
1198 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1
1199 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252
1202 /***********************************/
1203 /* MC_CMD_CSR_READ32
1204 * Read 32bit words from the indirect memory map.
1206 #define MC_CMD_CSR_READ32 0xc
1208 /* MC_CMD_CSR_READ32_IN msgrequest */
1209 #define MC_CMD_CSR_READ32_IN_LEN 12
1211 #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0
1212 #define MC_CMD_CSR_READ32_IN_STEP_OFST 4
1213 #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8
1215 /* MC_CMD_CSR_READ32_OUT msgresponse */
1216 #define MC_CMD_CSR_READ32_OUT_LENMIN 4
1217 #define MC_CMD_CSR_READ32_OUT_LENMAX 252
1218 #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num))
1219 /* The last dword is the status, not a value read */
1220 #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0
1221 #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4
1222 #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1
1223 #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63
1226 /***********************************/
1227 /* MC_CMD_CSR_WRITE32
1228 * Write 32bit dwords to the indirect memory map.
1230 #define MC_CMD_CSR_WRITE32 0xd
1232 /* MC_CMD_CSR_WRITE32_IN msgrequest */
1233 #define MC_CMD_CSR_WRITE32_IN_LENMIN 12
1234 #define MC_CMD_CSR_WRITE32_IN_LENMAX 252
1235 #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num))
1237 #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0
1238 #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4
1239 #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8
1240 #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4
1241 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1
1242 #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61
1244 /* MC_CMD_CSR_WRITE32_OUT msgresponse */
1245 #define MC_CMD_CSR_WRITE32_OUT_LEN 4
1246 #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0
1249 /***********************************/
1251 * These commands are used for HP related features. They are grouped under one
1252 * MCDI command to avoid creating too many MCDI commands.
1254 #define MC_CMD_HP 0x54
1256 /* MC_CMD_HP_IN msgrequest */
1257 #define MC_CMD_HP_IN_LEN 16
1258 /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at
1259 * the specified address with the specified interval.When address is NULL,
1260 * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current
1261 * state / 2: (debug) Show temperature reported by one of the supported
1264 #define MC_CMD_HP_IN_SUBCMD_OFST 0
1265 /* enum: OCSD (Option Card Sensor Data) sub-command. */
1266 #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0
1267 /* enum: Last known valid HP sub-command. */
1268 #define MC_CMD_HP_IN_LAST_SUBCMD 0x0
1269 /* The address to the array of sensor fields. (Or NULL to use a sub-command.)
1271 #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4
1272 #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8
1273 #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4
1274 #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8
1275 /* The requested update interval, in seconds. (Or the sub-command if ADDR is
1278 #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12
1280 /* MC_CMD_HP_OUT msgresponse */
1281 #define MC_CMD_HP_OUT_LEN 4
1282 #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0
1283 /* enum: OCSD stopped for this card. */
1284 #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1
1285 /* enum: OCSD was successfully started with the address provided. */
1286 #define MC_CMD_HP_OUT_OCSD_STARTED 0x2
1287 /* enum: OCSD was already started for this card. */
1288 #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3
1291 /***********************************/
1293 * Get stack information.
1295 #define MC_CMD_STACKINFO 0xf
1297 /* MC_CMD_STACKINFO_IN msgrequest */
1298 #define MC_CMD_STACKINFO_IN_LEN 0
1300 /* MC_CMD_STACKINFO_OUT msgresponse */
1301 #define MC_CMD_STACKINFO_OUT_LENMIN 12
1302 #define MC_CMD_STACKINFO_OUT_LENMAX 252
1303 #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num))
1304 /* (thread ptr, stack size, free space) for each thread in system */
1305 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0
1306 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12
1307 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1
1308 #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21
1311 /***********************************/
1313 * MDIO register read.
1315 #define MC_CMD_MDIO_READ 0x10
1317 /* MC_CMD_MDIO_READ_IN msgrequest */
1318 #define MC_CMD_MDIO_READ_IN_LEN 16
1319 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for
1322 #define MC_CMD_MDIO_READ_IN_BUS_OFST 0
1323 /* enum: Internal. */
1324 #define MC_CMD_MDIO_BUS_INTERNAL 0x0
1325 /* enum: External. */
1326 #define MC_CMD_MDIO_BUS_EXTERNAL 0x1
1328 #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4
1329 /* Device Address or clause 22. */
1330 #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8
1331 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
1332 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
1334 #define MC_CMD_MDIO_CLAUSE22 0x20
1336 #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12
1338 /* MC_CMD_MDIO_READ_OUT msgresponse */
1339 #define MC_CMD_MDIO_READ_OUT_LEN 8
1341 #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0
1342 /* Status the MDIO commands return the raw status bits from the MDIO block. A
1343 * "good" transaction should have the DONE bit set and all other bits clear.
1345 #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4
1347 #define MC_CMD_MDIO_STATUS_GOOD 0x8
1350 /***********************************/
1351 /* MC_CMD_MDIO_WRITE
1352 * MDIO register write.
1354 #define MC_CMD_MDIO_WRITE 0x11
1356 /* MC_CMD_MDIO_WRITE_IN msgrequest */
1357 #define MC_CMD_MDIO_WRITE_IN_LEN 20
1358 /* Bus number; there are two MDIO buses: one for the internal PHY, and one for
1361 #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0
1362 /* enum: Internal. */
1363 /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */
1364 /* enum: External. */
1365 /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */
1367 #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4
1368 /* Device Address or clause 22. */
1369 #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8
1370 /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you
1371 * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22.
1373 /* MC_CMD_MDIO_CLAUSE22 0x20 */
1375 #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12
1377 #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16
1379 /* MC_CMD_MDIO_WRITE_OUT msgresponse */
1380 #define MC_CMD_MDIO_WRITE_OUT_LEN 4
1381 /* Status; the MDIO commands return the raw status bits from the MDIO block. A
1382 * "good" transaction should have the DONE bit set and all other bits clear.
1384 #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0
1386 /* MC_CMD_MDIO_STATUS_GOOD 0x8 */
1389 /***********************************/
1391 * Write DBI register(s).
1393 #define MC_CMD_DBI_WRITE 0x12
1395 /* MC_CMD_DBI_WRITE_IN msgrequest */
1396 #define MC_CMD_DBI_WRITE_IN_LENMIN 12
1397 #define MC_CMD_DBI_WRITE_IN_LENMAX 252
1398 #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num))
1399 /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset
1400 * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF.
1402 #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0
1403 #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12
1404 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1
1405 #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21
1407 /* MC_CMD_DBI_WRITE_OUT msgresponse */
1408 #define MC_CMD_DBI_WRITE_OUT_LEN 0
1410 /* MC_CMD_DBIWROP_TYPEDEF structuredef */
1411 #define MC_CMD_DBIWROP_TYPEDEF_LEN 12
1412 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0
1413 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0
1414 #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32
1415 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4
1416 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16
1417 #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16
1418 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15
1419 #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1
1420 #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14
1421 #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1
1422 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32
1423 #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32
1424 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8
1425 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64
1426 #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32
1429 /***********************************/
1430 /* MC_CMD_PORT_READ32
1431 * Read a 32-bit register from the indirect port register map. The port to
1432 * access is implied by the Shared memory channel used.
1434 #define MC_CMD_PORT_READ32 0x14
1436 /* MC_CMD_PORT_READ32_IN msgrequest */
1437 #define MC_CMD_PORT_READ32_IN_LEN 4
1439 #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0
1441 /* MC_CMD_PORT_READ32_OUT msgresponse */
1442 #define MC_CMD_PORT_READ32_OUT_LEN 8
1444 #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0
1446 #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4
1449 /***********************************/
1450 /* MC_CMD_PORT_WRITE32
1451 * Write a 32-bit register to the indirect port register map. The port to
1452 * access is implied by the Shared memory channel used.
1454 #define MC_CMD_PORT_WRITE32 0x15
1456 /* MC_CMD_PORT_WRITE32_IN msgrequest */
1457 #define MC_CMD_PORT_WRITE32_IN_LEN 8
1459 #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0
1461 #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4
1463 /* MC_CMD_PORT_WRITE32_OUT msgresponse */
1464 #define MC_CMD_PORT_WRITE32_OUT_LEN 4
1466 #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0
1469 /***********************************/
1470 /* MC_CMD_PORT_READ128
1471 * Read a 128-bit register from the indirect port register map. The port to
1472 * access is implied by the Shared memory channel used.
1474 #define MC_CMD_PORT_READ128 0x16
1476 /* MC_CMD_PORT_READ128_IN msgrequest */
1477 #define MC_CMD_PORT_READ128_IN_LEN 4
1479 #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0
1481 /* MC_CMD_PORT_READ128_OUT msgresponse */
1482 #define MC_CMD_PORT_READ128_OUT_LEN 20
1484 #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0
1485 #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16
1487 #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16
1490 /***********************************/
1491 /* MC_CMD_PORT_WRITE128
1492 * Write a 128-bit register to the indirect port register map. The port to
1493 * access is implied by the Shared memory channel used.
1495 #define MC_CMD_PORT_WRITE128 0x17
1497 /* MC_CMD_PORT_WRITE128_IN msgrequest */
1498 #define MC_CMD_PORT_WRITE128_IN_LEN 20
1500 #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0
1502 #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4
1503 #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16
1505 /* MC_CMD_PORT_WRITE128_OUT msgresponse */
1506 #define MC_CMD_PORT_WRITE128_OUT_LEN 4
1508 #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0
1510 /* MC_CMD_CAPABILITIES structuredef */
1511 #define MC_CMD_CAPABILITIES_LEN 4
1512 /* Small buf table. */
1513 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0
1514 #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1
1515 /* Turbo mode (for Maranello). */
1516 #define MC_CMD_CAPABILITIES_TURBO_LBN 1
1517 #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1
1518 /* Turbo mode active (for Maranello). */
1519 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2
1520 #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1
1522 #define MC_CMD_CAPABILITIES_PTP_LBN 3
1523 #define MC_CMD_CAPABILITIES_PTP_WIDTH 1
1525 #define MC_CMD_CAPABILITIES_AOE_LBN 4
1526 #define MC_CMD_CAPABILITIES_AOE_WIDTH 1
1527 /* AOE mode active. */
1528 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5
1529 #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1
1530 /* AOE mode active. */
1531 #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6
1532 #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1
1533 #define MC_CMD_CAPABILITIES_RESERVED_LBN 7
1534 #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25
1537 /***********************************/
1538 /* MC_CMD_GET_BOARD_CFG
1539 * Returns the MC firmware configuration structure.
1541 #define MC_CMD_GET_BOARD_CFG 0x18
1543 /* MC_CMD_GET_BOARD_CFG_IN msgrequest */
1544 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0
1546 /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */
1547 #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96
1548 #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136
1549 #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num))
1550 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
1551 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
1552 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32
1553 /* See MC_CMD_CAPABILITIES */
1554 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36
1555 /* See MC_CMD_CAPABILITIES */
1556 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40
1557 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44
1558 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6
1559 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50
1560 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6
1561 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56
1562 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60
1563 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64
1564 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68
1565 /* This field contains a 16-bit value for each of the types of NVRAM area. The
1566 * values are defined in the firmware/mc/platform/.c file for a specific board
1567 * type, but otherwise have no meaning to the MC; they are used by the driver
1568 * to manage selection of appropriate firmware updates.
1570 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72
1571 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2
1572 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12
1573 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32
1576 /***********************************/
1578 * Read DBI register(s) -- extended functionality
1580 #define MC_CMD_DBI_READX 0x19
1582 /* MC_CMD_DBI_READX_IN msgrequest */
1583 #define MC_CMD_DBI_READX_IN_LENMIN 8
1584 #define MC_CMD_DBI_READX_IN_LENMAX 248
1585 #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num))
1586 /* Each Read op consists of an address (offset 0), VF/CS2) */
1587 #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0
1588 #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8
1589 #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0
1590 #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4
1591 #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1
1592 #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31
1594 /* MC_CMD_DBI_READX_OUT msgresponse */
1595 #define MC_CMD_DBI_READX_OUT_LENMIN 4
1596 #define MC_CMD_DBI_READX_OUT_LENMAX 252
1597 #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num))
1599 #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0
1600 #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4
1601 #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1
1602 #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63
1604 /* MC_CMD_DBIRDOP_TYPEDEF structuredef */
1605 #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8
1606 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0
1607 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0
1608 #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32
1609 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4
1610 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16
1611 #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16
1612 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15
1613 #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1
1614 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14
1615 #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1
1616 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32
1617 #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32
1620 /***********************************/
1621 /* MC_CMD_SET_RAND_SEED
1622 * Set the 16byte seed for the MC pseudo-random generator.
1624 #define MC_CMD_SET_RAND_SEED 0x1a
1626 /* MC_CMD_SET_RAND_SEED_IN msgrequest */
1627 #define MC_CMD_SET_RAND_SEED_IN_LEN 16
1629 #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0
1630 #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16
1632 /* MC_CMD_SET_RAND_SEED_OUT msgresponse */
1633 #define MC_CMD_SET_RAND_SEED_OUT_LEN 0
1636 /***********************************/
1637 /* MC_CMD_LTSSM_HIST
1638 * Retrieve the history of the LTSSM, if the build supports it.
1640 #define MC_CMD_LTSSM_HIST 0x1b
1642 /* MC_CMD_LTSSM_HIST_IN msgrequest */
1643 #define MC_CMD_LTSSM_HIST_IN_LEN 0
1645 /* MC_CMD_LTSSM_HIST_OUT msgresponse */
1646 #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0
1647 #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252
1648 #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num))
1649 /* variable number of LTSSM values, as bytes. The history is read-to-clear. */
1650 #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0
1651 #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4
1652 #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0
1653 #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63
1656 /***********************************/
1657 /* MC_CMD_DRV_ATTACH
1658 * Inform MCPU that this port is managed on the host (i.e. driver active). For
1659 * Huntington, also request the preferred datapath firmware to use if possible
1660 * (it may not be possible for this request to be fulfilled; the driver must
1661 * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which
1662 * features are actually available). The FIRMWARE_ID field is ignored by older
1665 #define MC_CMD_DRV_ATTACH 0x1c
1667 /* MC_CMD_DRV_ATTACH_IN msgrequest */
1668 #define MC_CMD_DRV_ATTACH_IN_LEN 12
1669 /* new state (0=detached, 1=attached) to set if UPDATE=1 */
1670 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
1671 /* 1 to set new state, or 0 to just report the existing state */
1672 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
1673 /* preferred datapath firmware (for Huntington; ignored for Siena) */
1674 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8
1675 /* enum: Prefer to use full featured firmware */
1676 #define MC_CMD_FW_FULL_FEATURED 0x0
1677 /* enum: Prefer to use firmware with fewer features but lower latency */
1678 #define MC_CMD_FW_LOW_LATENCY 0x1
1680 /* MC_CMD_DRV_ATTACH_OUT msgresponse */
1681 #define MC_CMD_DRV_ATTACH_OUT_LEN 4
1682 /* previous or existing state (0=detached, 1=attached) */
1683 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
1685 /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */
1686 #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8
1687 /* previous or existing state (0=detached, 1=attached) */
1688 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
1689 /* Flags associated with this function */
1690 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
1691 /* enum: Labels the lowest-numbered function visible to the OS */
1692 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
1693 /* enum: The function can control the link state of the physical port it is
1696 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
1697 /* enum: The function can perform privileged operations */
1698 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
1701 /***********************************/
1703 * Route UART output to circular buffer in shared memory instead.
1705 #define MC_CMD_SHMUART 0x1f
1707 /* MC_CMD_SHMUART_IN msgrequest */
1708 #define MC_CMD_SHMUART_IN_LEN 4
1710 #define MC_CMD_SHMUART_IN_FLAG_OFST 0
1712 /* MC_CMD_SHMUART_OUT msgresponse */
1713 #define MC_CMD_SHMUART_OUT_LEN 0
1716 /***********************************/
1717 /* MC_CMD_PORT_RESET
1718 * Generic per-port reset. There is no equivalent for per-board reset. Locks
1719 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
1720 * use MC_CMD_ENTITY_RESET instead.
1722 #define MC_CMD_PORT_RESET 0x20
1724 /* MC_CMD_PORT_RESET_IN msgrequest */
1725 #define MC_CMD_PORT_RESET_IN_LEN 0
1727 /* MC_CMD_PORT_RESET_OUT msgresponse */
1728 #define MC_CMD_PORT_RESET_OUT_LEN 0
1731 /***********************************/
1732 /* MC_CMD_ENTITY_RESET
1733 * Generic per-resource reset. There is no equivalent for per-board reset.
1734 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
1735 * extended version of the deprecated MC_CMD_PORT_RESET with added fields.
1737 #define MC_CMD_ENTITY_RESET 0x20
1739 /* MC_CMD_ENTITY_RESET_IN msgrequest */
1740 #define MC_CMD_ENTITY_RESET_IN_LEN 4
1741 /* Optional flags field. Omitting this will perform a "legacy" reset action
1744 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
1745 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
1746 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1
1748 /* MC_CMD_ENTITY_RESET_OUT msgresponse */
1749 #define MC_CMD_ENTITY_RESET_OUT_LEN 0
1752 /***********************************/
1753 /* MC_CMD_PCIE_CREDITS
1754 * Read instantaneous and minimum flow control thresholds.
1756 #define MC_CMD_PCIE_CREDITS 0x21
1758 /* MC_CMD_PCIE_CREDITS_IN msgrequest */
1759 #define MC_CMD_PCIE_CREDITS_IN_LEN 8
1760 /* poll period. 0 is disabled */
1761 #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0
1762 /* wipe statistics */
1763 #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4
1765 /* MC_CMD_PCIE_CREDITS_OUT msgresponse */
1766 #define MC_CMD_PCIE_CREDITS_OUT_LEN 16
1767 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0
1768 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2
1769 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2
1770 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2
1771 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4
1772 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2
1773 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6
1774 #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2
1775 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8
1776 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2
1777 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10
1778 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2
1779 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12
1780 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2
1781 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14
1782 #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2
1785 /***********************************/
1786 /* MC_CMD_RXD_MONITOR
1787 * Get histogram of RX queue fill level.
1789 #define MC_CMD_RXD_MONITOR 0x22
1791 /* MC_CMD_RXD_MONITOR_IN msgrequest */
1792 #define MC_CMD_RXD_MONITOR_IN_LEN 12
1793 #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0
1794 #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4
1795 #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8
1797 /* MC_CMD_RXD_MONITOR_OUT msgresponse */
1798 #define MC_CMD_RXD_MONITOR_OUT_LEN 80
1799 #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0
1800 #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4
1801 #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8
1802 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12
1803 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16
1804 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20
1805 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24
1806 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28
1807 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32
1808 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36
1809 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40
1810 #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44
1811 #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48
1812 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52
1813 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56
1814 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60
1815 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64
1816 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68
1817 #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72
1818 #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76
1821 /***********************************/
1823 * Copy the given ASCII string out onto UART and/or out of the network port.
1825 #define MC_CMD_PUTS 0x23
1827 /* MC_CMD_PUTS_IN msgrequest */
1828 #define MC_CMD_PUTS_IN_LENMIN 13
1829 #define MC_CMD_PUTS_IN_LENMAX 252
1830 #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num))
1831 #define MC_CMD_PUTS_IN_DEST_OFST 0
1832 #define MC_CMD_PUTS_IN_UART_LBN 0
1833 #define MC_CMD_PUTS_IN_UART_WIDTH 1
1834 #define MC_CMD_PUTS_IN_PORT_LBN 1
1835 #define MC_CMD_PUTS_IN_PORT_WIDTH 1
1836 #define MC_CMD_PUTS_IN_DHOST_OFST 4
1837 #define MC_CMD_PUTS_IN_DHOST_LEN 6
1838 #define MC_CMD_PUTS_IN_STRING_OFST 12
1839 #define MC_CMD_PUTS_IN_STRING_LEN 1
1840 #define MC_CMD_PUTS_IN_STRING_MINNUM 1
1841 #define MC_CMD_PUTS_IN_STRING_MAXNUM 240
1843 /* MC_CMD_PUTS_OUT msgresponse */
1844 #define MC_CMD_PUTS_OUT_LEN 0
1847 /***********************************/
1848 /* MC_CMD_GET_PHY_CFG
1849 * Report PHY configuration. This guarantees to succeed even if the PHY is in a
1850 * 'zombie' state. Locks required: None
1852 #define MC_CMD_GET_PHY_CFG 0x24
1854 /* MC_CMD_GET_PHY_CFG_IN msgrequest */
1855 #define MC_CMD_GET_PHY_CFG_IN_LEN 0
1857 /* MC_CMD_GET_PHY_CFG_OUT msgresponse */
1858 #define MC_CMD_GET_PHY_CFG_OUT_LEN 72
1860 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
1861 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
1862 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1
1863 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1
1864 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1
1865 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2
1866 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1
1867 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3
1868 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1
1869 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
1870 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1
1871 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5
1872 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1
1873 #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6
1874 #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1
1876 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
1877 /* Bitmask of supported capabilities */
1878 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8
1879 #define MC_CMD_PHY_CAP_10HDX_LBN 1
1880 #define MC_CMD_PHY_CAP_10HDX_WIDTH 1
1881 #define MC_CMD_PHY_CAP_10FDX_LBN 2
1882 #define MC_CMD_PHY_CAP_10FDX_WIDTH 1
1883 #define MC_CMD_PHY_CAP_100HDX_LBN 3
1884 #define MC_CMD_PHY_CAP_100HDX_WIDTH 1
1885 #define MC_CMD_PHY_CAP_100FDX_LBN 4
1886 #define MC_CMD_PHY_CAP_100FDX_WIDTH 1
1887 #define MC_CMD_PHY_CAP_1000HDX_LBN 5
1888 #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1
1889 #define MC_CMD_PHY_CAP_1000FDX_LBN 6
1890 #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1
1891 #define MC_CMD_PHY_CAP_10000FDX_LBN 7
1892 #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1
1893 #define MC_CMD_PHY_CAP_PAUSE_LBN 8
1894 #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1
1895 #define MC_CMD_PHY_CAP_ASYM_LBN 9
1896 #define MC_CMD_PHY_CAP_ASYM_WIDTH 1
1897 #define MC_CMD_PHY_CAP_AN_LBN 10
1898 #define MC_CMD_PHY_CAP_AN_WIDTH 1
1899 #define MC_CMD_PHY_CAP_40000FDX_LBN 11
1900 #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1
1901 #define MC_CMD_PHY_CAP_DDM_LBN 12
1902 #define MC_CMD_PHY_CAP_DDM_WIDTH 1
1904 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12
1906 #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16
1908 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20
1910 #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24
1911 #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20
1913 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44
1915 #define MC_CMD_MEDIA_XAUI 0x1
1917 #define MC_CMD_MEDIA_CX4 0x2
1919 #define MC_CMD_MEDIA_KX4 0x3
1920 /* enum: XFP Far. */
1921 #define MC_CMD_MEDIA_XFP 0x4
1923 #define MC_CMD_MEDIA_SFP_PLUS 0x5
1924 /* enum: 10GBaseT. */
1925 #define MC_CMD_MEDIA_BASE_T 0x6
1926 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48
1927 /* enum: Native clause 22 */
1928 #define MC_CMD_MMD_CLAUSE22 0x0
1929 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
1930 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
1931 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
1932 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
1933 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
1934 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
1935 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
1936 /* enum: Clause22 proxied over clause45 by PHY. */
1937 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
1938 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
1939 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
1940 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52
1941 #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20
1944 /***********************************/
1945 /* MC_CMD_START_BIST
1946 * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST
1947 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
1949 #define MC_CMD_START_BIST 0x25
1951 /* MC_CMD_START_BIST_IN msgrequest */
1952 #define MC_CMD_START_BIST_IN_LEN 4
1954 #define MC_CMD_START_BIST_IN_TYPE_OFST 0
1955 /* enum: Run the PHY's short cable BIST. */
1956 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1
1957 /* enum: Run the PHY's long cable BIST. */
1958 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2
1959 /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */
1960 #define MC_CMD_BPX_SERDES_BIST 0x3
1961 /* enum: Run the MC loopback tests. */
1962 #define MC_CMD_MC_LOOPBACK_BIST 0x4
1963 /* enum: Run the PHY's standard BIST. */
1964 #define MC_CMD_PHY_BIST 0x5
1965 /* enum: Run MC RAM test. */
1966 #define MC_CMD_MC_MEM_BIST 0x6
1967 /* enum: Run Port RAM test. */
1968 #define MC_CMD_PORT_MEM_BIST 0x7
1969 /* enum: Run register test. */
1970 #define MC_CMD_REG_BIST 0x8
1972 /* MC_CMD_START_BIST_OUT msgresponse */
1973 #define MC_CMD_START_BIST_OUT_LEN 0
1976 /***********************************/
1978 * Poll for BIST completion. Returns a single status code, and optionally some
1979 * PHY specific bist output. The driver should only consume the BIST output
1980 * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't
1981 * successfully parse the BIST output, it should still respect the pass/Fail in
1982 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
1983 * EACCES (if PHY_LOCK is not held).
1985 #define MC_CMD_POLL_BIST 0x26
1987 /* MC_CMD_POLL_BIST_IN msgrequest */
1988 #define MC_CMD_POLL_BIST_IN_LEN 0
1990 /* MC_CMD_POLL_BIST_OUT msgresponse */
1991 #define MC_CMD_POLL_BIST_OUT_LEN 8
1993 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
1994 /* enum: Running. */
1995 #define MC_CMD_POLL_BIST_RUNNING 0x1
1997 #define MC_CMD_POLL_BIST_PASSED 0x2
1999 #define MC_CMD_POLL_BIST_FAILED 0x3
2000 /* enum: Timed-out. */
2001 #define MC_CMD_POLL_BIST_TIMEOUT 0x4
2002 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
2004 /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */
2005 #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36
2007 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
2008 /* Enum values, see field(s): */
2009 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
2010 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
2011 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8
2012 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12
2013 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16
2014 /* Status of each channel A */
2015 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20
2017 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
2019 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
2020 /* enum: Intra-pair short. */
2021 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
2022 /* enum: Inter-pair short. */
2023 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
2025 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
2026 /* Status of each channel B */
2027 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24
2028 /* Enum values, see field(s): */
2029 /* CABLE_STATUS_A */
2030 /* Status of each channel C */
2031 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28
2032 /* Enum values, see field(s): */
2033 /* CABLE_STATUS_A */
2034 /* Status of each channel D */
2035 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32
2036 /* Enum values, see field(s): */
2037 /* CABLE_STATUS_A */
2039 /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */
2040 #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8
2042 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
2043 /* Enum values, see field(s): */
2044 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
2045 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
2046 /* enum: Complete. */
2047 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
2048 /* enum: Bus switch off I2C write. */
2049 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
2050 /* enum: Bus switch off I2C no access IO exp. */
2051 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
2052 /* enum: Bus switch off I2C no access module. */
2053 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
2054 /* enum: IO exp I2C configure. */
2055 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
2056 /* enum: Bus switch I2C no cross talk. */
2057 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
2058 /* enum: Module presence. */
2059 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
2060 /* enum: Module ID I2C access. */
2061 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
2062 /* enum: Module ID sane value. */
2063 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
2065 /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */
2066 #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36
2068 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
2069 /* Enum values, see field(s): */
2070 /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */
2071 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
2072 /* enum: Test has completed. */
2073 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
2074 /* enum: RAM test - walk ones. */
2075 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
2076 /* enum: RAM test - walk zeros. */
2077 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
2078 /* enum: RAM test - walking inversions zeros/ones. */
2079 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
2080 /* enum: RAM test - walking inversions checkerboard. */
2081 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
2082 /* enum: Register test - set / clear individual bits. */
2083 #define MC_CMD_POLL_BIST_MEM_REG 0x5
2084 /* enum: ECC error detected. */
2085 #define MC_CMD_POLL_BIST_MEM_ECC 0x6
2086 /* Failure address, only valid if result is POLL_BIST_FAILED */
2087 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8
2088 /* Bus or address space to which the failure address corresponds */
2089 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12
2090 /* enum: MC MIPS bus. */
2091 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
2092 /* enum: CSR IREG bus. */
2093 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
2094 /* enum: RX DPCPU bus. */
2095 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
2096 /* enum: TX0 DPCPU bus. */
2097 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
2098 /* enum: TX1 DPCPU bus. */
2099 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
2100 /* enum: RX DICPU bus. */
2101 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
2102 /* enum: TX DICPU bus. */
2103 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
2104 /* Pattern written to RAM / register */
2105 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16
2106 /* Actual value read from RAM / register */
2107 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20
2108 /* ECC error mask */
2109 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24
2110 /* ECC parity error mask */
2111 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28
2112 /* ECC fatal error mask */
2113 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32
2116 /***********************************/
2117 /* MC_CMD_FLUSH_RX_QUEUES
2118 * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ
2119 * flushes should be initiated via this MCDI operation, rather than via
2120 * directly writing FLUSH_CMD.
2122 * The flush is completed (either done/fail) asynchronously (after this command
2123 * returns). The driver must still wait for flush done/failure events as usual.
2125 #define MC_CMD_FLUSH_RX_QUEUES 0x27
2127 /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */
2128 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4
2129 #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252
2130 #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num))
2131 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0
2132 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4
2133 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1
2134 #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63
2136 /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */
2137 #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0
2140 /***********************************/
2141 /* MC_CMD_GET_LOOPBACK_MODES
2142 * Returns a bitmask of loopback modes available at each speed.
2144 #define MC_CMD_GET_LOOPBACK_MODES 0x28
2146 /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */
2147 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
2149 /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */
2150 #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40
2151 /* Supported loopbacks. */
2152 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
2153 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8
2154 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
2155 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
2157 #define MC_CMD_LOOPBACK_NONE 0x0
2159 #define MC_CMD_LOOPBACK_DATA 0x1
2161 #define MC_CMD_LOOPBACK_GMAC 0x2
2163 #define MC_CMD_LOOPBACK_XGMII 0x3
2165 #define MC_CMD_LOOPBACK_XGXS 0x4
2167 #define MC_CMD_LOOPBACK_XAUI 0x5
2169 #define MC_CMD_LOOPBACK_GMII 0x6
2171 #define MC_CMD_LOOPBACK_SGMII 0x7
2173 #define MC_CMD_LOOPBACK_XGBR 0x8
2175 #define MC_CMD_LOOPBACK_XFI 0x9
2176 /* enum: XAUI Far. */
2177 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa
2178 /* enum: GMII Far. */
2179 #define MC_CMD_LOOPBACK_GMII_FAR 0xb
2180 /* enum: SGMII Far. */
2181 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc
2182 /* enum: XFI Far. */
2183 #define MC_CMD_LOOPBACK_XFI_FAR 0xd
2185 #define MC_CMD_LOOPBACK_GPHY 0xe
2187 #define MC_CMD_LOOPBACK_PHYXS 0xf
2189 #define MC_CMD_LOOPBACK_PCS 0x10
2190 /* enum: PMA-PMD. */
2191 #define MC_CMD_LOOPBACK_PMAPMD 0x11
2192 /* enum: Cross-Port. */
2193 #define MC_CMD_LOOPBACK_XPORT 0x12
2194 /* enum: XGMII-Wireside. */
2195 #define MC_CMD_LOOPBACK_XGMII_WS 0x13
2196 /* enum: XAUI Wireside. */
2197 #define MC_CMD_LOOPBACK_XAUI_WS 0x14
2198 /* enum: XAUI Wireside Far. */
2199 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
2200 /* enum: XAUI Wireside near. */
2201 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
2202 /* enum: GMII Wireside. */
2203 #define MC_CMD_LOOPBACK_GMII_WS 0x17
2204 /* enum: XFI Wireside. */
2205 #define MC_CMD_LOOPBACK_XFI_WS 0x18
2206 /* enum: XFI Wireside Far. */
2207 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
2208 /* enum: PhyXS Wireside. */
2209 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
2210 /* enum: PMA lanes MAC-Serdes. */
2211 #define MC_CMD_LOOPBACK_PMA_INT 0x1b
2212 /* enum: KR Serdes Parallel (Encoder). */
2213 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c
2214 /* enum: KR Serdes Serial. */
2215 #define MC_CMD_LOOPBACK_SD_FAR 0x1d
2216 /* enum: PMA lanes MAC-Serdes Wireside. */
2217 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
2218 /* enum: KR Serdes Parallel Wireside (Full PCS). */
2219 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
2220 /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */
2221 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
2222 /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */
2223 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
2224 /* enum: KR Serdes Serial Wireside. */
2225 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22
2226 /* Supported loopbacks. */
2227 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8
2228 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8
2229 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8
2230 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12
2231 /* Enum values, see field(s): */
2233 /* Supported loopbacks. */
2234 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16
2235 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8
2236 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16
2237 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20
2238 /* Enum values, see field(s): */
2240 /* Supported loopbacks. */
2241 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24
2242 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8
2243 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24
2244 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28
2245 /* Enum values, see field(s): */
2247 /* Supported loopbacks. */
2248 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32
2249 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8
2250 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32
2251 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36
2252 /* Enum values, see field(s): */
2256 /***********************************/
2258 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
2261 #define MC_CMD_GET_LINK 0x29
2263 /* MC_CMD_GET_LINK_IN msgrequest */
2264 #define MC_CMD_GET_LINK_IN_LEN 0
2266 /* MC_CMD_GET_LINK_OUT msgresponse */
2267 #define MC_CMD_GET_LINK_OUT_LEN 28
2268 /* near-side advertised capabilities */
2269 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0
2270 /* link-partner advertised capabilities */
2271 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
2272 /* Autonegotiated speed in mbit/s. The link may still be down even if this
2275 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8
2276 /* Current loopback setting. */
2277 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12
2278 /* Enum values, see field(s): */
2279 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
2280 #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16
2281 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
2282 #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1
2283 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1
2284 #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1
2285 #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2
2286 #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1
2287 #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3
2288 #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1
2289 /* This returns the negotiated flow control value. */
2290 #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20
2291 /* enum: Flow control is off. */
2292 #define MC_CMD_FCNTL_OFF 0x0
2293 /* enum: Respond to flow control. */
2294 #define MC_CMD_FCNTL_RESPOND 0x1
2295 /* enum: Respond to and Issue flow control. */
2296 #define MC_CMD_FCNTL_BIDIR 0x2
2297 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24
2298 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
2299 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1
2300 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1
2301 #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1
2302 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2
2303 #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1
2304 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3
2305 #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1
2308 /***********************************/
2310 * Write the unified MAC/PHY link configuration. Locks required: None. Return
2311 * code: 0, EINVAL, ETIME
2313 #define MC_CMD_SET_LINK 0x2a
2315 /* MC_CMD_SET_LINK_IN msgrequest */
2316 #define MC_CMD_SET_LINK_IN_LEN 16
2318 #define MC_CMD_SET_LINK_IN_CAP_OFST 0
2320 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
2321 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
2322 #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1
2323 #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1
2324 #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1
2325 #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2
2326 #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1
2327 /* Loopback mode. */
2328 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8
2329 /* Enum values, see field(s): */
2330 /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */
2331 /* A loopback speed of "0" is supported, and means (choose any available
2334 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12
2336 /* MC_CMD_SET_LINK_OUT msgresponse */
2337 #define MC_CMD_SET_LINK_OUT_LEN 0
2340 /***********************************/
2341 /* MC_CMD_SET_ID_LED
2342 * Set identification LED state. Locks required: None. Return code: 0, EINVAL
2344 #define MC_CMD_SET_ID_LED 0x2b
2346 /* MC_CMD_SET_ID_LED_IN msgrequest */
2347 #define MC_CMD_SET_ID_LED_IN_LEN 4
2348 /* Set LED state. */
2349 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
2350 #define MC_CMD_LED_OFF 0x0 /* enum */
2351 #define MC_CMD_LED_ON 0x1 /* enum */
2352 #define MC_CMD_LED_DEFAULT 0x2 /* enum */
2354 /* MC_CMD_SET_ID_LED_OUT msgresponse */
2355 #define MC_CMD_SET_ID_LED_OUT_LEN 0
2358 /***********************************/
2360 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
2362 #define MC_CMD_SET_MAC 0x2c
2364 /* MC_CMD_SET_MAC_IN msgrequest */
2365 #define MC_CMD_SET_MAC_IN_LEN 24
2366 /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of
2367 * EtherII, VLAN, bug16011 padding).
2369 #define MC_CMD_SET_MAC_IN_MTU_OFST 0
2370 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
2371 #define MC_CMD_SET_MAC_IN_ADDR_OFST 8
2372 #define MC_CMD_SET_MAC_IN_ADDR_LEN 8
2373 #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8
2374 #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12
2375 #define MC_CMD_SET_MAC_IN_REJECT_OFST 16
2376 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
2377 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1
2378 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1
2379 #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1
2380 #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20
2381 /* enum: Flow control is off. */
2382 /* MC_CMD_FCNTL_OFF 0x0 */
2383 /* enum: Respond to flow control. */
2384 /* MC_CMD_FCNTL_RESPOND 0x1 */
2385 /* enum: Respond to and Issue flow control. */
2386 /* MC_CMD_FCNTL_BIDIR 0x2 */
2387 /* enum: Auto neg flow control. */
2388 #define MC_CMD_FCNTL_AUTO 0x3
2390 /* MC_CMD_SET_MAC_OUT msgresponse */
2391 #define MC_CMD_SET_MAC_OUT_LEN 0
2394 /***********************************/
2396 * Get generic PHY statistics. This call returns the statistics for a generic
2397 * PHY in a sparse array (indexed by the enumerate). Each value is represented
2398 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
2399 * statistics may be read from the message response. If DMA_ADDR != 0, then the
2400 * statistics are dmad to that (page-aligned location). Locks required: None.
2403 #define MC_CMD_PHY_STATS 0x2d
2405 /* MC_CMD_PHY_STATS_IN msgrequest */
2406 #define MC_CMD_PHY_STATS_IN_LEN 8
2408 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
2409 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8
2410 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
2411 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
2413 /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */
2414 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
2416 /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */
2417 #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3)
2418 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
2419 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
2420 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS
2422 #define MC_CMD_OUI 0x0
2423 /* enum: PMA-PMD Link Up. */
2424 #define MC_CMD_PMA_PMD_LINK_UP 0x1
2425 /* enum: PMA-PMD RX Fault. */
2426 #define MC_CMD_PMA_PMD_RX_FAULT 0x2
2427 /* enum: PMA-PMD TX Fault. */
2428 #define MC_CMD_PMA_PMD_TX_FAULT 0x3
2429 /* enum: PMA-PMD Signal */
2430 #define MC_CMD_PMA_PMD_SIGNAL 0x4
2431 /* enum: PMA-PMD SNR A. */
2432 #define MC_CMD_PMA_PMD_SNR_A 0x5
2433 /* enum: PMA-PMD SNR B. */
2434 #define MC_CMD_PMA_PMD_SNR_B 0x6
2435 /* enum: PMA-PMD SNR C. */
2436 #define MC_CMD_PMA_PMD_SNR_C 0x7
2437 /* enum: PMA-PMD SNR D. */
2438 #define MC_CMD_PMA_PMD_SNR_D 0x8
2439 /* enum: PCS Link Up. */
2440 #define MC_CMD_PCS_LINK_UP 0x9
2441 /* enum: PCS RX Fault. */
2442 #define MC_CMD_PCS_RX_FAULT 0xa
2443 /* enum: PCS TX Fault. */
2444 #define MC_CMD_PCS_TX_FAULT 0xb
2445 /* enum: PCS BER. */
2446 #define MC_CMD_PCS_BER 0xc
2447 /* enum: PCS Block Errors. */
2448 #define MC_CMD_PCS_BLOCK_ERRORS 0xd
2449 /* enum: PhyXS Link Up. */
2450 #define MC_CMD_PHYXS_LINK_UP 0xe
2451 /* enum: PhyXS RX Fault. */
2452 #define MC_CMD_PHYXS_RX_FAULT 0xf
2453 /* enum: PhyXS TX Fault. */
2454 #define MC_CMD_PHYXS_TX_FAULT 0x10
2455 /* enum: PhyXS Align. */
2456 #define MC_CMD_PHYXS_ALIGN 0x11
2457 /* enum: PhyXS Sync. */
2458 #define MC_CMD_PHYXS_SYNC 0x12
2459 /* enum: AN link-up. */
2460 #define MC_CMD_AN_LINK_UP 0x13
2461 /* enum: AN Complete. */
2462 #define MC_CMD_AN_COMPLETE 0x14
2463 /* enum: AN 10GBaseT Status. */
2464 #define MC_CMD_AN_10GBT_STATUS 0x15
2465 /* enum: Clause 22 Link-Up. */
2466 #define MC_CMD_CL22_LINK_UP 0x16
2467 /* enum: (Last entry) */
2468 #define MC_CMD_PHY_NSTATS 0x17
2471 /***********************************/
2473 * Get generic MAC statistics. This call returns unified statistics maintained
2474 * by the MC as it switches between the GMAC and XMAC. The MC will write out
2475 * all supported stats. The driver should zero initialise the buffer to
2476 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
2477 * performed, and the statistics may be read from the message response. If
2478 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
2479 * Locks required: None. Returns: 0, ETIME
2481 #define MC_CMD_MAC_STATS 0x2e
2483 /* MC_CMD_MAC_STATS_IN msgrequest */
2484 #define MC_CMD_MAC_STATS_IN_LEN 16
2486 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
2487 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8
2488 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
2489 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
2490 #define MC_CMD_MAC_STATS_IN_CMD_OFST 8
2491 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0
2492 #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1
2493 #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1
2494 #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1
2495 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2
2496 #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1
2497 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3
2498 #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1
2499 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
2500 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1
2501 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5
2502 #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1
2503 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16
2504 #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16
2505 #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12
2507 /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */
2508 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
2510 /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */
2511 #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3)
2512 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
2513 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8
2514 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
2515 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
2516 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS
2517 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
2518 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
2519 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
2520 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
2521 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
2522 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
2523 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
2524 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
2525 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
2526 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
2527 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
2528 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
2529 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
2530 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
2531 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
2532 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
2533 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
2534 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
2535 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
2536 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
2537 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
2538 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
2539 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
2540 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
2541 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
2542 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
2543 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
2544 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
2545 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
2546 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
2547 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
2548 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
2549 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
2550 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
2551 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
2552 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
2553 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
2554 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
2555 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
2556 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
2557 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
2558 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
2559 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
2560 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
2561 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
2562 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
2563 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
2564 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
2565 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
2566 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
2567 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
2568 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
2569 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
2570 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
2571 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
2572 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
2573 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
2574 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
2575 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
2576 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
2577 /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
2580 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
2581 /* enum: PM discard_bb_overflow counter. Valid for EF10 with
2582 * PM_AND_RXDP_COUNTERS capability only.
2584 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
2585 /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
2588 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
2589 /* enum: PM discard_vfifo_full counter. Valid for EF10 with
2590 * PM_AND_RXDP_COUNTERS capability only.
2592 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
2593 /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
2596 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40
2597 /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
2600 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41
2601 /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS
2604 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
2605 /* enum: RXDP counter: Number of packets dropped due to the queue being
2606 * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
2608 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
2609 /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10
2610 * with PM_AND_RXDP_COUNTERS capability only.
2612 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
2613 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
2614 * PM_AND_RXDP_COUNTERS capability only.
2616 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
2617 /* enum: RXDP counter: Number of times an emergency descriptor fetch was
2618 * performed. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
2620 #define MC_CMD_MAC_RXDP_EMERGENCY_FETCH_CONDITIONS 0x47
2621 /* enum: RXDP counter: Number of times the DPCPU waited for an existing
2622 * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only.
2624 #define MC_CMD_MAC_RXDP_EMERGENCY_WAIT_CONDITIONS 0x48
2625 /* enum: Start of GMAC stats buffer space, for Siena only. */
2626 #define MC_CMD_GMAC_DMABUF_START 0x40
2627 /* enum: End of GMAC stats buffer space, for Siena only. */
2628 #define MC_CMD_GMAC_DMABUF_END 0x5f
2629 #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */
2630 #define MC_CMD_MAC_NSTATS 0x61 /* enum */
2633 /***********************************/
2637 #define MC_CMD_SRIOV 0x30
2639 /* MC_CMD_SRIOV_IN msgrequest */
2640 #define MC_CMD_SRIOV_IN_LEN 12
2641 #define MC_CMD_SRIOV_IN_ENABLE_OFST 0
2642 #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4
2643 #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8
2645 /* MC_CMD_SRIOV_OUT msgresponse */
2646 #define MC_CMD_SRIOV_OUT_LEN 8
2647 #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0
2648 #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4
2650 /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */
2651 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32
2652 /* this is only used for the first record */
2653 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0
2654 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0
2655 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32
2656 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4
2657 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32
2658 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32
2659 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8
2660 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8
2661 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8
2662 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12
2663 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64
2664 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64
2665 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16
2666 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */
2667 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128
2668 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32
2669 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20
2670 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8
2671 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20
2672 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24
2673 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160
2674 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64
2675 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28
2676 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224
2677 #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32
2680 /***********************************/
2682 * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data
2683 * embedded directly in the command.
2685 * A common pattern is for a client to use generation counts to signal a dma
2686 * update of a datastructure. To facilitate this, this MCDI operation can
2687 * contain multiple requests which are executed in strict order. Requests take
2688 * the form of duplicating the entire MCDI request continuously (including the
2689 * requests record, which is ignored in all but the first structure)
2691 * The source data can either come from a DMA from the host, or it can be
2692 * embedded within the request directly, thereby eliminating a DMA read. To
2693 * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and
2694 * ADDR_LO=offset, and inserts the data at %offset from the start of the
2695 * payload. It's the callers responsibility to ensure that the embedded data
2696 * doesn't overlap the records.
2698 * Returns: 0, EINVAL (invalid RID)
2700 #define MC_CMD_MEMCPY 0x31
2702 /* MC_CMD_MEMCPY_IN msgrequest */
2703 #define MC_CMD_MEMCPY_IN_LENMIN 32
2704 #define MC_CMD_MEMCPY_IN_LENMAX 224
2705 #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num))
2706 /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */
2707 #define MC_CMD_MEMCPY_IN_RECORD_OFST 0
2708 #define MC_CMD_MEMCPY_IN_RECORD_LEN 32
2709 #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1
2710 #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7
2712 /* MC_CMD_MEMCPY_OUT msgresponse */
2713 #define MC_CMD_MEMCPY_OUT_LEN 0
2716 /***********************************/
2717 /* MC_CMD_WOL_FILTER_SET
2720 #define MC_CMD_WOL_FILTER_SET 0x32
2722 /* MC_CMD_WOL_FILTER_SET_IN msgrequest */
2723 #define MC_CMD_WOL_FILTER_SET_IN_LEN 192
2724 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
2725 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
2726 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
2727 /* A type value of 1 is unused. */
2728 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
2730 #define MC_CMD_WOL_TYPE_MAGIC 0x0
2731 /* enum: MS Windows Magic */
2732 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
2733 /* enum: IPv4 Syn */
2734 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
2735 /* enum: IPv6 Syn */
2736 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
2738 #define MC_CMD_WOL_TYPE_BITMAP 0x5
2740 #define MC_CMD_WOL_TYPE_LINK 0x6
2741 /* enum: (Above this for future use) */
2742 #define MC_CMD_WOL_TYPE_MAX 0x7
2743 #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8
2744 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
2745 #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46
2747 /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */
2748 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16
2749 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
2750 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
2751 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8
2752 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8
2753 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8
2754 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12
2756 /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */
2757 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20
2758 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
2759 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
2760 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8
2761 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12
2762 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16
2763 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2
2764 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18
2765 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2
2767 /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */
2768 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44
2769 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
2770 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
2771 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8
2772 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16
2773 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24
2774 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16
2775 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40
2776 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2
2777 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42
2778 #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2
2780 /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */
2781 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187
2782 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
2783 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
2784 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8
2785 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48
2786 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56
2787 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128
2788 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184
2789 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1
2790 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185
2791 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1
2792 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186
2793 #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1
2795 /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */
2796 #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12
2797 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
2798 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
2799 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8
2800 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
2801 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1
2802 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1
2803 #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1
2805 /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */
2806 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
2807 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
2810 /***********************************/
2811 /* MC_CMD_WOL_FILTER_REMOVE
2812 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
2814 #define MC_CMD_WOL_FILTER_REMOVE 0x33
2816 /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */
2817 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
2818 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
2820 /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */
2821 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
2824 /***********************************/
2825 /* MC_CMD_WOL_FILTER_RESET
2826 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
2829 #define MC_CMD_WOL_FILTER_RESET 0x34
2831 /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */
2832 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
2833 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
2834 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
2835 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
2837 /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */
2838 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
2841 /***********************************/
2842 /* MC_CMD_SET_MCAST_HASH
2843 * Set the MCAST hash value without otherwise reconfiguring the MAC
2845 #define MC_CMD_SET_MCAST_HASH 0x35
2847 /* MC_CMD_SET_MCAST_HASH_IN msgrequest */
2848 #define MC_CMD_SET_MCAST_HASH_IN_LEN 32
2849 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0
2850 #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16
2851 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16
2852 #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16
2854 /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */
2855 #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0
2858 /***********************************/
2859 /* MC_CMD_NVRAM_TYPES
2860 * Return bitfield indicating available types of virtual NVRAM partitions.
2861 * Locks required: none. Returns: 0
2863 #define MC_CMD_NVRAM_TYPES 0x36
2865 /* MC_CMD_NVRAM_TYPES_IN msgrequest */
2866 #define MC_CMD_NVRAM_TYPES_IN_LEN 0
2868 /* MC_CMD_NVRAM_TYPES_OUT msgresponse */
2869 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4
2870 /* Bit mask of supported types. */
2871 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
2872 /* enum: Disabled callisto. */
2873 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
2874 /* enum: MC firmware. */
2875 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1
2876 /* enum: MC backup firmware. */
2877 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
2878 /* enum: Static configuration Port0. */
2879 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
2880 /* enum: Static configuration Port1. */
2881 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
2882 /* enum: Dynamic configuration Port0. */
2883 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
2884 /* enum: Dynamic configuration Port1. */
2885 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
2886 /* enum: Expansion Rom. */
2887 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
2888 /* enum: Expansion Rom Configuration Port0. */
2889 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
2890 /* enum: Expansion Rom Configuration Port1. */
2891 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
2892 /* enum: Phy Configuration Port0. */
2893 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
2894 /* enum: Phy Configuration Port1. */
2895 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
2897 #define MC_CMD_NVRAM_TYPE_LOG 0xc
2898 /* enum: FPGA image. */
2899 #define MC_CMD_NVRAM_TYPE_FPGA 0xd
2900 /* enum: FPGA backup image */
2901 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
2902 /* enum: FC firmware. */
2903 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf
2904 /* enum: FC backup firmware. */
2905 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
2906 /* enum: CPLD image. */
2907 #define MC_CMD_NVRAM_TYPE_CPLD 0x11
2908 /* enum: Licensing information. */
2909 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12
2911 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13
2914 /***********************************/
2915 /* MC_CMD_NVRAM_INFO
2916 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
2917 * EINVAL (bad type).
2919 #define MC_CMD_NVRAM_INFO 0x37
2921 /* MC_CMD_NVRAM_INFO_IN msgrequest */
2922 #define MC_CMD_NVRAM_INFO_IN_LEN 4
2923 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
2924 /* Enum values, see field(s): */
2925 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
2927 /* MC_CMD_NVRAM_INFO_OUT msgresponse */
2928 #define MC_CMD_NVRAM_INFO_OUT_LEN 24
2929 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
2930 /* Enum values, see field(s): */
2931 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
2932 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
2933 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8
2934 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12
2935 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
2936 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1
2937 #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1
2938 #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1
2939 #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7
2940 #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1
2941 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16
2942 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20
2945 /***********************************/
2946 /* MC_CMD_NVRAM_UPDATE_START
2947 * Start a group of update operations on a virtual NVRAM partition. Locks
2948 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
2949 * PHY_LOCK required and not held).
2951 #define MC_CMD_NVRAM_UPDATE_START 0x38
2953 /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */
2954 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
2955 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
2956 /* Enum values, see field(s): */
2957 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
2959 /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */
2960 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
2963 /***********************************/
2964 /* MC_CMD_NVRAM_READ
2965 * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if
2966 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
2967 * PHY_LOCK required and not held)
2969 #define MC_CMD_NVRAM_READ 0x39
2971 /* MC_CMD_NVRAM_READ_IN msgrequest */
2972 #define MC_CMD_NVRAM_READ_IN_LEN 12
2973 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
2974 /* Enum values, see field(s): */
2975 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
2976 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
2977 /* amount to read in bytes */
2978 #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8
2980 /* MC_CMD_NVRAM_READ_OUT msgresponse */
2981 #define MC_CMD_NVRAM_READ_OUT_LENMIN 1
2982 #define MC_CMD_NVRAM_READ_OUT_LENMAX 252
2983 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
2984 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
2985 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1
2986 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1
2987 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252
2990 /***********************************/
2991 /* MC_CMD_NVRAM_WRITE
2992 * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if
2993 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
2994 * PHY_LOCK required and not held)
2996 #define MC_CMD_NVRAM_WRITE 0x3a
2998 /* MC_CMD_NVRAM_WRITE_IN msgrequest */
2999 #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13
3000 #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252
3001 #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num))
3002 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
3003 /* Enum values, see field(s): */
3004 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3005 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
3006 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8
3007 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12
3008 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1
3009 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1
3010 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240
3012 /* MC_CMD_NVRAM_WRITE_OUT msgresponse */
3013 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0
3016 /***********************************/
3017 /* MC_CMD_NVRAM_ERASE
3018 * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if
3019 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
3020 * PHY_LOCK required and not held)
3022 #define MC_CMD_NVRAM_ERASE 0x3b
3024 /* MC_CMD_NVRAM_ERASE_IN msgrequest */
3025 #define MC_CMD_NVRAM_ERASE_IN_LEN 12
3026 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
3027 /* Enum values, see field(s): */
3028 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3029 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
3030 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8
3032 /* MC_CMD_NVRAM_ERASE_OUT msgresponse */
3033 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0
3036 /***********************************/
3037 /* MC_CMD_NVRAM_UPDATE_FINISH
3038 * Finish a group of update operations on a virtual NVRAM partition. Locks
3039 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad
3040 * type/offset/length), EACCES (if PHY_LOCK required and not held)
3042 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
3044 /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */
3045 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8
3046 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
3047 /* Enum values, see field(s): */
3048 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3049 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
3051 /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */
3052 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
3055 /***********************************/
3059 * The AFTER_ASSERTION flag is intended to be used when the driver notices an
3060 * assertion failure (at which point it is expected to perform a complete tear
3061 * down and reinitialise), to allow both ports to reset the MC once in an
3064 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1,
3065 * which means that they will automatically reboot out of the assertion
3066 * handler, so this is in practise an optional operation. It is still
3067 * recommended that drivers execute this to support custom firmwares with
3068 * REBOOT_ON_ASSERT=0.
3070 * Locks required: NONE Returns: Nothing. You get back a response with ERR=1,
3073 #define MC_CMD_REBOOT 0x3d
3075 /* MC_CMD_REBOOT_IN msgrequest */
3076 #define MC_CMD_REBOOT_IN_LEN 4
3077 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0
3078 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
3080 /* MC_CMD_REBOOT_OUT msgresponse */
3081 #define MC_CMD_REBOOT_OUT_LEN 0
3084 /***********************************/
3086 * Request scheduler info. Locks required: NONE. Returns: An array of
3087 * (timeslice,maximum overrun), one for each thread, in ascending order of
3090 #define MC_CMD_SCHEDINFO 0x3e
3092 /* MC_CMD_SCHEDINFO_IN msgrequest */
3093 #define MC_CMD_SCHEDINFO_IN_LEN 0
3095 /* MC_CMD_SCHEDINFO_OUT msgresponse */
3096 #define MC_CMD_SCHEDINFO_OUT_LENMIN 4
3097 #define MC_CMD_SCHEDINFO_OUT_LENMAX 252
3098 #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num))
3099 #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0
3100 #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4
3101 #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1
3102 #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63
3105 /***********************************/
3106 /* MC_CMD_REBOOT_MODE
3107 * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot
3108 * mode to the specified value. Returns the old mode.
3110 #define MC_CMD_REBOOT_MODE 0x3f
3112 /* MC_CMD_REBOOT_MODE_IN msgrequest */
3113 #define MC_CMD_REBOOT_MODE_IN_LEN 4
3114 #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0
3116 #define MC_CMD_REBOOT_MODE_NORMAL 0x0
3117 /* enum: Power-on Reset. */
3118 #define MC_CMD_REBOOT_MODE_POR 0x2
3119 /* enum: Snapper. */
3120 #define MC_CMD_REBOOT_MODE_SNAPPER 0x3
3121 /* enum: snapper fake POR */
3122 #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4
3123 #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7
3124 #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1
3126 /* MC_CMD_REBOOT_MODE_OUT msgresponse */
3127 #define MC_CMD_REBOOT_MODE_OUT_LEN 4
3128 #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0
3131 /***********************************/
3132 /* MC_CMD_SENSOR_INFO
3133 * Returns information about every available sensor.
3135 * Each sensor has a single (16bit) value, and a corresponding state. The
3136 * mapping between value and state is nominally determined by the MC, but may
3137 * be implemented using up to 2 ranges per sensor.
3139 * This call returns a mask (32bit) of the sensors that are supported by this
3140 * platform, then an array of sensor information structures, in order of sensor
3141 * type (but without gaps for unimplemented sensors). Each structure defines
3142 * the ranges for the corresponding sensor. An unused range is indicated by
3143 * equal limit values. If one range is used, a value outside that range results
3144 * in STATE_FATAL. If two ranges are used, a value outside the second range
3145 * results in STATE_FATAL while a value outside the first and inside the second
3146 * range results in STATE_WARNING.
3148 * Sensor masks and sensor information arrays are organised into pages. For
3149 * backward compatibility, older host software can only use sensors in page 0.
3150 * Bit 32 in the sensor mask was previously unused, and is no reserved for use
3151 * as the next page flag.
3153 * If the request does not contain a PAGE value then firmware will only return
3154 * page 0 of sensor information, with bit 31 in the sensor mask cleared.
3156 * If the request contains a PAGE value then firmware responds with the sensor
3157 * mask and sensor information array for that page of sensors. In this case bit
3158 * 31 in the mask is set if another page exists.
3160 * Locks required: None Returns: 0
3162 #define MC_CMD_SENSOR_INFO 0x41
3164 /* MC_CMD_SENSOR_INFO_IN msgrequest */
3165 #define MC_CMD_SENSOR_INFO_IN_LEN 0
3167 /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */
3168 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
3169 /* Which page of sensors to report.
3171 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
3173 * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc.
3175 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
3177 /* MC_CMD_SENSOR_INFO_OUT msgresponse */
3178 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 12
3179 #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252
3180 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
3181 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
3182 /* enum: Controller temperature: degC */
3183 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
3184 /* enum: Phy common temperature: degC */
3185 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
3186 /* enum: Controller cooling: bool */
3187 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
3188 /* enum: Phy 0 temperature: degC */
3189 #define MC_CMD_SENSOR_PHY0_TEMP 0x3
3190 /* enum: Phy 0 cooling: bool */
3191 #define MC_CMD_SENSOR_PHY0_COOLING 0x4
3192 /* enum: Phy 1 temperature: degC */
3193 #define MC_CMD_SENSOR_PHY1_TEMP 0x5
3194 /* enum: Phy 1 cooling: bool */
3195 #define MC_CMD_SENSOR_PHY1_COOLING 0x6
3196 /* enum: 1.0v power: mV */
3197 #define MC_CMD_SENSOR_IN_1V0 0x7
3198 /* enum: 1.2v power: mV */
3199 #define MC_CMD_SENSOR_IN_1V2 0x8
3200 /* enum: 1.8v power: mV */
3201 #define MC_CMD_SENSOR_IN_1V8 0x9
3202 /* enum: 2.5v power: mV */
3203 #define MC_CMD_SENSOR_IN_2V5 0xa
3204 /* enum: 3.3v power: mV */
3205 #define MC_CMD_SENSOR_IN_3V3 0xb
3206 /* enum: 12v power: mV */
3207 #define MC_CMD_SENSOR_IN_12V0 0xc
3208 /* enum: 1.2v analogue power: mV */
3209 #define MC_CMD_SENSOR_IN_1V2A 0xd
3210 /* enum: reference voltage: mV */
3211 #define MC_CMD_SENSOR_IN_VREF 0xe
3212 /* enum: AOE FPGA power: mV */
3213 #define MC_CMD_SENSOR_OUT_VAOE 0xf
3214 /* enum: AOE FPGA temperature: degC */
3215 #define MC_CMD_SENSOR_AOE_TEMP 0x10
3216 /* enum: AOE FPGA PSU temperature: degC */
3217 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
3218 /* enum: AOE PSU temperature: degC */
3219 #define MC_CMD_SENSOR_PSU_TEMP 0x12
3220 /* enum: Fan 0 speed: RPM */
3221 #define MC_CMD_SENSOR_FAN_0 0x13
3222 /* enum: Fan 1 speed: RPM */
3223 #define MC_CMD_SENSOR_FAN_1 0x14
3224 /* enum: Fan 2 speed: RPM */
3225 #define MC_CMD_SENSOR_FAN_2 0x15
3226 /* enum: Fan 3 speed: RPM */
3227 #define MC_CMD_SENSOR_FAN_3 0x16
3228 /* enum: Fan 4 speed: RPM */
3229 #define MC_CMD_SENSOR_FAN_4 0x17
3230 /* enum: AOE FPGA input power: mV */
3231 #define MC_CMD_SENSOR_IN_VAOE 0x18
3232 /* enum: AOE FPGA current: mA */
3233 #define MC_CMD_SENSOR_OUT_IAOE 0x19
3234 /* enum: AOE FPGA input current: mA */
3235 #define MC_CMD_SENSOR_IN_IAOE 0x1a
3236 /* enum: NIC power consumption: W */
3237 #define MC_CMD_SENSOR_NIC_POWER 0x1b
3238 /* enum: 0.9v power voltage: mV */
3239 #define MC_CMD_SENSOR_IN_0V9 0x1c
3240 /* enum: 0.9v power current: mA */
3241 #define MC_CMD_SENSOR_IN_I0V9 0x1d
3242 /* enum: 1.2v power current: mA */
3243 #define MC_CMD_SENSOR_IN_I1V2 0x1e
3244 /* enum: Not a sensor: reserved for the next page flag */
3245 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
3246 /* enum: 0.9v power voltage (at ADC): mV */
3247 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20
3248 /* enum: Controller temperature 2: degC */
3249 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
3250 /* enum: Voltage regulator internal temperature: degC */
3251 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
3252 /* enum: 0.9V voltage regulator temperature: degC */
3253 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
3254 /* enum: 1.2V voltage regulator temperature: degC */
3255 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
3256 /* enum: controller internal temperature sensor voltage (internal ADC): mV */
3257 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
3258 /* enum: controller internal temperature (internal ADC): degC */
3259 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
3260 /* enum: controller internal temperature sensor voltage (external ADC): mV */
3261 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
3262 /* enum: controller internal temperature (external ADC): degC */
3263 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
3264 /* enum: ambient temperature: degC */
3265 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
3266 /* enum: air flow: bool */
3267 #define MC_CMD_SENSOR_AIRFLOW 0x2a
3268 /* enum: voltage between VSS08D and VSS08D at CSR: mV */
3269 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
3270 /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */
3271 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
3272 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
3273 #define MC_CMD_SENSOR_ENTRY_OFST 4
3274 #define MC_CMD_SENSOR_ENTRY_LEN 8
3275 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4
3276 #define MC_CMD_SENSOR_ENTRY_HI_OFST 8
3277 #define MC_CMD_SENSOR_ENTRY_MINNUM 1
3278 #define MC_CMD_SENSOR_ENTRY_MAXNUM 31
3280 /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */
3281 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 12
3282 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252
3283 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
3284 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
3285 /* Enum values, see field(s): */
3286 /* MC_CMD_SENSOR_INFO_OUT */
3287 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31
3288 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1
3289 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */
3290 /* MC_CMD_SENSOR_ENTRY_OFST 4 */
3291 /* MC_CMD_SENSOR_ENTRY_LEN 8 */
3292 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
3293 /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */
3294 /* MC_CMD_SENSOR_ENTRY_MINNUM 1 */
3295 /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */
3297 /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */
3298 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8
3299 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
3300 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2
3301 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
3302 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16
3303 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2
3304 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2
3305 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16
3306 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16
3307 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
3308 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2
3309 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32
3310 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16
3311 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6
3312 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2
3313 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48
3314 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16
3317 /***********************************/
3318 /* MC_CMD_READ_SENSORS
3319 * Returns the current reading from each sensor. DMAs an array of sensor
3320 * readings, in order of sensor type (but without gaps for unimplemented
3321 * sensors), into host memory. Each array element is a
3322 * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword.
3324 * If the request does not contain the LENGTH field then only sensors 0 to 30
3325 * are reported, to avoid DMA buffer overflow in older host software. If the
3326 * sensor reading require more space than the LENGTH allows, then return
3329 * The MC will send a SENSOREVT event every time any sensor changes state. The
3330 * driver is responsible for ensuring that it doesn't miss any events. The
3331 * board will function normally if all sensors are in STATE_OK or
3332 * STATE_WARNING. Otherwise the board should not be expected to function.
3334 #define MC_CMD_READ_SENSORS 0x42
3336 /* MC_CMD_READ_SENSORS_IN msgrequest */
3337 #define MC_CMD_READ_SENSORS_IN_LEN 8
3338 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */
3339 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
3340 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8
3341 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
3342 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
3344 /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */
3345 #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12
3346 /* DMA address of host buffer for sensor readings */
3347 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
3348 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8
3349 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
3350 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
3351 /* Size in bytes of host buffer. */
3352 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8
3354 /* MC_CMD_READ_SENSORS_OUT msgresponse */
3355 #define MC_CMD_READ_SENSORS_OUT_LEN 0
3357 /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */
3358 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
3360 /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */
3361 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
3362 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
3363 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2
3364 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
3365 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16
3366 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2
3367 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1
3369 #define MC_CMD_SENSOR_STATE_OK 0x0
3370 /* enum: Breached warning threshold. */
3371 #define MC_CMD_SENSOR_STATE_WARNING 0x1
3372 /* enum: Breached fatal threshold. */
3373 #define MC_CMD_SENSOR_STATE_FATAL 0x2
3374 /* enum: Fault with sensor. */
3375 #define MC_CMD_SENSOR_STATE_BROKEN 0x3
3376 /* enum: Sensor is working but does not currently have a reading. */
3377 #define MC_CMD_SENSOR_STATE_NO_READING 0x4
3378 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16
3379 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8
3380 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3
3381 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1
3382 /* Enum values, see field(s): */
3383 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
3384 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24
3385 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8
3388 /***********************************/
3389 /* MC_CMD_GET_PHY_STATE
3390 * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot
3391 * (e.g. due to missing or corrupted firmware). Locks required: None. Return
3394 #define MC_CMD_GET_PHY_STATE 0x43
3396 /* MC_CMD_GET_PHY_STATE_IN msgrequest */
3397 #define MC_CMD_GET_PHY_STATE_IN_LEN 0
3399 /* MC_CMD_GET_PHY_STATE_OUT msgresponse */
3400 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4
3401 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
3403 #define MC_CMD_PHY_STATE_OK 0x1
3405 #define MC_CMD_PHY_STATE_ZOMBIE 0x2
3408 /***********************************/
3409 /* MC_CMD_SETUP_8021QBB
3410 * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to
3411 * disable 802.Qbb for a given priority.
3413 #define MC_CMD_SETUP_8021QBB 0x44
3415 /* MC_CMD_SETUP_8021QBB_IN msgrequest */
3416 #define MC_CMD_SETUP_8021QBB_IN_LEN 32
3417 #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0
3418 #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32
3420 /* MC_CMD_SETUP_8021QBB_OUT msgresponse */
3421 #define MC_CMD_SETUP_8021QBB_OUT_LEN 0
3424 /***********************************/
3425 /* MC_CMD_WOL_FILTER_GET
3426 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
3428 #define MC_CMD_WOL_FILTER_GET 0x45
3430 /* MC_CMD_WOL_FILTER_GET_IN msgrequest */
3431 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0
3433 /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */
3434 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
3435 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
3438 /***********************************/
3439 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD
3440 * Add a protocol offload to NIC for lights-out state. Locks required: None.
3441 * Returns: 0, ENOSYS
3443 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46
3445 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */
3446 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8
3447 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252
3448 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num))
3449 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
3450 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */
3451 #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */
3452 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4
3453 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4
3454 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1
3455 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62
3457 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */
3458 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14
3459 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
3460 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4
3461 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6
3462 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10
3464 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */
3465 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42
3466 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */
3467 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4
3468 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6
3469 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10
3470 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16
3471 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26
3472 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16
3474 /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */
3475 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4
3476 #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0
3479 /***********************************/
3480 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD
3481 * Remove a protocol offload from NIC for lights-out state. Locks required:
3482 * None. Returns: 0, ENOSYS
3484 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47
3486 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */
3487 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8
3488 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0
3489 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4
3491 /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */
3492 #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0
3495 /***********************************/
3496 /* MC_CMD_MAC_RESET_RESTORE
3497 * Restore MAC after block reset. Locks required: None. Returns: 0.
3499 #define MC_CMD_MAC_RESET_RESTORE 0x48
3501 /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */
3502 #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0
3504 /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */
3505 #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0
3508 /***********************************/
3509 /* MC_CMD_TESTASSERT
3510 * Deliberately trigger an assert-detonation in the firmware for testing
3511 * purposes (i.e. to allow tests that the driver copes gracefully). Locks
3512 * required: None Returns: 0
3514 #define MC_CMD_TESTASSERT 0x49
3516 /* MC_CMD_TESTASSERT_IN msgrequest */
3517 #define MC_CMD_TESTASSERT_IN_LEN 0
3519 /* MC_CMD_TESTASSERT_OUT msgresponse */
3520 #define MC_CMD_TESTASSERT_OUT_LEN 0
3523 /***********************************/
3524 /* MC_CMD_WORKAROUND
3525 * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't
3526 * understand the given workaround number - which should not be treated as a
3527 * hard error by client code. This op does not imply any semantics about each
3528 * workaround, that's between the driver and the mcfw on a per-workaround
3529 * basis. Locks required: None. Returns: 0, EINVAL .
3531 #define MC_CMD_WORKAROUND 0x4a
3533 /* MC_CMD_WORKAROUND_IN msgrequest */
3534 #define MC_CMD_WORKAROUND_IN_LEN 8
3535 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
3536 /* enum: Bug 17230 work around. */
3537 #define MC_CMD_WORKAROUND_BUG17230 0x1
3538 /* enum: Bug 35388 work around (unsafe EVQ writes). */
3539 #define MC_CMD_WORKAROUND_BUG35388 0x2
3540 /* enum: Bug35017 workaround (A64 tables must be identity map) */
3541 #define MC_CMD_WORKAROUND_BUG35017 0x3
3542 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
3544 /* MC_CMD_WORKAROUND_OUT msgresponse */
3545 #define MC_CMD_WORKAROUND_OUT_LEN 0
3548 /***********************************/
3549 /* MC_CMD_GET_PHY_MEDIA_INFO
3550 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
3551 * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG
3552 * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the
3553 * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1
3554 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
3555 * Anything else: currently undefined. Locks required: None. Return code: 0.
3557 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
3559 /* MC_CMD_GET_PHY_MEDIA_INFO_IN msgrequest */
3560 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
3561 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
3563 /* MC_CMD_GET_PHY_MEDIA_INFO_OUT msgresponse */
3564 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMIN 5
3565 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LENMAX 252
3566 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
3568 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
3569 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
3570 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_LEN 1
3571 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MINNUM 1
3572 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_MAXNUM 248
3575 /***********************************/
3576 /* MC_CMD_NVRAM_TEST
3577 * Test a particular NVRAM partition for valid contents (where "valid" depends
3578 * on the type of partition).
3580 #define MC_CMD_NVRAM_TEST 0x4c
3582 /* MC_CMD_NVRAM_TEST_IN msgrequest */
3583 #define MC_CMD_NVRAM_TEST_IN_LEN 4
3584 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
3585 /* Enum values, see field(s): */
3586 /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */
3588 /* MC_CMD_NVRAM_TEST_OUT msgresponse */
3589 #define MC_CMD_NVRAM_TEST_OUT_LEN 4
3590 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
3592 #define MC_CMD_NVRAM_TEST_PASS 0x0
3594 #define MC_CMD_NVRAM_TEST_FAIL 0x1
3595 /* enum: Not supported. */
3596 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2
3599 /***********************************/
3600 /* MC_CMD_MRSFP_TWEAK
3601 * Read status and/or set parameters for the 'mrsfp' driver in mr_rusty builds.
3602 * I2C I/O expander bits are always read; if equaliser parameters are supplied,
3603 * they are configured first. Locks required: None. Return code: 0, EINVAL.
3605 #define MC_CMD_MRSFP_TWEAK 0x4d
3607 /* MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG msgrequest */
3608 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_LEN 16
3609 /* 0-6 low->high de-emph. */
3610 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_LEVEL_OFST 0
3611 /* 0-8 low->high ref.V */
3612 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_TXEQ_DT_CFG_OFST 4
3613 /* 0-8 0-8 low->high boost */
3614 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_BOOST_OFST 8
3615 /* 0-8 low->high ref.V */
3616 #define MC_CMD_MRSFP_TWEAK_IN_EQ_CONFIG_RXEQ_DT_CFG_OFST 12
3618 /* MC_CMD_MRSFP_TWEAK_IN_READ_ONLY msgrequest */
3619 #define MC_CMD_MRSFP_TWEAK_IN_READ_ONLY_LEN 0
3621 /* MC_CMD_MRSFP_TWEAK_OUT msgresponse */
3622 #define MC_CMD_MRSFP_TWEAK_OUT_LEN 12
3624 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0
3626 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4
3628 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8
3630 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OUT 0x0
3632 #define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_IN 0x1
3635 /***********************************/
3636 /* MC_CMD_SENSOR_SET_LIMS
3637 * Adjusts the sensor limits. This is a warranty-voiding operation. Returns:
3638 * ENOENT if the sensor specified does not exist, EINVAL if the limits are out
3641 #define MC_CMD_SENSOR_SET_LIMS 0x4e
3643 /* MC_CMD_SENSOR_SET_LIMS_IN msgrequest */
3644 #define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20
3645 #define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0
3646 /* Enum values, see field(s): */
3647 /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */
3648 /* interpretation is is sensor-specific. */
3649 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4
3650 /* interpretation is is sensor-specific. */
3651 #define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8
3652 /* interpretation is is sensor-specific. */
3653 #define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12
3654 /* interpretation is is sensor-specific. */
3655 #define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16
3657 /* MC_CMD_SENSOR_SET_LIMS_OUT msgresponse */
3658 #define MC_CMD_SENSOR_SET_LIMS_OUT_LEN 0
3661 /***********************************/
3662 /* MC_CMD_GET_RESOURCE_LIMITS
3664 #define MC_CMD_GET_RESOURCE_LIMITS 0x4f
3666 /* MC_CMD_GET_RESOURCE_LIMITS_IN msgrequest */
3667 #define MC_CMD_GET_RESOURCE_LIMITS_IN_LEN 0
3669 /* MC_CMD_GET_RESOURCE_LIMITS_OUT msgresponse */
3670 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_LEN 16
3671 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_BUFTBL_OFST 0
3672 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_EVQ_OFST 4
3673 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_RXQ_OFST 8
3674 #define MC_CMD_GET_RESOURCE_LIMITS_OUT_TXQ_OFST 12
3677 /***********************************/
3678 /* MC_CMD_NVRAM_PARTITIONS
3679 * Reads the list of available virtual NVRAM partition types. Locks required:
3680 * none. Returns: 0, EINVAL (bad type).
3682 #define MC_CMD_NVRAM_PARTITIONS 0x51
3684 /* MC_CMD_NVRAM_PARTITIONS_IN msgrequest */
3685 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
3687 /* MC_CMD_NVRAM_PARTITIONS_OUT msgresponse */
3688 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
3689 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMAX 252
3690 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
3691 /* total number of partitions */
3692 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
3693 /* type ID code for each of NUM_PARTITIONS partitions */
3694 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
3695 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
3696 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
3697 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MAXNUM 62
3700 /***********************************/
3701 /* MC_CMD_NVRAM_METADATA
3702 * Reads soft metadata for a virtual NVRAM partition type. Locks required:
3703 * none. Returns: 0, EINVAL (bad type).
3705 #define MC_CMD_NVRAM_METADATA 0x52
3707 /* MC_CMD_NVRAM_METADATA_IN msgrequest */
3708 #define MC_CMD_NVRAM_METADATA_IN_LEN 4
3709 /* Partition type ID code */
3710 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
3712 /* MC_CMD_NVRAM_METADATA_OUT msgresponse */
3713 #define MC_CMD_NVRAM_METADATA_OUT_LENMIN 20
3714 #define MC_CMD_NVRAM_METADATA_OUT_LENMAX 252
3715 #define MC_CMD_NVRAM_METADATA_OUT_LEN(num) (20+1*(num))
3716 /* Partition type ID code */
3717 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
3718 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
3719 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
3720 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_WIDTH 1
3721 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_LBN 1
3722 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_WIDTH 1
3723 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_LBN 2
3724 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_WIDTH 1
3725 /* Subtype ID code for content of this partition */
3726 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_OFST 8
3727 /* 1st component of W.X.Y.Z version number for content of this partition */
3728 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_OFST 12
3729 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_W_LEN 2
3730 /* 2nd component of W.X.Y.Z version number for content of this partition */
3731 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_OFST 14
3732 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_X_LEN 2
3733 /* 3rd component of W.X.Y.Z version number for content of this partition */
3734 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_OFST 16
3735 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Y_LEN 2
3736 /* 4th component of W.X.Y.Z version number for content of this partition */
3737 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_OFST 18
3738 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_Z_LEN 2
3739 /* Zero-terminated string describing the content of this partition */
3740 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_OFST 20
3741 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_LEN 1
3742 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
3743 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MAXNUM 232
3746 /***********************************/
3747 /* MC_CMD_GET_MAC_ADDRESSES
3748 * Returns the base MAC, count and stride for the requestiong function
3750 #define MC_CMD_GET_MAC_ADDRESSES 0x55
3752 /* MC_CMD_GET_MAC_ADDRESSES_IN msgrequest */
3753 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
3755 /* MC_CMD_GET_MAC_ADDRESSES_OUT msgresponse */
3756 #define MC_CMD_GET_MAC_ADDRESSES_OUT_LEN 16
3757 /* Base MAC address */
3758 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
3759 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_LEN 6
3761 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_OFST 6
3762 #define MC_CMD_GET_MAC_ADDRESSES_OUT_RESERVED_LEN 2
3763 /* Number of allocated MAC addresses */
3764 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_OFST 8
3765 /* Spacing of allocated MAC addresses */
3766 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_OFST 12
3768 /* MC_CMD_RESOURCE_SPECIFIER enum */
3770 #define MC_CMD_RESOURCE_INSTANCE_ANY 0xffffffff
3772 #define MC_CMD_RESOURCE_INSTANCE_NONE 0xfffffffe
3774 /* EVB_PORT_ID structuredef */
3775 #define EVB_PORT_ID_LEN 4
3776 #define EVB_PORT_ID_PORT_ID_OFST 0
3777 /* enum: An invalid port handle. */
3778 #define EVB_PORT_ID_NULL 0x0
3779 /* enum: The port assigned to this function.. */
3780 #define EVB_PORT_ID_ASSIGNED 0x1000000
3781 /* enum: External network port 0 */
3782 #define EVB_PORT_ID_MAC0 0x2000000
3783 /* enum: External network port 1 */
3784 #define EVB_PORT_ID_MAC1 0x2000001
3785 /* enum: External network port 2 */
3786 #define EVB_PORT_ID_MAC2 0x2000002
3787 /* enum: External network port 3 */
3788 #define EVB_PORT_ID_MAC3 0x2000003
3789 #define EVB_PORT_ID_PORT_ID_LBN 0
3790 #define EVB_PORT_ID_PORT_ID_WIDTH 32
3792 /* EVB_VLAN_TAG structuredef */
3793 #define EVB_VLAN_TAG_LEN 2
3794 /* The VLAN tag value */
3795 #define EVB_VLAN_TAG_VLAN_ID_LBN 0
3796 #define EVB_VLAN_TAG_VLAN_ID_WIDTH 12
3797 #define EVB_VLAN_TAG_MODE_LBN 12
3798 #define EVB_VLAN_TAG_MODE_WIDTH 4
3799 /* enum: Insert the VLAN. */
3800 #define EVB_VLAN_TAG_INSERT 0x0
3801 /* enum: Replace the VLAN if already present. */
3802 #define EVB_VLAN_TAG_REPLACE 0x1
3804 /* BUFTBL_ENTRY structuredef */
3805 #define BUFTBL_ENTRY_LEN 12
3807 #define BUFTBL_ENTRY_OID_OFST 0
3808 #define BUFTBL_ENTRY_OID_LEN 2
3809 #define BUFTBL_ENTRY_OID_LBN 0
3810 #define BUFTBL_ENTRY_OID_WIDTH 16
3811 /* the page parameter as one of ESE_DZ_SMC_PAGE_SIZE_ */
3812 #define BUFTBL_ENTRY_PGSZ_OFST 2
3813 #define BUFTBL_ENTRY_PGSZ_LEN 2
3814 #define BUFTBL_ENTRY_PGSZ_LBN 16
3815 #define BUFTBL_ENTRY_PGSZ_WIDTH 16
3816 /* the raw 64-bit address field from the SMC, not adjusted for page size */
3817 #define BUFTBL_ENTRY_RAWADDR_OFST 4
3818 #define BUFTBL_ENTRY_RAWADDR_LEN 8
3819 #define BUFTBL_ENTRY_RAWADDR_LO_OFST 4
3820 #define BUFTBL_ENTRY_RAWADDR_HI_OFST 8
3821 #define BUFTBL_ENTRY_RAWADDR_LBN 32
3822 #define BUFTBL_ENTRY_RAWADDR_WIDTH 64
3824 /* NVRAM_PARTITION_TYPE structuredef */
3825 #define NVRAM_PARTITION_TYPE_LEN 2
3826 #define NVRAM_PARTITION_TYPE_ID_OFST 0
3827 #define NVRAM_PARTITION_TYPE_ID_LEN 2
3828 /* enum: Primary MC firmware partition */
3829 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
3830 /* enum: Secondary MC firmware partition */
3831 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
3832 /* enum: Expansion ROM partition */
3833 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
3834 /* enum: Static configuration TLV partition */
3835 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
3836 /* enum: Dynamic configuration TLV partition */
3837 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
3838 /* enum: Expansion ROM configuration data for port 0 */
3839 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
3840 /* enum: Expansion ROM configuration data for port 1 */
3841 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
3842 /* enum: Expansion ROM configuration data for port 2 */
3843 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
3844 /* enum: Expansion ROM configuration data for port 3 */
3845 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
3846 /* enum: Non-volatile log output partition */
3847 #define NVRAM_PARTITION_TYPE_LOG 0x700
3848 /* enum: Device state dump output partition */
3849 #define NVRAM_PARTITION_TYPE_DUMP 0x800
3850 /* enum: Application license key storage partition */
3851 #define NVRAM_PARTITION_TYPE_LICENSE 0x900
3852 /* enum: Start of range used for PHY partitions (low 8 bits are the PHY ID) */
3853 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
3854 /* enum: End of range used for PHY partitions (low 8 bits are the PHY ID) */
3855 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
3856 /* enum: Start of reserved value range (firmware may use for any purpose) */
3857 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
3858 /* enum: End of reserved value range (firmware may use for any purpose) */
3859 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
3860 /* enum: Recovery partition map (provided if real map is missing or corrupt) */
3861 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
3862 /* enum: Partition map (real map as stored in flash) */
3863 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
3864 #define NVRAM_PARTITION_TYPE_ID_LBN 0
3865 #define NVRAM_PARTITION_TYPE_ID_WIDTH 16
3868 /***********************************/
3870 * Get a dump of the MCPU registers
3872 #define MC_CMD_READ_REGS 0x50
3874 /* MC_CMD_READ_REGS_IN msgrequest */
3875 #define MC_CMD_READ_REGS_IN_LEN 0
3877 /* MC_CMD_READ_REGS_OUT msgresponse */
3878 #define MC_CMD_READ_REGS_OUT_LEN 308
3879 /* Whether the corresponding register entry contains a valid value */
3880 #define MC_CMD_READ_REGS_OUT_MASK_OFST 0
3881 #define MC_CMD_READ_REGS_OUT_MASK_LEN 16
3882 /* Same order as MIPS GDB (r0-r31, sr, lo, hi, bad, cause, 32 x float, fsr,
3885 #define MC_CMD_READ_REGS_OUT_REGS_OFST 16
3886 #define MC_CMD_READ_REGS_OUT_REGS_LEN 4
3887 #define MC_CMD_READ_REGS_OUT_REGS_NUM 73
3890 /***********************************/
3892 * Set up an event queue according to the supplied parameters. The IN arguments
3893 * end with an address for each 4k of host memory required to back the EVQ.
3895 #define MC_CMD_INIT_EVQ 0x80
3897 /* MC_CMD_INIT_EVQ_IN msgrequest */
3898 #define MC_CMD_INIT_EVQ_IN_LENMIN 44
3899 #define MC_CMD_INIT_EVQ_IN_LENMAX 548
3900 #define MC_CMD_INIT_EVQ_IN_LEN(num) (36+8*(num))
3901 /* Size, in entries */
3902 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
3903 /* Desired instance. Must be set to a specific instance, which is a function
3904 * local queue index.
3906 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
3907 /* The initial timer value. The load value is ignored if the timer mode is DIS.
3909 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_OFST 8
3910 /* The reload value is ignored in one-shot modes */
3911 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_OFST 12
3913 #define MC_CMD_INIT_EVQ_IN_FLAGS_OFST 16
3914 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
3915 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_WIDTH 1
3916 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_LBN 1
3917 #define MC_CMD_INIT_EVQ_IN_FLAG_RPTR_DOS_WIDTH 1
3918 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_LBN 2
3919 #define MC_CMD_INIT_EVQ_IN_FLAG_INT_ARMD_WIDTH 1
3920 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_LBN 3
3921 #define MC_CMD_INIT_EVQ_IN_FLAG_CUT_THRU_WIDTH 1
3922 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
3923 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_WIDTH 1
3924 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_LBN 5
3925 #define MC_CMD_INIT_EVQ_IN_FLAG_TX_MERGE_WIDTH 1
3926 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_OFST 20
3927 /* enum: Disabled */
3928 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
3929 /* enum: Immediate */
3930 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
3931 /* enum: Triggered */
3932 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
3933 /* enum: Hold-off */
3934 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
3935 /* Target EVQ for wakeups if in wakeup mode. */
3936 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_OFST 24
3937 /* Target interrupt if in interrupting mode (note union with target EVQ). Use
3938 * MC_CMD_RESOURCE_INSTANCE_ANY unless a specific one required for test
3941 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_OFST 24
3942 /* Event Counter Mode. */
3943 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_OFST 28
3944 /* enum: Disabled */
3945 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
3946 /* enum: Disabled */
3947 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
3948 /* enum: Disabled */
3949 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
3950 /* enum: Disabled */
3951 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
3952 /* Event queue packet count threshold. */
3953 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_OFST 32
3954 /* 64-bit address of 4k of 4k-aligned host memory buffer */
3955 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_OFST 36
3956 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LEN 8
3957 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_OFST 36
3958 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_OFST 40
3959 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MINNUM 1
3960 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_MAXNUM 64
3962 /* MC_CMD_INIT_EVQ_OUT msgresponse */
3963 #define MC_CMD_INIT_EVQ_OUT_LEN 4
3964 /* Only valid if INTRFLAG was true */
3965 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
3967 /* QUEUE_CRC_MODE structuredef */
3968 #define QUEUE_CRC_MODE_LEN 1
3969 #define QUEUE_CRC_MODE_MODE_LBN 0
3970 #define QUEUE_CRC_MODE_MODE_WIDTH 4
3972 #define QUEUE_CRC_MODE_NONE 0x0
3973 /* enum: CRC Fiber channel over ethernet. */
3974 #define QUEUE_CRC_MODE_FCOE 0x1
3975 /* enum: CRC (digest) iSCSI header only. */
3976 #define QUEUE_CRC_MODE_ISCSI_HDR 0x2
3977 /* enum: CRC (digest) iSCSI header and payload. */
3978 #define QUEUE_CRC_MODE_ISCSI 0x3
3979 /* enum: CRC Fiber channel over IP over ethernet. */
3980 #define QUEUE_CRC_MODE_FCOIPOE 0x4
3981 /* enum: CRC MPA. */
3982 #define QUEUE_CRC_MODE_MPA 0x5
3983 #define QUEUE_CRC_MODE_SPARE_LBN 4
3984 #define QUEUE_CRC_MODE_SPARE_WIDTH 4
3987 /***********************************/
3989 * set up a receive queue according to the supplied parameters. The IN
3990 * arguments end with an address for each 4k of host memory required to back
3993 #define MC_CMD_INIT_RXQ 0x81
3995 /* MC_CMD_INIT_RXQ_IN msgrequest */
3996 #define MC_CMD_INIT_RXQ_IN_LENMIN 36
3997 #define MC_CMD_INIT_RXQ_IN_LENMAX 252
3998 #define MC_CMD_INIT_RXQ_IN_LEN(num) (28+8*(num))
3999 /* Size, in entries */
4000 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
4001 /* The EVQ to send events to. This is an index originally specified to INIT_EVQ
4003 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
4004 /* The value to put in the event data. Check hardware spec. for valid range. */
4005 #define MC_CMD_INIT_RXQ_IN_LABEL_OFST 8
4006 /* Desired instance. Must be set to a specific instance, which is a function
4007 * local queue index.
4009 #define MC_CMD_INIT_RXQ_IN_INSTANCE_OFST 12
4010 /* There will be more flags here. */
4011 #define MC_CMD_INIT_RXQ_IN_FLAGS_OFST 16
4012 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
4013 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_WIDTH 1
4014 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_LBN 1
4015 #define MC_CMD_INIT_RXQ_IN_FLAG_HDR_SPLIT_WIDTH 1
4016 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_LBN 2
4017 #define MC_CMD_INIT_RXQ_IN_FLAG_TIMESTAMP_WIDTH 1
4018 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_LBN 3
4019 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
4020 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_LBN 7
4021 #define MC_CMD_INIT_RXQ_IN_FLAG_CHAIN_WIDTH 1
4022 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_LBN 8
4023 #define MC_CMD_INIT_RXQ_IN_FLAG_PREFIX_WIDTH 1
4024 /* Owner ID to use if in buffer mode (zero if physical) */
4025 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_OFST 20
4026 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
4027 #define MC_CMD_INIT_RXQ_IN_PORT_ID_OFST 24
4028 /* 64-bit address of 4k of 4k-aligned host memory buffer */
4029 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_OFST 28
4030 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LEN 8
4031 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_OFST 28
4032 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_OFST 32
4033 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MINNUM 1
4034 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_MAXNUM 28
4036 /* MC_CMD_INIT_RXQ_OUT msgresponse */
4037 #define MC_CMD_INIT_RXQ_OUT_LEN 0
4040 /***********************************/
4043 #define MC_CMD_INIT_TXQ 0x82
4045 /* MC_CMD_INIT_TXQ_IN msgrequest */
4046 #define MC_CMD_INIT_TXQ_IN_LENMIN 36
4047 #define MC_CMD_INIT_TXQ_IN_LENMAX 252
4048 #define MC_CMD_INIT_TXQ_IN_LEN(num) (28+8*(num))
4049 /* Size, in entries */
4050 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
4051 /* The EVQ to send events to. This is an index originally specified to
4054 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
4055 /* The value to put in the event data. Check hardware spec. for valid range. */
4056 #define MC_CMD_INIT_TXQ_IN_LABEL_OFST 8
4057 /* Desired instance. Must be set to a specific instance, which is a function
4058 * local queue index.
4060 #define MC_CMD_INIT_TXQ_IN_INSTANCE_OFST 12
4061 /* There will be more flags here. */
4062 #define MC_CMD_INIT_TXQ_IN_FLAGS_OFST 16
4063 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
4064 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_WIDTH 1
4065 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_LBN 1
4066 #define MC_CMD_INIT_TXQ_IN_FLAG_IP_CSUM_DIS_WIDTH 1
4067 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_LBN 2
4068 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_CSUM_DIS_WIDTH 1
4069 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_LBN 3
4070 #define MC_CMD_INIT_TXQ_IN_FLAG_TCP_UDP_ONLY_WIDTH 1
4071 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
4072 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
4073 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_LBN 8
4074 #define MC_CMD_INIT_TXQ_IN_FLAG_TIMESTAMP_WIDTH 1
4075 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_LBN 9
4076 #define MC_CMD_INIT_TXQ_IN_FLAG_PACER_BYPASS_WIDTH 1
4077 /* Owner ID to use if in buffer mode (zero if physical) */
4078 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_OFST 20
4079 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
4080 #define MC_CMD_INIT_TXQ_IN_PORT_ID_OFST 24
4081 /* 64-bit address of 4k of 4k-aligned host memory buffer */
4082 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_OFST 28
4083 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LEN 8
4084 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_OFST 28
4085 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_OFST 32
4086 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MINNUM 1
4087 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_MAXNUM 28
4089 /* MC_CMD_INIT_TXQ_OUT msgresponse */
4090 #define MC_CMD_INIT_TXQ_OUT_LEN 0
4093 /***********************************/
4097 * All DMAQs or EVQs that point to the EVQ to tear down must be torn down first
4098 * or the operation will fail with EBUSY
4100 #define MC_CMD_FINI_EVQ 0x83
4102 /* MC_CMD_FINI_EVQ_IN msgrequest */
4103 #define MC_CMD_FINI_EVQ_IN_LEN 4
4104 /* Instance of EVQ to destroy. Should be the same instance as that previously
4105 * passed to INIT_EVQ
4107 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
4109 /* MC_CMD_FINI_EVQ_OUT msgresponse */
4110 #define MC_CMD_FINI_EVQ_OUT_LEN 0
4113 /***********************************/
4117 #define MC_CMD_FINI_RXQ 0x84
4119 /* MC_CMD_FINI_RXQ_IN msgrequest */
4120 #define MC_CMD_FINI_RXQ_IN_LEN 4
4121 /* Instance of RXQ to destroy */
4122 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
4124 /* MC_CMD_FINI_RXQ_OUT msgresponse */
4125 #define MC_CMD_FINI_RXQ_OUT_LEN 0
4128 /***********************************/
4132 #define MC_CMD_FINI_TXQ 0x85
4134 /* MC_CMD_FINI_TXQ_IN msgrequest */
4135 #define MC_CMD_FINI_TXQ_IN_LEN 4
4136 /* Instance of TXQ to destroy */
4137 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
4139 /* MC_CMD_FINI_TXQ_OUT msgresponse */
4140 #define MC_CMD_FINI_TXQ_OUT_LEN 0
4143 /***********************************/
4144 /* MC_CMD_DRIVER_EVENT
4145 * Generate an event on an EVQ belonging to the function issuing the command.
4147 #define MC_CMD_DRIVER_EVENT 0x86
4149 /* MC_CMD_DRIVER_EVENT_IN msgrequest */
4150 #define MC_CMD_DRIVER_EVENT_IN_LEN 12
4151 /* Handle of target EVQ */
4152 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
4153 /* Bits 0 - 63 of event */
4154 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
4155 #define MC_CMD_DRIVER_EVENT_IN_DATA_LEN 8
4156 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
4157 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_OFST 8
4159 /* MC_CMD_DRIVER_EVENT_OUT msgresponse */
4160 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0
4163 /***********************************/
4165 * Execute an arbitrary MCDI command on behalf of a different function, subject
4166 * to security restrictions. The command to be proxied follows immediately
4167 * afterward in the host buffer (or on the UART). This command supercedes
4168 * MC_CMD_SET_FUNC, which remains available for Siena but now deprecated.
4170 #define MC_CMD_PROXY_CMD 0x5b
4172 /* MC_CMD_PROXY_CMD_IN msgrequest */
4173 #define MC_CMD_PROXY_CMD_IN_LEN 4
4174 /* The handle of the target function. */
4175 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
4176 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0
4177 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_WIDTH 16
4178 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_LBN 16
4179 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_WIDTH 16
4180 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
4183 /***********************************/
4184 /* MC_CMD_ALLOC_BUFTBL_CHUNK
4185 * Allocate a set of buffer table entries using the specified owner ID. This
4186 * operation allocates the required buffer table entries (and fails if it
4187 * cannot do so). The buffer table entries will initially be zeroed.
4189 #define MC_CMD_ALLOC_BUFTBL_CHUNK 0x87
4191 /* MC_CMD_ALLOC_BUFTBL_CHUNK_IN msgrequest */
4192 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_LEN 8
4193 /* Owner ID to use */
4194 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_OWNER_OFST 0
4195 /* Size of buffer table pages to use, in bytes (note that only a few values are
4196 * legal on any specific hardware).
4198 #define MC_CMD_ALLOC_BUFTBL_CHUNK_IN_PAGE_SIZE_OFST 4
4200 /* MC_CMD_ALLOC_BUFTBL_CHUNK_OUT msgresponse */
4201 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_LEN 12
4202 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_HANDLE_OFST 0
4203 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_NUMENTRIES_OFST 4
4204 /* Buffer table IDs for use in DMA descriptors. */
4205 #define MC_CMD_ALLOC_BUFTBL_CHUNK_OUT_ID_OFST 8
4208 /***********************************/
4209 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES
4210 * Reprogram a set of buffer table entries in the specified chunk.
4212 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES 0x88
4214 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN msgrequest */
4215 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMIN 20
4216 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LENMAX 252
4217 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_LEN(num) (12+8*(num))
4218 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_HANDLE_OFST 0
4220 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_FIRSTID_OFST 4
4222 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 8
4223 /* Buffer table entry address */
4224 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_OFST 12
4225 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LEN 8
4226 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_LO_OFST 12
4227 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_HI_OFST 16
4228 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MINNUM 1
4229 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_IN_ENTRY_MAXNUM 30
4231 /* MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT msgresponse */
4232 #define MC_CMD_PROGRAM_BUFTBL_ENTRIES_OUT_LEN 0
4235 /***********************************/
4236 /* MC_CMD_FREE_BUFTBL_CHUNK
4238 #define MC_CMD_FREE_BUFTBL_CHUNK 0x89
4240 /* MC_CMD_FREE_BUFTBL_CHUNK_IN msgrequest */
4241 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_LEN 4
4242 #define MC_CMD_FREE_BUFTBL_CHUNK_IN_HANDLE_OFST 0
4244 /* MC_CMD_FREE_BUFTBL_CHUNK_OUT msgresponse */
4245 #define MC_CMD_FREE_BUFTBL_CHUNK_OUT_LEN 0
4248 /***********************************/
4250 * Multiplexed MCDI call for filter operations
4252 #define MC_CMD_FILTER_OP 0x8a
4254 /* MC_CMD_FILTER_OP_IN msgrequest */
4255 #define MC_CMD_FILTER_OP_IN_LEN 108
4256 /* identifies the type of operation requested */
4257 #define MC_CMD_FILTER_OP_IN_OP_OFST 0
4258 /* enum: single-recipient filter insert */
4259 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
4260 /* enum: single-recipient filter remove */
4261 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
4262 /* enum: multi-recipient filter subscribe */
4263 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
4264 /* enum: multi-recipient filter unsubscribe */
4265 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
4266 /* enum: replace one recipient with another (warning - the filter handle may
4269 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
4270 /* filter handle (for remove / unsubscribe operations) */
4271 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
4272 #define MC_CMD_FILTER_OP_IN_HANDLE_LEN 8
4273 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
4274 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_OFST 8
4275 /* The port ID associated with the v-adaptor which should contain this filter.
4277 #define MC_CMD_FILTER_OP_IN_PORT_ID_OFST 12
4278 /* fields to include in match criteria */
4279 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_OFST 16
4280 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
4281 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_WIDTH 1
4282 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_LBN 1
4283 #define MC_CMD_FILTER_OP_IN_MATCH_DST_IP_WIDTH 1
4284 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_LBN 2
4285 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_MAC_WIDTH 1
4286 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_LBN 3
4287 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_PORT_WIDTH 1
4288 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
4289 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_WIDTH 1
4290 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_LBN 5
4291 #define MC_CMD_FILTER_OP_IN_MATCH_DST_PORT_WIDTH 1
4292 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_LBN 6
4293 #define MC_CMD_FILTER_OP_IN_MATCH_ETHER_TYPE_WIDTH 1
4294 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_LBN 7
4295 #define MC_CMD_FILTER_OP_IN_MATCH_INNER_VLAN_WIDTH 1
4296 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_LBN 8
4297 #define MC_CMD_FILTER_OP_IN_MATCH_OUTER_VLAN_WIDTH 1
4298 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_LBN 9
4299 #define MC_CMD_FILTER_OP_IN_MATCH_IP_PROTO_WIDTH 1
4300 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_LBN 10
4301 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF0_WIDTH 1
4302 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_LBN 11
4303 #define MC_CMD_FILTER_OP_IN_MATCH_FWDEF1_WIDTH 1
4304 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_LBN 30
4305 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_MCAST_DST_WIDTH 1
4306 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_LBN 31
4307 #define MC_CMD_FILTER_OP_IN_MATCH_UNKNOWN_UCAST_DST_WIDTH 1
4308 /* receive destination */
4309 #define MC_CMD_FILTER_OP_IN_RX_DEST_OFST 20
4310 /* enum: drop packets */
4311 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
4312 /* enum: receive to host */
4313 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
4314 /* enum: receive to MC */
4315 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
4316 /* enum: loop back to port 0 TX MAC */
4317 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
4318 /* enum: loop back to port 1 TX MAC */
4319 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
4320 /* receive queue handle (for multiple queue modes, this is the base queue) */
4321 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_OFST 24
4323 #define MC_CMD_FILTER_OP_IN_RX_MODE_OFST 28
4324 /* enum: receive to just the specified queue */
4325 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
4326 /* enum: receive to multiple queues using RSS context */
4327 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
4328 /* enum: receive to multiple queues using .1p mapping */
4329 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
4330 /* enum: install a filter entry that will never match; for test purposes only
4332 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
4333 /* RSS context (for RX_MODE_RSS) or .1p mapping handle (for
4334 * RX_MODE_DOT1P_MAPPING), as returned by MC_CMD_RSS_CONTEXT_ALLOC or
4335 * MC_CMD_DOT1P_MAPPING_ALLOC. Note that these handles should be considered
4336 * opaque to the host, although a value of 0xFFFFFFFF is guaranteed never to be
4339 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_OFST 32
4340 /* transmit domain (reserved; set to 0) */
4341 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_OFST 36
4342 /* transmit destination (either set the MAC and/or PM bits for explicit
4343 * control, or set this field to TX_DEST_DEFAULT for sensible default
4346 #define MC_CMD_FILTER_OP_IN_TX_DEST_OFST 40
4347 /* enum: request default behaviour (based on filter type) */
4348 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
4349 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
4350 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_WIDTH 1
4351 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_LBN 1
4352 #define MC_CMD_FILTER_OP_IN_TX_DEST_PM_WIDTH 1
4353 /* source MAC address to match (as bytes in network order) */
4354 #define MC_CMD_FILTER_OP_IN_SRC_MAC_OFST 44
4355 #define MC_CMD_FILTER_OP_IN_SRC_MAC_LEN 6
4356 /* source port to match (as bytes in network order) */
4357 #define MC_CMD_FILTER_OP_IN_SRC_PORT_OFST 50
4358 #define MC_CMD_FILTER_OP_IN_SRC_PORT_LEN 2
4359 /* destination MAC address to match (as bytes in network order) */
4360 #define MC_CMD_FILTER_OP_IN_DST_MAC_OFST 52
4361 #define MC_CMD_FILTER_OP_IN_DST_MAC_LEN 6
4362 /* destination port to match (as bytes in network order) */
4363 #define MC_CMD_FILTER_OP_IN_DST_PORT_OFST 58
4364 #define MC_CMD_FILTER_OP_IN_DST_PORT_LEN 2
4365 /* Ethernet type to match (as bytes in network order) */
4366 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_OFST 60
4367 #define MC_CMD_FILTER_OP_IN_ETHER_TYPE_LEN 2
4368 /* Inner VLAN tag to match (as bytes in network order) */
4369 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_OFST 62
4370 #define MC_CMD_FILTER_OP_IN_INNER_VLAN_LEN 2
4371 /* Outer VLAN tag to match (as bytes in network order) */
4372 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_OFST 64
4373 #define MC_CMD_FILTER_OP_IN_OUTER_VLAN_LEN 2
4374 /* IP protocol to match (in low byte; set high byte to 0) */
4375 #define MC_CMD_FILTER_OP_IN_IP_PROTO_OFST 66
4376 #define MC_CMD_FILTER_OP_IN_IP_PROTO_LEN 2
4377 /* Firmware defined register 0 to match (reserved; set to 0) */
4378 #define MC_CMD_FILTER_OP_IN_FWDEF0_OFST 68
4379 /* Firmware defined register 1 to match (reserved; set to 0) */
4380 #define MC_CMD_FILTER_OP_IN_FWDEF1_OFST 72
4381 /* source IP address to match (as bytes in network order; set last 12 bytes to
4382 * 0 for IPv4 address)
4384 #define MC_CMD_FILTER_OP_IN_SRC_IP_OFST 76
4385 #define MC_CMD_FILTER_OP_IN_SRC_IP_LEN 16
4386 /* destination IP address to match (as bytes in network order; set last 12
4387 * bytes to 0 for IPv4 address)
4389 #define MC_CMD_FILTER_OP_IN_DST_IP_OFST 92
4390 #define MC_CMD_FILTER_OP_IN_DST_IP_LEN 16
4392 /* MC_CMD_FILTER_OP_OUT msgresponse */
4393 #define MC_CMD_FILTER_OP_OUT_LEN 12
4394 /* identifies the type of operation requested */
4395 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0
4396 /* Enum values, see field(s): */
4397 /* MC_CMD_FILTER_OP_IN/OP */
4398 /* Returned filter handle (for insert / subscribe operations). Note that these
4399 * handles should be considered opaque to the host, although a value of
4400 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
4402 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
4403 #define MC_CMD_FILTER_OP_OUT_HANDLE_LEN 8
4404 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
4405 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_OFST 8
4408 /***********************************/
4409 /* MC_CMD_GET_PARSER_DISP_INFO
4410 * Get information related to the parser-dispatcher subsystem
4412 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4
4414 /* MC_CMD_GET_PARSER_DISP_INFO_IN msgrequest */
4415 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
4416 /* identifies the type of operation requested */
4417 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
4418 /* enum: read the list of supported RX filter matches */
4419 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
4421 /* MC_CMD_GET_PARSER_DISP_INFO_OUT msgresponse */
4422 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMIN 8
4423 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LENMAX 252
4424 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
4425 /* identifies the type of operation requested */
4426 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
4427 /* Enum values, see field(s): */
4428 /* MC_CMD_GET_PARSER_DISP_INFO_IN/OP */
4429 /* number of supported match types */
4430 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
4431 /* array of supported match types (valid MATCH_FIELDS values for
4432 * MC_CMD_FILTER_OP) sorted in decreasing priority order
4434 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_OFST 8
4435 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
4436 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
4437 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MAXNUM 61
4440 /***********************************/
4441 /* MC_CMD_PARSER_DISP_RW
4442 * Direct read/write of parser-dispatcher state (DICPUs and LUE) for debugging
4444 #define MC_CMD_PARSER_DISP_RW 0xe5
4446 /* MC_CMD_PARSER_DISP_RW_IN msgrequest */
4447 #define MC_CMD_PARSER_DISP_RW_IN_LEN 32
4448 /* identifies the target of the operation */
4449 #define MC_CMD_PARSER_DISP_RW_IN_TARGET_OFST 0
4450 /* enum: RX dispatcher CPU */
4451 #define MC_CMD_PARSER_DISP_RW_IN_RX_DICPU 0x0
4452 /* enum: TX dispatcher CPU */
4453 #define MC_CMD_PARSER_DISP_RW_IN_TX_DICPU 0x1
4454 /* enum: Lookup engine */
4455 #define MC_CMD_PARSER_DISP_RW_IN_LUE 0x2
4456 /* identifies the type of operation requested */
4457 #define MC_CMD_PARSER_DISP_RW_IN_OP_OFST 4
4458 /* enum: read a word of DICPU DMEM or a LUE entry */
4459 #define MC_CMD_PARSER_DISP_RW_IN_READ 0x0
4460 /* enum: write a word of DICPU DMEM or a LUE entry */
4461 #define MC_CMD_PARSER_DISP_RW_IN_WRITE 0x1
4462 /* enum: read-modify-write a word of DICPU DMEM (not valid for LUE) */
4463 #define MC_CMD_PARSER_DISP_RW_IN_RMW 0x2
4464 /* data memory address or LUE index */
4465 #define MC_CMD_PARSER_DISP_RW_IN_ADDRESS_OFST 8
4466 /* value to write (for DMEM writes) */
4467 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_WRITE_VALUE_OFST 12
4468 /* XOR value (for DMEM read-modify-writes: new = (old & mask) ^ value) */
4469 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_XOR_VALUE_OFST 12
4470 /* AND mask (for DMEM read-modify-writes: new = (old & mask) ^ value) */
4471 #define MC_CMD_PARSER_DISP_RW_IN_DMEM_RMW_AND_MASK_OFST 16
4472 /* value to write (for LUE writes) */
4473 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_OFST 12
4474 #define MC_CMD_PARSER_DISP_RW_IN_LUE_WRITE_VALUE_LEN 20
4476 /* MC_CMD_PARSER_DISP_RW_OUT msgresponse */
4477 #define MC_CMD_PARSER_DISP_RW_OUT_LEN 52
4478 /* value read (for DMEM reads) */
4479 #define MC_CMD_PARSER_DISP_RW_OUT_DMEM_READ_VALUE_OFST 0
4480 /* value read (for LUE reads) */
4481 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_OFST 0
4482 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_READ_VALUE_LEN 20
4483 /* up to 8 32-bit words of additional soft state from the LUE manager (the
4484 * exact content is firmware-dependent and intended only for debug use)
4486 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_OFST 20
4487 #define MC_CMD_PARSER_DISP_RW_OUT_LUE_MGR_STATE_LEN 32
4490 /***********************************/
4491 /* MC_CMD_GET_PF_COUNT
4492 * Get number of PFs on the device.
4494 #define MC_CMD_GET_PF_COUNT 0xb6
4496 /* MC_CMD_GET_PF_COUNT_IN msgrequest */
4497 #define MC_CMD_GET_PF_COUNT_IN_LEN 0
4499 /* MC_CMD_GET_PF_COUNT_OUT msgresponse */
4500 #define MC_CMD_GET_PF_COUNT_OUT_LEN 1
4501 /* Identifies the number of PFs on the device. */
4502 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_OFST 0
4503 #define MC_CMD_GET_PF_COUNT_OUT_PF_COUNT_LEN 1
4506 /***********************************/
4507 /* MC_CMD_SET_PF_COUNT
4508 * Set number of PFs on the device.
4510 #define MC_CMD_SET_PF_COUNT 0xb7
4512 /* MC_CMD_SET_PF_COUNT_IN msgrequest */
4513 #define MC_CMD_SET_PF_COUNT_IN_LEN 4
4514 /* New number of PFs on the device. */
4515 #define MC_CMD_SET_PF_COUNT_IN_PF_COUNT_OFST 0
4517 /* MC_CMD_SET_PF_COUNT_OUT msgresponse */
4518 #define MC_CMD_SET_PF_COUNT_OUT_LEN 0
4521 /***********************************/
4522 /* MC_CMD_GET_PORT_ASSIGNMENT
4523 * Get port assignment for current PCI function.
4525 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
4527 /* MC_CMD_GET_PORT_ASSIGNMENT_IN msgrequest */
4528 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
4530 /* MC_CMD_GET_PORT_ASSIGNMENT_OUT msgresponse */
4531 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
4532 /* Identifies the port assignment for this function. */
4533 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
4536 /***********************************/
4537 /* MC_CMD_SET_PORT_ASSIGNMENT
4538 * Set port assignment for current PCI function.
4540 #define MC_CMD_SET_PORT_ASSIGNMENT 0xb9
4542 /* MC_CMD_SET_PORT_ASSIGNMENT_IN msgrequest */
4543 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_LEN 4
4544 /* Identifies the port assignment for this function. */
4545 #define MC_CMD_SET_PORT_ASSIGNMENT_IN_PORT_OFST 0
4547 /* MC_CMD_SET_PORT_ASSIGNMENT_OUT msgresponse */
4548 #define MC_CMD_SET_PORT_ASSIGNMENT_OUT_LEN 0
4551 /***********************************/
4553 * Allocate VIs for current PCI function.
4555 #define MC_CMD_ALLOC_VIS 0x8b
4557 /* MC_CMD_ALLOC_VIS_IN msgrequest */
4558 #define MC_CMD_ALLOC_VIS_IN_LEN 8
4559 /* The minimum number of VIs that is acceptable */
4560 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
4561 /* The maximum number of VIs that would be useful */
4562 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
4564 /* MC_CMD_ALLOC_VIS_OUT msgresponse */
4565 #define MC_CMD_ALLOC_VIS_OUT_LEN 8
4566 /* The number of VIs allocated on this function */
4567 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
4568 /* The base absolute VI number allocated to this function. Required to
4569 * correctly interpret wakeup events.
4571 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
4574 /***********************************/
4576 * Free VIs for current PCI function. Any linked PIO buffers will be unlinked,
4579 #define MC_CMD_FREE_VIS 0x8c
4581 /* MC_CMD_FREE_VIS_IN msgrequest */
4582 #define MC_CMD_FREE_VIS_IN_LEN 0
4584 /* MC_CMD_FREE_VIS_OUT msgresponse */
4585 #define MC_CMD_FREE_VIS_OUT_LEN 0
4588 /***********************************/
4589 /* MC_CMD_GET_SRIOV_CFG
4590 * Get SRIOV config for this PF.
4592 #define MC_CMD_GET_SRIOV_CFG 0xba
4594 /* MC_CMD_GET_SRIOV_CFG_IN msgrequest */
4595 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0
4597 /* MC_CMD_GET_SRIOV_CFG_OUT msgresponse */
4598 #define MC_CMD_GET_SRIOV_CFG_OUT_LEN 20
4599 /* Number of VFs currently enabled. */
4600 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
4601 /* Max number of VFs before sriov stride and offset may need to be changed. */
4602 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
4603 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_OFST 8
4604 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
4605 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_WIDTH 1
4606 /* RID offset of first VF from PF. */
4607 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_OFST 12
4608 /* RID offset of each subsequent VF from the previous. */
4609 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_OFST 16
4612 /***********************************/
4613 /* MC_CMD_SET_SRIOV_CFG
4614 * Set SRIOV config for this PF.
4616 #define MC_CMD_SET_SRIOV_CFG 0xbb
4618 /* MC_CMD_SET_SRIOV_CFG_IN msgrequest */
4619 #define MC_CMD_SET_SRIOV_CFG_IN_LEN 20
4620 /* Number of VFs currently enabled. */
4621 #define MC_CMD_SET_SRIOV_CFG_IN_VF_CURRENT_OFST 0
4622 /* Max number of VFs before sriov stride and offset may need to be changed. */
4623 #define MC_CMD_SET_SRIOV_CFG_IN_VF_MAX_OFST 4
4624 #define MC_CMD_SET_SRIOV_CFG_IN_FLAGS_OFST 8
4625 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_LBN 0
4626 #define MC_CMD_SET_SRIOV_CFG_IN_VF_ENABLED_WIDTH 1
4627 /* RID offset of first VF from PF, or 0 for no change, or
4628 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate an offset.
4630 #define MC_CMD_SET_SRIOV_CFG_IN_VF_OFFSET_OFST 12
4631 /* RID offset of each subsequent VF from the previous, 0 for no change, or
4632 * MC_CMD_RESOURCE_INSTANCE_ANY to allow the system to allocate a stride.
4634 #define MC_CMD_SET_SRIOV_CFG_IN_VF_STRIDE_OFST 16
4636 /* MC_CMD_SET_SRIOV_CFG_OUT msgresponse */
4637 #define MC_CMD_SET_SRIOV_CFG_OUT_LEN 0
4640 /***********************************/
4641 /* MC_CMD_GET_VI_ALLOC_INFO
4642 * Get information about number of VI's and base VI number allocated to this
4645 #define MC_CMD_GET_VI_ALLOC_INFO 0x8d
4647 /* MC_CMD_GET_VI_ALLOC_INFO_IN msgrequest */
4648 #define MC_CMD_GET_VI_ALLOC_INFO_IN_LEN 0
4650 /* MC_CMD_GET_VI_ALLOC_INFO_OUT msgresponse */
4651 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_LEN 8
4652 /* The number of VIs allocated on this function */
4653 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_COUNT_OFST 0
4654 /* The base absolute VI number allocated to this function. Required to
4655 * correctly interpret wakeup events.
4657 #define MC_CMD_GET_VI_ALLOC_INFO_OUT_VI_BASE_OFST 4
4660 /***********************************/
4661 /* MC_CMD_DUMP_VI_STATE
4662 * For CmdClient use. Dump pertinent information on a specific absolute VI.
4664 #define MC_CMD_DUMP_VI_STATE 0x8e
4666 /* MC_CMD_DUMP_VI_STATE_IN msgrequest */
4667 #define MC_CMD_DUMP_VI_STATE_IN_LEN 4
4668 /* The VI number to query. */
4669 #define MC_CMD_DUMP_VI_STATE_IN_VI_NUMBER_OFST 0
4671 /* MC_CMD_DUMP_VI_STATE_OUT msgresponse */
4672 #define MC_CMD_DUMP_VI_STATE_OUT_LEN 96
4673 /* The PF part of the function owning this VI. */
4674 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_OFST 0
4675 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_PF_LEN 2
4676 /* The VF part of the function owning this VI. */
4677 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_OFST 2
4678 #define MC_CMD_DUMP_VI_STATE_OUT_OWNER_VF_LEN 2
4679 /* Base of VIs allocated to this function. */
4680 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_OFST 4
4681 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_BASE_LEN 2
4682 /* Count of VIs allocated to the owner function. */
4683 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_OFST 6
4684 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VI_COUNT_LEN 2
4685 /* Base interrupt vector allocated to this function. */
4686 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_OFST 8
4687 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_BASE_LEN 2
4688 /* Number of interrupt vectors allocated to this function. */
4689 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_OFST 10
4690 #define MC_CMD_DUMP_VI_STATE_OUT_FUNC_VECTOR_COUNT_LEN 2
4691 /* Raw evq ptr table data. */
4692 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_OFST 12
4693 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LEN 8
4694 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_LO_OFST 12
4695 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EVQ_PTR_RAW_HI_OFST 16
4696 /* Raw evq timer table data. */
4697 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_OFST 20
4698 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LEN 8
4699 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_LO_OFST 20
4700 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_TIMER_RAW_HI_OFST 24
4701 /* Combined metadata field. */
4702 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_OFST 28
4703 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_LBN 0
4704 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_BASE_WIDTH 16
4705 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_LBN 16
4706 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_BUFS_NPAGES_WIDTH 8
4707 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_LBN 24
4708 #define MC_CMD_DUMP_VI_STATE_OUT_VI_EV_META_WKUP_REF_WIDTH 8
4709 /* TXDPCPU raw table data for queue. */
4710 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_OFST 32
4711 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LEN 8
4712 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_LO_OFST 32
4713 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_0_HI_OFST 36
4714 /* TXDPCPU raw table data for queue. */
4715 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_OFST 40
4716 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LEN 8
4717 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_LO_OFST 40
4718 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_1_HI_OFST 44
4719 /* TXDPCPU raw table data for queue. */
4720 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_OFST 48
4721 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LEN 8
4722 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_LO_OFST 48
4723 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_RAW_TBL_2_HI_OFST 52
4724 /* Combined metadata field. */
4725 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_OFST 56
4726 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LEN 8
4727 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_LO_OFST 56
4728 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_HI_OFST 60
4729 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_LBN 0
4730 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_BASE_WIDTH 16
4731 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_LBN 16
4732 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_BUFS_NPAGES_WIDTH 8
4733 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_LBN 24
4734 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_QSTATE_WIDTH 8
4735 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_LBN 32
4736 #define MC_CMD_DUMP_VI_STATE_OUT_VI_TX_META_WAITCOUNT_WIDTH 8
4737 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_LBN 40
4738 #define MC_CMD_DUMP_VI_STATE_OUT_VI_PADDING_WIDTH 24
4739 /* RXDPCPU raw table data for queue. */
4740 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_OFST 64
4741 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LEN 8
4742 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_LO_OFST 64
4743 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_0_HI_OFST 68
4744 /* RXDPCPU raw table data for queue. */
4745 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_OFST 72
4746 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LEN 8
4747 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_LO_OFST 72
4748 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_1_HI_OFST 76
4749 /* Reserved, currently 0. */
4750 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_OFST 80
4751 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LEN 8
4752 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_LO_OFST 80
4753 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_RAW_TBL_2_HI_OFST 84
4754 /* Combined metadata field. */
4755 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_OFST 88
4756 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LEN 8
4757 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_LO_OFST 88
4758 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_HI_OFST 92
4759 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_LBN 0
4760 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_BASE_WIDTH 16
4761 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_LBN 16
4762 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_BUFS_NPAGES_WIDTH 8
4763 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_LBN 24
4764 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_QSTATE_WIDTH 8
4765 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_LBN 32
4766 #define MC_CMD_DUMP_VI_STATE_OUT_VI_RX_META_WAITCOUNT_WIDTH 8
4769 /***********************************/
4770 /* MC_CMD_ALLOC_PIOBUF
4771 * Allocate a push I/O buffer for later use with a tx queue.
4773 #define MC_CMD_ALLOC_PIOBUF 0x8f
4775 /* MC_CMD_ALLOC_PIOBUF_IN msgrequest */
4776 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0
4778 /* MC_CMD_ALLOC_PIOBUF_OUT msgresponse */
4779 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
4780 /* Handle for allocated push I/O buffer. */
4781 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
4784 /***********************************/
4785 /* MC_CMD_FREE_PIOBUF
4786 * Free a push I/O buffer.
4788 #define MC_CMD_FREE_PIOBUF 0x90
4790 /* MC_CMD_FREE_PIOBUF_IN msgrequest */
4791 #define MC_CMD_FREE_PIOBUF_IN_LEN 4
4792 /* Handle for allocated push I/O buffer. */
4793 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
4795 /* MC_CMD_FREE_PIOBUF_OUT msgresponse */
4796 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0
4799 /***********************************/
4800 /* MC_CMD_GET_VI_TLP_PROCESSING
4801 * Get TLP steering and ordering information for a VI.
4803 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
4805 /* MC_CMD_GET_VI_TLP_PROCESSING_IN msgrequest */
4806 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
4807 /* VI number to get information for. */
4808 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
4810 /* MC_CMD_GET_VI_TLP_PROCESSING_OUT msgresponse */
4811 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_LEN 4
4812 /* Transaction processing steering hint 1 for use with the Rx Queue. */
4813 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_OFST 0
4814 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG1_RX_LEN 1
4815 /* Transaction processing steering hint 2 for use with the Ev Queue. */
4816 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_OFST 1
4817 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_TAG2_EV_LEN 1
4818 /* Use Relaxed ordering model for TLPs on this VI. */
4819 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_LBN 16
4820 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_RELAXED_ORDERING_WIDTH 1
4821 /* Use ID based ordering for TLPs on this VI. */
4822 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_LBN 17
4823 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_ID_BASED_ORDERING_WIDTH 1
4824 /* Set no snoop bit for TLPs on this VI. */
4825 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_LBN 18
4826 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_NO_SNOOP_WIDTH 1
4827 /* Enable TPH for TLPs on this VI. */
4828 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_LBN 19
4829 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_TPH_ON_WIDTH 1
4830 #define MC_CMD_GET_VI_TLP_PROCESSING_OUT_DATA_OFST 0
4833 /***********************************/
4834 /* MC_CMD_SET_VI_TLP_PROCESSING
4835 * Set TLP steering and ordering information for a VI.
4837 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
4839 /* MC_CMD_SET_VI_TLP_PROCESSING_IN msgrequest */
4840 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_LEN 8
4841 /* VI number to set information for. */
4842 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
4843 /* Transaction processing steering hint 1 for use with the Rx Queue. */
4844 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_OFST 4
4845 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG1_RX_LEN 1
4846 /* Transaction processing steering hint 2 for use with the Ev Queue. */
4847 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_OFST 5
4848 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_TAG2_EV_LEN 1
4849 /* Use Relaxed ordering model for TLPs on this VI. */
4850 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_LBN 48
4851 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_RELAXED_ORDERING_WIDTH 1
4852 /* Use ID based ordering for TLPs on this VI. */
4853 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_LBN 49
4854 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_ID_BASED_ORDERING_WIDTH 1
4855 /* Set the no snoop bit for TLPs on this VI. */
4856 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_LBN 50
4857 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_NO_SNOOP_WIDTH 1
4858 /* Enable TPH for TLPs on this VI. */
4859 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_LBN 51
4860 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_TPH_ON_WIDTH 1
4861 #define MC_CMD_SET_VI_TLP_PROCESSING_IN_DATA_OFST 4
4863 /* MC_CMD_SET_VI_TLP_PROCESSING_OUT msgresponse */
4864 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
4867 /***********************************/
4868 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS
4869 * Get global PCIe steering and transaction processing configuration.
4871 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS 0xbc
4873 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN msgrequest */
4874 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_LEN 4
4875 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
4877 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_MISC 0x0
4879 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_IDO 0x1
4881 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_RO 0x2
4882 /* enum: TPH Type. */
4883 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_TPH_TYPE 0x3
4885 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
4886 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_LEN 8
4887 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_GLOBAL_CATEGORY_OFST 0
4888 /* Enum values, see field(s): */
4889 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
4890 /* Amalgamated TLP info word. */
4891 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_WORD_OFST 4
4892 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_LBN 0
4893 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_WTAG_EN_WIDTH 1
4894 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_LBN 1
4895 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_MISC_SPARE_WIDTH 31
4896 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_LBN 0
4897 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_DL_EN_WIDTH 1
4898 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_LBN 1
4899 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_TX_EN_WIDTH 1
4900 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_LBN 2
4901 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_EV_EN_WIDTH 1
4902 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_LBN 3
4903 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_RX_EN_WIDTH 1
4904 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_LBN 4
4905 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_IDO_SPARE_WIDTH 28
4906 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_LBN 0
4907 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_RXDMA_EN_WIDTH 1
4908 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_LBN 1
4909 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_TXDMA_EN_WIDTH 1
4910 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_LBN 2
4911 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_DL_EN_WIDTH 1
4912 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_LBN 3
4913 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_RO_SPARE_WIDTH 29
4914 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_LBN 0
4915 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
4916 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_LBN 2
4917 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_DL_WIDTH 2
4918 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_LBN 4
4919 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_TX_WIDTH 2
4920 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_LBN 6
4921 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_EV_WIDTH 2
4922 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_LBN 8
4923 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TPH_TYPE_RX_WIDTH 2
4924 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_LBN 9
4925 #define MC_CMD_GET_TLP_PROCESSING_GLOBALS_OUT_TLP_INFO_TLP_TYPE_SPARE_WIDTH 23
4928 /***********************************/
4929 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS
4930 * Set global PCIe steering and transaction processing configuration.
4932 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS 0xbd
4934 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN msgrequest */
4935 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_LEN 8
4936 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_GLOBAL_CATEGORY_OFST 0
4937 /* Enum values, see field(s): */
4938 /* MC_CMD_GET_TLP_PROCESSING_GLOBALS/MC_CMD_GET_TLP_PROCESSING_GLOBALS_IN/TLP_GLOBAL_CATEGORY */
4939 /* Amalgamated TLP info word. */
4940 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_WORD_OFST 4
4941 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_LBN 0
4942 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_MISC_WTAG_EN_WIDTH 1
4943 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_LBN 0
4944 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_DL_EN_WIDTH 1
4945 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_LBN 1
4946 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_TX_EN_WIDTH 1
4947 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_LBN 2
4948 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_EV_EN_WIDTH 1
4949 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_LBN 3
4950 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_IDO_RX_EN_WIDTH 1
4951 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_LBN 0
4952 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_RXDMA_EN_WIDTH 1
4953 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_LBN 1
4954 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_TXDMA_EN_WIDTH 1
4955 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_LBN 2
4956 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_RO_DL_EN_WIDTH 1
4957 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_LBN 0
4958 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_MSIX_WIDTH 2
4959 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_LBN 2
4960 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_DL_WIDTH 2
4961 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_LBN 4
4962 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_TX_WIDTH 2
4963 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_LBN 6
4964 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_EV_WIDTH 2
4965 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_LBN 8
4966 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_TPH_TYPE_RX_WIDTH 2
4967 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_LBN 10
4968 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_IN_TLP_INFO_SPARE_WIDTH 22
4970 /* MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT msgresponse */
4971 #define MC_CMD_SET_TLP_PROCESSING_GLOBALS_OUT_LEN 0
4974 /***********************************/
4975 /* MC_CMD_SATELLITE_DOWNLOAD
4976 * Download a new set of images to the satellite CPUs from the host.
4978 #define MC_CMD_SATELLITE_DOWNLOAD 0x91
4980 /* MC_CMD_SATELLITE_DOWNLOAD_IN msgrequest: The reset requirements for the CPUs
4981 * are subtle, and so downloads must proceed in a number of phases.
4983 * 1) PHASE_RESET with a target of TARGET_ALL and chunk ID/length of 0.
4985 * 2) PHASE_IMEMS for each of the IMEM targets (target IDs 0-11). Each download
4986 * may consist of multiple chunks. The final chunk (with CHUNK_ID_LAST) should
4987 * be a checksum (a simple 32-bit sum) of the transferred data. An individual
4988 * download may be aborted using CHUNK_ID_ABORT.
4990 * 3) PHASE_VECTORS for each of the vector table targets (target IDs 12-15),
4991 * similar to PHASE_IMEMS.
4993 * 4) PHASE_READY with a target of TARGET_ALL and chunk ID/length of 0.
4995 * After any error (a requested abort is not considered to be an error) the
4996 * sequence must be restarted from PHASE_RESET.
4998 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMIN 20
4999 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LENMAX 252
5000 #define MC_CMD_SATELLITE_DOWNLOAD_IN_LEN(num) (16+4*(num))
5001 /* Download phase. (Note: the IDLE phase is used internally and is never valid
5002 * in a command from the host.)
5004 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_OFST 0
5005 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IDLE 0x0 /* enum */
5006 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_RESET 0x1 /* enum */
5007 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_IMEMS 0x2 /* enum */
5008 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_VECTORS 0x3 /* enum */
5009 #define MC_CMD_SATELLITE_DOWNLOAD_IN_PHASE_READY 0x4 /* enum */
5010 /* Target for download. (These match the blob numbers defined in
5011 * mc_flash_layout.h.)
5013 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_OFST 4
5014 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
5015 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_TEXT 0x0
5016 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
5017 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_TEXT 0x1
5018 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
5019 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDP_TEXT 0x2
5020 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
5021 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDP_TEXT 0x3
5022 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
5023 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT 0x4
5024 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
5025 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_LUT_CFG 0x5
5026 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
5027 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT 0x6
5028 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
5029 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_LUT_CFG 0x7
5030 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
5031 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_HR_PGM 0x8
5032 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
5033 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXHRSL_SL_PGM 0x9
5034 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
5035 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_HR_PGM 0xa
5036 /* enum: Valid in phase 2 (PHASE_IMEMS) only */
5037 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXHRSL_SL_PGM 0xb
5038 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
5039 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL0 0xc
5040 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
5041 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL0 0xd
5042 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
5043 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_RXDI_VTBL1 0xe
5044 /* enum: Valid in phase 3 (PHASE_VECTORS) only */
5045 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_TXDI_VTBL1 0xf
5046 /* enum: Valid in phases 1 (PHASE_RESET) and 4 (PHASE_READY) only */
5047 #define MC_CMD_SATELLITE_DOWNLOAD_IN_TARGET_ALL 0xffffffff
5048 /* Chunk ID, or CHUNK_ID_LAST or CHUNK_ID_ABORT */
5049 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_OFST 8
5050 /* enum: Last chunk, containing checksum rather than data */
5051 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_LAST 0xffffffff
5052 /* enum: Abort download of this item */
5053 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_ID_ABORT 0xfffffffe
5054 /* Length of this chunk in bytes */
5055 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_LEN_OFST 12
5056 /* Data for this chunk */
5057 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_OFST 16
5058 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_LEN 4
5059 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MINNUM 1
5060 #define MC_CMD_SATELLITE_DOWNLOAD_IN_CHUNK_DATA_MAXNUM 59
5062 /* MC_CMD_SATELLITE_DOWNLOAD_OUT msgresponse */
5063 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_LEN 8
5064 /* Same as MC_CMD_ERR field, but included as 0 in success cases */
5065 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_RESULT_OFST 0
5066 /* Extra status information */
5067 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_INFO_OFST 4
5068 /* enum: Code download OK, completed. */
5069 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_COMPLETE 0x0
5070 /* enum: Code download aborted as requested. */
5071 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_ABORTED 0x1
5072 /* enum: Code download OK so far, send next chunk. */
5073 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_OK_NEXT_CHUNK 0x2
5074 /* enum: Download phases out of sequence */
5075 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_PHASE 0x100
5076 /* enum: Bad target for this phase */
5077 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_TARGET 0x101
5078 /* enum: Chunk ID out of sequence */
5079 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_ID 0x200
5080 /* enum: Chunk length zero or too large */
5081 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHUNK_LEN 0x201
5082 /* enum: Checksum was incorrect */
5083 #define MC_CMD_SATELLITE_DOWNLOAD_OUT_ERR_BAD_CHECKSUM 0x300
5086 /***********************************/
5087 /* MC_CMD_GET_CAPABILITIES
5088 * Get device capabilities.
5090 * This is supplementary to the MC_CMD_GET_BOARD_CFG command, and intended to
5091 * reference inherent device capabilities as opposed to current NVRAM config.
5093 #define MC_CMD_GET_CAPABILITIES 0xbe
5095 /* MC_CMD_GET_CAPABILITIES_IN msgrequest */
5096 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0
5098 /* MC_CMD_GET_CAPABILITIES_OUT msgresponse */
5099 #define MC_CMD_GET_CAPABILITIES_OUT_LEN 20
5100 /* First word of flags. */
5101 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
5102 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_LBN 19
5103 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_WIDTH 1
5104 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_LBN 20
5105 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_WIDTH 1
5106 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_LBN 21
5107 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_WIDTH 1
5108 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_LBN 22
5109 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_WIDTH 1
5110 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_LBN 23
5111 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_WIDTH 1
5112 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_LBN 24
5113 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_WIDTH 1
5114 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_LBN 25
5115 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_WIDTH 1
5116 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_LBN 26
5117 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_WIDTH 1
5118 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_LBN 27
5119 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_WIDTH 1
5120 /* RxDPCPU firmware id. */
5121 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
5122 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_LEN 2
5123 /* enum: Standard RXDP firmware */
5124 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
5125 /* enum: Low latency RXDP firmware */
5126 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
5127 /* enum: RXDP Test firmware image 1 */
5128 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
5129 /* enum: RXDP Test firmware image 2 */
5130 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
5131 /* enum: RXDP Test firmware image 3 */
5132 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
5133 /* enum: RXDP Test firmware image 4 */
5134 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
5135 /* enum: RXDP Test firmware image 5 */
5136 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
5137 /* enum: RXDP Test firmware image 6 */
5138 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
5139 /* enum: RXDP Test firmware image 7 */
5140 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
5141 /* enum: RXDP Test firmware image 8 */
5142 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
5143 /* TxDPCPU firmware id. */
5144 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_OFST 6
5145 #define MC_CMD_GET_CAPABILITIES_OUT_TX_DPCPU_FW_ID_LEN 2
5146 /* enum: Standard TXDP firmware */
5147 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
5148 /* enum: Low latency TXDP firmware */
5149 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
5150 /* enum: TXDP Test firmware image 1 */
5151 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
5152 /* enum: TXDP Test firmware image 2 */
5153 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
5154 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_OFST 8
5155 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_LEN 2
5156 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
5157 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_WIDTH 12
5158 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_LBN 12
5159 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
5160 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1 /* enum */
5161 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2 /* enum */
5162 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3 /* enum */
5163 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 /* enum */
5164 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
5165 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_OFST 10
5166 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_LEN 2
5167 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
5168 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_WIDTH 12
5169 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_LBN 12
5170 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
5171 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1 /* enum */
5172 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2 /* enum */
5173 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3 /* enum */
5174 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4 /* enum */
5175 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
5176 /* Hardware capabilities of NIC */
5177 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_OFST 12
5178 /* Licensed capabilities */
5179 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_OFST 16
5182 /***********************************/
5184 * Encapsulation for a v2 extended command
5186 #define MC_CMD_V2_EXTN 0x7f
5188 /* MC_CMD_V2_EXTN_IN msgrequest */
5189 #define MC_CMD_V2_EXTN_IN_LEN 4
5190 /* the extended command number */
5191 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
5192 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_WIDTH 15
5193 #define MC_CMD_V2_EXTN_IN_UNUSED_LBN 15
5194 #define MC_CMD_V2_EXTN_IN_UNUSED_WIDTH 1
5195 /* the actual length of the encapsulated command (which is not in the v1
5198 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_LBN 16
5199 #define MC_CMD_V2_EXTN_IN_ACTUAL_LEN_WIDTH 10
5200 #define MC_CMD_V2_EXTN_IN_UNUSED2_LBN 26
5201 #define MC_CMD_V2_EXTN_IN_UNUSED2_WIDTH 6
5204 /***********************************/
5205 /* MC_CMD_TCM_BUCKET_ALLOC
5206 * Allocate a pacer bucket (for qau rp or a snapper test)
5208 #define MC_CMD_TCM_BUCKET_ALLOC 0xb2
5210 /* MC_CMD_TCM_BUCKET_ALLOC_IN msgrequest */
5211 #define MC_CMD_TCM_BUCKET_ALLOC_IN_LEN 0
5213 /* MC_CMD_TCM_BUCKET_ALLOC_OUT msgresponse */
5214 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_LEN 4
5216 #define MC_CMD_TCM_BUCKET_ALLOC_OUT_BUCKET_OFST 0
5219 /***********************************/
5220 /* MC_CMD_TCM_BUCKET_FREE
5221 * Free a pacer bucket
5223 #define MC_CMD_TCM_BUCKET_FREE 0xb3
5225 /* MC_CMD_TCM_BUCKET_FREE_IN msgrequest */
5226 #define MC_CMD_TCM_BUCKET_FREE_IN_LEN 4
5228 #define MC_CMD_TCM_BUCKET_FREE_IN_BUCKET_OFST 0
5230 /* MC_CMD_TCM_BUCKET_FREE_OUT msgresponse */
5231 #define MC_CMD_TCM_BUCKET_FREE_OUT_LEN 0
5234 /***********************************/
5235 /* MC_CMD_TCM_BUCKET_INIT
5236 * Initialise pacer bucket with a given rate
5238 #define MC_CMD_TCM_BUCKET_INIT 0xb4
5240 /* MC_CMD_TCM_BUCKET_INIT_IN msgrequest */
5241 #define MC_CMD_TCM_BUCKET_INIT_IN_LEN 8
5243 #define MC_CMD_TCM_BUCKET_INIT_IN_BUCKET_OFST 0
5244 /* the rate in mbps */
5245 #define MC_CMD_TCM_BUCKET_INIT_IN_RATE_OFST 4
5247 /* MC_CMD_TCM_BUCKET_INIT_OUT msgresponse */
5248 #define MC_CMD_TCM_BUCKET_INIT_OUT_LEN 0
5251 /***********************************/
5252 /* MC_CMD_TCM_TXQ_INIT
5253 * Initialise txq in pacer with given options or set options
5255 #define MC_CMD_TCM_TXQ_INIT 0xb5
5257 /* MC_CMD_TCM_TXQ_INIT_IN msgrequest */
5258 #define MC_CMD_TCM_TXQ_INIT_IN_LEN 28
5260 #define MC_CMD_TCM_TXQ_INIT_IN_QID_OFST 0
5261 /* the static priority associated with the txq */
5262 #define MC_CMD_TCM_TXQ_INIT_IN_LABEL_OFST 4
5263 /* bitmask of the priority queues this txq is inserted into */
5264 #define MC_CMD_TCM_TXQ_INIT_IN_PQ_FLAGS_OFST 8
5265 /* the reaction point (RP) bucket */
5266 #define MC_CMD_TCM_TXQ_INIT_IN_RP_BKT_OFST 12
5267 /* an already reserved bucket (typically set to bucket associated with outer
5270 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT1_OFST 16
5271 /* an already reserved bucket (typically set to bucket associated with inner
5274 #define MC_CMD_TCM_TXQ_INIT_IN_MAX_BKT2_OFST 20
5275 /* the min bucket (typically for ETS/minimum bandwidth) */
5276 #define MC_CMD_TCM_TXQ_INIT_IN_MIN_BKT_OFST 24
5278 /* MC_CMD_TCM_TXQ_INIT_OUT msgresponse */
5279 #define MC_CMD_TCM_TXQ_INIT_OUT_LEN 0
5282 /***********************************/
5283 /* MC_CMD_LINK_PIOBUF
5284 * Link a push I/O buffer to a TxQ
5286 #define MC_CMD_LINK_PIOBUF 0x92
5288 /* MC_CMD_LINK_PIOBUF_IN msgrequest */
5289 #define MC_CMD_LINK_PIOBUF_IN_LEN 8
5290 /* Handle for allocated push I/O buffer. */
5291 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
5292 /* Function Local Instance (VI) number. */
5293 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
5295 /* MC_CMD_LINK_PIOBUF_OUT msgresponse */
5296 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0
5299 /***********************************/
5300 /* MC_CMD_UNLINK_PIOBUF
5301 * Unlink a push I/O buffer from a TxQ
5303 #define MC_CMD_UNLINK_PIOBUF 0x93
5305 /* MC_CMD_UNLINK_PIOBUF_IN msgrequest */
5306 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4
5307 /* Function Local Instance (VI) number. */
5308 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
5310 /* MC_CMD_UNLINK_PIOBUF_OUT msgresponse */
5311 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
5314 /***********************************/
5315 /* MC_CMD_VSWITCH_ALLOC
5316 * allocate and initialise a v-switch.
5318 #define MC_CMD_VSWITCH_ALLOC 0x94
5320 /* MC_CMD_VSWITCH_ALLOC_IN msgrequest */
5321 #define MC_CMD_VSWITCH_ALLOC_IN_LEN 16
5322 /* The port to connect to the v-switch's upstream port. */
5323 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
5324 /* The type of v-switch to create. */
5325 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
5327 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
5329 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
5331 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
5332 /* Flags controlling v-port creation */
5333 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_OFST 8
5334 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
5335 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
5336 /* The number of VLAN tags to support. */
5337 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
5339 /* MC_CMD_VSWITCH_ALLOC_OUT msgresponse */
5340 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
5343 /***********************************/
5344 /* MC_CMD_VSWITCH_FREE
5345 * de-allocate a v-switch.
5347 #define MC_CMD_VSWITCH_FREE 0x95
5349 /* MC_CMD_VSWITCH_FREE_IN msgrequest */
5350 #define MC_CMD_VSWITCH_FREE_IN_LEN 4
5351 /* The port to which the v-switch is connected. */
5352 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
5354 /* MC_CMD_VSWITCH_FREE_OUT msgresponse */
5355 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0
5358 /***********************************/
5359 /* MC_CMD_VPORT_ALLOC
5360 * allocate a v-port.
5362 #define MC_CMD_VPORT_ALLOC 0x96
5364 /* MC_CMD_VPORT_ALLOC_IN msgrequest */
5365 #define MC_CMD_VPORT_ALLOC_IN_LEN 20
5366 /* The port to which the v-switch is connected. */
5367 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
5368 /* The type of the new v-port. */
5369 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
5370 /* enum: VLAN (obsolete) */
5371 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
5372 /* enum: VEB (obsolete) */
5373 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
5374 /* enum: VEPA (obsolete) */
5375 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
5376 /* enum: A normal v-port receives packets which match a specified MAC and/or
5379 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
5380 /* enum: An expansion v-port packets traffic which don't match any other
5383 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
5384 /* enum: An test v-port receives packets which match any filters installed by
5385 * its downstream components.
5387 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
5388 /* Flags controlling v-port creation */
5389 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_OFST 8
5390 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
5391 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_WIDTH 1
5392 /* The number of VLAN tags to insert/remove. */
5393 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_OFST 12
5394 /* The actual VLAN tags to insert/remove */
5395 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_OFST 16
5396 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
5397 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_WIDTH 16
5398 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_LBN 16
5399 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_1_WIDTH 16
5401 /* MC_CMD_VPORT_ALLOC_OUT msgresponse */
5402 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4
5403 /* The handle of the new v-port */
5404 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
5407 /***********************************/
5408 /* MC_CMD_VPORT_FREE
5409 * de-allocate a v-port.
5411 #define MC_CMD_VPORT_FREE 0x97
5413 /* MC_CMD_VPORT_FREE_IN msgrequest */
5414 #define MC_CMD_VPORT_FREE_IN_LEN 4
5415 /* The handle of the v-port */
5416 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
5418 /* MC_CMD_VPORT_FREE_OUT msgresponse */
5419 #define MC_CMD_VPORT_FREE_OUT_LEN 0
5422 /***********************************/
5423 /* MC_CMD_VADAPTOR_ALLOC
5424 * allocate a v-adaptor.
5426 #define MC_CMD_VADAPTOR_ALLOC 0x98
5428 /* MC_CMD_VADAPTOR_ALLOC_IN msgrequest */
5429 #define MC_CMD_VADAPTOR_ALLOC_IN_LEN 16
5430 /* The port to connect to the v-adaptor's port. */
5431 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
5432 /* Flags controlling v-adaptor creation */
5433 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_OFST 8
5434 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
5435 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_WIDTH 1
5436 /* The number of VLAN tags to strip on receive */
5437 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_OFST 12
5439 /* MC_CMD_VADAPTOR_ALLOC_OUT msgresponse */
5440 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
5443 /***********************************/
5444 /* MC_CMD_VADAPTOR_FREE
5445 * de-allocate a v-adaptor.
5447 #define MC_CMD_VADAPTOR_FREE 0x99
5449 /* MC_CMD_VADAPTOR_FREE_IN msgrequest */
5450 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4
5451 /* The port to which the v-adaptor is connected. */
5452 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
5454 /* MC_CMD_VADAPTOR_FREE_OUT msgresponse */
5455 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0
5458 /***********************************/
5459 /* MC_CMD_EVB_PORT_ASSIGN
5460 * assign a port to a PCI function.
5462 #define MC_CMD_EVB_PORT_ASSIGN 0x9a
5464 /* MC_CMD_EVB_PORT_ASSIGN_IN msgrequest */
5465 #define MC_CMD_EVB_PORT_ASSIGN_IN_LEN 8
5466 /* The port to assign. */
5467 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
5468 /* The target function to modify. */
5469 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
5470 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
5471 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_WIDTH 16
5472 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_LBN 16
5473 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_WIDTH 16
5475 /* MC_CMD_EVB_PORT_ASSIGN_OUT msgresponse */
5476 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
5479 /***********************************/
5480 /* MC_CMD_RDWR_A64_REGIONS
5481 * Assign the 64 bit region addresses.
5483 #define MC_CMD_RDWR_A64_REGIONS 0x9b
5485 /* MC_CMD_RDWR_A64_REGIONS_IN msgrequest */
5486 #define MC_CMD_RDWR_A64_REGIONS_IN_LEN 17
5487 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION0_OFST 0
5488 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION1_OFST 4
5489 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION2_OFST 8
5490 #define MC_CMD_RDWR_A64_REGIONS_IN_REGION3_OFST 12
5491 /* Write enable bits 0-3, set to write, clear to read. */
5492 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_LBN 128
5493 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_WIDTH 4
5494 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_OFST 16
5495 #define MC_CMD_RDWR_A64_REGIONS_IN_WRITE_MASK_BYTE_LEN 1
5497 /* MC_CMD_RDWR_A64_REGIONS_OUT msgresponse: This data always included
5498 * regardless of state of write bits in the request.
5500 #define MC_CMD_RDWR_A64_REGIONS_OUT_LEN 16
5501 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION0_OFST 0
5502 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION1_OFST 4
5503 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION2_OFST 8
5504 #define MC_CMD_RDWR_A64_REGIONS_OUT_REGION3_OFST 12
5507 /***********************************/
5508 /* MC_CMD_ONLOAD_STACK_ALLOC
5509 * Allocate an Onload stack ID.
5511 #define MC_CMD_ONLOAD_STACK_ALLOC 0x9c
5513 /* MC_CMD_ONLOAD_STACK_ALLOC_IN msgrequest */
5514 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_LEN 4
5515 /* The handle of the owning upstream port */
5516 #define MC_CMD_ONLOAD_STACK_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
5518 /* MC_CMD_ONLOAD_STACK_ALLOC_OUT msgresponse */
5519 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_LEN 4
5520 /* The handle of the new Onload stack */
5521 #define MC_CMD_ONLOAD_STACK_ALLOC_OUT_ONLOAD_STACK_ID_OFST 0
5524 /***********************************/
5525 /* MC_CMD_ONLOAD_STACK_FREE
5526 * Free an Onload stack ID.
5528 #define MC_CMD_ONLOAD_STACK_FREE 0x9d
5530 /* MC_CMD_ONLOAD_STACK_FREE_IN msgrequest */
5531 #define MC_CMD_ONLOAD_STACK_FREE_IN_LEN 4
5532 /* The handle of the Onload stack */
5533 #define MC_CMD_ONLOAD_STACK_FREE_IN_ONLOAD_STACK_ID_OFST 0
5535 /* MC_CMD_ONLOAD_STACK_FREE_OUT msgresponse */
5536 #define MC_CMD_ONLOAD_STACK_FREE_OUT_LEN 0
5539 /***********************************/
5540 /* MC_CMD_RSS_CONTEXT_ALLOC
5541 * Allocate an RSS context.
5543 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
5545 /* MC_CMD_RSS_CONTEXT_ALLOC_IN msgrequest */
5546 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_LEN 12
5547 /* The handle of the owning upstream port */
5548 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
5549 /* The type of context to allocate */
5550 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
5551 /* enum: Allocate a context for exclusive use. The key and indirection table
5552 * must be explicitly configured.
5554 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
5555 /* enum: Allocate a context for shared use; this will spread across a range of
5556 * queues, but the key and indirection table are pre-configured and may not be
5557 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
5559 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
5560 /* Number of queues spanned by this context, in the range 1-64; valid offsets
5561 * in the indirection table will be in the range 0 to NUM_QUEUES-1.
5563 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_OFST 8
5565 /* MC_CMD_RSS_CONTEXT_ALLOC_OUT msgresponse */
5566 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
5567 /* The handle of the new RSS context */
5568 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
5571 /***********************************/
5572 /* MC_CMD_RSS_CONTEXT_FREE
5573 * Free an RSS context.
5575 #define MC_CMD_RSS_CONTEXT_FREE 0x9f
5577 /* MC_CMD_RSS_CONTEXT_FREE_IN msgrequest */
5578 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
5579 /* The handle of the RSS context */
5580 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
5582 /* MC_CMD_RSS_CONTEXT_FREE_OUT msgresponse */
5583 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
5586 /***********************************/
5587 /* MC_CMD_RSS_CONTEXT_SET_KEY
5588 * Set the Toeplitz hash key for an RSS context.
5590 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
5592 /* MC_CMD_RSS_CONTEXT_SET_KEY_IN msgrequest */
5593 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_LEN 44
5594 /* The handle of the RSS context */
5595 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
5596 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
5597 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
5598 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_LEN 40
5600 /* MC_CMD_RSS_CONTEXT_SET_KEY_OUT msgresponse */
5601 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
5604 /***********************************/
5605 /* MC_CMD_RSS_CONTEXT_GET_KEY
5606 * Get the Toeplitz hash key for an RSS context.
5608 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
5610 /* MC_CMD_RSS_CONTEXT_GET_KEY_IN msgrequest */
5611 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
5612 /* The handle of the RSS context */
5613 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
5615 /* MC_CMD_RSS_CONTEXT_GET_KEY_OUT msgresponse */
5616 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_LEN 44
5617 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
5618 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
5619 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_LEN 40
5622 /***********************************/
5623 /* MC_CMD_RSS_CONTEXT_SET_TABLE
5624 * Set the indirection table for an RSS context.
5626 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
5628 /* MC_CMD_RSS_CONTEXT_SET_TABLE_IN msgrequest */
5629 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_LEN 132
5630 /* The handle of the RSS context */
5631 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
5632 /* The 128-byte indirection table (1 byte per entry) */
5633 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
5634 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_LEN 128
5636 /* MC_CMD_RSS_CONTEXT_SET_TABLE_OUT msgresponse */
5637 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
5640 /***********************************/
5641 /* MC_CMD_RSS_CONTEXT_GET_TABLE
5642 * Get the indirection table for an RSS context.
5644 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
5646 /* MC_CMD_RSS_CONTEXT_GET_TABLE_IN msgrequest */
5647 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
5648 /* The handle of the RSS context */
5649 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
5651 /* MC_CMD_RSS_CONTEXT_GET_TABLE_OUT msgresponse */
5652 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_LEN 132
5653 /* The 128-byte indirection table (1 byte per entry) */
5654 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
5655 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_LEN 128
5658 /***********************************/
5659 /* MC_CMD_RSS_CONTEXT_SET_FLAGS
5660 * Set various control flags for an RSS context.
5662 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
5664 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_IN msgrequest */
5665 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_LEN 8
5666 /* The handle of the RSS context */
5667 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
5668 /* Hash control flags */
5669 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
5670 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
5671 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_WIDTH 1
5672 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_LBN 1
5673 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_WIDTH 1
5674 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_LBN 2
5675 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_WIDTH 1
5676 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_LBN 3
5677 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_WIDTH 1
5679 /* MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT msgresponse */
5680 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
5683 /***********************************/
5684 /* MC_CMD_RSS_CONTEXT_GET_FLAGS
5685 * Get various control flags for an RSS context.
5687 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
5689 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_IN msgrequest */
5690 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
5691 /* The handle of the RSS context */
5692 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
5694 /* MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT msgresponse */
5695 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_LEN 8
5696 /* Hash control flags */
5697 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
5698 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
5699 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_WIDTH 1
5700 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_LBN 1
5701 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_WIDTH 1
5702 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_LBN 2
5703 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_WIDTH 1
5704 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_LBN 3
5705 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_WIDTH 1
5708 /***********************************/
5709 /* MC_CMD_DOT1P_MAPPING_ALLOC
5710 * Allocate a .1p mapping.
5712 #define MC_CMD_DOT1P_MAPPING_ALLOC 0xa4
5714 /* MC_CMD_DOT1P_MAPPING_ALLOC_IN msgrequest */
5715 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_LEN 8
5716 /* The handle of the owning upstream port */
5717 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
5718 /* Number of queues spanned by this mapping, in the range 1-64; valid fixed
5719 * offsets in the mapping table will be in the range 0 to NUM_QUEUES-1, and
5720 * referenced RSS contexts must span no more than this number.
5722 #define MC_CMD_DOT1P_MAPPING_ALLOC_IN_NUM_QUEUES_OFST 4
5724 /* MC_CMD_DOT1P_MAPPING_ALLOC_OUT msgresponse */
5725 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_LEN 4
5726 /* The handle of the new .1p mapping */
5727 #define MC_CMD_DOT1P_MAPPING_ALLOC_OUT_DOT1P_MAPPING_ID_OFST 0
5730 /***********************************/
5731 /* MC_CMD_DOT1P_MAPPING_FREE
5732 * Free a .1p mapping.
5734 #define MC_CMD_DOT1P_MAPPING_FREE 0xa5
5736 /* MC_CMD_DOT1P_MAPPING_FREE_IN msgrequest */
5737 #define MC_CMD_DOT1P_MAPPING_FREE_IN_LEN 4
5738 /* The handle of the .1p mapping */
5739 #define MC_CMD_DOT1P_MAPPING_FREE_IN_DOT1P_MAPPING_ID_OFST 0
5741 /* MC_CMD_DOT1P_MAPPING_FREE_OUT msgresponse */
5742 #define MC_CMD_DOT1P_MAPPING_FREE_OUT_LEN 0
5745 /***********************************/
5746 /* MC_CMD_DOT1P_MAPPING_SET_TABLE
5747 * Set the mapping table for a .1p mapping.
5749 #define MC_CMD_DOT1P_MAPPING_SET_TABLE 0xa6
5751 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_IN msgrequest */
5752 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_LEN 36
5753 /* The handle of the .1p mapping */
5754 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
5755 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
5758 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_OFST 4
5759 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_IN_MAPPING_TABLE_LEN 32
5761 /* MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT msgresponse */
5762 #define MC_CMD_DOT1P_MAPPING_SET_TABLE_OUT_LEN 0
5765 /***********************************/
5766 /* MC_CMD_DOT1P_MAPPING_GET_TABLE
5767 * Get the mapping table for a .1p mapping.
5769 #define MC_CMD_DOT1P_MAPPING_GET_TABLE 0xa7
5771 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_IN msgrequest */
5772 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_LEN 4
5773 /* The handle of the .1p mapping */
5774 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_IN_DOT1P_MAPPING_ID_OFST 0
5776 /* MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT msgresponse */
5777 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_LEN 36
5778 /* Per-priority mappings (1 32-bit word per entry - an offset or RSS context
5781 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_OFST 4
5782 #define MC_CMD_DOT1P_MAPPING_GET_TABLE_OUT_MAPPING_TABLE_LEN 32
5785 /***********************************/
5786 /* MC_CMD_GET_VECTOR_CFG
5787 * Get Interrupt Vector config for this PF.
5789 #define MC_CMD_GET_VECTOR_CFG 0xbf
5791 /* MC_CMD_GET_VECTOR_CFG_IN msgrequest */
5792 #define MC_CMD_GET_VECTOR_CFG_IN_LEN 0
5794 /* MC_CMD_GET_VECTOR_CFG_OUT msgresponse */
5795 #define MC_CMD_GET_VECTOR_CFG_OUT_LEN 12
5796 /* Base absolute interrupt vector number. */
5797 #define MC_CMD_GET_VECTOR_CFG_OUT_VEC_BASE_OFST 0
5798 /* Number of interrupt vectors allocate to this PF. */
5799 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_PF_OFST 4
5800 /* Number of interrupt vectors to allocate per VF. */
5801 #define MC_CMD_GET_VECTOR_CFG_OUT_VECS_PER_VF_OFST 8
5804 /***********************************/
5805 /* MC_CMD_SET_VECTOR_CFG
5806 * Set Interrupt Vector config for this PF.
5808 #define MC_CMD_SET_VECTOR_CFG 0xc0
5810 /* MC_CMD_SET_VECTOR_CFG_IN msgrequest */
5811 #define MC_CMD_SET_VECTOR_CFG_IN_LEN 12
5812 /* Base absolute interrupt vector number, or MC_CMD_RESOURCE_INSTANCE_ANY to
5813 * let the system find a suitable base.
5815 #define MC_CMD_SET_VECTOR_CFG_IN_VEC_BASE_OFST 0
5816 /* Number of interrupt vectors allocate to this PF. */
5817 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_PF_OFST 4
5818 /* Number of interrupt vectors to allocate per VF. */
5819 #define MC_CMD_SET_VECTOR_CFG_IN_VECS_PER_VF_OFST 8
5821 /* MC_CMD_SET_VECTOR_CFG_OUT msgresponse */
5822 #define MC_CMD_SET_VECTOR_CFG_OUT_LEN 0
5825 /***********************************/
5826 /* MC_CMD_RMON_RX_CLASS_STATS
5827 * Retrieve rmon rx class statistics
5829 #define MC_CMD_RMON_RX_CLASS_STATS 0xc3
5831 /* MC_CMD_RMON_RX_CLASS_STATS_IN msgrequest */
5832 #define MC_CMD_RMON_RX_CLASS_STATS_IN_LEN 4
5834 #define MC_CMD_RMON_RX_CLASS_STATS_IN_FLAGS_OFST 0
5835 #define MC_CMD_RMON_RX_CLASS_STATS_IN_CLASS_LBN 0
5836 #define MC_CMD_RMON_RX_CLASS_STATS_IN_CLASS_WIDTH 8
5837 #define MC_CMD_RMON_RX_CLASS_STATS_IN_RST_LBN 8
5838 #define MC_CMD_RMON_RX_CLASS_STATS_IN_RST_WIDTH 1
5840 /* MC_CMD_RMON_RX_CLASS_STATS_OUT msgresponse */
5841 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_LENMIN 4
5842 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_LENMAX 252
5843 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_LEN(num) (0+4*(num))
5844 /* Array of stats */
5845 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_OFST 0
5846 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_LEN 4
5847 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_MINNUM 1
5848 #define MC_CMD_RMON_RX_CLASS_STATS_OUT_BUFFER_MAXNUM 63
5851 /***********************************/
5852 /* MC_CMD_RMON_TX_CLASS_STATS
5853 * Retrieve rmon tx class statistics
5855 #define MC_CMD_RMON_TX_CLASS_STATS 0xc4
5857 /* MC_CMD_RMON_TX_CLASS_STATS_IN msgrequest */
5858 #define MC_CMD_RMON_TX_CLASS_STATS_IN_LEN 4
5860 #define MC_CMD_RMON_TX_CLASS_STATS_IN_FLAGS_OFST 0
5861 #define MC_CMD_RMON_TX_CLASS_STATS_IN_CLASS_LBN 0
5862 #define MC_CMD_RMON_TX_CLASS_STATS_IN_CLASS_WIDTH 8
5863 #define MC_CMD_RMON_TX_CLASS_STATS_IN_RST_LBN 8
5864 #define MC_CMD_RMON_TX_CLASS_STATS_IN_RST_WIDTH 1
5866 /* MC_CMD_RMON_TX_CLASS_STATS_OUT msgresponse */
5867 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_LENMIN 4
5868 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_LENMAX 252
5869 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_LEN(num) (0+4*(num))
5870 /* Array of stats */
5871 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_OFST 0
5872 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_LEN 4
5873 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_MINNUM 1
5874 #define MC_CMD_RMON_TX_CLASS_STATS_OUT_BUFFER_MAXNUM 63
5877 /***********************************/
5878 /* MC_CMD_RMON_RX_SUPER_CLASS_STATS
5879 * Retrieve rmon rx super_class statistics
5881 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS 0xc5
5883 /* MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN msgrequest */
5884 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_LEN 4
5886 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_FLAGS_OFST 0
5887 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_SUPER_CLASS_LBN 0
5888 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_SUPER_CLASS_WIDTH 4
5889 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_RST_LBN 4
5890 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_IN_RST_WIDTH 1
5892 /* MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT msgresponse */
5893 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LENMIN 4
5894 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LENMAX 252
5895 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_LEN(num) (0+4*(num))
5896 /* Array of stats */
5897 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_OFST 0
5898 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_LEN 4
5899 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_MINNUM 1
5900 #define MC_CMD_RMON_RX_SUPER_CLASS_STATS_OUT_BUFFER_MAXNUM 63
5903 /***********************************/
5904 /* MC_CMD_RMON_TX_SUPER_CLASS_STATS
5905 * Retrieve rmon tx super_class statistics
5907 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS 0xc6
5909 /* MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN msgrequest */
5910 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_LEN 4
5912 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_FLAGS_OFST 0
5913 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_SUPER_CLASS_LBN 0
5914 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_SUPER_CLASS_WIDTH 4
5915 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_RST_LBN 4
5916 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_IN_RST_WIDTH 1
5918 /* MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT msgresponse */
5919 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LENMIN 4
5920 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LENMAX 252
5921 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_LEN(num) (0+4*(num))
5922 /* Array of stats */
5923 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_OFST 0
5924 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_LEN 4
5925 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_MINNUM 1
5926 #define MC_CMD_RMON_TX_SUPER_CLASS_STATS_OUT_BUFFER_MAXNUM 63
5929 /***********************************/
5930 /* MC_CMD_RMON_RX_ADD_QID_TO_CLASS
5931 * Add qid to class for statistics collection
5933 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS 0xc7
5935 /* MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN msgrequest */
5936 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_LEN 12
5938 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_CLASS_OFST 0
5940 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_QID_OFST 4
5942 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8
5943 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0
5944 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4
5945 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4
5946 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4
5947 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_MTU_LBN 8
5948 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14
5950 /* MC_CMD_RMON_RX_ADD_QID_TO_CLASS_OUT msgresponse */
5951 #define MC_CMD_RMON_RX_ADD_QID_TO_CLASS_OUT_LEN 0
5954 /***********************************/
5955 /* MC_CMD_RMON_TX_ADD_QID_TO_CLASS
5956 * Add qid to class for statistics collection
5958 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS 0xc8
5960 /* MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN msgrequest */
5961 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_LEN 12
5963 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_CLASS_OFST 0
5965 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_QID_OFST 4
5967 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8
5968 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0
5969 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4
5970 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4
5971 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4
5972 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_MTU_LBN 8
5973 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14
5975 /* MC_CMD_RMON_TX_ADD_QID_TO_CLASS_OUT msgresponse */
5976 #define MC_CMD_RMON_TX_ADD_QID_TO_CLASS_OUT_LEN 0
5979 /***********************************/
5980 /* MC_CMD_RMON_MC_ADD_QID_TO_CLASS
5981 * Add qid to class for statistics collection
5983 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS 0xc9
5985 /* MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN msgrequest */
5986 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_LEN 12
5988 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_CLASS_OFST 0
5990 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_QID_OFST 4
5992 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_FLAGS_OFST 8
5993 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_SUPER_CLASS_LBN 0
5994 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_SUPER_CLASS_WIDTH 4
5995 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_PE_DELTA_LBN 4
5996 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_PE_DELTA_WIDTH 4
5997 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_MTU_LBN 8
5998 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_IN_MTU_WIDTH 14
6000 /* MC_CMD_RMON_MC_ADD_QID_TO_CLASS_OUT msgresponse */
6001 #define MC_CMD_RMON_MC_ADD_QID_TO_CLASS_OUT_LEN 0
6004 /***********************************/
6005 /* MC_CMD_RMON_ALLOC_CLASS
6006 * Allocate an rmon class
6008 #define MC_CMD_RMON_ALLOC_CLASS 0xca
6010 /* MC_CMD_RMON_ALLOC_CLASS_IN msgrequest */
6011 #define MC_CMD_RMON_ALLOC_CLASS_IN_LEN 0
6013 /* MC_CMD_RMON_ALLOC_CLASS_OUT msgresponse */
6014 #define MC_CMD_RMON_ALLOC_CLASS_OUT_LEN 4
6016 #define MC_CMD_RMON_ALLOC_CLASS_OUT_CLASS_OFST 0
6019 /***********************************/
6020 /* MC_CMD_RMON_DEALLOC_CLASS
6021 * Deallocate an rmon class
6023 #define MC_CMD_RMON_DEALLOC_CLASS 0xcb
6025 /* MC_CMD_RMON_DEALLOC_CLASS_IN msgrequest */
6026 #define MC_CMD_RMON_DEALLOC_CLASS_IN_LEN 4
6028 #define MC_CMD_RMON_DEALLOC_CLASS_IN_CLASS_OFST 0
6030 /* MC_CMD_RMON_DEALLOC_CLASS_OUT msgresponse */
6031 #define MC_CMD_RMON_DEALLOC_CLASS_OUT_LEN 0
6034 /***********************************/
6035 /* MC_CMD_RMON_ALLOC_SUPER_CLASS
6036 * Allocate an rmon super_class
6038 #define MC_CMD_RMON_ALLOC_SUPER_CLASS 0xcc
6040 /* MC_CMD_RMON_ALLOC_SUPER_CLASS_IN msgrequest */
6041 #define MC_CMD_RMON_ALLOC_SUPER_CLASS_IN_LEN 0
6043 /* MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT msgresponse */
6044 #define MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT_LEN 4
6046 #define MC_CMD_RMON_ALLOC_SUPER_CLASS_OUT_SUPER_CLASS_OFST 0
6049 /***********************************/
6050 /* MC_CMD_RMON_DEALLOC_SUPER_CLASS
6051 * Deallocate an rmon tx super_class
6053 #define MC_CMD_RMON_DEALLOC_SUPER_CLASS 0xcd
6055 /* MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN msgrequest */
6056 #define MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN_LEN 4
6058 #define MC_CMD_RMON_DEALLOC_SUPER_CLASS_IN_SUPER_CLASS_OFST 0
6060 /* MC_CMD_RMON_DEALLOC_SUPER_CLASS_OUT msgresponse */
6061 #define MC_CMD_RMON_DEALLOC_SUPER_CLASS_OUT_LEN 0
6064 /***********************************/
6065 /* MC_CMD_RMON_RX_UP_CONV_STATS
6066 * Retrieve up converter statistics
6068 #define MC_CMD_RMON_RX_UP_CONV_STATS 0xce
6070 /* MC_CMD_RMON_RX_UP_CONV_STATS_IN msgrequest */
6071 #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_LEN 4
6073 #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_FLAGS_OFST 0
6074 #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_PORT_LBN 0
6075 #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_PORT_WIDTH 2
6076 #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_RST_LBN 2
6077 #define MC_CMD_RMON_RX_UP_CONV_STATS_IN_RST_WIDTH 1
6079 /* MC_CMD_RMON_RX_UP_CONV_STATS_OUT msgresponse */
6080 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LENMIN 4
6081 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LENMAX 252
6082 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_LEN(num) (0+4*(num))
6083 /* Array of stats */
6084 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_OFST 0
6085 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_LEN 4
6086 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_MINNUM 1
6087 #define MC_CMD_RMON_RX_UP_CONV_STATS_OUT_BUFFER_MAXNUM 63
6090 /***********************************/
6091 /* MC_CMD_RMON_RX_IPI_STATS
6092 * Retrieve rx ipi stats
6094 #define MC_CMD_RMON_RX_IPI_STATS 0xcf
6096 /* MC_CMD_RMON_RX_IPI_STATS_IN msgrequest */
6097 #define MC_CMD_RMON_RX_IPI_STATS_IN_LEN 4
6099 #define MC_CMD_RMON_RX_IPI_STATS_IN_FLAGS_OFST 0
6100 #define MC_CMD_RMON_RX_IPI_STATS_IN_VFIFO_LBN 0
6101 #define MC_CMD_RMON_RX_IPI_STATS_IN_VFIFO_WIDTH 5
6102 #define MC_CMD_RMON_RX_IPI_STATS_IN_RST_LBN 5
6103 #define MC_CMD_RMON_RX_IPI_STATS_IN_RST_WIDTH 1
6105 /* MC_CMD_RMON_RX_IPI_STATS_OUT msgresponse */
6106 #define MC_CMD_RMON_RX_IPI_STATS_OUT_LENMIN 4
6107 #define MC_CMD_RMON_RX_IPI_STATS_OUT_LENMAX 252
6108 #define MC_CMD_RMON_RX_IPI_STATS_OUT_LEN(num) (0+4*(num))
6109 /* Array of stats */
6110 #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_OFST 0
6111 #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_LEN 4
6112 #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_MINNUM 1
6113 #define MC_CMD_RMON_RX_IPI_STATS_OUT_BUFFER_MAXNUM 63
6116 /***********************************/
6117 /* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS
6118 * Retrieve rx ipsec cntxt_ptr indexed stats
6120 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS 0xd0
6122 /* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN msgrequest */
6123 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_LEN 4
6125 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_FLAGS_OFST 0
6126 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_LBN 0
6127 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_WIDTH 9
6128 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_RST_LBN 9
6129 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_IN_RST_WIDTH 1
6131 /* MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT msgresponse */
6132 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LENMIN 4
6133 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LENMAX 252
6134 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_LEN(num) (0+4*(num))
6135 /* Array of stats */
6136 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_OFST 0
6137 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_LEN 4
6138 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MINNUM 1
6139 #define MC_CMD_RMON_RX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MAXNUM 63
6142 /***********************************/
6143 /* MC_CMD_RMON_RX_IPSEC_PORT_STATS
6144 * Retrieve rx ipsec port indexed stats
6146 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS 0xd1
6148 /* MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN msgrequest */
6149 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_LEN 4
6151 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_FLAGS_OFST 0
6152 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_PORT_LBN 0
6153 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_PORT_WIDTH 2
6154 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_RST_LBN 2
6155 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_IN_RST_WIDTH 1
6157 /* MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT msgresponse */
6158 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LENMIN 4
6159 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LENMAX 252
6160 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_LEN(num) (0+4*(num))
6161 /* Array of stats */
6162 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_OFST 0
6163 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_LEN 4
6164 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_MINNUM 1
6165 #define MC_CMD_RMON_RX_IPSEC_PORT_STATS_OUT_BUFFER_MAXNUM 63
6168 /***********************************/
6169 /* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS
6170 * Retrieve tx ipsec overflow
6172 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS 0xd2
6174 /* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN msgrequest */
6175 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_LEN 4
6177 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_FLAGS_OFST 0
6178 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_PORT_LBN 0
6179 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_PORT_WIDTH 2
6180 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_RST_LBN 2
6181 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_IN_RST_WIDTH 1
6183 /* MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT msgresponse */
6184 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LENMIN 4
6185 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LENMAX 252
6186 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_LEN(num) (0+4*(num))
6187 /* Array of stats */
6188 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_OFST 0
6189 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_LEN 4
6190 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_MINNUM 1
6191 #define MC_CMD_RMON_RX_IPSEC_OFLOW_STATS_OUT_BUFFER_MAXNUM 63
6194 /***********************************/
6195 /* MC_CMD_VPORT_ADD_MAC_ADDRESS
6196 * Add a MAC address to a v-port
6198 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
6200 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_IN msgrequest */
6201 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_LEN 10
6202 /* The handle of the v-port */
6203 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
6204 /* MAC address to add */
6205 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
6206 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_LEN 6
6208 /* MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT msgresponse */
6209 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
6212 /***********************************/
6213 /* MC_CMD_VPORT_DEL_MAC_ADDRESS
6214 * Delete a MAC address from a v-port
6216 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
6218 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_IN msgrequest */
6219 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_LEN 10
6220 /* The handle of the v-port */
6221 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
6222 /* MAC address to add */
6223 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
6224 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_LEN 6
6226 /* MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT msgresponse */
6227 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
6230 /***********************************/
6231 /* MC_CMD_VPORT_GET_MAC_ADDRESSES
6232 * Delete a MAC address from a v-port
6234 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
6236 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_IN msgrequest */
6237 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
6238 /* The handle of the v-port */
6239 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
6241 /* MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT msgresponse */
6242 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
6243 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX 250
6244 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
6245 /* The number of MAC addresses returned */
6246 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
6247 /* Array of MAC addresses */
6248 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
6249 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_LEN 6
6250 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
6251 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MAXNUM 41
6254 /***********************************/
6255 /* MC_CMD_DUMP_BUFTBL_ENTRIES
6256 * Dump buffer table entries, mainly for command client debug use. Dumps
6257 * absolute entries, and does not use chunk handles. All entries must be in
6258 * range, and used for q page mapping, Although the latter restriction may be
6261 #define MC_CMD_DUMP_BUFTBL_ENTRIES 0xab
6263 /* MC_CMD_DUMP_BUFTBL_ENTRIES_IN msgrequest */
6264 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_LEN 8
6265 /* Index of the first buffer table entry. */
6266 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_FIRSTID_OFST 0
6267 /* Number of buffer table entries to dump. */
6268 #define MC_CMD_DUMP_BUFTBL_ENTRIES_IN_NUMENTRIES_OFST 4
6270 /* MC_CMD_DUMP_BUFTBL_ENTRIES_OUT msgresponse */
6271 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMIN 12
6272 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LENMAX 252
6273 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_LEN(num) (0+12*(num))
6274 /* Raw buffer table entries, layed out as BUFTBL_ENTRY. */
6275 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_OFST 0
6276 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_LEN 12
6277 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MINNUM 1
6278 #define MC_CMD_DUMP_BUFTBL_ENTRIES_OUT_ENTRY_MAXNUM 21
6281 /***********************************/
6282 /* MC_CMD_SET_RXDP_CONFIG
6283 * Set global RXDP configuration settings
6285 #define MC_CMD_SET_RXDP_CONFIG 0xc1
6287 /* MC_CMD_SET_RXDP_CONFIG_IN msgrequest */
6288 #define MC_CMD_SET_RXDP_CONFIG_IN_LEN 4
6289 #define MC_CMD_SET_RXDP_CONFIG_IN_DATA_OFST 0
6290 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_LBN 0
6291 #define MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_DMA_WIDTH 1
6293 /* MC_CMD_SET_RXDP_CONFIG_OUT msgresponse */
6294 #define MC_CMD_SET_RXDP_CONFIG_OUT_LEN 0
6297 /***********************************/
6298 /* MC_CMD_GET_RXDP_CONFIG
6299 * Get global RXDP configuration settings
6301 #define MC_CMD_GET_RXDP_CONFIG 0xc2
6303 /* MC_CMD_GET_RXDP_CONFIG_IN msgrequest */
6304 #define MC_CMD_GET_RXDP_CONFIG_IN_LEN 0
6306 /* MC_CMD_GET_RXDP_CONFIG_OUT msgresponse */
6307 #define MC_CMD_GET_RXDP_CONFIG_OUT_LEN 4
6308 #define MC_CMD_GET_RXDP_CONFIG_OUT_DATA_OFST 0
6309 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_LBN 0
6310 #define MC_CMD_GET_RXDP_CONFIG_OUT_PAD_HOST_DMA_WIDTH 1
6313 /***********************************/
6314 /* MC_CMD_RMON_RX_CLASS_DROPS_STATS
6315 * Retrieve rx class drop stats
6317 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS 0xd3
6319 /* MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN msgrequest */
6320 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_LEN 4
6322 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_FLAGS_OFST 0
6323 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_CLASS_LBN 0
6324 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_CLASS_WIDTH 8
6325 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_RST_LBN 8
6326 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_IN_RST_WIDTH 1
6328 /* MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT msgresponse */
6329 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LENMIN 4
6330 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LENMAX 252
6331 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_LEN(num) (0+4*(num))
6332 /* Array of stats */
6333 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_OFST 0
6334 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_LEN 4
6335 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_MINNUM 1
6336 #define MC_CMD_RMON_RX_CLASS_DROPS_STATS_OUT_BUFFER_MAXNUM 63
6339 /***********************************/
6340 /* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS
6341 * Retrieve rx super class drop stats
6343 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS 0xd4
6345 /* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN msgrequest */
6346 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_LEN 4
6348 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_FLAGS_OFST 0
6349 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_SUPER_CLASS_LBN 0
6350 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_SUPER_CLASS_WIDTH 4
6351 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_RST_LBN 4
6352 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_IN_RST_WIDTH 1
6354 /* MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT msgresponse */
6355 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LENMIN 4
6356 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LENMAX 252
6357 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_LEN(num) (0+4*(num))
6358 /* Array of stats */
6359 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_OFST 0
6360 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_LEN 4
6361 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_MINNUM 1
6362 #define MC_CMD_RMON_RX_SUPER_CLASS_DROPS_STATS_OUT_BUFFER_MAXNUM 63
6365 /***********************************/
6366 /* MC_CMD_RMON_RX_ERRORS_STATS
6367 * Retrieve rxdp errors
6369 #define MC_CMD_RMON_RX_ERRORS_STATS 0xd5
6371 /* MC_CMD_RMON_RX_ERRORS_STATS_IN msgrequest */
6372 #define MC_CMD_RMON_RX_ERRORS_STATS_IN_LEN 4
6374 #define MC_CMD_RMON_RX_ERRORS_STATS_IN_FLAGS_OFST 0
6375 #define MC_CMD_RMON_RX_ERRORS_STATS_IN_QID_LBN 0
6376 #define MC_CMD_RMON_RX_ERRORS_STATS_IN_QID_WIDTH 11
6377 #define MC_CMD_RMON_RX_ERRORS_STATS_IN_RST_LBN 11
6378 #define MC_CMD_RMON_RX_ERRORS_STATS_IN_RST_WIDTH 1
6380 /* MC_CMD_RMON_RX_ERRORS_STATS_OUT msgresponse */
6381 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LENMIN 4
6382 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LENMAX 252
6383 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_LEN(num) (0+4*(num))
6384 /* Array of stats */
6385 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_OFST 0
6386 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_LEN 4
6387 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_MINNUM 1
6388 #define MC_CMD_RMON_RX_ERRORS_STATS_OUT_BUFFER_MAXNUM 63
6391 /***********************************/
6392 /* MC_CMD_RMON_RX_OVERFLOW_STATS
6393 * Retrieve rxdp overflow
6395 #define MC_CMD_RMON_RX_OVERFLOW_STATS 0xd6
6397 /* MC_CMD_RMON_RX_OVERFLOW_STATS_IN msgrequest */
6398 #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_LEN 4
6400 #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_FLAGS_OFST 0
6401 #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_CLASS_LBN 0
6402 #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_CLASS_WIDTH 8
6403 #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_RST_LBN 8
6404 #define MC_CMD_RMON_RX_OVERFLOW_STATS_IN_RST_WIDTH 1
6406 /* MC_CMD_RMON_RX_OVERFLOW_STATS_OUT msgresponse */
6407 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LENMIN 4
6408 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LENMAX 252
6409 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_LEN(num) (0+4*(num))
6410 /* Array of stats */
6411 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_OFST 0
6412 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_LEN 4
6413 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_MINNUM 1
6414 #define MC_CMD_RMON_RX_OVERFLOW_STATS_OUT_BUFFER_MAXNUM 63
6417 /***********************************/
6418 /* MC_CMD_RMON_TX_IPI_STATS
6419 * Retrieve tx ipi stats
6421 #define MC_CMD_RMON_TX_IPI_STATS 0xd7
6423 /* MC_CMD_RMON_TX_IPI_STATS_IN msgrequest */
6424 #define MC_CMD_RMON_TX_IPI_STATS_IN_LEN 4
6426 #define MC_CMD_RMON_TX_IPI_STATS_IN_FLAGS_OFST 0
6427 #define MC_CMD_RMON_TX_IPI_STATS_IN_VFIFO_LBN 0
6428 #define MC_CMD_RMON_TX_IPI_STATS_IN_VFIFO_WIDTH 5
6429 #define MC_CMD_RMON_TX_IPI_STATS_IN_RST_LBN 5
6430 #define MC_CMD_RMON_TX_IPI_STATS_IN_RST_WIDTH 1
6432 /* MC_CMD_RMON_TX_IPI_STATS_OUT msgresponse */
6433 #define MC_CMD_RMON_TX_IPI_STATS_OUT_LENMIN 4
6434 #define MC_CMD_RMON_TX_IPI_STATS_OUT_LENMAX 252
6435 #define MC_CMD_RMON_TX_IPI_STATS_OUT_LEN(num) (0+4*(num))
6436 /* Array of stats */
6437 #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_OFST 0
6438 #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_LEN 4
6439 #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_MINNUM 1
6440 #define MC_CMD_RMON_TX_IPI_STATS_OUT_BUFFER_MAXNUM 63
6443 /***********************************/
6444 /* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS
6445 * Retrieve tx ipsec counters by cntxt_ptr
6447 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS 0xd8
6449 /* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN msgrequest */
6450 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_LEN 4
6452 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_FLAGS_OFST 0
6453 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_LBN 0
6454 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_CNTXT_PTR_WIDTH 9
6455 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_RST_LBN 9
6456 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_IN_RST_WIDTH 1
6458 /* MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT msgresponse */
6459 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LENMIN 4
6460 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LENMAX 252
6461 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_LEN(num) (0+4*(num))
6462 /* Array of stats */
6463 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_OFST 0
6464 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_LEN 4
6465 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MINNUM 1
6466 #define MC_CMD_RMON_TX_IPSEC_CNTXT_PTR_STATS_OUT_BUFFER_MAXNUM 63
6469 /***********************************/
6470 /* MC_CMD_RMON_TX_IPSEC_PORT_STATS
6471 * Retrieve tx ipsec counters by port
6473 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS 0xd9
6475 /* MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN msgrequest */
6476 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_LEN 4
6478 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_FLAGS_OFST 0
6479 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_PORT_LBN 0
6480 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_PORT_WIDTH 2
6481 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_RST_LBN 2
6482 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_IN_RST_WIDTH 1
6484 /* MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT msgresponse */
6485 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LENMIN 4
6486 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LENMAX 252
6487 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_LEN(num) (0+4*(num))
6488 /* Array of stats */
6489 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_OFST 0
6490 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_LEN 4
6491 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_MINNUM 1
6492 #define MC_CMD_RMON_TX_IPSEC_PORT_STATS_OUT_BUFFER_MAXNUM 63
6495 /***********************************/
6496 /* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS
6497 * Retrieve tx ipsec overflow
6499 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS 0xda
6501 /* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN msgrequest */
6502 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_LEN 4
6504 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_FLAGS_OFST 0
6505 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_PORT_LBN 0
6506 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_PORT_WIDTH 2
6507 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_RST_LBN 2
6508 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_IN_RST_WIDTH 1
6510 /* MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT msgresponse */
6511 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LENMIN 4
6512 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LENMAX 252
6513 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_LEN(num) (0+4*(num))
6514 /* Array of stats */
6515 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_OFST 0
6516 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_LEN 4
6517 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_MINNUM 1
6518 #define MC_CMD_RMON_TX_IPSEC_OFLOW_STATS_OUT_BUFFER_MAXNUM 63
6521 /***********************************/
6522 /* MC_CMD_RMON_TX_NOWHERE_STATS
6523 * Retrieve tx nowhere stats
6525 #define MC_CMD_RMON_TX_NOWHERE_STATS 0xdb
6527 /* MC_CMD_RMON_TX_NOWHERE_STATS_IN msgrequest */
6528 #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_LEN 4
6530 #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_FLAGS_OFST 0
6531 #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_CLASS_LBN 0
6532 #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_CLASS_WIDTH 8
6533 #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_RST_LBN 8
6534 #define MC_CMD_RMON_TX_NOWHERE_STATS_IN_RST_WIDTH 1
6536 /* MC_CMD_RMON_TX_NOWHERE_STATS_OUT msgresponse */
6537 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LENMIN 4
6538 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LENMAX 252
6539 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_LEN(num) (0+4*(num))
6540 /* Array of stats */
6541 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_OFST 0
6542 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_LEN 4
6543 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_MINNUM 1
6544 #define MC_CMD_RMON_TX_NOWHERE_STATS_OUT_BUFFER_MAXNUM 63
6547 /***********************************/
6548 /* MC_CMD_RMON_TX_NOWHERE_QBB_STATS
6549 * Retrieve tx nowhere qbb stats
6551 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS 0xdc
6553 /* MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN msgrequest */
6554 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_LEN 4
6556 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_FLAGS_OFST 0
6557 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_PRIORITY_LBN 0
6558 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_PRIORITY_WIDTH 3
6559 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_RST_LBN 3
6560 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_IN_RST_WIDTH 1
6562 /* MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT msgresponse */
6563 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LENMIN 4
6564 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LENMAX 252
6565 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_LEN(num) (0+4*(num))
6566 /* Array of stats */
6567 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_OFST 0
6568 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_LEN 4
6569 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_MINNUM 1
6570 #define MC_CMD_RMON_TX_NOWHERE_QBB_STATS_OUT_BUFFER_MAXNUM 63
6573 /***********************************/
6574 /* MC_CMD_RMON_TX_ERRORS_STATS
6575 * Retrieve rxdp errors
6577 #define MC_CMD_RMON_TX_ERRORS_STATS 0xdd
6579 /* MC_CMD_RMON_TX_ERRORS_STATS_IN msgrequest */
6580 #define MC_CMD_RMON_TX_ERRORS_STATS_IN_LEN 4
6582 #define MC_CMD_RMON_TX_ERRORS_STATS_IN_FLAGS_OFST 0
6583 #define MC_CMD_RMON_TX_ERRORS_STATS_IN_QID_LBN 0
6584 #define MC_CMD_RMON_TX_ERRORS_STATS_IN_QID_WIDTH 11
6585 #define MC_CMD_RMON_TX_ERRORS_STATS_IN_RST_LBN 11
6586 #define MC_CMD_RMON_TX_ERRORS_STATS_IN_RST_WIDTH 1
6588 /* MC_CMD_RMON_TX_ERRORS_STATS_OUT msgresponse */
6589 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LENMIN 4
6590 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LENMAX 252
6591 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_LEN(num) (0+4*(num))
6592 /* Array of stats */
6593 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_OFST 0
6594 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_LEN 4
6595 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_MINNUM 1
6596 #define MC_CMD_RMON_TX_ERRORS_STATS_OUT_BUFFER_MAXNUM 63
6599 /***********************************/
6600 /* MC_CMD_RMON_TX_OVERFLOW_STATS
6601 * Retrieve rxdp overflow
6603 #define MC_CMD_RMON_TX_OVERFLOW_STATS 0xde
6605 /* MC_CMD_RMON_TX_OVERFLOW_STATS_IN msgrequest */
6606 #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_LEN 4
6608 #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_FLAGS_OFST 0
6609 #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_CLASS_LBN 0
6610 #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_CLASS_WIDTH 8
6611 #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_RST_LBN 8
6612 #define MC_CMD_RMON_TX_OVERFLOW_STATS_IN_RST_WIDTH 1
6614 /* MC_CMD_RMON_TX_OVERFLOW_STATS_OUT msgresponse */
6615 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LENMIN 4
6616 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LENMAX 252
6617 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_LEN(num) (0+4*(num))
6618 /* Array of stats */
6619 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_OFST 0
6620 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_LEN 4
6621 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_MINNUM 1
6622 #define MC_CMD_RMON_TX_OVERFLOW_STATS_OUT_BUFFER_MAXNUM 63
6625 /***********************************/
6626 /* MC_CMD_RMON_COLLECT_CLASS_STATS
6627 * Explicitly collect class stats at the specified evb port
6629 #define MC_CMD_RMON_COLLECT_CLASS_STATS 0xdf
6631 /* MC_CMD_RMON_COLLECT_CLASS_STATS_IN msgrequest */
6632 #define MC_CMD_RMON_COLLECT_CLASS_STATS_IN_LEN 4
6633 /* The port id associated with the vport/pport at which to collect class stats
6635 #define MC_CMD_RMON_COLLECT_CLASS_STATS_IN_PORT_ID_OFST 0
6637 /* MC_CMD_RMON_COLLECT_CLASS_STATS_OUT msgresponse */
6638 #define MC_CMD_RMON_COLLECT_CLASS_STATS_OUT_LEN 4
6640 #define MC_CMD_RMON_COLLECT_CLASS_STATS_OUT_CLASS_OFST 0
6643 /***********************************/
6644 /* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS
6645 * Explicitly collect class stats at the specified evb port
6647 #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS 0xe0
6649 /* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN msgrequest */
6650 #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN_LEN 4
6651 /* The port id associated with the vport/pport at which to collect class stats
6653 #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_IN_PORT_ID_OFST 0
6655 /* MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT msgresponse */
6656 #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT_LEN 4
6658 #define MC_CMD_RMON_COLLECT_SUPER_CLASS_STATS_OUT_SUPER_CLASS_OFST 0
6661 /***********************************/
6663 * Return the system and PDCPU clock frequencies.
6665 #define MC_CMD_GET_CLOCK 0xac
6667 /* MC_CMD_GET_CLOCK_IN msgrequest */
6668 #define MC_CMD_GET_CLOCK_IN_LEN 0
6670 /* MC_CMD_GET_CLOCK_OUT msgresponse */
6671 #define MC_CMD_GET_CLOCK_OUT_LEN 8
6672 /* System frequency, MHz */
6673 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
6674 /* DPCPU frequency, MHz */
6675 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
6678 /***********************************/
6680 * Control the system and DPCPU clock frequencies. Changes are lost reboot.
6682 #define MC_CMD_SET_CLOCK 0xad
6684 /* MC_CMD_SET_CLOCK_IN msgrequest */
6685 #define MC_CMD_SET_CLOCK_IN_LEN 12
6686 /* Requested system frequency in MHz; 0 leaves unchanged. */
6687 #define MC_CMD_SET_CLOCK_IN_SYS_FREQ_OFST 0
6688 /* Requested inter-core frequency in MHz; 0 leaves unchanged. */
6689 #define MC_CMD_SET_CLOCK_IN_ICORE_FREQ_OFST 4
6690 /* Request DPCPU frequency in MHz; 0 leaves unchanged. */
6691 #define MC_CMD_SET_CLOCK_IN_DPCPU_FREQ_OFST 8
6693 /* MC_CMD_SET_CLOCK_OUT msgresponse */
6694 #define MC_CMD_SET_CLOCK_OUT_LEN 12
6695 /* Resulting system frequency in MHz */
6696 #define MC_CMD_SET_CLOCK_OUT_SYS_FREQ_OFST 0
6697 /* Resulting inter-core frequency in MHz */
6698 #define MC_CMD_SET_CLOCK_OUT_ICORE_FREQ_OFST 4
6699 /* Resulting DPCPU frequency in MHz */
6700 #define MC_CMD_SET_CLOCK_OUT_DPCPU_FREQ_OFST 8
6703 /***********************************/
6705 * Send an arbitrary DPCPU message.
6707 #define MC_CMD_DPCPU_RPC 0xae
6709 /* MC_CMD_DPCPU_RPC_IN msgrequest */
6710 #define MC_CMD_DPCPU_RPC_IN_LEN 36
6711 #define MC_CMD_DPCPU_RPC_IN_CPU_OFST 0
6713 #define MC_CMD_DPCPU_RPC_IN_DPCPU_RX 0x0
6714 /* enum: TxDPCPU0 */
6715 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX0 0x1
6716 /* enum: TxDPCPU1 */
6717 #define MC_CMD_DPCPU_RPC_IN_DPCPU_TX1 0x2
6718 /* First 8 bits [39:32] of DATA are consumed by MC-DPCPU protocol and must be
6719 * initialised to zero
6721 #define MC_CMD_DPCPU_RPC_IN_DATA_OFST 4
6722 #define MC_CMD_DPCPU_RPC_IN_DATA_LEN 32
6723 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_LBN 8
6724 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_CMDNUM_WIDTH 8
6725 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_READ 0x6 /* enum */
6726 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_WRITE 0x7 /* enum */
6727 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_SELF_TEST 0xc /* enum */
6728 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_TXDPCPU_CSR_ACCESS 0xe /* enum */
6729 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_READ 0x46 /* enum */
6730 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_WRITE 0x47 /* enum */
6731 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SELF_TEST 0x4a /* enum */
6732 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_CSR_ACCESS 0x4c /* enum */
6733 #define MC_CMD_DPCPU_RPC_IN_CMDNUM_RXDPCPU_SET_MC_REPLAY_CNTXT 0x4d /* enum */
6734 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_LBN 16
6735 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_OBJID_WIDTH 16
6736 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_LBN 16
6737 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_ADDR_WIDTH 16
6738 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_LBN 48
6739 #define MC_CMD_DPCPU_RPC_IN_HDR_CMD_REQ_COUNT_WIDTH 16
6740 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_LBN 16
6741 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_INFO_WIDTH 240
6742 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_LBN 16
6743 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_WIDTH 16
6744 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_STOP_RETURN_RESULT 0x0 /* enum */
6745 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_READ 0x1 /* enum */
6746 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE 0x2 /* enum */
6747 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_WRITE_READ 0x3 /* enum */
6748 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_CMD_START_PIPELINED_READ 0x4 /* enum */
6749 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_LBN 48
6750 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_START_DELAY_WIDTH 16
6751 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_LBN 64
6752 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_RPT_COUNT_WIDTH 16
6753 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_LBN 80
6754 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_GAP_DELAY_WIDTH 16
6755 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_LBN 16
6756 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_WIDTH 16
6757 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_CUT_THROUGH 0x1 /* enum */
6758 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD 0x2 /* enum */
6759 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_MODE_STORE_FORWARD_FIRST 0x3 /* enum */
6760 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_LBN 64
6761 #define MC_CMD_DPCPU_RPC_IN_MC_REPLAY_CNTXT_WIDTH 16
6762 #define MC_CMD_DPCPU_RPC_IN_WDATA_OFST 12
6763 #define MC_CMD_DPCPU_RPC_IN_WDATA_LEN 24
6764 /* Register data to write. Only valid in write/write-read. */
6765 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_DATA_OFST 16
6766 /* Register address. */
6767 #define MC_CMD_DPCPU_RPC_IN_CSR_ACCESS_ADDRESS_OFST 20
6769 /* MC_CMD_DPCPU_RPC_OUT msgresponse */
6770 #define MC_CMD_DPCPU_RPC_OUT_LEN 36
6771 #define MC_CMD_DPCPU_RPC_OUT_RC_OFST 0
6773 #define MC_CMD_DPCPU_RPC_OUT_DATA_OFST 4
6774 #define MC_CMD_DPCPU_RPC_OUT_DATA_LEN 32
6775 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_LBN 32
6776 #define MC_CMD_DPCPU_RPC_OUT_HDR_CMD_RESP_ERRCODE_WIDTH 16
6777 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_LBN 48
6778 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_COUNT_WIDTH 16
6779 #define MC_CMD_DPCPU_RPC_OUT_RDATA_OFST 12
6780 #define MC_CMD_DPCPU_RPC_OUT_RDATA_LEN 24
6781 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_1_OFST 12
6782 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_2_OFST 16
6783 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_3_OFST 20
6784 #define MC_CMD_DPCPU_RPC_OUT_CSR_ACCESS_READ_VAL_4_OFST 24
6787 /***********************************/
6788 /* MC_CMD_TRIGGER_INTERRUPT
6789 * Trigger an interrupt by prodding the BIU.
6791 #define MC_CMD_TRIGGER_INTERRUPT 0xe3
6793 /* MC_CMD_TRIGGER_INTERRUPT_IN msgrequest */
6794 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
6795 /* Interrupt level relative to base for function. */
6796 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
6798 /* MC_CMD_TRIGGER_INTERRUPT_OUT msgresponse */
6799 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
6802 /***********************************/
6804 * Take a dump of the DUT state
6806 #define MC_CMD_DUMP_DO 0xe8
6808 /* MC_CMD_DUMP_DO_IN msgrequest */
6809 #define MC_CMD_DUMP_DO_IN_LEN 52
6810 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0
6811 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4
6812 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
6813 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
6814 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
6815 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
6816 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
6817 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
6818 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
6819 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
6820 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
6821 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
6822 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
6823 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
6824 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
6825 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
6826 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
6827 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
6828 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
6829 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
6830 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_OFST 28
6831 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
6832 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
6833 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
6834 /* Enum values, see field(s): */
6835 /* MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
6836 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
6837 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
6838 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
6839 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
6840 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
6841 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
6842 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
6843 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
6844 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
6846 /* MC_CMD_DUMP_DO_OUT msgresponse */
6847 #define MC_CMD_DUMP_DO_OUT_LEN 4
6848 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0
6851 /***********************************/
6852 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED
6853 * Configure unsolicited dumps
6855 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
6857 /* MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN msgrequest */
6858 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_LEN 52
6859 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0
6860 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4
6861 /* Enum values, see field(s): */
6862 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC */
6863 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_OFST 8
6864 /* Enum values, see field(s): */
6865 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
6866 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 12
6867 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_OFST 16
6868 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 12
6869 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 16
6870 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 12
6871 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 16
6872 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 20
6873 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_OFST 12
6874 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_OFST 24
6875 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_OFST 28
6876 /* Enum values, see field(s): */
6877 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPFILE_DST */
6878 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_OFST 32
6879 /* Enum values, see field(s): */
6880 /* MC_CMD_DUMP_DO/MC_CMD_DUMP_DO_IN/DUMPSPEC_SRC_CUSTOM_TYPE */
6881 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_OFST 36
6882 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_OFST 40
6883 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_OFST 36
6884 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_OFST 40
6885 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_OFST 36
6886 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_OFST 40
6887 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_OFST 44
6888 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_OFST 36
6889 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_OFST 48
6892 /***********************************/
6894 * Adjusts power supply parameters. This is a warranty-voiding operation.
6895 * Returns: ENOENT if the parameter or rail specified does not exist, EINVAL if
6896 * the parameter is out of range.
6898 #define MC_CMD_SET_PSU 0xea
6900 /* MC_CMD_SET_PSU_IN msgrequest */
6901 #define MC_CMD_SET_PSU_IN_LEN 12
6902 #define MC_CMD_SET_PSU_IN_PARAM_OFST 0
6903 #define MC_CMD_SET_PSU_IN_PARAM_SUPPLY_VOLTAGE 0x0 /* enum */
6904 #define MC_CMD_SET_PSU_IN_RAIL_OFST 4
6905 #define MC_CMD_SET_PSU_IN_RAIL_0V9 0x0 /* enum */
6906 #define MC_CMD_SET_PSU_IN_RAIL_1V2 0x1 /* enum */
6907 /* desired value, eg voltage in mV */
6908 #define MC_CMD_SET_PSU_IN_VALUE_OFST 8
6910 /* MC_CMD_SET_PSU_OUT msgresponse */
6911 #define MC_CMD_SET_PSU_OUT_LEN 0
6914 /***********************************/
6915 /* MC_CMD_GET_FUNCTION_INFO
6916 * Get function information. PF and VF number.
6918 #define MC_CMD_GET_FUNCTION_INFO 0xec
6920 /* MC_CMD_GET_FUNCTION_INFO_IN msgrequest */
6921 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
6923 /* MC_CMD_GET_FUNCTION_INFO_OUT msgresponse */
6924 #define MC_CMD_GET_FUNCTION_INFO_OUT_LEN 8
6925 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
6926 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
6929 /***********************************/
6930 /* MC_CMD_ENABLE_OFFLINE_BIST
6931 * Enters offline BIST mode. All queues are torn down, chip enters quiescent
6932 * mode, calling function gets exclusive MCDI ownership. The only way out is
6935 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed
6937 /* MC_CMD_ENABLE_OFFLINE_BIST_IN msgrequest */
6938 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
6940 /* MC_CMD_ENABLE_OFFLINE_BIST_OUT msgresponse */
6941 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
6944 /***********************************/
6945 /* MC_CMD_START_KR_EYE_PLOT
6946 * Start KR Serdes Eye diagram plot on a given lane. Lane must have valid
6949 #define MC_CMD_START_KR_EYE_PLOT 0xee
6951 /* MC_CMD_START_KR_EYE_PLOT_IN msgrequest */
6952 #define MC_CMD_START_KR_EYE_PLOT_IN_LEN 4
6953 #define MC_CMD_START_KR_EYE_PLOT_IN_LANE_OFST 0
6955 /* MC_CMD_START_KR_EYE_PLOT_OUT msgresponse */
6956 #define MC_CMD_START_KR_EYE_PLOT_OUT_LEN 0
6959 /***********************************/
6960 /* MC_CMD_POLL_KR_EYE_PLOT
6961 * Poll KR Serdes Eye diagram plot. Returns one row of BER data. The caller
6962 * should call this command repeatedly after starting eye plot, until no more
6965 #define MC_CMD_POLL_KR_EYE_PLOT 0xef
6967 /* MC_CMD_POLL_KR_EYE_PLOT_IN msgrequest */
6968 #define MC_CMD_POLL_KR_EYE_PLOT_IN_LEN 0
6970 /* MC_CMD_POLL_KR_EYE_PLOT_OUT msgresponse */
6971 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_LENMIN 0
6972 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_LENMAX 252
6973 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_LEN(num) (0+2*(num))
6974 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_SAMPLES_OFST 0
6975 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_SAMPLES_LEN 2
6976 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_SAMPLES_MINNUM 0
6977 #define MC_CMD_POLL_KR_EYE_PLOT_OUT_SAMPLES_MAXNUM 126
6980 /***********************************/
6981 /* MC_CMD_READ_FUSES
6982 * Read data programmed into the device One-Time-Programmable (OTP) Fuses
6984 #define MC_CMD_READ_FUSES 0xf0
6986 /* MC_CMD_READ_FUSES_IN msgrequest */
6987 #define MC_CMD_READ_FUSES_IN_LEN 8
6988 /* Offset in OTP to read */
6989 #define MC_CMD_READ_FUSES_IN_OFFSET_OFST 0
6990 /* Length of data to read in bytes */
6991 #define MC_CMD_READ_FUSES_IN_LENGTH_OFST 4
6993 /* MC_CMD_READ_FUSES_OUT msgresponse */
6994 #define MC_CMD_READ_FUSES_OUT_LENMIN 4
6995 #define MC_CMD_READ_FUSES_OUT_LENMAX 252
6996 #define MC_CMD_READ_FUSES_OUT_LEN(num) (4+1*(num))
6997 /* Length of returned OTP data in bytes */
6998 #define MC_CMD_READ_FUSES_OUT_LENGTH_OFST 0
7000 #define MC_CMD_READ_FUSES_OUT_DATA_OFST 4
7001 #define MC_CMD_READ_FUSES_OUT_DATA_LEN 1
7002 #define MC_CMD_READ_FUSES_OUT_DATA_MINNUM 0
7003 #define MC_CMD_READ_FUSES_OUT_DATA_MAXNUM 248
7006 /***********************************/
7008 * Get or set KR Serdes RXEQ and TX Driver settings
7010 #define MC_CMD_KR_TUNE 0xf1
7012 /* MC_CMD_KR_TUNE_IN msgrequest */
7013 #define MC_CMD_KR_TUNE_IN_LENMIN 4
7014 #define MC_CMD_KR_TUNE_IN_LENMAX 252
7015 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
7016 /* Requested operation */
7017 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
7018 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_LEN 1
7019 /* enum: Get current RXEQ settings */
7020 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
7021 /* enum: Override RXEQ settings */
7022 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
7023 /* enum: Get current TX Driver settings */
7024 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
7025 /* enum: Override TX Driver settings */
7026 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
7027 /* enum: Force KR Serdes reset / recalibration */
7028 #define MC_CMD_KR_TUNE_IN_RECAL 0x4
7029 /* Align the arguments to 32 bits */
7030 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_OFST 1
7031 #define MC_CMD_KR_TUNE_IN_KR_TUNE_RSVD_LEN 3
7032 /* Arguments specific to the operation */
7033 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4
7034 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4
7035 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0
7036 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MAXNUM 62
7038 /* MC_CMD_KR_TUNE_OUT msgresponse */
7039 #define MC_CMD_KR_TUNE_OUT_LEN 0
7041 /* MC_CMD_KR_TUNE_RXEQ_GET_IN msgrequest */
7042 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4
7043 /* Requested operation */
7044 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0
7045 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_LEN 1
7046 /* Align the arguments to 32 bits */
7047 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_OFST 1
7048 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_RSVD_LEN 3
7050 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT msgresponse */
7051 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4
7052 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMAX 252
7053 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
7054 /* RXEQ Parameter */
7055 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
7056 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
7057 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
7058 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
7059 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
7060 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
7061 /* enum: Attenuation (0-15) */
7062 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
7063 /* enum: CTLE Boost (0-15) */
7064 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
7065 /* enum: Edge DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
7066 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
7067 /* enum: Edge DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
7068 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
7069 /* enum: Edge DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
7070 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
7071 /* enum: Edge DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
7072 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
7073 /* enum: Edge DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
7074 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
7075 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
7076 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 3
7077 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
7078 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
7079 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
7080 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
7081 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
7082 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_LBN 11
7083 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_WIDTH 1
7084 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12
7085 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4
7086 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_LBN 16
7087 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_WIDTH 8
7088 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
7089 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
7091 /* MC_CMD_KR_TUNE_RXEQ_SET_IN msgrequest */
7092 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMIN 8
7093 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LENMAX 252
7094 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
7095 /* Requested operation */
7096 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
7097 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_LEN 1
7098 /* Align the arguments to 32 bits */
7099 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_OFST 1
7100 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_RSVD_LEN 3
7101 /* RXEQ Parameter */
7102 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4
7103 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4
7104 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MINNUM 1
7105 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_MAXNUM 62
7106 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
7107 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_WIDTH 8
7108 /* Enum values, see field(s): */
7109 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_ID */
7110 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_LBN 8
7111 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_WIDTH 3
7112 /* Enum values, see field(s): */
7113 /* MC_CMD_KR_TUNE_RXEQ_GET_OUT/PARAM_LANE */
7114 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_LBN 11
7115 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_WIDTH 1
7116 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_LBN 12
7117 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4
7118 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_LBN 16
7119 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_WIDTH 8
7120 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_LBN 24
7121 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_WIDTH 8
7123 /* MC_CMD_KR_TUNE_RXEQ_SET_OUT msgresponse */
7124 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0
7126 /* MC_CMD_KR_TUNE_RECAL_IN msgrequest */
7127 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4
7128 /* Requested operation */
7129 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0
7130 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_LEN 1
7131 /* Align the arguments to 32 bits */
7132 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_OFST 1
7133 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_RSVD_LEN 3
7135 /* MC_CMD_KR_TUNE_RECAL_OUT msgresponse */
7136 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0
7139 /***********************************/
7141 * Get or set PCIE Serdes RXEQ and TX Driver settings
7143 #define MC_CMD_PCIE_TUNE 0xf2
7145 /* MC_CMD_PCIE_TUNE_IN msgrequest */
7146 #define MC_CMD_PCIE_TUNE_IN_LENMIN 4
7147 #define MC_CMD_PCIE_TUNE_IN_LENMAX 252
7148 #define MC_CMD_PCIE_TUNE_IN_LEN(num) (4+4*(num))
7149 /* Requested operation */
7150 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_OFST 0
7151 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_OP_LEN 1
7152 /* enum: Get current RXEQ settings */
7153 #define MC_CMD_PCIE_TUNE_IN_RXEQ_GET 0x0
7154 /* enum: Override RXEQ settings */
7155 #define MC_CMD_PCIE_TUNE_IN_RXEQ_SET 0x1
7156 /* enum: Get current TX Driver settings */
7157 #define MC_CMD_PCIE_TUNE_IN_TXEQ_GET 0x2
7158 /* enum: Override TX Driver settings */
7159 #define MC_CMD_PCIE_TUNE_IN_TXEQ_SET 0x3
7160 /* Align the arguments to 32 bits */
7161 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_OFST 1
7162 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_RSVD_LEN 3
7163 /* Arguments specific to the operation */
7164 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_OFST 4
7165 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_LEN 4
7166 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MINNUM 0
7167 #define MC_CMD_PCIE_TUNE_IN_PCIE_TUNE_ARGS_MAXNUM 62
7169 /* MC_CMD_PCIE_TUNE_OUT msgresponse */
7170 #define MC_CMD_PCIE_TUNE_OUT_LEN 0
7172 /* MC_CMD_PCIE_TUNE_RXEQ_GET_IN msgrequest */
7173 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_LEN 4
7174 /* Requested operation */
7175 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
7176 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
7177 /* Align the arguments to 32 bits */
7178 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
7179 #define MC_CMD_PCIE_TUNE_RXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
7181 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT msgresponse */
7182 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMIN 4
7183 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LENMAX 252
7184 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
7185 /* RXEQ Parameter */
7186 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
7187 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
7188 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MINNUM 1
7189 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_MAXNUM 63
7190 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
7191 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_ID_WIDTH 8
7192 /* enum: Attenuation (0-15) */
7193 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_ATT 0x0
7194 /* enum: CTLE Boost (0-15) */
7195 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_BOOST 0x1
7196 /* enum: DFE Tap1 (0 - max negative, 64 - zero, 127 - max positive) */
7197 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP1 0x2
7198 /* enum: DFE Tap2 (0 - max negative, 32 - zero, 63 - max positive) */
7199 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x3
7200 /* enum: DFE Tap3 (0 - max negative, 32 - zero, 63 - max positive) */
7201 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x4
7202 /* enum: DFE Tap4 (0 - max negative, 32 - zero, 63 - max positive) */
7203 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x5
7204 /* enum: DFE Tap5 (0 - max negative, 32 - zero, 63 - max positive) */
7205 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x6
7206 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_LBN 8
7207 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_LANE_WIDTH 4
7208 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
7209 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
7210 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
7211 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
7212 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_4 0x4 /* enum */
7213 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_5 0x5 /* enum */
7214 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_6 0x6 /* enum */
7215 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_7 0x7 /* enum */
7216 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_LANE_ALL 0x8 /* enum */
7217 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_LBN 12
7218 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 12
7219 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_LBN 24
7220 #define MC_CMD_PCIE_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
7222 /* MC_CMD_PCIE_TUNE_TXEQ_GET_IN msgrequest */
7223 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_LEN 4
7224 /* Requested operation */
7225 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_OFST 0
7226 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_OP_LEN 1
7227 /* Align the arguments to 32 bits */
7228 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_OFST 1
7229 #define MC_CMD_PCIE_TUNE_TXEQ_GET_IN_PCIE_TUNE_RSVD_LEN 3
7231 /* MC_CMD_PCIE_TUNE_TXEQ_GET_OUT msgresponse */
7232 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMIN 4
7233 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LENMAX 252
7234 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
7235 /* RXEQ Parameter */
7236 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
7237 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
7238 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MINNUM 1
7239 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_MAXNUM 63
7240 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
7241 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_ID_WIDTH 8
7242 /* enum: TxMargin (PIPE) */
7243 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXMARGIN 0x0
7244 /* enum: TxSwing (PIPE) */
7245 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_TXSWING 0x1
7246 /* enum: De-emphasis coefficient C(-1) (PIPE) */
7247 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CM1 0x2
7248 /* enum: De-emphasis coefficient C(0) (PIPE) */
7249 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_C0 0x3
7250 /* enum: De-emphasis coefficient C(+1) (PIPE) */
7251 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_CP1 0x4
7252 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_LBN 8
7253 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_LANE_WIDTH 4
7254 /* Enum values, see field(s): */
7255 /* MC_CMD_PCIE_TUNE_RXEQ_GET_OUT/PARAM_LANE */
7256 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_LBN 12
7257 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_RESERVED_WIDTH 12
7258 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_LBN 24
7259 #define MC_CMD_PCIE_TUNE_TXEQ_GET_OUT_PARAM_CURRENT_WIDTH 8
7262 /***********************************/
7264 * Operations on the NVRAM_PARTITION_TYPE_LICENSE application license partition
7266 #define MC_CMD_LICENSING 0xf3
7268 /* MC_CMD_LICENSING_IN msgrequest */
7269 #define MC_CMD_LICENSING_IN_LEN 4
7270 /* identifies the type of operation requested */
7271 #define MC_CMD_LICENSING_IN_OP_OFST 0
7272 /* enum: re-read and apply licenses after a license key partition update; note
7273 * that this operation returns a zero-length response
7275 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
7276 /* enum: report counts of installed licenses */
7277 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
7279 /* MC_CMD_LICENSING_OUT msgresponse */
7280 #define MC_CMD_LICENSING_OUT_LEN 28
7281 /* count of application keys which are valid */
7282 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
7283 /* sum of UNVERIFIABLE_APP_KEYS + WRONG_NODE_APP_KEYS (for compatibility with
7284 * MC_CMD_FC_OP_LICENSE)
7286 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
7287 /* count of application keys which are invalid due to being blacklisted */
7288 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_OFST 8
7289 /* count of application keys which are invalid due to being unverifiable */
7290 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_OFST 12
7291 /* count of application keys which are invalid due to being for the wrong node
7293 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_OFST 16
7294 /* licensing state (for diagnostics; the exact meaning of the bits in this
7295 * field are private to the firmware)
7297 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_OFST 20
7298 /* licensing subsystem self-test report (for manftest) */
7299 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_OFST 24
7300 /* enum: licensing subsystem self-test failed */
7301 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
7302 /* enum: licensing subsystem self-test passed */
7303 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
7306 /***********************************/
7307 /* MC_CMD_MC2MC_PROXY
7308 * Execute an arbitrary MCDI command on the slave MC of a dual-core device.
7309 * This will fail on a single-core system.
7311 #define MC_CMD_MC2MC_PROXY 0xf4
7314 #endif /* MCDI_PCOL_H */