drivers/net/ethernet/samsung/sxgbe/sxgbe_main.c

   1 /* 10G controller driver for Samsung SoCs
   2  *
   3  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/clk.h>
  16 #include <linux/crc32.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if.h>
  21 #include <linux/if_ether.h>
  22 #include <linux/if_vlan.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/ip.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mii.h>
  28 #include <linux/module.h>
  29 #include <linux/net_tstamp.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/phy.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/prefetch.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/slab.h>
  36 #include <linux/tcp.h>
  37 #include <linux/sxgbe_platform.h>
  38
  39 #include "sxgbe_common.h"
  40 #include "sxgbe_desc.h"
  41 #include "sxgbe_dma.h"
  42 #include "sxgbe_mtl.h"
  43 #include "sxgbe_reg.h"
  44
  45 #define SXGBE_ALIGN(x)  L1_CACHE_ALIGN(x)
  46 #define JUMBO_LEN       9000
  47
  48 /* Module parameters */
  49 #define TX_TIMEO        5000
  50 #define DMA_TX_SIZE     512
  51 #define DMA_RX_SIZE     1024
  52 #define TC_DEFAULT      64
  53 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB
  54 /* The default timer value as per the sxgbe specification 1 sec(1000 ms) */
  55 #define SXGBE_DEFAULT_LPI_TIMER 1000
  56
  57 static int debug = -1;
  58 static int eee_timer = SXGBE_DEFAULT_LPI_TIMER;
  59
  60 module_param(eee_timer, int, S_IRUGO | S_IWUSR);
  61
  62 module_param(debug, int, S_IRUGO | S_IWUSR);
  63 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
  64                                       NETIF_MSG_LINK | NETIF_MSG_IFUP |
  65                                       NETIF_MSG_IFDOWN | NETIF_MSG_TIMER);
  66
  67 static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id);
  68 static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id);
  69 static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id);
  70
  71 #define SXGBE_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
  72
  73 #define SXGBE_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x))
  74
  75 /**
  76  * sxgbe_verify_args - verify the driver parameters.
  77  * Description: it verifies if some wrong parameter is passed to the driver.
  78  * Note that wrong parameters are replaced with the default values.
  79  */
  80 static void sxgbe_verify_args(void)
  81 {
  82         if (unlikely(eee_timer < 0))
  83                 eee_timer = SXGBE_DEFAULT_LPI_TIMER;
  84 }
  85
  86 static void sxgbe_enable_eee_mode(const struct sxgbe_priv_data *priv)
  87 {
  88         /* Check and enter in LPI mode */
  89         if (!priv->tx_path_in_lpi_mode)
  90                 priv->hw->mac->set_eee_mode(priv->ioaddr);
  91 }
  92
  93 void sxgbe_disable_eee_mode(struct sxgbe_priv_data * const priv)
  94 {
  95         /* Exit and disable EEE in case of we are are in LPI state. */
  96         priv->hw->mac->reset_eee_mode(priv->ioaddr);
  97         del_timer_sync(&priv->eee_ctrl_timer);
  98         priv->tx_path_in_lpi_mode = false;
  99 }
 100
 101 /**
 102  * sxgbe_eee_ctrl_timer
 103  * @arg : data hook
 104  * Description:
 105  *  If there is no data transfer and if we are not in LPI state,
 106  *  then MAC Transmitter can be moved to LPI state.
 107  */
 108 static void sxgbe_eee_ctrl_timer(unsigned long arg)
 109 {
 110         struct sxgbe_priv_data *priv = (struct sxgbe_priv_data *)arg;
 111
 112         sxgbe_enable_eee_mode(priv);
 113         mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer));
 114 }
 115
 116 /**
 117  * sxgbe_eee_init
 118  * @priv: private device pointer
 119  * Description:
 120  *  If the EEE support has been enabled while configuring the driver,
 121  *  if the GMAC actually supports the EEE (from the HW cap reg) and the
 122  *  phy can also manage EEE, so enable the LPI state and start the timer
 123  *  to verify if the tx path can enter in LPI state.
 124  */
 125 bool sxgbe_eee_init(struct sxgbe_priv_data * const priv)
 126 {
 127         bool ret = false;
 128
 129         /* MAC core supports the EEE feature. */
 130         if (priv->hw_cap.eee) {
 131                 /* Check if the PHY supports EEE */
 132                 if (phy_init_eee(priv->phydev, 1))
 133                         return false;
 134
 135                 priv->eee_active = 1;
 136                 setup_timer(&priv->eee_ctrl_timer, sxgbe_eee_ctrl_timer,
 137                             (unsigned long)priv);
 138                 priv->eee_ctrl_timer.expires = SXGBE_LPI_TIMER(eee_timer);
 139                 add_timer(&priv->eee_ctrl_timer);
 140
 141                 priv->hw->mac->set_eee_timer(priv->ioaddr,
 142                                              SXGBE_DEFAULT_LPI_TIMER,
 143                                              priv->tx_lpi_timer);
 144
 145                 pr_info("Energy-Efficient Ethernet initialized\n");
 146
 147                 ret = true;
 148         }
 149
 150         return ret;
 151 }
 152
 153 static void sxgbe_eee_adjust(const struct sxgbe_priv_data *priv)
 154 {
 155         /* When the EEE has been already initialised we have to
 156          * modify the PLS bit in the LPI ctrl & status reg according
 157          * to the PHY link status. For this reason.
 158          */
 159         if (priv->eee_enabled)
 160                 priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link);
 161 }
 162
 163 /**
 164  * sxgbe_clk_csr_set - dynamically set the MDC clock
 165  * @priv: driver private structure
 166  * Description: this is to dynamically set the MDC clock according to the csr
 167  * clock input.
 168  */
 169 static void sxgbe_clk_csr_set(struct sxgbe_priv_data *priv)
 170 {
 171         u32 clk_rate = clk_get_rate(priv->sxgbe_clk);
 172
 173         /* assign the proper divider, this will be used during
 174          * mdio communication
 175          */
 176         if (clk_rate < SXGBE_CSR_F_150M)
 177                 priv->clk_csr = SXGBE_CSR_100_150M;
 178         else if (clk_rate <= SXGBE_CSR_F_250M)
 179                 priv->clk_csr = SXGBE_CSR_150_250M;
 180         else if (clk_rate <= SXGBE_CSR_F_300M)
 181                 priv->clk_csr = SXGBE_CSR_250_300M;
 182         else if (clk_rate <= SXGBE_CSR_F_350M)
 183                 priv->clk_csr = SXGBE_CSR_300_350M;
 184         else if (clk_rate <= SXGBE_CSR_F_400M)
 185                 priv->clk_csr = SXGBE_CSR_350_400M;
 186         else if (clk_rate <= SXGBE_CSR_F_500M)
 187                 priv->clk_csr = SXGBE_CSR_400_500M;
 188 }
 189
 190 /* minimum number of free TX descriptors required to wake up TX process */
 191 #define SXGBE_TX_THRESH(x)      (x->dma_tx_size/4)
 192
 193 static inline u32 sxgbe_tx_avail(struct sxgbe_tx_queue *queue, int tx_qsize)
 194 {
 195         return queue->dirty_tx + tx_qsize - queue->cur_tx - 1;
 196 }
 197
 198 /**
 199  * sxgbe_adjust_link
 200  * @dev: net device structure
 201  * Description: it adjusts the link parameters.
 202  */
 203 static void sxgbe_adjust_link(struct net_device *dev)
 204 {
 205         struct sxgbe_priv_data *priv = netdev_priv(dev);
 206         struct phy_device *phydev = priv->phydev;
 207         u8 new_state = 0;
 208         u8 speed = 0xff;
 209
 210         if (!phydev)
 211                 return;
 212
 213         /* SXGBE is not supporting auto-negotiation and
 214          * half duplex mode. so, not handling duplex change
 215          * in this function. only handling speed and link status
 216          */
 217         if (phydev->link) {
 218                 if (phydev->speed != priv->speed) {
 219                         new_state = 1;
 220                         switch (phydev->speed) {
 221                         case SPEED_10000:
 222                                 speed = SXGBE_SPEED_10G;
 223                                 break;
 224                         case SPEED_2500:
 225                                 speed = SXGBE_SPEED_2_5G;
 226                                 break;
 227                         case SPEED_1000:
 228                                 speed = SXGBE_SPEED_1G;
 229                                 break;
 230                         default:
 231                                 netif_err(priv, link, dev,
 232                                           "Speed (%d) not supported\n",
 233                                           phydev->speed);
 234                         }
 235
 236                         priv->speed = phydev->speed;
 237                         priv->hw->mac->set_speed(priv->ioaddr, speed);
 238                 }
 239
 240                 if (!priv->oldlink) {
 241                         new_state = 1;
 242                         priv->oldlink = 1;
 243                 }
 244         } else if (priv->oldlink) {
 245                 new_state = 1;
 246                 priv->oldlink = 0;
 247                 priv->speed = SPEED_UNKNOWN;
 248         }
 249
 250         if (new_state & netif_msg_link(priv))
 251                 phy_print_status(phydev);
 252
 253         /* Alter the MAC settings for EEE */
 254         sxgbe_eee_adjust(priv);
 255 }
 256
 257 /**
 258  * sxgbe_init_phy - PHY initialization
 259  * @dev: net device structure
 260  * Description: it initializes the driver's PHY state, and attaches the PHY
 261  * to the mac driver.
 262  *  Return value:
 263  *  0 on success
 264  */
 265 static int sxgbe_init_phy(struct net_device *ndev)
 266 {
 267         char phy_id_fmt[MII_BUS_ID_SIZE + 3];
 268         char bus_id[MII_BUS_ID_SIZE];
 269         struct phy_device *phydev;
 270         struct sxgbe_priv_data *priv = netdev_priv(ndev);
 271         int phy_iface = priv->plat->interface;
 272
 273         /* assign default link status */
 274         priv->oldlink = 0;
 275         priv->speed = SPEED_UNKNOWN;
 276         priv->oldduplex = DUPLEX_UNKNOWN;
 277
 278         if (priv->plat->phy_bus_name)
 279                 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
 280                          priv->plat->phy_bus_name, priv->plat->bus_id);
 281         else
 282                 snprintf(bus_id, MII_BUS_ID_SIZE, "sxgbe-%x",
 283                          priv->plat->bus_id);
 284
 285         snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
 286                  priv->plat->phy_addr);
 287         netdev_dbg(ndev, "%s: trying to attach to %s\n", __func__, phy_id_fmt);
 288
 289         phydev = phy_connect(ndev, phy_id_fmt, &sxgbe_adjust_link, phy_iface);
 290
 291         if (IS_ERR(phydev)) {
 292                 netdev_err(ndev, "Could not attach to PHY\n");
 293                 return PTR_ERR(phydev);
 294         }
 295
 296         /* Stop Advertising 1000BASE Capability if interface is not GMII */
 297         if ((phy_iface == PHY_INTERFACE_MODE_MII) ||
 298             (phy_iface == PHY_INTERFACE_MODE_RMII))
 299                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
 300                                          SUPPORTED_1000baseT_Full);
 301         if (phydev->phy_id == 0) {
 302                 phy_disconnect(phydev);
 303                 return -ENODEV;
 304         }
 305
 306         netdev_dbg(ndev, "%s: attached to PHY (UID 0x%x) Link = %d\n",
 307                    __func__, phydev->phy_id, phydev->link);
 308
 309         /* save phy device in private structure */
 310         priv->phydev = phydev;
 311
 312         return 0;
 313 }
 314
 315 /**
 316  * sxgbe_clear_descriptors: clear descriptors
 317  * @priv: driver private structure
 318  * Description: this function is called to clear the tx and rx descriptors
 319  * in case of both basic and extended descriptors are used.
 320  */
 321 static void sxgbe_clear_descriptors(struct sxgbe_priv_data *priv)
 322 {
 323         int i, j;
 324         unsigned int txsize = priv->dma_tx_size;
 325         unsigned int rxsize = priv->dma_rx_size;
 326
 327         /* Clear the Rx/Tx descriptors */
 328         for (j = 0; j < SXGBE_RX_QUEUES; j++) {
 329                 for (i = 0; i < rxsize; i++)
 330                         priv->hw->desc->init_rx_desc(&priv->rxq[j]->dma_rx[i],
 331                                                      priv->use_riwt, priv->mode,
 332                                                      (i == rxsize - 1));
 333         }
 334
 335         for (j = 0; j < SXGBE_TX_QUEUES; j++) {
 336                 for (i = 0; i < txsize; i++)
 337                         priv->hw->desc->init_tx_desc(&priv->txq[j]->dma_tx[i]);
 338         }
 339 }
 340
 341 static int sxgbe_init_rx_buffers(struct net_device *dev,
 342                                  struct sxgbe_rx_norm_desc *p, int i,
 343                                  unsigned int dma_buf_sz,
 344                                  struct sxgbe_rx_queue *rx_ring)
 345 {
 346         struct sxgbe_priv_data *priv = netdev_priv(dev);
 347         struct sk_buff *skb;
 348
 349         skb = __netdev_alloc_skb_ip_align(dev, dma_buf_sz, GFP_KERNEL);
 350         if (!skb)
 351                 return -ENOMEM;
 352
 353         rx_ring->rx_skbuff[i] = skb;
 354         rx_ring->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data,
 355                                                    dma_buf_sz, DMA_FROM_DEVICE);
 356
 357         if (dma_mapping_error(priv->device, rx_ring->rx_skbuff_dma[i])) {
 358                 netdev_err(dev, "%s: DMA mapping error\n", __func__);
 359                 dev_kfree_skb_any(skb);
 360                 return -EINVAL;
 361         }
 362
 363         p->rdes23.rx_rd_des23.buf2_addr = rx_ring->rx_skbuff_dma[i];
 364
 365         return 0;
 366 }
 367 /**
 368  * init_tx_ring - init the TX descriptor ring
 369  * @dev: net device structure
 370  * @tx_ring: ring to be intialised
 371  * @tx_rsize: ring size
 372  * Description:  this function initializes the DMA TX descriptor
 373  */
 374 static int init_tx_ring(struct device *dev, u8 queue_no,
 375                         struct sxgbe_tx_queue *tx_ring, int tx_rsize)
 376 {
 377         /* TX ring is not allcoated */
 378         if (!tx_ring) {
 379                 dev_err(dev, "No memory for TX queue of SXGBE\n");
 380                 return -ENOMEM;
 381         }
 382
 383         /* allocate memory for TX descriptors */
 384         tx_ring->dma_tx = dma_zalloc_coherent(dev,
 385                                               tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
 386                                               &tx_ring->dma_tx_phy, GFP_KERNEL);
 387         if (!tx_ring->dma_tx)
 388                 return -ENOMEM;
 389
 390         /* allocate memory for TX skbuff array */
 391         tx_ring->tx_skbuff_dma = devm_kcalloc(dev, tx_rsize,
 392                                               sizeof(dma_addr_t), GFP_KERNEL);
 393         if (!tx_ring->tx_skbuff_dma)
 394                 goto dmamem_err;
 395
 396         tx_ring->tx_skbuff = devm_kcalloc(dev, tx_rsize,
 397                                           sizeof(struct sk_buff *), GFP_KERNEL);
 398
 399         if (!tx_ring->tx_skbuff)
 400                 goto dmamem_err;
 401
 402         /* assign queue number */
 403         tx_ring->queue_no = queue_no;
 404
 405         /* initalise counters */
 406         tx_ring->dirty_tx = 0;
 407         tx_ring->cur_tx = 0;
 408
 409         /* initalise TX queue lock */
 410         spin_lock_init(&tx_ring->tx_lock);
 411
 412         return 0;
 413
 414 dmamem_err:
 415         dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
 416                           tx_ring->dma_tx, tx_ring->dma_tx_phy);
 417         return -ENOMEM;
 418 }
 419
 420 /**
 421  * free_rx_ring - free the RX descriptor ring
 422  * @dev: net device structure
 423  * @rx_ring: ring to be intialised
 424  * @rx_rsize: ring size
 425  * Description:  this function initializes the DMA RX descriptor
 426  */
 427 static void free_rx_ring(struct device *dev, struct sxgbe_rx_queue *rx_ring,
 428                          int rx_rsize)
 429 {
 430         dma_free_coherent(dev, rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
 431                           rx_ring->dma_rx, rx_ring->dma_rx_phy);
 432         kfree(rx_ring->rx_skbuff_dma);
 433         kfree(rx_ring->rx_skbuff);
 434 }
 435
 436 /**
 437  * init_rx_ring - init the RX descriptor ring
 438  * @dev: net device structure
 439  * @rx_ring: ring to be intialised
 440  * @rx_rsize: ring size
 441  * Description:  this function initializes the DMA RX descriptor
 442  */
 443 static int init_rx_ring(struct net_device *dev, u8 queue_no,
 444                         struct sxgbe_rx_queue *rx_ring, int rx_rsize)
 445 {
 446         struct sxgbe_priv_data *priv = netdev_priv(dev);
 447         int desc_index;
 448         unsigned int bfsize = 0;
 449         unsigned int ret = 0;
 450
 451         /* Set the max buffer size according to the MTU. */
 452         bfsize = ALIGN(dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN, 8);
 453
 454         netif_dbg(priv, probe, dev, "%s: bfsize %d\n", __func__, bfsize);
 455
 456         /* RX ring is not allcoated */
 457         if (rx_ring == NULL) {
 458                 netdev_err(dev, "No memory for RX queue\n");
 459                 goto error;
 460         }
 461
 462         /* assign queue number */
 463         rx_ring->queue_no = queue_no;
 464
 465         /* allocate memory for RX descriptors */
 466         rx_ring->dma_rx = dma_zalloc_coherent(priv->device,
 467                                               rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
 468                                               &rx_ring->dma_rx_phy, GFP_KERNEL);
 469
 470         if (rx_ring->dma_rx == NULL)
 471                 goto error;
 472
 473         /* allocate memory for RX skbuff array */
 474         rx_ring->rx_skbuff_dma = kmalloc_array(rx_rsize,
 475                                                sizeof(dma_addr_t), GFP_KERNEL);
 476         if (!rx_ring->rx_skbuff_dma) {
 477                 dma_free_coherent(priv->device,
 478                                   rx_rsize * sizeof(struct sxgbe_rx_norm_desc),
 479                                   rx_ring->dma_rx, rx_ring->dma_rx_phy);
 480                 goto error;
 481         }
 482
 483         rx_ring->rx_skbuff = kmalloc_array(rx_rsize,
 484                                            sizeof(struct sk_buff *), GFP_KERNEL);
 485         if (!rx_ring->rx_skbuff) {
 486                 kfree(rx_ring->rx_skbuff_dma);
 487                 goto error;
 488         }
 489
 490         /* initialise the buffers */
 491         for (desc_index = 0; desc_index < rx_rsize; desc_index++) {
 492                 struct sxgbe_rx_norm_desc *p;
 493                 p = rx_ring->dma_rx + desc_index;
 494                 ret = sxgbe_init_rx_buffers(dev, p, desc_index,
 495                                             bfsize, rx_ring);
 496                 if (ret)
 497                         goto err_init_rx_buffers;
 498         }
 499
 500         /* initalise counters */
 501         rx_ring->cur_rx = 0;
 502         rx_ring->dirty_rx = (unsigned int)(desc_index - rx_rsize);
 503         priv->dma_buf_sz = bfsize;
 504
 505         return 0;
 506
 507 err_init_rx_buffers:
 508         while (--desc_index >= 0)
 509                 free_rx_ring(priv->device, rx_ring, desc_index);
 510 error:
 511         return -ENOMEM;
 512 }
 513 /**
 514  * free_tx_ring - free the TX descriptor ring
 515  * @dev: net device structure
 516  * @tx_ring: ring to be intialised
 517  * @tx_rsize: ring size
 518  * Description:  this function initializes the DMA TX descriptor
 519  */
 520 static void free_tx_ring(struct device *dev, struct sxgbe_tx_queue *tx_ring,
 521                          int tx_rsize)
 522 {
 523         dma_free_coherent(dev, tx_rsize * sizeof(struct sxgbe_tx_norm_desc),
 524                           tx_ring->dma_tx, tx_ring->dma_tx_phy);
 525 }
 526
 527 /**
 528  * init_dma_desc_rings - init the RX/TX descriptor rings
 529  * @dev: net device structure
 530  * Description:  this function initializes the DMA RX/TX descriptors
 531  * and allocates the socket buffers. It suppors the chained and ring
 532  * modes.
 533  */
 534 static int init_dma_desc_rings(struct net_device *netd)
 535 {
 536         int queue_num, ret;
 537         struct sxgbe_priv_data *priv = netdev_priv(netd);
 538         int tx_rsize = priv->dma_tx_size;
 539         int rx_rsize = priv->dma_rx_size;
 540
 541         /* Allocate memory for queue structures and TX descs */
 542         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 543                 ret = init_tx_ring(priv->device, queue_num,
 544                                    priv->txq[queue_num], tx_rsize);
 545                 if (ret) {
 546                         dev_err(&netd->dev, "TX DMA ring allocation failed!\n");
 547                         goto txalloc_err;
 548                 }
 549
 550                 /* save private pointer in each ring this
 551                  * pointer is needed during cleaing TX queue
 552                  */
 553                 priv->txq[queue_num]->priv_ptr = priv;
 554         }
 555
 556         /* Allocate memory for queue structures and RX descs */
 557         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
 558                 ret = init_rx_ring(netd, queue_num,
 559                                    priv->rxq[queue_num], rx_rsize);
 560                 if (ret) {
 561                         netdev_err(netd, "RX DMA ring allocation failed!!\n");
 562                         goto rxalloc_err;
 563                 }
 564
 565                 /* save private pointer in each ring this
 566                  * pointer is needed during cleaing TX queue
 567                  */
 568                 priv->rxq[queue_num]->priv_ptr = priv;
 569         }
 570
 571         sxgbe_clear_descriptors(priv);
 572
 573         return 0;
 574
 575 txalloc_err:
 576         while (queue_num--)
 577                 free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize);
 578         return ret;
 579
 580 rxalloc_err:
 581         while (queue_num--)
 582                 free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize);
 583         return ret;
 584 }
 585
 586 static void tx_free_ring_skbufs(struct sxgbe_tx_queue *txqueue)
 587 {
 588         int dma_desc;
 589         struct sxgbe_priv_data *priv = txqueue->priv_ptr;
 590         int tx_rsize = priv->dma_tx_size;
 591
 592         for (dma_desc = 0; dma_desc < tx_rsize; dma_desc++) {
 593                 struct sxgbe_tx_norm_desc *tdesc = txqueue->dma_tx + dma_desc;
 594
 595                 if (txqueue->tx_skbuff_dma[dma_desc])
 596                         dma_unmap_single(priv->device,
 597                                          txqueue->tx_skbuff_dma[dma_desc],
 598                                          priv->hw->desc->get_tx_len(tdesc),
 599                                          DMA_TO_DEVICE);
 600
 601                 dev_kfree_skb_any(txqueue->tx_skbuff[dma_desc]);
 602                 txqueue->tx_skbuff[dma_desc] = NULL;
 603                 txqueue->tx_skbuff_dma[dma_desc] = 0;
 604         }
 605 }
 606
 607
 608 static void dma_free_tx_skbufs(struct sxgbe_priv_data *priv)
 609 {
 610         int queue_num;
 611
 612         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 613                 struct sxgbe_tx_queue *tqueue = priv->txq[queue_num];
 614                 tx_free_ring_skbufs(tqueue);
 615         }
 616 }
 617
 618 static void free_dma_desc_resources(struct sxgbe_priv_data *priv)
 619 {
 620         int queue_num;
 621         int tx_rsize = priv->dma_tx_size;
 622         int rx_rsize = priv->dma_rx_size;
 623
 624         /* Release the DMA TX buffers */
 625         dma_free_tx_skbufs(priv);
 626
 627         /* Release the TX ring memory also */
 628         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 629                 free_tx_ring(priv->device, priv->txq[queue_num], tx_rsize);
 630         }
 631
 632         /* Release the RX ring memory also */
 633         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
 634                 free_rx_ring(priv->device, priv->rxq[queue_num], rx_rsize);
 635         }
 636 }
 637
 638 static int txring_mem_alloc(struct sxgbe_priv_data *priv)
 639 {
 640         int queue_num;
 641
 642         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 643                 priv->txq[queue_num] = devm_kmalloc(priv->device,
 644                                                     sizeof(struct sxgbe_tx_queue), GFP_KERNEL);
 645                 if (!priv->txq[queue_num])
 646                         return -ENOMEM;
 647         }
 648
 649         return 0;
 650 }
 651
 652 static int rxring_mem_alloc(struct sxgbe_priv_data *priv)
 653 {
 654         int queue_num;
 655
 656         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
 657                 priv->rxq[queue_num] = devm_kmalloc(priv->device,
 658                                                     sizeof(struct sxgbe_rx_queue), GFP_KERNEL);
 659                 if (!priv->rxq[queue_num])
 660                         return -ENOMEM;
 661         }
 662
 663         return 0;
 664 }
 665
 666 /**
 667  *  sxgbe_mtl_operation_mode - HW MTL operation mode
 668  *  @priv: driver private structure
 669  *  Description: it sets the MTL operation mode: tx/rx MTL thresholds
 670  *  or Store-And-Forward capability.
 671  */
 672 static void sxgbe_mtl_operation_mode(struct sxgbe_priv_data *priv)
 673 {
 674         int queue_num;
 675
 676         /* TX/RX threshold control */
 677         if (likely(priv->plat->force_sf_dma_mode)) {
 678                 /* set TC mode for TX QUEUES */
 679                 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num)
 680                         priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num,
 681                                                        SXGBE_MTL_SFMODE);
 682                 priv->tx_tc = SXGBE_MTL_SFMODE;
 683
 684                 /* set TC mode for RX QUEUES */
 685                 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num)
 686                         priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num,
 687                                                        SXGBE_MTL_SFMODE);
 688                 priv->rx_tc = SXGBE_MTL_SFMODE;
 689         } else if (unlikely(priv->plat->force_thresh_dma_mode)) {
 690                 /* set TC mode for TX QUEUES */
 691                 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.tx_mtl_queues, queue_num)
 692                         priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr, queue_num,
 693                                                        priv->tx_tc);
 694                 /* set TC mode for RX QUEUES */
 695                 SXGBE_FOR_EACH_QUEUE(priv->hw_cap.rx_mtl_queues, queue_num)
 696                         priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr, queue_num,
 697                                                        priv->rx_tc);
 698         } else {
 699                 pr_err("ERROR: %s: Invalid TX threshold mode\n", __func__);
 700         }
 701 }
 702
 703 /**
 704  * sxgbe_tx_queue_clean:
 705  * @priv: driver private structure
 706  * Description: it reclaims resources after transmission completes.
 707  */
 708 static void sxgbe_tx_queue_clean(struct sxgbe_tx_queue *tqueue)
 709 {
 710         struct sxgbe_priv_data *priv = tqueue->priv_ptr;
 711         unsigned int tx_rsize = priv->dma_tx_size;
 712         struct netdev_queue *dev_txq;
 713         u8 queue_no = tqueue->queue_no;
 714
 715         dev_txq = netdev_get_tx_queue(priv->dev, queue_no);
 716
 717         spin_lock(&tqueue->tx_lock);
 718
 719         priv->xstats.tx_clean++;
 720         while (tqueue->dirty_tx != tqueue->cur_tx) {
 721                 unsigned int entry = tqueue->dirty_tx % tx_rsize;
 722                 struct sk_buff *skb = tqueue->tx_skbuff[entry];
 723                 struct sxgbe_tx_norm_desc *p;
 724
 725                 p = tqueue->dma_tx + entry;
 726
 727                 /* Check if the descriptor is owned by the DMA. */
 728                 if (priv->hw->desc->get_tx_owner(p))
 729                         break;
 730
 731                 if (netif_msg_tx_done(priv))
 732                         pr_debug("%s: curr %d, dirty %d\n",
 733                                  __func__, tqueue->cur_tx, tqueue->dirty_tx);
 734
 735                 if (likely(tqueue->tx_skbuff_dma[entry])) {
 736                         dma_unmap_single(priv->device,
 737                                          tqueue->tx_skbuff_dma[entry],
 738                                          priv->hw->desc->get_tx_len(p),
 739                                          DMA_TO_DEVICE);
 740                         tqueue->tx_skbuff_dma[entry] = 0;
 741                 }
 742
 743                 if (likely(skb)) {
 744                         dev_kfree_skb(skb);
 745                         tqueue->tx_skbuff[entry] = NULL;
 746                 }
 747
 748                 priv->hw->desc->release_tx_desc(p);
 749
 750                 tqueue->dirty_tx++;
 751         }
 752
 753         /* wake up queue */
 754         if (unlikely(netif_tx_queue_stopped(dev_txq) &&
 755                      sxgbe_tx_avail(tqueue, tx_rsize) > SXGBE_TX_THRESH(priv))) {
 756                 netif_tx_lock(priv->dev);
 757                 if (netif_tx_queue_stopped(dev_txq) &&
 758                     sxgbe_tx_avail(tqueue, tx_rsize) > SXGBE_TX_THRESH(priv)) {
 759                         if (netif_msg_tx_done(priv))
 760                                 pr_debug("%s: restart transmit\n", __func__);
 761                         netif_tx_wake_queue(dev_txq);
 762                 }
 763                 netif_tx_unlock(priv->dev);
 764         }
 765
 766         spin_unlock(&tqueue->tx_lock);
 767 }
 768
 769 /**
 770  * sxgbe_tx_clean:
 771  * @priv: driver private structure
 772  * Description: it reclaims resources after transmission completes.
 773  */
 774 static void sxgbe_tx_all_clean(struct sxgbe_priv_data * const priv)
 775 {
 776         u8 queue_num;
 777
 778         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 779                 struct sxgbe_tx_queue *tqueue = priv->txq[queue_num];
 780
 781                 sxgbe_tx_queue_clean(tqueue);
 782         }
 783
 784         if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) {
 785                 sxgbe_enable_eee_mode(priv);
 786                 mod_timer(&priv->eee_ctrl_timer, SXGBE_LPI_TIMER(eee_timer));
 787         }
 788 }
 789
 790 /**
 791  * sxgbe_restart_tx_queue: irq tx error mng function
 792  * @priv: driver private structure
 793  * Description: it cleans the descriptors and restarts the transmission
 794  * in case of errors.
 795  */
 796 static void sxgbe_restart_tx_queue(struct sxgbe_priv_data *priv, int queue_num)
 797 {
 798         struct sxgbe_tx_queue *tx_ring = priv->txq[queue_num];
 799         struct netdev_queue *dev_txq = netdev_get_tx_queue(priv->dev,
 800                                                            queue_num);
 801
 802         /* stop the queue */
 803         netif_tx_stop_queue(dev_txq);
 804
 805         /* stop the tx dma */
 806         priv->hw->dma->stop_tx_queue(priv->ioaddr, queue_num);
 807
 808         /* free the skbuffs of the ring */
 809         tx_free_ring_skbufs(tx_ring);
 810
 811         /* initalise counters */
 812         tx_ring->cur_tx = 0;
 813         tx_ring->dirty_tx = 0;
 814
 815         /* start the tx dma */
 816         priv->hw->dma->start_tx_queue(priv->ioaddr, queue_num);
 817
 818         priv->dev->stats.tx_errors++;
 819
 820         /* wakeup the queue */
 821         netif_tx_wake_queue(dev_txq);
 822 }
 823
 824 /**
 825  * sxgbe_reset_all_tx_queues: irq tx error mng function
 826  * @priv: driver private structure
 827  * Description: it cleans all the descriptors and
 828  * restarts the transmission on all queues in case of errors.
 829  */
 830 static void sxgbe_reset_all_tx_queues(struct sxgbe_priv_data *priv)
 831 {
 832         int queue_num;
 833
 834         /* On TX timeout of net device, resetting of all queues
 835          * may not be proper way, revisit this later if needed
 836          */
 837         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
 838                 sxgbe_restart_tx_queue(priv, queue_num);
 839 }
 840
 841 /**
 842  * sxgbe_get_hw_features: get XMAC capabilities from the HW cap. register.
 843  * @priv: driver private structure
 844  * Description:
 845  *  new GMAC chip generations have a new register to indicate the
 846  *  presence of the optional feature/functions.
 847  *  This can be also used to override the value passed through the
 848  *  platform and necessary for old MAC10/100 and GMAC chips.
 849  */
 850 static int sxgbe_get_hw_features(struct sxgbe_priv_data * const priv)
 851 {
 852         int rval = 0;
 853         struct sxgbe_hw_features *features = &priv->hw_cap;
 854
 855         /* Read First Capability Register CAP[0] */
 856         rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 0);
 857         if (rval) {
 858                 features->pmt_remote_wake_up =
 859                         SXGBE_HW_FEAT_PMT_TEMOTE_WOP(rval);
 860                 features->pmt_magic_frame = SXGBE_HW_FEAT_PMT_MAGIC_PKT(rval);
 861                 features->atime_stamp = SXGBE_HW_FEAT_IEEE1500_2008(rval);
 862                 features->tx_csum_offload =
 863                         SXGBE_HW_FEAT_TX_CSUM_OFFLOAD(rval);
 864                 features->rx_csum_offload =
 865                         SXGBE_HW_FEAT_RX_CSUM_OFFLOAD(rval);
 866                 features->multi_macaddr = SXGBE_HW_FEAT_MACADDR_COUNT(rval);
 867                 features->tstamp_srcselect = SXGBE_HW_FEAT_TSTMAP_SRC(rval);
 868                 features->sa_vlan_insert = SXGBE_HW_FEAT_SRCADDR_VLAN(rval);
 869                 features->eee = SXGBE_HW_FEAT_EEE(rval);
 870         }
 871
 872         /* Read First Capability Register CAP[1] */
 873         rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 1);
 874         if (rval) {
 875                 features->rxfifo_size = SXGBE_HW_FEAT_RX_FIFO_SIZE(rval);
 876                 features->txfifo_size = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval);
 877                 features->atstmap_hword = SXGBE_HW_FEAT_TX_FIFO_SIZE(rval);
 878                 features->dcb_enable = SXGBE_HW_FEAT_DCB(rval);
 879                 features->splithead_enable = SXGBE_HW_FEAT_SPLIT_HDR(rval);
 880                 features->tcpseg_offload = SXGBE_HW_FEAT_TSO(rval);
 881                 features->debug_mem = SXGBE_HW_FEAT_DEBUG_MEM_IFACE(rval);
 882                 features->rss_enable = SXGBE_HW_FEAT_RSS(rval);
 883                 features->hash_tsize = SXGBE_HW_FEAT_HASH_TABLE_SIZE(rval);
 884                 features->l3l4_filer_size = SXGBE_HW_FEAT_L3L4_FILTER_NUM(rval);
 885         }
 886
 887         /* Read First Capability Register CAP[2] */
 888         rval = priv->hw->mac->get_hw_feature(priv->ioaddr, 2);
 889         if (rval) {
 890                 features->rx_mtl_queues = SXGBE_HW_FEAT_RX_MTL_QUEUES(rval);
 891                 features->tx_mtl_queues = SXGBE_HW_FEAT_TX_MTL_QUEUES(rval);
 892                 features->rx_dma_channels = SXGBE_HW_FEAT_RX_DMA_CHANNELS(rval);
 893                 features->tx_dma_channels = SXGBE_HW_FEAT_TX_DMA_CHANNELS(rval);
 894                 features->pps_output_count = SXGBE_HW_FEAT_PPS_OUTPUTS(rval);
 895                 features->aux_input_count = SXGBE_HW_FEAT_AUX_SNAPSHOTS(rval);
 896         }
 897
 898         return rval;
 899 }
 900
 901 /**
 902  * sxgbe_check_ether_addr: check if the MAC addr is valid
 903  * @priv: driver private structure
 904  * Description:
 905  * it is to verify if the MAC address is valid, in case of failures it
 906  * generates a random MAC address
 907  */
 908 static void sxgbe_check_ether_addr(struct sxgbe_priv_data *priv)
 909 {
 910         if (!is_valid_ether_addr(priv->dev->dev_addr)) {
 911                 priv->hw->mac->get_umac_addr((void __iomem *)
 912                                              priv->ioaddr,
 913                                              priv->dev->dev_addr, 0);
 914                 if (!is_valid_ether_addr(priv->dev->dev_addr))
 915                         eth_hw_addr_random(priv->dev);
 916         }
 917         dev_info(priv->device, "device MAC address %pM\n",
 918                  priv->dev->dev_addr);
 919 }
 920
 921 /**
 922  * sxgbe_init_dma_engine: DMA init.
 923  * @priv: driver private structure
 924  * Description:
 925  * It inits the DMA invoking the specific SXGBE callback.
 926  * Some DMA parameters can be passed from the platform;
 927  * in case of these are not passed a default is kept for the MAC or GMAC.
 928  */
 929 static int sxgbe_init_dma_engine(struct sxgbe_priv_data *priv)
 930 {
 931         int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_map = 0;
 932         int queue_num;
 933
 934         if (priv->plat->dma_cfg) {
 935                 pbl = priv->plat->dma_cfg->pbl;
 936                 fixed_burst = priv->plat->dma_cfg->fixed_burst;
 937                 burst_map = priv->plat->dma_cfg->burst_map;
 938         }
 939
 940         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
 941                 priv->hw->dma->cha_init(priv->ioaddr, queue_num,
 942                                         fixed_burst, pbl,
 943                                         (priv->txq[queue_num])->dma_tx_phy,
 944                                         (priv->rxq[queue_num])->dma_rx_phy,
 945                                         priv->dma_tx_size, priv->dma_rx_size);
 946
 947         return priv->hw->dma->init(priv->ioaddr, fixed_burst, burst_map);
 948 }
 949
 950 /**
 951  * sxgbe_init_mtl_engine: MTL init.
 952  * @priv: driver private structure
 953  * Description:
 954  * It inits the MTL invoking the specific SXGBE callback.
 955  */
 956 static void sxgbe_init_mtl_engine(struct sxgbe_priv_data *priv)
 957 {
 958         int queue_num;
 959
 960         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
 961                 priv->hw->mtl->mtl_set_txfifosize(priv->ioaddr, queue_num,
 962                                                   priv->hw_cap.tx_mtl_qsize);
 963                 priv->hw->mtl->mtl_enable_txqueue(priv->ioaddr, queue_num);
 964         }
 965 }
 966
 967 /**
 968  * sxgbe_disable_mtl_engine: MTL disable.
 969  * @priv: driver private structure
 970  * Description:
 971  * It disables the MTL queues by invoking the specific SXGBE callback.
 972  */
 973 static void sxgbe_disable_mtl_engine(struct sxgbe_priv_data *priv)
 974 {
 975         int queue_num;
 976
 977         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num)
 978                 priv->hw->mtl->mtl_disable_txqueue(priv->ioaddr, queue_num);
 979 }
 980
 981
 982 /**
 983  * sxgbe_tx_timer: mitigation sw timer for tx.
 984  * @data: data pointer
 985  * Description:
 986  * This is the timer handler to directly invoke the sxgbe_tx_clean.
 987  */
 988 static void sxgbe_tx_timer(unsigned long data)
 989 {
 990         struct sxgbe_tx_queue *p = (struct sxgbe_tx_queue *)data;
 991         sxgbe_tx_queue_clean(p);
 992 }
 993
 994 /**
 995  * sxgbe_init_tx_coalesce: init tx mitigation options.
 996  * @priv: driver private structure
 997  * Description:
 998  * This inits the transmit coalesce parameters: i.e. timer rate,
 999  * timer handler and default threshold used for enabling the
1000  * interrupt on completion bit.
1001  */
1002 static void sxgbe_tx_init_coalesce(struct sxgbe_priv_data *priv)
1003 {
1004         u8 queue_num;
1005
1006         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1007                 struct sxgbe_tx_queue *p = priv->txq[queue_num];
1008                 p->tx_coal_frames =  SXGBE_TX_FRAMES;
1009                 p->tx_coal_timer = SXGBE_COAL_TX_TIMER;
1010                 setup_timer(&p->txtimer, sxgbe_tx_timer,
1011                             (unsigned long)&priv->txq[queue_num]);
1012                 p->txtimer.expires = SXGBE_COAL_TIMER(p->tx_coal_timer);
1013                 add_timer(&p->txtimer);
1014         }
1015 }
1016
1017 static void sxgbe_tx_del_timer(struct sxgbe_priv_data *priv)
1018 {
1019         u8 queue_num;
1020
1021         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1022                 struct sxgbe_tx_queue *p = priv->txq[queue_num];
1023                 del_timer_sync(&p->txtimer);
1024         }
1025 }
1026
1027 /**
1028  *  sxgbe_open - open entry point of the driver
1029  *  @dev : pointer to the device structure.
1030  *  Description:
1031  *  This function is the open entry point of the driver.
1032  *  Return value:
1033  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1034  *  file on failure.
1035  */
1036 static int sxgbe_open(struct net_device *dev)
1037 {
1038         struct sxgbe_priv_data *priv = netdev_priv(dev);
1039         int ret, queue_num;
1040
1041         clk_prepare_enable(priv->sxgbe_clk);
1042
1043         sxgbe_check_ether_addr(priv);
1044
1045         /* Init the phy */
1046         ret = sxgbe_init_phy(dev);
1047         if (ret) {
1048                 netdev_err(dev, "%s: Cannot attach to PHY (error: %d)\n",
1049                            __func__, ret);
1050                 goto phy_error;
1051         }
1052
1053         /* Create and initialize the TX/RX descriptors chains. */
1054         priv->dma_tx_size = SXGBE_ALIGN(DMA_TX_SIZE);
1055         priv->dma_rx_size = SXGBE_ALIGN(DMA_RX_SIZE);
1056         priv->dma_buf_sz = SXGBE_ALIGN(DMA_BUFFER_SIZE);
1057         priv->tx_tc = TC_DEFAULT;
1058         priv->rx_tc = TC_DEFAULT;
1059         init_dma_desc_rings(dev);
1060
1061         /* DMA initialization and SW reset */
1062         ret = sxgbe_init_dma_engine(priv);
1063         if (ret < 0) {
1064                 netdev_err(dev, "%s: DMA initialization failed\n", __func__);
1065                 goto init_error;
1066         }
1067
1068         /*  MTL initialization */
1069         sxgbe_init_mtl_engine(priv);
1070
1071         /* Copy the MAC addr into the HW  */
1072         priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0);
1073
1074         /* Initialize the MAC Core */
1075         priv->hw->mac->core_init(priv->ioaddr);
1076         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
1077                 priv->hw->mac->enable_rxqueue(priv->ioaddr, queue_num);
1078         }
1079
1080         /* Request the IRQ lines */
1081         ret = devm_request_irq(priv->device, priv->irq, sxgbe_common_interrupt,
1082                                IRQF_SHARED, dev->name, dev);
1083         if (unlikely(ret < 0)) {
1084                 netdev_err(dev, "%s: ERROR: allocating the IRQ %d (error: %d)\n",
1085                            __func__, priv->irq, ret);
1086                 goto init_error;
1087         }
1088
1089         /* If the LPI irq is different from the mac irq
1090          * register a dedicated handler
1091          */
1092         if (priv->lpi_irq != dev->irq) {
1093                 ret = devm_request_irq(priv->device, priv->lpi_irq,
1094                                        sxgbe_common_interrupt,
1095                                        IRQF_SHARED, dev->name, dev);
1096                 if (unlikely(ret < 0)) {
1097                         netdev_err(dev, "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
1098                                    __func__, priv->lpi_irq, ret);
1099                         goto init_error;
1100                 }
1101         }
1102
1103         /* Request TX DMA irq lines */
1104         SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
1105                 ret = devm_request_irq(priv->device,
1106                                        (priv->txq[queue_num])->irq_no,
1107                                        sxgbe_tx_interrupt, 0,
1108                                        dev->name, priv->txq[queue_num]);
1109                 if (unlikely(ret < 0)) {
1110                         netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n",
1111                                    __func__, priv->irq, ret);
1112                         goto init_error;
1113                 }
1114         }
1115
1116         /* Request RX DMA irq lines */
1117         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
1118                 ret = devm_request_irq(priv->device,
1119                                        (priv->rxq[queue_num])->irq_no,
1120                                        sxgbe_rx_interrupt, 0,
1121                                        dev->name, priv->rxq[queue_num]);
1122                 if (unlikely(ret < 0)) {
1123                         netdev_err(dev, "%s: ERROR: allocating TX IRQ %d (error: %d)\n",
1124                                    __func__, priv->irq, ret);
1125                         goto init_error;
1126                 }
1127         }
1128
1129         /* Enable the MAC Rx/Tx */
1130         priv->hw->mac->enable_tx(priv->ioaddr, true);
1131         priv->hw->mac->enable_rx(priv->ioaddr, true);
1132
1133         /* Set the HW DMA mode and the COE */
1134         sxgbe_mtl_operation_mode(priv);
1135
1136         /* Extra statistics */
1137         memset(&priv->xstats, 0, sizeof(struct sxgbe_extra_stats));
1138
1139         priv->xstats.tx_threshold = priv->tx_tc;
1140         priv->xstats.rx_threshold = priv->rx_tc;
1141
1142         /* Start the ball rolling... */
1143         netdev_dbg(dev, "DMA RX/TX processes started...\n");
1144         priv->hw->dma->start_tx(priv->ioaddr, SXGBE_TX_QUEUES);
1145         priv->hw->dma->start_rx(priv->ioaddr, SXGBE_RX_QUEUES);
1146
1147         if (priv->phydev)
1148                 phy_start(priv->phydev);
1149
1150         /* initalise TX coalesce parameters */
1151         sxgbe_tx_init_coalesce(priv);
1152
1153         if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) {
1154                 priv->rx_riwt = SXGBE_MAX_DMA_RIWT;
1155                 priv->hw->dma->rx_watchdog(priv->ioaddr, SXGBE_MAX_DMA_RIWT);
1156         }
1157
1158         priv->tx_lpi_timer = SXGBE_DEFAULT_LPI_TIMER;
1159         priv->eee_enabled = sxgbe_eee_init(priv);
1160
1161         napi_enable(&priv->napi);
1162         netif_start_queue(dev);
1163
1164         return 0;
1165
1166 init_error:
1167         free_dma_desc_resources(priv);
1168         if (priv->phydev)
1169                 phy_disconnect(priv->phydev);
1170 phy_error:
1171         clk_disable_unprepare(priv->sxgbe_clk);
1172
1173         return ret;
1174 }
1175
1176 /**
1177  *  sxgbe_release - close entry point of the driver
1178  *  @dev : device pointer.
1179  *  Description:
1180  *  This is the stop entry point of the driver.
1181  */
1182 static int sxgbe_release(struct net_device *dev)
1183 {
1184         struct sxgbe_priv_data *priv = netdev_priv(dev);
1185
1186         if (priv->eee_enabled)
1187                 del_timer_sync(&priv->eee_ctrl_timer);
1188
1189         /* Stop and disconnect the PHY */
1190         if (priv->phydev) {
1191                 phy_stop(priv->phydev);
1192                 phy_disconnect(priv->phydev);
1193                 priv->phydev = NULL;
1194         }
1195
1196         netif_tx_stop_all_queues(dev);
1197
1198         napi_disable(&priv->napi);
1199
1200         /* delete TX timers */
1201         sxgbe_tx_del_timer(priv);
1202
1203         /* Stop TX/RX DMA and clear the descriptors */
1204         priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES);
1205         priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES);
1206
1207         /* disable MTL queue */
1208         sxgbe_disable_mtl_engine(priv);
1209
1210         /* Release and free the Rx/Tx resources */
1211         free_dma_desc_resources(priv);
1212
1213         /* Disable the MAC Rx/Tx */
1214         priv->hw->mac->enable_tx(priv->ioaddr, false);
1215         priv->hw->mac->enable_rx(priv->ioaddr, false);
1216
1217         clk_disable_unprepare(priv->sxgbe_clk);
1218
1219         return 0;
1220 }
1221 /* Prepare first Tx descriptor for doing TSO operation */
1222 static void sxgbe_tso_prepare(struct sxgbe_priv_data *priv,
1223                               struct sxgbe_tx_norm_desc *first_desc,
1224                               struct sk_buff *skb)
1225 {
1226         unsigned int total_hdr_len, tcp_hdr_len;
1227
1228         /* Write first Tx descriptor with appropriate value */
1229         tcp_hdr_len = tcp_hdrlen(skb);
1230         total_hdr_len = skb_transport_offset(skb) + tcp_hdr_len;
1231
1232         first_desc->tdes01 = dma_map_single(priv->device, skb->data,
1233                                             total_hdr_len, DMA_TO_DEVICE);
1234         if (dma_mapping_error(priv->device, first_desc->tdes01))
1235                 pr_err("%s: TX dma mapping failed!!\n", __func__);
1236
1237         first_desc->tdes23.tx_rd_des23.first_desc = 1;
1238         priv->hw->desc->tx_desc_enable_tse(first_desc, 1, total_hdr_len,
1239                                            tcp_hdr_len,
1240                                            skb->len - total_hdr_len);
1241 }
1242
1243 /**
1244  *  sxgbe_xmit: Tx entry point of the driver
1245  *  @skb : the socket buffer
1246  *  @dev : device pointer
1247  *  Description : this is the tx entry point of the driver.
1248  *  It programs the chain or the ring and supports oversized frames
1249  *  and SG feature.
1250  */
1251 static netdev_tx_t sxgbe_xmit(struct sk_buff *skb, struct net_device *dev)
1252 {
1253         unsigned int entry, frag_num;
1254         int cksum_flag = 0;
1255         struct netdev_queue *dev_txq;
1256         unsigned txq_index = skb_get_queue_mapping(skb);
1257         struct sxgbe_priv_data *priv = netdev_priv(dev);
1258         unsigned int tx_rsize = priv->dma_tx_size;
1259         struct sxgbe_tx_queue *tqueue = priv->txq[txq_index];
1260         struct sxgbe_tx_norm_desc *tx_desc, *first_desc;
1261         struct sxgbe_tx_ctxt_desc *ctxt_desc = NULL;
1262         int nr_frags = skb_shinfo(skb)->nr_frags;
1263         int no_pagedlen = skb_headlen(skb);
1264         int is_jumbo = 0;
1265         u16 cur_mss = skb_shinfo(skb)->gso_size;
1266         u32 ctxt_desc_req = 0;
1267
1268         /* get the TX queue handle */
1269         dev_txq = netdev_get_tx_queue(dev, txq_index);
1270
1271         if (unlikely(skb_is_gso(skb) && tqueue->prev_mss != cur_mss))
1272                 ctxt_desc_req = 1;
1273
1274         if (unlikely(skb_vlan_tag_present(skb) ||
1275                      ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1276                       tqueue->hwts_tx_en)))
1277                 ctxt_desc_req = 1;
1278
1279         /* get the spinlock */
1280         spin_lock(&tqueue->tx_lock);
1281
1282         if (priv->tx_path_in_lpi_mode)
1283                 sxgbe_disable_eee_mode(priv);
1284
1285         if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) < nr_frags + 1)) {
1286                 if (!netif_tx_queue_stopped(dev_txq)) {
1287                         netif_tx_stop_queue(dev_txq);
1288                         netdev_err(dev, "%s: Tx Ring is full when %d queue is awake\n",
1289                                    __func__, txq_index);
1290                 }
1291                 /* release the spin lock in case of BUSY */
1292                 spin_unlock(&tqueue->tx_lock);
1293                 return NETDEV_TX_BUSY;
1294         }
1295
1296         entry = tqueue->cur_tx % tx_rsize;
1297         tx_desc = tqueue->dma_tx + entry;
1298
1299         first_desc = tx_desc;
1300         if (ctxt_desc_req)
1301                 ctxt_desc = (struct sxgbe_tx_ctxt_desc *)first_desc;
1302
1303         /* save the skb address */
1304         tqueue->tx_skbuff[entry] = skb;
1305
1306         if (!is_jumbo) {
1307                 if (likely(skb_is_gso(skb))) {
1308                         /* TSO support */
1309                         if (unlikely(tqueue->prev_mss != cur_mss)) {
1310                                 priv->hw->desc->tx_ctxt_desc_set_mss(
1311                                                 ctxt_desc, cur_mss);
1312                                 priv->hw->desc->tx_ctxt_desc_set_tcmssv(
1313                                                 ctxt_desc);
1314                                 priv->hw->desc->tx_ctxt_desc_reset_ostc(
1315                                                 ctxt_desc);
1316                                 priv->hw->desc->tx_ctxt_desc_set_ctxt(
1317                                                 ctxt_desc);
1318                                 priv->hw->desc->tx_ctxt_desc_set_owner(
1319                                                 ctxt_desc);
1320
1321                                 entry = (++tqueue->cur_tx) % tx_rsize;
1322                                 first_desc = tqueue->dma_tx + entry;
1323
1324                                 tqueue->prev_mss = cur_mss;
1325                         }
1326                         sxgbe_tso_prepare(priv, first_desc, skb);
1327                 } else {
1328                         tx_desc->tdes01 = dma_map_single(priv->device,
1329                                                          skb->data, no_pagedlen, DMA_TO_DEVICE);
1330                         if (dma_mapping_error(priv->device, tx_desc->tdes01))
1331                                 netdev_err(dev, "%s: TX dma mapping failed!!\n",
1332                                            __func__);
1333
1334                         priv->hw->desc->prepare_tx_desc(tx_desc, 1, no_pagedlen,
1335                                                         no_pagedlen, cksum_flag);
1336                 }
1337         }
1338
1339         for (frag_num = 0; frag_num < nr_frags; frag_num++) {
1340                 const skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_num];
1341                 int len = skb_frag_size(frag);
1342
1343                 entry = (++tqueue->cur_tx) % tx_rsize;
1344                 tx_desc = tqueue->dma_tx + entry;
1345                 tx_desc->tdes01 = skb_frag_dma_map(priv->device, frag, 0, len,
1346                                                    DMA_TO_DEVICE);
1347
1348                 tqueue->tx_skbuff_dma[entry] = tx_desc->tdes01;
1349                 tqueue->tx_skbuff[entry] = NULL;
1350
1351                 /* prepare the descriptor */
1352                 priv->hw->desc->prepare_tx_desc(tx_desc, 0, len,
1353                                                 len, cksum_flag);
1354                 /* memory barrier to flush descriptor */
1355                 wmb();
1356
1357                 /* set the owner */
1358                 priv->hw->desc->set_tx_owner(tx_desc);
1359         }
1360
1361         /* close the descriptors */
1362         priv->hw->desc->close_tx_desc(tx_desc);
1363
1364         /* memory barrier to flush descriptor */
1365         wmb();
1366
1367         tqueue->tx_count_frames += nr_frags + 1;
1368         if (tqueue->tx_count_frames > tqueue->tx_coal_frames) {
1369                 priv->hw->desc->clear_tx_ic(tx_desc);
1370                 priv->xstats.tx_reset_ic_bit++;
1371                 mod_timer(&tqueue->txtimer,
1372                           SXGBE_COAL_TIMER(tqueue->tx_coal_timer));
1373         } else {
1374                 tqueue->tx_count_frames = 0;
1375         }
1376
1377         /* set owner for first desc */
1378         priv->hw->desc->set_tx_owner(first_desc);
1379
1380         /* memory barrier to flush descriptor */
1381         wmb();
1382
1383         tqueue->cur_tx++;
1384
1385         /* display current ring */
1386         netif_dbg(priv, pktdata, dev, "%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d\n",
1387                   __func__, tqueue->cur_tx % tx_rsize,
1388                   tqueue->dirty_tx % tx_rsize, entry,
1389                   first_desc, nr_frags);
1390
1391         if (unlikely(sxgbe_tx_avail(tqueue, tx_rsize) <= (MAX_SKB_FRAGS + 1))) {
1392                 netif_dbg(priv, hw, dev, "%s: stop transmitted packets\n",
1393                           __func__);
1394                 netif_tx_stop_queue(dev_txq);
1395         }
1396
1397         dev->stats.tx_bytes += skb->len;
1398
1399         if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1400                      tqueue->hwts_tx_en)) {
1401                 /* declare that device is doing timestamping */
1402                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1403                 priv->hw->desc->tx_enable_tstamp(first_desc);
1404         }
1405
1406         if (!tqueue->hwts_tx_en)
1407                 skb_tx_timestamp(skb);
1408
1409         priv->hw->dma->enable_dma_transmission(priv->ioaddr, txq_index);
1410
1411         spin_unlock(&tqueue->tx_lock);
1412
1413         return NETDEV_TX_OK;
1414 }
1415
1416 /**
1417  * sxgbe_rx_refill: refill used skb preallocated buffers
1418  * @priv: driver private structure
1419  * Description : this is to reallocate the skb for the reception process
1420  * that is based on zero-copy.
1421  */
1422 static void sxgbe_rx_refill(struct sxgbe_priv_data *priv)
1423 {
1424         unsigned int rxsize = priv->dma_rx_size;
1425         int bfsize = priv->dma_buf_sz;
1426         u8 qnum = priv->cur_rx_qnum;
1427
1428         for (; priv->rxq[qnum]->cur_rx - priv->rxq[qnum]->dirty_rx > 0;
1429              priv->rxq[qnum]->dirty_rx++) {
1430                 unsigned int entry = priv->rxq[qnum]->dirty_rx % rxsize;
1431                 struct sxgbe_rx_norm_desc *p;
1432
1433                 p = priv->rxq[qnum]->dma_rx + entry;
1434
1435                 if (likely(priv->rxq[qnum]->rx_skbuff[entry] == NULL)) {
1436                         struct sk_buff *skb;
1437
1438                         skb = netdev_alloc_skb_ip_align(priv->dev, bfsize);
1439
1440                         if (unlikely(skb == NULL))
1441                                 break;
1442
1443                         priv->rxq[qnum]->rx_skbuff[entry] = skb;
1444                         priv->rxq[qnum]->rx_skbuff_dma[entry] =
1445                                 dma_map_single(priv->device, skb->data, bfsize,
1446                                                DMA_FROM_DEVICE);
1447
1448                         p->rdes23.rx_rd_des23.buf2_addr =
1449                                 priv->rxq[qnum]->rx_skbuff_dma[entry];
1450                 }
1451
1452                 /* Added memory barrier for RX descriptor modification */
1453                 wmb();
1454                 priv->hw->desc->set_rx_owner(p);
1455                 priv->hw->desc->set_rx_int_on_com(p);
1456                 /* Added memory barrier for RX descriptor modification */
1457                 wmb();
1458         }
1459 }
1460
1461 /**
1462  * sxgbe_rx: receive the frames from the remote host
1463  * @priv: driver private structure
1464  * @limit: napi bugget.
1465  * Description :  this the function called by the napi poll method.
1466  * It gets all the frames inside the ring.
1467  */
1468 static int sxgbe_rx(struct sxgbe_priv_data *priv, int limit)
1469 {
1470         u8 qnum = priv->cur_rx_qnum;
1471         unsigned int rxsize = priv->dma_rx_size;
1472         unsigned int entry = priv->rxq[qnum]->cur_rx;
1473         unsigned int next_entry = 0;
1474         unsigned int count = 0;
1475         int checksum;
1476         int status;
1477
1478         while (count < limit) {
1479                 struct sxgbe_rx_norm_desc *p;
1480                 struct sk_buff *skb;
1481                 int frame_len;
1482
1483                 p = priv->rxq[qnum]->dma_rx + entry;
1484
1485                 if (priv->hw->desc->get_rx_owner(p))
1486                         break;
1487
1488                 count++;
1489
1490                 next_entry = (++priv->rxq[qnum]->cur_rx) % rxsize;
1491                 prefetch(priv->rxq[qnum]->dma_rx + next_entry);
1492
1493                 /* Read the status of the incoming frame and also get checksum
1494                  * value based on whether it is enabled in SXGBE hardware or
1495                  * not.
1496                  */
1497                 status = priv->hw->desc->rx_wbstatus(p, &priv->xstats,
1498                                                      &checksum);
1499                 if (unlikely(status < 0)) {
1500                         entry = next_entry;
1501                         continue;
1502                 }
1503                 if (unlikely(!priv->rxcsum_insertion))
1504                         checksum = CHECKSUM_NONE;
1505
1506                 skb = priv->rxq[qnum]->rx_skbuff[entry];
1507
1508                 if (unlikely(!skb))
1509                         netdev_err(priv->dev, "rx descriptor is not consistent\n");
1510
1511                 prefetch(skb->data - NET_IP_ALIGN);
1512                 priv->rxq[qnum]->rx_skbuff[entry] = NULL;
1513
1514                 frame_len = priv->hw->desc->get_rx_frame_len(p);
1515
1516                 skb_put(skb, frame_len);
1517
1518                 skb->ip_summed = checksum;
1519                 if (checksum == CHECKSUM_NONE)
1520                         netif_receive_skb(skb);
1521                 else
1522                         napi_gro_receive(&priv->napi, skb);
1523
1524                 entry = next_entry;
1525         }
1526
1527         sxgbe_rx_refill(priv);
1528
1529         return count;
1530 }
1531
1532 /**
1533  *  sxgbe_poll - sxgbe poll method (NAPI)
1534  *  @napi : pointer to the napi structure.
1535  *  @budget : maximum number of packets that the current CPU can receive from
1536  *            all interfaces.
1537  *  Description :
1538  *  To look at the incoming frames and clear the tx resources.
1539  */
1540 static int sxgbe_poll(struct napi_struct *napi, int budget)
1541 {
1542         struct sxgbe_priv_data *priv = container_of(napi,
1543                                                     struct sxgbe_priv_data, napi);
1544         int work_done = 0;
1545         u8 qnum = priv->cur_rx_qnum;
1546
1547         priv->xstats.napi_poll++;
1548         /* first, clean the tx queues */
1549         sxgbe_tx_all_clean(priv);
1550
1551         work_done = sxgbe_rx(priv, budget);
1552         if (work_done < budget) {
1553                 napi_complete(napi);
1554                 priv->hw->dma->enable_dma_irq(priv->ioaddr, qnum);
1555         }
1556
1557         return work_done;
1558 }
1559
1560 /**
1561  *  sxgbe_tx_timeout
1562  *  @dev : Pointer to net device structure
1563  *  Description: this function is called when a packet transmission fails to
1564  *   complete within a reasonable time. The driver will mark the error in the
1565  *   netdev structure and arrange for the device to be reset to a sane state
1566  *   in order to transmit a new packet.
1567  */
1568 static void sxgbe_tx_timeout(struct net_device *dev)
1569 {
1570         struct sxgbe_priv_data *priv = netdev_priv(dev);
1571
1572         sxgbe_reset_all_tx_queues(priv);
1573 }
1574
1575 /**
1576  *  sxgbe_common_interrupt - main ISR
1577  *  @irq: interrupt number.
1578  *  @dev_id: to pass the net device pointer.
1579  *  Description: this is the main driver interrupt service routine.
1580  *  It calls the DMA ISR and also the core ISR to manage PMT, MMC, LPI
1581  *  interrupts.
1582  */
1583 static irqreturn_t sxgbe_common_interrupt(int irq, void *dev_id)
1584 {
1585         struct net_device *netdev = (struct net_device *)dev_id;
1586         struct sxgbe_priv_data *priv = netdev_priv(netdev);
1587         int status;
1588
1589         status = priv->hw->mac->host_irq_status(priv->ioaddr, &priv->xstats);
1590         /* For LPI we need to save the tx status */
1591         if (status & TX_ENTRY_LPI_MODE) {
1592                 priv->xstats.tx_lpi_entry_n++;
1593                 priv->tx_path_in_lpi_mode = true;
1594         }
1595         if (status & TX_EXIT_LPI_MODE) {
1596                 priv->xstats.tx_lpi_exit_n++;
1597                 priv->tx_path_in_lpi_mode = false;
1598         }
1599         if (status & RX_ENTRY_LPI_MODE)
1600                 priv->xstats.rx_lpi_entry_n++;
1601         if (status & RX_EXIT_LPI_MODE)
1602                 priv->xstats.rx_lpi_exit_n++;
1603
1604         return IRQ_HANDLED;
1605 }
1606
1607 /**
1608  *  sxgbe_tx_interrupt - TX DMA ISR
1609  *  @irq: interrupt number.
1610  *  @dev_id: to pass the net device pointer.
1611  *  Description: this is the tx dma interrupt service routine.
1612  */
1613 static irqreturn_t sxgbe_tx_interrupt(int irq, void *dev_id)
1614 {
1615         int status;
1616         struct sxgbe_tx_queue *txq = (struct sxgbe_tx_queue *)dev_id;
1617         struct sxgbe_priv_data *priv = txq->priv_ptr;
1618
1619         /* get the channel status */
1620         status = priv->hw->dma->tx_dma_int_status(priv->ioaddr, txq->queue_no,
1621                                                   &priv->xstats);
1622         /* check for normal path */
1623         if (likely((status & handle_tx)))
1624                 napi_schedule(&priv->napi);
1625
1626         /* check for unrecoverable error */
1627         if (unlikely((status & tx_hard_error)))
1628                 sxgbe_restart_tx_queue(priv, txq->queue_no);
1629
1630         /* check for TC configuration change */
1631         if (unlikely((status & tx_bump_tc) &&
1632                      (priv->tx_tc != SXGBE_MTL_SFMODE) &&
1633                      (priv->tx_tc < 512))) {
1634                 /* step of TX TC is 32 till 128, otherwise 64 */
1635                 priv->tx_tc += (priv->tx_tc < 128) ? 32 : 64;
1636                 priv->hw->mtl->set_tx_mtl_mode(priv->ioaddr,
1637                                                txq->queue_no, priv->tx_tc);
1638                 priv->xstats.tx_threshold = priv->tx_tc;
1639         }
1640
1641         return IRQ_HANDLED;
1642 }
1643
1644 /**
1645  *  sxgbe_rx_interrupt - RX DMA ISR
1646  *  @irq: interrupt number.
1647  *  @dev_id: to pass the net device pointer.
1648  *  Description: this is the rx dma interrupt service routine.
1649  */
1650 static irqreturn_t sxgbe_rx_interrupt(int irq, void *dev_id)
1651 {
1652         int status;
1653         struct sxgbe_rx_queue *rxq = (struct sxgbe_rx_queue *)dev_id;
1654         struct sxgbe_priv_data *priv = rxq->priv_ptr;
1655
1656         /* get the channel status */
1657         status = priv->hw->dma->rx_dma_int_status(priv->ioaddr, rxq->queue_no,
1658                                                   &priv->xstats);
1659
1660         if (likely((status & handle_rx) && (napi_schedule_prep(&priv->napi)))) {
1661                 priv->hw->dma->disable_dma_irq(priv->ioaddr, rxq->queue_no);
1662                 __napi_schedule(&priv->napi);
1663         }
1664
1665         /* check for TC configuration change */
1666         if (unlikely((status & rx_bump_tc) &&
1667                      (priv->rx_tc != SXGBE_MTL_SFMODE) &&
1668                      (priv->rx_tc < 128))) {
1669                 /* step of TC is 32 */
1670                 priv->rx_tc += 32;
1671                 priv->hw->mtl->set_rx_mtl_mode(priv->ioaddr,
1672                                                rxq->queue_no, priv->rx_tc);
1673                 priv->xstats.rx_threshold = priv->rx_tc;
1674         }
1675
1676         return IRQ_HANDLED;
1677 }
1678
1679 static inline u64 sxgbe_get_stat64(void __iomem *ioaddr, int reg_lo, int reg_hi)
1680 {
1681         u64 val = readl(ioaddr + reg_lo);
1682
1683         val |= ((u64)readl(ioaddr + reg_hi)) << 32;
1684
1685         return val;
1686 }
1687
1688
1689 /*  sxgbe_get_stats64 - entry point to see statistical information of device
1690  *  @dev : device pointer.
1691  *  @stats : pointer to hold all the statistical information of device.
1692  *  Description:
1693  *  This function is a driver entry point whenever ifconfig command gets
1694  *  executed to see device statistics. Statistics are number of
1695  *  bytes sent or received, errors occured etc.
1696  *  Return value:
1697  *  This function returns various statistical information of device.
1698  */
1699 static struct rtnl_link_stats64 *sxgbe_get_stats64(struct net_device *dev,
1700                                                    struct rtnl_link_stats64 *stats)
1701 {
1702         struct sxgbe_priv_data *priv = netdev_priv(dev);
1703         void __iomem *ioaddr = priv->ioaddr;
1704         u64 count;
1705
1706         spin_lock(&priv->stats_lock);
1707         /* Freeze the counter registers before reading value otherwise it may
1708          * get updated by hardware while we are reading them
1709          */
1710         writel(SXGBE_MMC_CTRL_CNT_FRZ, ioaddr + SXGBE_MMC_CTL_REG);
1711
1712         stats->rx_bytes = sxgbe_get_stat64(ioaddr,
1713                                            SXGBE_MMC_RXOCTETLO_GCNT_REG,
1714                                            SXGBE_MMC_RXOCTETHI_GCNT_REG);
1715
1716         stats->rx_packets = sxgbe_get_stat64(ioaddr,
1717                                              SXGBE_MMC_RXFRAMELO_GBCNT_REG,
1718                                              SXGBE_MMC_RXFRAMEHI_GBCNT_REG);
1719
1720         stats->multicast = sxgbe_get_stat64(ioaddr,
1721                                             SXGBE_MMC_RXMULTILO_GCNT_REG,
1722                                             SXGBE_MMC_RXMULTIHI_GCNT_REG);
1723
1724         stats->rx_crc_errors = sxgbe_get_stat64(ioaddr,
1725                                                 SXGBE_MMC_RXCRCERRLO_REG,
1726                                                 SXGBE_MMC_RXCRCERRHI_REG);
1727
1728         stats->rx_length_errors = sxgbe_get_stat64(ioaddr,
1729                                                   SXGBE_MMC_RXLENERRLO_REG,
1730                                                   SXGBE_MMC_RXLENERRHI_REG);
1731
1732         stats->rx_missed_errors = sxgbe_get_stat64(ioaddr,
1733                                                    SXGBE_MMC_RXFIFOOVERFLOWLO_GBCNT_REG,
1734                                                    SXGBE_MMC_RXFIFOOVERFLOWHI_GBCNT_REG);
1735
1736         stats->tx_bytes = sxgbe_get_stat64(ioaddr,
1737                                            SXGBE_MMC_TXOCTETLO_GCNT_REG,
1738                                            SXGBE_MMC_TXOCTETHI_GCNT_REG);
1739
1740         count = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GBCNT_REG,
1741                                  SXGBE_MMC_TXFRAMEHI_GBCNT_REG);
1742
1743         stats->tx_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXFRAMELO_GCNT_REG,
1744                                             SXGBE_MMC_TXFRAMEHI_GCNT_REG);
1745         stats->tx_errors = count - stats->tx_errors;
1746         stats->tx_packets = count;
1747         stats->tx_fifo_errors = sxgbe_get_stat64(ioaddr, SXGBE_MMC_TXUFLWLO_GBCNT_REG,
1748                                                  SXGBE_MMC_TXUFLWHI_GBCNT_REG);
1749         writel(0, ioaddr + SXGBE_MMC_CTL_REG);
1750         spin_unlock(&priv->stats_lock);
1751
1752         return stats;
1753 }
1754
1755 /*  sxgbe_set_features - entry point to set offload features of the device.
1756  *  @dev : device pointer.
1757  *  @features : features which are required to be set.
1758  *  Description:
1759  *  This function is a driver entry point and called by Linux kernel whenever
1760  *  any device features are set or reset by user.
1761  *  Return value:
1762  *  This function returns 0 after setting or resetting device features.
1763  */
1764 static int sxgbe_set_features(struct net_device *dev,
1765                               netdev_features_t features)
1766 {
1767         struct sxgbe_priv_data *priv = netdev_priv(dev);
1768         netdev_features_t changed = dev->features ^ features;
1769
1770         if (changed & NETIF_F_RXCSUM) {
1771                 if (features & NETIF_F_RXCSUM) {
1772                         priv->hw->mac->enable_rx_csum(priv->ioaddr);
1773                         priv->rxcsum_insertion = true;
1774                 } else {
1775                         priv->hw->mac->disable_rx_csum(priv->ioaddr);
1776                         priv->rxcsum_insertion = false;
1777                 }
1778         }
1779
1780         return 0;
1781 }
1782
1783 /*  sxgbe_change_mtu - entry point to change MTU size for the device.
1784  *  @dev : device pointer.
1785  *  @new_mtu : the new MTU size for the device.
1786  *  Description: the Maximum Transfer Unit (MTU) is used by the network layer
1787  *  to drive packet transmission. Ethernet has an MTU of 1500 octets
1788  *  (ETH_DATA_LEN). This value can be changed with ifconfig.
1789  *  Return value:
1790  *  0 on success and an appropriate (-)ve integer as defined in errno.h
1791  *  file on failure.
1792  */
1793 static int sxgbe_change_mtu(struct net_device *dev, int new_mtu)
1794 {
1795         /* RFC 791, page 25, "Every internet module must be able to forward
1796          * a datagram of 68 octets without further fragmentation."
1797          */
1798         if (new_mtu < MIN_MTU || (new_mtu > MAX_MTU)) {
1799                 netdev_err(dev, "invalid MTU, MTU should be in between %d and %d\n",
1800                            MIN_MTU, MAX_MTU);
1801                 return -EINVAL;
1802         }
1803
1804         /* Return if the buffer sizes will not change */
1805         if (dev->mtu == new_mtu)
1806                 return 0;
1807
1808         dev->mtu = new_mtu;
1809
1810         if (!netif_running(dev))
1811                 return 0;
1812
1813         /* Recevice ring buffer size is needed to be set based on MTU. If MTU is
1814          * changed then reinitilisation of the receive ring buffers need to be
1815          * done. Hence bring interface down and bring interface back up
1816          */
1817         sxgbe_release(dev);
1818         return sxgbe_open(dev);
1819 }
1820
1821 static void sxgbe_set_umac_addr(void __iomem *ioaddr, unsigned char *addr,
1822                                 unsigned int reg_n)
1823 {
1824         unsigned long data;
1825
1826         data = (addr[5] << 8) | addr[4];
1827         /* For MAC Addr registers se have to set the Address Enable (AE)
1828          * bit that has no effect on the High Reg 0 where the bit 31 (MO)
1829          * is RO.
1830          */
1831         writel(data | SXGBE_HI_REG_AE, ioaddr + SXGBE_ADDR_HIGH(reg_n));
1832         data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
1833         writel(data, ioaddr + SXGBE_ADDR_LOW(reg_n));
1834 }
1835
1836 /**
1837  * sxgbe_set_rx_mode - entry point for setting different receive mode of
1838  * a device. unicast, multicast addressing
1839  * @dev : pointer to the device structure
1840  * Description:
1841  * This function is a driver entry point which gets called by the kernel
1842  * whenever different receive mode like unicast, multicast and promiscuous
1843  * must be enabled/disabled.
1844  * Return value:
1845  * void.
1846  */
1847 static void sxgbe_set_rx_mode(struct net_device *dev)
1848 {
1849         struct sxgbe_priv_data *priv = netdev_priv(dev);
1850         void __iomem *ioaddr = (void __iomem *)priv->ioaddr;
1851         unsigned int value = 0;
1852         u32 mc_filter[2];
1853         struct netdev_hw_addr *ha;
1854         int reg = 1;
1855
1856         netdev_dbg(dev, "%s: # mcasts %d, # unicast %d\n",
1857                    __func__, netdev_mc_count(dev), netdev_uc_count(dev));
1858
1859         if (dev->flags & IFF_PROMISC) {
1860                 value = SXGBE_FRAME_FILTER_PR;
1861
1862         } else if ((netdev_mc_count(dev) > SXGBE_HASH_TABLE_SIZE) ||
1863                    (dev->flags & IFF_ALLMULTI)) {
1864                 value = SXGBE_FRAME_FILTER_PM;  /* pass all multi */
1865                 writel(0xffffffff, ioaddr + SXGBE_HASH_HIGH);
1866                 writel(0xffffffff, ioaddr + SXGBE_HASH_LOW);
1867
1868         } else if (!netdev_mc_empty(dev)) {
1869                 /* Hash filter for multicast */
1870                 value = SXGBE_FRAME_FILTER_HMC;
1871
1872                 memset(mc_filter, 0, sizeof(mc_filter));
1873                 netdev_for_each_mc_addr(ha, dev) {
1874                         /* The upper 6 bits of the calculated CRC are used to
1875                          * index the contens of the hash table
1876                          */
1877                         int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
1878
1879                         /* The most significant bit determines the register to
1880                          * use (H/L) while the other 5 bits determine the bit
1881                          * within the register.
1882                          */
1883                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1884                 }
1885                 writel(mc_filter[0], ioaddr + SXGBE_HASH_LOW);
1886                 writel(mc_filter[1], ioaddr + SXGBE_HASH_HIGH);
1887         }
1888
1889         /* Handle multiple unicast addresses (perfect filtering) */
1890         if (netdev_uc_count(dev) > SXGBE_MAX_PERFECT_ADDRESSES)
1891                 /* Switch to promiscuous mode if more than 16 addrs
1892                  * are required
1893                  */
1894                 value |= SXGBE_FRAME_FILTER_PR;
1895         else {
1896                 netdev_for_each_uc_addr(ha, dev) {
1897                         sxgbe_set_umac_addr(ioaddr, ha->addr, reg);
1898                         reg++;
1899                 }
1900         }
1901 #ifdef FRAME_FILTER_DEBUG
1902         /* Enable Receive all mode (to debug filtering_fail errors) */
1903         value |= SXGBE_FRAME_FILTER_RA;
1904 #endif
1905         writel(value, ioaddr + SXGBE_FRAME_FILTER);
1906
1907         netdev_dbg(dev, "Filter: 0x%08x\n\tHash: HI 0x%08x, LO 0x%08x\n",
1908                    readl(ioaddr + SXGBE_FRAME_FILTER),
1909                    readl(ioaddr + SXGBE_HASH_HIGH),
1910                    readl(ioaddr + SXGBE_HASH_LOW));
1911 }
1912
1913 #ifdef CONFIG_NET_POLL_CONTROLLER
1914 /**
1915  * sxgbe_poll_controller - entry point for polling receive by device
1916  * @dev : pointer to the device structure
1917  * Description:
1918  * This function is used by NETCONSOLE and other diagnostic tools
1919  * to allow network I/O with interrupts disabled.
1920  * Return value:
1921  * Void.
1922  */
1923 static void sxgbe_poll_controller(struct net_device *dev)
1924 {
1925         struct sxgbe_priv_data *priv = netdev_priv(dev);
1926
1927         disable_irq(priv->irq);
1928         sxgbe_rx_interrupt(priv->irq, dev);
1929         enable_irq(priv->irq);
1930 }
1931 #endif
1932
1933 /*  sxgbe_ioctl - Entry point for the Ioctl
1934  *  @dev: Device pointer.
1935  *  @rq: An IOCTL specefic structure, that can contain a pointer to
1936  *  a proprietary structure used to pass information to the driver.
1937  *  @cmd: IOCTL command
1938  *  Description:
1939  *  Currently it supports the phy_mii_ioctl(...) and HW time stamping.
1940  */
1941 static int sxgbe_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1942 {
1943         struct sxgbe_priv_data *priv = netdev_priv(dev);
1944         int ret = -EOPNOTSUPP;
1945
1946         if (!netif_running(dev))
1947                 return -EINVAL;
1948
1949         switch (cmd) {
1950         case SIOCGMIIPHY:
1951         case SIOCGMIIREG:
1952         case SIOCSMIIREG:
1953                 if (!priv->phydev)
1954                         return -EINVAL;
1955                 ret = phy_mii_ioctl(priv->phydev, rq, cmd);
1956                 break;
1957         default:
1958                 break;
1959         }
1960
1961         return ret;
1962 }
1963
1964 static const struct net_device_ops sxgbe_netdev_ops = {
1965         .ndo_open               = sxgbe_open,
1966         .ndo_start_xmit         = sxgbe_xmit,
1967         .ndo_stop               = sxgbe_release,
1968         .ndo_get_stats64        = sxgbe_get_stats64,
1969         .ndo_change_mtu         = sxgbe_change_mtu,
1970         .ndo_set_features       = sxgbe_set_features,
1971         .ndo_set_rx_mode        = sxgbe_set_rx_mode,
1972         .ndo_tx_timeout         = sxgbe_tx_timeout,
1973         .ndo_do_ioctl           = sxgbe_ioctl,
1974 #ifdef CONFIG_NET_POLL_CONTROLLER
1975         .ndo_poll_controller    = sxgbe_poll_controller,
1976 #endif
1977         .ndo_set_mac_address    = eth_mac_addr,
1978 };
1979
1980 /* Get the hardware ops */
1981 static void sxgbe_get_ops(struct sxgbe_ops * const ops_ptr)
1982 {
1983         ops_ptr->mac            = sxgbe_get_core_ops();
1984         ops_ptr->desc           = sxgbe_get_desc_ops();
1985         ops_ptr->dma            = sxgbe_get_dma_ops();
1986         ops_ptr->mtl            = sxgbe_get_mtl_ops();
1987
1988         /* set the MDIO communication Address/Data regisers */
1989         ops_ptr->mii.addr       = SXGBE_MDIO_SCMD_ADD_REG;
1990         ops_ptr->mii.data       = SXGBE_MDIO_SCMD_DATA_REG;
1991
1992         /* Assigning the default link settings
1993          * no SXGBE defined default values to be set in registers,
1994          * so assigning as 0 for port and duplex
1995          */
1996         ops_ptr->link.port      = 0;
1997         ops_ptr->link.duplex    = 0;
1998         ops_ptr->link.speed     = SXGBE_SPEED_10G;
1999 }
2000
2001 /**
2002  *  sxgbe_hw_init - Init the GMAC device
2003  *  @priv: driver private structure
2004  *  Description: this function checks the HW capability
2005  *  (if supported) and sets the driver's features.
2006  */
2007 static int sxgbe_hw_init(struct sxgbe_priv_data * const priv)
2008 {
2009         u32 ctrl_ids;
2010
2011         priv->hw = kmalloc(sizeof(*priv->hw), GFP_KERNEL);
2012         if(!priv->hw)
2013                 return -ENOMEM;
2014
2015         /* get the hardware ops */
2016         sxgbe_get_ops(priv->hw);
2017
2018         /* get the controller id */
2019         ctrl_ids = priv->hw->mac->get_controller_version(priv->ioaddr);
2020         priv->hw->ctrl_uid = (ctrl_ids & 0x00ff0000) >> 16;
2021         priv->hw->ctrl_id = (ctrl_ids & 0x000000ff);
2022         pr_info("user ID: 0x%x, Controller ID: 0x%x\n",
2023                 priv->hw->ctrl_uid, priv->hw->ctrl_id);
2024
2025         /* get the H/W features */
2026         if (!sxgbe_get_hw_features(priv))
2027                 pr_info("Hardware features not found\n");
2028
2029         if (priv->hw_cap.tx_csum_offload)
2030                 pr_info("TX Checksum offload supported\n");
2031
2032         if (priv->hw_cap.rx_csum_offload)
2033                 pr_info("RX Checksum offload supported\n");
2034
2035         return 0;
2036 }
2037
2038 static int sxgbe_sw_reset(void __iomem *addr)
2039 {
2040         int retry_count = 10;
2041
2042         writel(SXGBE_DMA_SOFT_RESET, addr + SXGBE_DMA_MODE_REG);
2043         while (retry_count--) {
2044                 if (!(readl(addr + SXGBE_DMA_MODE_REG) &
2045                       SXGBE_DMA_SOFT_RESET))
2046                         break;
2047                 mdelay(10);
2048         }
2049
2050         if (retry_count < 0)
2051                 return -EBUSY;
2052
2053         return 0;
2054 }
2055
2056 /**
2057  * sxgbe_drv_probe
2058  * @device: device pointer
2059  * @plat_dat: platform data pointer
2060  * @addr: iobase memory address
2061  * Description: this is the main probe function used to
2062  * call the alloc_etherdev, allocate the priv structure.
2063  */
2064 struct sxgbe_priv_data *sxgbe_drv_probe(struct device *device,
2065                                         struct sxgbe_plat_data *plat_dat,
2066                                         void __iomem *addr)
2067 {
2068         struct sxgbe_priv_data *priv;
2069         struct net_device *ndev;
2070         int ret;
2071         u8 queue_num;
2072
2073         ndev = alloc_etherdev_mqs(sizeof(struct sxgbe_priv_data),
2074                                   SXGBE_TX_QUEUES, SXGBE_RX_QUEUES);
2075         if (!ndev)
2076                 return NULL;
2077
2078         SET_NETDEV_DEV(ndev, device);
2079
2080         priv = netdev_priv(ndev);
2081         priv->device = device;
2082         priv->dev = ndev;
2083
2084         sxgbe_set_ethtool_ops(ndev);
2085         priv->plat = plat_dat;
2086         priv->ioaddr = addr;
2087
2088         ret = sxgbe_sw_reset(priv->ioaddr);
2089         if (ret)
2090                 goto error_free_netdev;
2091
2092         /* Verify driver arguments */
2093         sxgbe_verify_args();
2094
2095         /* Init MAC and get the capabilities */
2096         ret = sxgbe_hw_init(priv);
2097         if (ret)
2098                 goto error_free_netdev;
2099
2100         /* allocate memory resources for Descriptor rings */
2101         ret = txring_mem_alloc(priv);
2102         if (ret)
2103                 goto error_free_hw;
2104
2105         ret = rxring_mem_alloc(priv);
2106         if (ret)
2107                 goto error_free_hw;
2108
2109         ndev->netdev_ops = &sxgbe_netdev_ops;
2110
2111         ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2112                 NETIF_F_RXCSUM | NETIF_F_TSO | NETIF_F_TSO6 |
2113                 NETIF_F_GRO;
2114         ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA;
2115         ndev->watchdog_timeo = msecs_to_jiffies(TX_TIMEO);
2116
2117         /* assign filtering support */
2118         ndev->priv_flags |= IFF_UNICAST_FLT;
2119
2120         priv->msg_enable = netif_msg_init(debug, default_msg_level);
2121
2122         /* Enable TCP segmentation offload for all DMA channels */
2123         if (priv->hw_cap.tcpseg_offload) {
2124                 SXGBE_FOR_EACH_QUEUE(SXGBE_TX_QUEUES, queue_num) {
2125                         priv->hw->dma->enable_tso(priv->ioaddr, queue_num);
2126                 }
2127         }
2128
2129         /* Enable Rx checksum offload */
2130         if (priv->hw_cap.rx_csum_offload) {
2131                 priv->hw->mac->enable_rx_csum(priv->ioaddr);
2132                 priv->rxcsum_insertion = true;
2133         }
2134
2135         /* Initialise pause frame settings */
2136         priv->rx_pause = 1;
2137         priv->tx_pause = 1;
2138
2139         /* Rx Watchdog is available, enable depend on platform data */
2140         if (!priv->plat->riwt_off) {
2141                 priv->use_riwt = 1;
2142                 pr_info("Enable RX Mitigation via HW Watchdog Timer\n");
2143         }
2144
2145         netif_napi_add(ndev, &priv->napi, sxgbe_poll, 64);
2146
2147         spin_lock_init(&priv->stats_lock);
2148
2149         priv->sxgbe_clk = clk_get(priv->device, SXGBE_RESOURCE_NAME);
2150         if (IS_ERR(priv->sxgbe_clk)) {
2151                 netdev_warn(ndev, "%s: warning: cannot get CSR clock\n",
2152                             __func__);
2153                 goto error_napi_del;
2154         }
2155
2156         /* If a specific clk_csr value is passed from the platform
2157          * this means that the CSR Clock Range selection cannot be
2158          * changed at run-time and it is fixed. Viceversa the driver'll try to
2159          * set the MDC clock dynamically according to the csr actual
2160          * clock input.
2161          */
2162         if (!priv->plat->clk_csr)
2163                 sxgbe_clk_csr_set(priv);
2164         else
2165                 priv->clk_csr = priv->plat->clk_csr;
2166
2167         /* MDIO bus Registration */
2168         ret = sxgbe_mdio_register(ndev);
2169         if (ret < 0) {
2170                 netdev_dbg(ndev, "%s: MDIO bus (id: %d) registration failed\n",
2171                            __func__, priv->plat->bus_id);
2172                 goto error_clk_put;
2173         }
2174
2175         ret = register_netdev(ndev);
2176         if (ret) {
2177                 pr_err("%s: ERROR %i registering the device\n", __func__, ret);
2178                 goto error_mdio_unregister;
2179         }
2180
2181         sxgbe_check_ether_addr(priv);
2182
2183         return priv;
2184
2185 error_mdio_unregister:
2186         sxgbe_mdio_unregister(ndev);
2187 error_clk_put:
2188         clk_put(priv->sxgbe_clk);
2189 error_napi_del:
2190         netif_napi_del(&priv->napi);
2191 error_free_hw:
2192         kfree(priv->hw);
2193 error_free_netdev:
2194         free_netdev(ndev);
2195
2196         return NULL;
2197 }
2198
2199 /**
2200  * sxgbe_drv_remove
2201  * @ndev: net device pointer
2202  * Description: this function resets the TX/RX processes, disables the MAC RX/TX
2203  * changes the link status, releases the DMA descriptor rings.
2204  */
2205 int sxgbe_drv_remove(struct net_device *ndev)
2206 {
2207         struct sxgbe_priv_data *priv = netdev_priv(ndev);
2208         u8 queue_num;
2209
2210         netdev_info(ndev, "%s: removing driver\n", __func__);
2211
2212         SXGBE_FOR_EACH_QUEUE(SXGBE_RX_QUEUES, queue_num) {
2213                 priv->hw->mac->disable_rxqueue(priv->ioaddr, queue_num);
2214         }
2215
2216         priv->hw->dma->stop_rx(priv->ioaddr, SXGBE_RX_QUEUES);
2217         priv->hw->dma->stop_tx(priv->ioaddr, SXGBE_TX_QUEUES);
2218
2219         priv->hw->mac->enable_tx(priv->ioaddr, false);
2220         priv->hw->mac->enable_rx(priv->ioaddr, false);
2221
2222         unregister_netdev(ndev);
2223
2224         sxgbe_mdio_unregister(ndev);
2225
2226         clk_put(priv->sxgbe_clk);
2227
2228         netif_napi_del(&priv->napi);
2229
2230         kfree(priv->hw);
2231
2232         free_netdev(ndev);
2233
2234         return 0;
2235 }
2236
2237 #ifdef CONFIG_PM
2238 int sxgbe_suspend(struct net_device *ndev)
2239 {
2240         return 0;
2241 }
2242
2243 int sxgbe_resume(struct net_device *ndev)
2244 {
2245         return 0;
2246 }
2247
2248 int sxgbe_freeze(struct net_device *ndev)
2249 {
2250         return -ENOSYS;
2251 }
2252
2253 int sxgbe_restore(struct net_device *ndev)
2254 {
2255         return -ENOSYS;
2256 }
2257 #endif /* CONFIG_PM */
2258
2259 /* Driver is configured as Platform driver */
2260 static int __init sxgbe_init(void)
2261 {
2262         int ret;
2263
2264         ret = sxgbe_register_platform();
2265         if (ret)
2266                 goto err;
2267         return 0;
2268 err:
2269         pr_err("driver registration failed\n");
2270         return ret;
2271 }
2272
2273 static void __exit sxgbe_exit(void)
2274 {
2275         sxgbe_unregister_platform();
2276 }
2277
2278 module_init(sxgbe_init);
2279 module_exit(sxgbe_exit);
2280
2281 #ifndef MODULE
2282 static int __init sxgbe_cmdline_opt(char *str)
2283 {
2284         char *opt;
2285
2286         if (!str || !*str)
2287                 return -EINVAL;
2288         while ((opt = strsep(&str, ",")) != NULL) {
2289                 if (!strncmp(opt, "eee_timer:", 6)) {
2290                         if (kstrtoint(opt + 10, 0, &eee_timer))
2291                                 goto err;
2292                 }
2293         }
2294         return 0;
2295
2296 err:
2297         pr_err("%s: ERROR broken module parameter conversion\n", __func__);
2298         return -EINVAL;
2299 }
2300
2301 __setup("sxgbeeth=", sxgbe_cmdline_opt);
2302 #endif /* MODULE */
2303
2304
2305
2306 MODULE_DESCRIPTION("SAMSUNG 10G/2.5G/1G Ethernet PLATFORM driver");
2307
2308 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)");
2309 MODULE_PARM_DESC(eee_timer, "EEE-LPI Default LS timer value");
2310
2311 MODULE_AUTHOR("Siva Reddy Kallam <siva.kallam@samsung.com>");
2312 MODULE_AUTHOR("ByungHo An <bh74.an@samsung.com>");
2313 MODULE_AUTHOR("Girish K S <ks.giri@samsung.com>");
2314 MODULE_AUTHOR("Vipul Pandya <vipul.pandya@samsung.com>");
2315
2316 MODULE_LICENSE("GPL");