1 /* SuperH Ethernet device driver
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2016 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
49 #define SH_ETH_DEF_MSG_ENABLE \
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
61 SH_ETH_OFFSET_DEFAULTS,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158 SH_ETH_OFFSET_DEFAULTS,
203 [TSU_CTRST] = 0x0004,
204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
207 [TSU_ADRH0] = 0x0100,
215 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
216 SH_ETH_OFFSET_DEFAULTS,
263 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
264 SH_ETH_OFFSET_DEFAULTS,
317 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
318 SH_ETH_OFFSET_DEFAULTS,
366 [TSU_CTRST] = 0x0004,
367 [TSU_FWEN0] = 0x0010,
368 [TSU_FWEN1] = 0x0014,
370 [TSU_BSYSL0] = 0x0020,
371 [TSU_BSYSL1] = 0x0024,
372 [TSU_PRISL0] = 0x0028,
373 [TSU_PRISL1] = 0x002c,
374 [TSU_FWSL0] = 0x0030,
375 [TSU_FWSL1] = 0x0034,
376 [TSU_FWSLC] = 0x0038,
377 [TSU_QTAGM0] = 0x0040,
378 [TSU_QTAGM1] = 0x0044,
379 [TSU_ADQT0] = 0x0048,
380 [TSU_ADQT1] = 0x004c,
382 [TSU_FWINMK] = 0x0054,
383 [TSU_ADSBSY] = 0x0060,
385 [TSU_POST1] = 0x0070,
386 [TSU_POST2] = 0x0074,
387 [TSU_POST3] = 0x0078,
388 [TSU_POST4] = 0x007c,
403 [TSU_ADRH0] = 0x0100,
406 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
407 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
411 struct sh_eth_private *mdp = netdev_priv(ndev);
412 u16 offset = mdp->reg_offset[enum_index];
414 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
417 iowrite32(data, mdp->addr + offset);
420 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
422 struct sh_eth_private *mdp = netdev_priv(ndev);
423 u16 offset = mdp->reg_offset[enum_index];
425 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
428 return ioread32(mdp->addr + offset);
431 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
434 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
438 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
440 return mdp->reg_offset == sh_eth_offset_gigabit;
443 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
445 return mdp->reg_offset == sh_eth_offset_fast_rz;
448 static void sh_eth_select_mii(struct net_device *ndev)
450 struct sh_eth_private *mdp = netdev_priv(ndev);
453 switch (mdp->phy_interface) {
454 case PHY_INTERFACE_MODE_GMII:
457 case PHY_INTERFACE_MODE_MII:
460 case PHY_INTERFACE_MODE_RMII:
465 "PHY interface mode was not setup. Set to MII.\n");
470 sh_eth_write(ndev, value, RMII_MII);
473 static void sh_eth_set_duplex(struct net_device *ndev)
475 struct sh_eth_private *mdp = netdev_priv(ndev);
477 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
480 static void sh_eth_chip_reset(struct net_device *ndev)
482 struct sh_eth_private *mdp = netdev_priv(ndev);
485 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
489 static void sh_eth_set_rate_gether(struct net_device *ndev)
491 struct sh_eth_private *mdp = netdev_priv(ndev);
493 switch (mdp->speed) {
494 case 10: /* 10BASE */
495 sh_eth_write(ndev, GECMR_10, GECMR);
497 case 100:/* 100BASE */
498 sh_eth_write(ndev, GECMR_100, GECMR);
500 case 1000: /* 1000BASE */
501 sh_eth_write(ndev, GECMR_1000, GECMR);
508 static struct sh_eth_cpu_data r7s72100_data = {
509 .chip_reset = sh_eth_chip_reset,
510 .set_duplex = sh_eth_set_duplex,
512 .register_type = SH_ETH_REG_FAST_RZ,
514 .ecsr_value = ECSR_ICD,
515 .ecsipr_value = ECSIPR_ICDIP,
516 .eesipr_value = 0xff7f009f,
518 .tx_check = EESR_TC1 | EESR_FTC,
519 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
520 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
522 .fdr_value = 0x0000070f,
530 .rpadir_value = 2 << 16,
538 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
540 struct sh_eth_private *mdp = netdev_priv(ndev);
543 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
546 sh_eth_select_mii(ndev);
550 static struct sh_eth_cpu_data r8a7740_data = {
551 .chip_reset = sh_eth_chip_reset_r8a7740,
552 .set_duplex = sh_eth_set_duplex,
553 .set_rate = sh_eth_set_rate_gether,
555 .register_type = SH_ETH_REG_GIGABIT,
557 .ecsr_value = ECSR_ICD | ECSR_MPD,
558 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
559 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
561 .tx_check = EESR_TC1 | EESR_FTC,
562 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
563 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
565 .fdr_value = 0x0000070f,
573 .rpadir_value = 2 << 16,
581 /* There is CPU dependent code */
582 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
584 struct sh_eth_private *mdp = netdev_priv(ndev);
586 switch (mdp->speed) {
587 case 10: /* 10BASE */
588 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
590 case 100:/* 100BASE */
591 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
597 static struct sh_eth_cpu_data r8a777x_data = {
598 .set_duplex = sh_eth_set_duplex,
599 .set_rate = sh_eth_set_rate_r8a777x,
601 .register_type = SH_ETH_REG_FAST_RCAR,
603 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
604 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
605 .eesipr_value = 0x01ff009f,
607 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
608 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
609 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
611 .fdr_value = 0x00000f0f,
620 static struct sh_eth_cpu_data r8a779x_data = {
621 .set_duplex = sh_eth_set_duplex,
622 .set_rate = sh_eth_set_rate_r8a777x,
624 .register_type = SH_ETH_REG_FAST_RCAR,
626 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
627 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
628 .eesipr_value = 0x01ff009f,
630 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
631 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
632 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
634 .fdr_value = 0x00000f0f,
636 .trscer_err_mask = DESC_I_RINT8,
644 #endif /* CONFIG_OF */
646 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
648 struct sh_eth_private *mdp = netdev_priv(ndev);
650 switch (mdp->speed) {
651 case 10: /* 10BASE */
652 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
654 case 100:/* 100BASE */
655 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
661 static struct sh_eth_cpu_data sh7724_data = {
662 .set_duplex = sh_eth_set_duplex,
663 .set_rate = sh_eth_set_rate_sh7724,
665 .register_type = SH_ETH_REG_FAST_SH4,
667 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
668 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
669 .eesipr_value = 0x01ff009f,
671 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
672 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
673 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
681 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
684 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
686 struct sh_eth_private *mdp = netdev_priv(ndev);
688 switch (mdp->speed) {
689 case 10: /* 10BASE */
690 sh_eth_write(ndev, 0, RTRATE);
692 case 100:/* 100BASE */
693 sh_eth_write(ndev, 1, RTRATE);
699 static struct sh_eth_cpu_data sh7757_data = {
700 .set_duplex = sh_eth_set_duplex,
701 .set_rate = sh_eth_set_rate_sh7757,
703 .register_type = SH_ETH_REG_FAST_SH4,
705 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
707 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
708 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
709 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
712 .irq_flags = IRQF_SHARED,
719 .rpadir_value = 2 << 16,
723 #define SH_GIGA_ETH_BASE 0xfee00000UL
724 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
725 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
726 static void sh_eth_chip_reset_giga(struct net_device *ndev)
729 u32 mahr[2], malr[2];
731 /* save MAHR and MALR */
732 for (i = 0; i < 2; i++) {
733 malr[i] = ioread32((void *)GIGA_MALR(i));
734 mahr[i] = ioread32((void *)GIGA_MAHR(i));
738 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
741 /* restore MAHR and MALR */
742 for (i = 0; i < 2; i++) {
743 iowrite32(malr[i], (void *)GIGA_MALR(i));
744 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
748 static void sh_eth_set_rate_giga(struct net_device *ndev)
750 struct sh_eth_private *mdp = netdev_priv(ndev);
752 switch (mdp->speed) {
753 case 10: /* 10BASE */
754 sh_eth_write(ndev, 0x00000000, GECMR);
756 case 100:/* 100BASE */
757 sh_eth_write(ndev, 0x00000010, GECMR);
759 case 1000: /* 1000BASE */
760 sh_eth_write(ndev, 0x00000020, GECMR);
765 /* SH7757(GETHERC) */
766 static struct sh_eth_cpu_data sh7757_data_giga = {
767 .chip_reset = sh_eth_chip_reset_giga,
768 .set_duplex = sh_eth_set_duplex,
769 .set_rate = sh_eth_set_rate_giga,
771 .register_type = SH_ETH_REG_GIGABIT,
773 .ecsr_value = ECSR_ICD | ECSR_MPD,
774 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
775 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
777 .tx_check = EESR_TC1 | EESR_FTC,
778 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
779 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
781 .fdr_value = 0x0000072f,
783 .irq_flags = IRQF_SHARED,
790 .rpadir_value = 2 << 16,
797 static struct sh_eth_cpu_data sh7734_data = {
798 .chip_reset = sh_eth_chip_reset,
799 .set_duplex = sh_eth_set_duplex,
800 .set_rate = sh_eth_set_rate_gether,
802 .register_type = SH_ETH_REG_GIGABIT,
804 .ecsr_value = ECSR_ICD | ECSR_MPD,
805 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
806 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
808 .tx_check = EESR_TC1 | EESR_FTC,
809 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
810 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
826 static struct sh_eth_cpu_data sh7763_data = {
827 .chip_reset = sh_eth_chip_reset,
828 .set_duplex = sh_eth_set_duplex,
829 .set_rate = sh_eth_set_rate_gether,
831 .register_type = SH_ETH_REG_GIGABIT,
833 .ecsr_value = ECSR_ICD | ECSR_MPD,
834 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
835 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
837 .tx_check = EESR_TC1 | EESR_FTC,
838 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
839 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
850 .irq_flags = IRQF_SHARED,
853 static struct sh_eth_cpu_data sh7619_data = {
854 .register_type = SH_ETH_REG_FAST_SH3_SH2,
856 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
864 static struct sh_eth_cpu_data sh771x_data = {
865 .register_type = SH_ETH_REG_FAST_SH3_SH2,
867 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
871 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
874 cd->ecsr_value = DEFAULT_ECSR_INIT;
876 if (!cd->ecsipr_value)
877 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
879 if (!cd->fcftr_value)
880 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
881 DEFAULT_FIFO_F_D_RFD;
884 cd->fdr_value = DEFAULT_FDR_INIT;
887 cd->tx_check = DEFAULT_TX_CHECK;
889 if (!cd->eesr_err_check)
890 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
892 if (!cd->trscer_err_mask)
893 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
896 static int sh_eth_check_reset(struct net_device *ndev)
902 if (!(sh_eth_read(ndev, EDMR) & 0x3))
908 netdev_err(ndev, "Device reset failed\n");
914 static int sh_eth_reset(struct net_device *ndev)
916 struct sh_eth_private *mdp = netdev_priv(ndev);
919 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
920 sh_eth_write(ndev, EDSR_ENALL, EDSR);
921 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
923 ret = sh_eth_check_reset(ndev);
928 sh_eth_write(ndev, 0x0, TDLAR);
929 sh_eth_write(ndev, 0x0, TDFAR);
930 sh_eth_write(ndev, 0x0, TDFXR);
931 sh_eth_write(ndev, 0x0, TDFFR);
932 sh_eth_write(ndev, 0x0, RDLAR);
933 sh_eth_write(ndev, 0x0, RDFAR);
934 sh_eth_write(ndev, 0x0, RDFXR);
935 sh_eth_write(ndev, 0x0, RDFFR);
937 /* Reset HW CRC register */
939 sh_eth_write(ndev, 0x0, CSMR);
941 /* Select MII mode */
942 if (mdp->cd->select_mii)
943 sh_eth_select_mii(ndev);
945 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
947 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
953 static void sh_eth_set_receive_align(struct sk_buff *skb)
955 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
958 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
961 /* Program the hardware MAC address from dev->dev_addr. */
962 static void update_mac_address(struct net_device *ndev)
965 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
966 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
968 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
971 /* Get MAC address from SuperH MAC address register
973 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
974 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
975 * When you want use this device, you must set MAC address in bootloader.
978 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
980 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
981 memcpy(ndev->dev_addr, mac, ETH_ALEN);
983 u32 mahr = sh_eth_read(ndev, MAHR);
984 u32 malr = sh_eth_read(ndev, MALR);
986 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
987 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
988 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
989 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
990 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
991 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
995 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
997 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
998 return EDTRR_TRNS_GETHER;
1000 return EDTRR_TRNS_ETHER;
1004 void (*set_gate)(void *addr);
1005 struct mdiobb_ctrl ctrl;
1009 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1011 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1014 if (bitbang->set_gate)
1015 bitbang->set_gate(bitbang->addr);
1017 pir = ioread32(bitbang->addr);
1022 iowrite32(pir, bitbang->addr);
1025 /* Data I/O pin control */
1026 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1028 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1032 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1034 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1038 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1040 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1042 if (bitbang->set_gate)
1043 bitbang->set_gate(bitbang->addr);
1045 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1048 /* MDC pin control */
1049 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1051 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1054 /* mdio bus control struct */
1055 static struct mdiobb_ops bb_ops = {
1056 .owner = THIS_MODULE,
1057 .set_mdc = sh_mdc_ctrl,
1058 .set_mdio_dir = sh_mmd_ctrl,
1059 .set_mdio_data = sh_set_mdio,
1060 .get_mdio_data = sh_get_mdio,
1063 /* free skb and descriptor buffer */
1064 static void sh_eth_ring_free(struct net_device *ndev)
1066 struct sh_eth_private *mdp = netdev_priv(ndev);
1069 /* Free Rx skb ringbuffer */
1070 if (mdp->rx_skbuff) {
1071 for (i = 0; i < mdp->num_rx_ring; i++)
1072 dev_kfree_skb(mdp->rx_skbuff[i]);
1074 kfree(mdp->rx_skbuff);
1075 mdp->rx_skbuff = NULL;
1077 /* Free Tx skb ringbuffer */
1078 if (mdp->tx_skbuff) {
1079 for (i = 0; i < mdp->num_tx_ring; i++)
1080 dev_kfree_skb(mdp->tx_skbuff[i]);
1082 kfree(mdp->tx_skbuff);
1083 mdp->tx_skbuff = NULL;
1086 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1087 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1089 mdp->rx_ring = NULL;
1093 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1094 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1096 mdp->tx_ring = NULL;
1100 /* format skb and descriptor buffer */
1101 static void sh_eth_ring_format(struct net_device *ndev)
1103 struct sh_eth_private *mdp = netdev_priv(ndev);
1105 struct sk_buff *skb;
1106 struct sh_eth_rxdesc *rxdesc = NULL;
1107 struct sh_eth_txdesc *txdesc = NULL;
1108 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1109 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1110 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1111 dma_addr_t dma_addr;
1119 memset(mdp->rx_ring, 0, rx_ringsize);
1121 /* build Rx ring buffer */
1122 for (i = 0; i < mdp->num_rx_ring; i++) {
1124 mdp->rx_skbuff[i] = NULL;
1125 skb = netdev_alloc_skb(ndev, skbuff_size);
1128 sh_eth_set_receive_align(skb);
1130 /* The size of the buffer is a multiple of 32 bytes. */
1131 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1132 dma_addr = dma_map_single(&ndev->dev, skb->data, buf_len,
1134 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1138 mdp->rx_skbuff[i] = skb;
1141 rxdesc = &mdp->rx_ring[i];
1142 rxdesc->len = cpu_to_le32(buf_len << 16);
1143 rxdesc->addr = cpu_to_le32(dma_addr);
1144 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1146 /* Rx descriptor address set */
1148 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1149 if (sh_eth_is_gether(mdp) ||
1150 sh_eth_is_rz_fast_ether(mdp))
1151 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1155 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1157 /* Mark the last entry as wrapping the ring. */
1159 rxdesc->status |= cpu_to_le32(RD_RDLE);
1161 memset(mdp->tx_ring, 0, tx_ringsize);
1163 /* build Tx ring buffer */
1164 for (i = 0; i < mdp->num_tx_ring; i++) {
1165 mdp->tx_skbuff[i] = NULL;
1166 txdesc = &mdp->tx_ring[i];
1167 txdesc->status = cpu_to_le32(TD_TFP);
1168 txdesc->len = cpu_to_le32(0);
1170 /* Tx descriptor address set */
1171 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1172 if (sh_eth_is_gether(mdp) ||
1173 sh_eth_is_rz_fast_ether(mdp))
1174 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1178 txdesc->status |= cpu_to_le32(TD_TDLE);
1181 /* Get skb and descriptor buffer */
1182 static int sh_eth_ring_init(struct net_device *ndev)
1184 struct sh_eth_private *mdp = netdev_priv(ndev);
1185 int rx_ringsize, tx_ringsize;
1187 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1188 * card needs room to do 8 byte alignment, +2 so we can reserve
1189 * the first 2 bytes, and +16 gets room for the status word from the
1192 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1193 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1194 if (mdp->cd->rpadir)
1195 mdp->rx_buf_sz += NET_IP_ALIGN;
1197 /* Allocate RX and TX skb rings */
1198 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1200 if (!mdp->rx_skbuff)
1203 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1205 if (!mdp->tx_skbuff)
1208 /* Allocate all Rx descriptors. */
1209 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1210 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1217 /* Allocate all Tx descriptors. */
1218 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1219 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1226 /* Free Rx and Tx skb ring buffer and DMA buffer */
1227 sh_eth_ring_free(ndev);
1232 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1234 struct sh_eth_private *mdp = netdev_priv(ndev);
1238 ret = sh_eth_reset(ndev);
1242 if (mdp->cd->rmiimode)
1243 sh_eth_write(ndev, 0x1, RMIIMODE);
1245 /* Descriptor format */
1246 sh_eth_ring_format(ndev);
1247 if (mdp->cd->rpadir)
1248 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1250 /* all sh_eth int mask */
1251 sh_eth_write(ndev, 0, EESIPR);
1253 #if defined(__LITTLE_ENDIAN)
1254 if (mdp->cd->hw_swap)
1255 sh_eth_write(ndev, EDMR_EL, EDMR);
1258 sh_eth_write(ndev, 0, EDMR);
1261 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1262 sh_eth_write(ndev, 0, TFTR);
1264 /* Frame recv control (enable multiple-packets per rx irq) */
1265 sh_eth_write(ndev, RMCR_RNC, RMCR);
1267 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1270 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1272 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1274 if (!mdp->cd->no_trimd)
1275 sh_eth_write(ndev, 0, TRIMD);
1277 /* Recv frame limit set register */
1278 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1281 sh_eth_modify(ndev, EESR, 0, 0);
1283 mdp->irq_enabled = true;
1284 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1287 /* PAUSE Prohibition */
1288 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1289 ECMR_TE | ECMR_RE, ECMR);
1291 if (mdp->cd->set_rate)
1292 mdp->cd->set_rate(ndev);
1294 /* E-MAC Status Register clear */
1295 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1297 /* E-MAC Interrupt Enable register */
1299 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1301 /* Set MAC address */
1302 update_mac_address(ndev);
1306 sh_eth_write(ndev, APR_AP, APR);
1308 sh_eth_write(ndev, MPR_MP, MPR);
1309 if (mdp->cd->tpauser)
1310 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1313 /* Setting the Rx mode will start the Rx process. */
1314 sh_eth_write(ndev, EDRRR_R, EDRRR);
1320 static void sh_eth_dev_exit(struct net_device *ndev)
1322 struct sh_eth_private *mdp = netdev_priv(ndev);
1325 /* Deactivate all TX descriptors, so DMA should stop at next
1326 * packet boundary if it's currently running
1328 for (i = 0; i < mdp->num_tx_ring; i++)
1329 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1331 /* Disable TX FIFO egress to MAC */
1332 sh_eth_rcv_snd_disable(ndev);
1334 /* Stop RX DMA at next packet boundary */
1335 sh_eth_write(ndev, 0, EDRRR);
1337 /* Aside from TX DMA, we can't tell when the hardware is
1338 * really stopped, so we need to reset to make sure.
1339 * Before doing that, wait for long enough to *probably*
1340 * finish transmitting the last packet and poll stats.
1342 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1343 sh_eth_get_stats(ndev);
1346 /* Set MAC address again */
1347 update_mac_address(ndev);
1350 /* free Tx skb function */
1351 static int sh_eth_txfree(struct net_device *ndev)
1353 struct sh_eth_private *mdp = netdev_priv(ndev);
1354 struct sh_eth_txdesc *txdesc;
1358 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1359 entry = mdp->dirty_tx % mdp->num_tx_ring;
1360 txdesc = &mdp->tx_ring[entry];
1361 if (txdesc->status & cpu_to_le32(TD_TACT))
1363 /* TACT bit must be checked before all the following reads */
1365 netif_info(mdp, tx_done, ndev,
1366 "tx entry %d status 0x%08x\n",
1367 entry, le32_to_cpu(txdesc->status));
1368 /* Free the original skb. */
1369 if (mdp->tx_skbuff[entry]) {
1370 dma_unmap_single(&ndev->dev, le32_to_cpu(txdesc->addr),
1371 le32_to_cpu(txdesc->len) >> 16,
1373 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1374 mdp->tx_skbuff[entry] = NULL;
1377 txdesc->status = cpu_to_le32(TD_TFP);
1378 if (entry >= mdp->num_tx_ring - 1)
1379 txdesc->status |= cpu_to_le32(TD_TDLE);
1381 ndev->stats.tx_packets++;
1382 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1387 /* Packet receive function */
1388 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1390 struct sh_eth_private *mdp = netdev_priv(ndev);
1391 struct sh_eth_rxdesc *rxdesc;
1393 int entry = mdp->cur_rx % mdp->num_rx_ring;
1394 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1396 struct sk_buff *skb;
1398 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1399 dma_addr_t dma_addr;
1403 boguscnt = min(boguscnt, *quota);
1405 rxdesc = &mdp->rx_ring[entry];
1406 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1407 /* RACT bit must be checked before all the following reads */
1409 desc_status = le32_to_cpu(rxdesc->status);
1410 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1415 netif_info(mdp, rx_status, ndev,
1416 "rx entry %d status 0x%08x len %d\n",
1417 entry, desc_status, pkt_len);
1419 if (!(desc_status & RDFEND))
1420 ndev->stats.rx_length_errors++;
1422 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1423 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1424 * bit 0. However, in case of the R8A7740 and R7S72100
1425 * the RFS bits are from bit 25 to bit 16. So, the
1426 * driver needs right shifting by 16.
1428 if (mdp->cd->shift_rd0)
1431 skb = mdp->rx_skbuff[entry];
1432 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1433 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1434 ndev->stats.rx_errors++;
1435 if (desc_status & RD_RFS1)
1436 ndev->stats.rx_crc_errors++;
1437 if (desc_status & RD_RFS2)
1438 ndev->stats.rx_frame_errors++;
1439 if (desc_status & RD_RFS3)
1440 ndev->stats.rx_length_errors++;
1441 if (desc_status & RD_RFS4)
1442 ndev->stats.rx_length_errors++;
1443 if (desc_status & RD_RFS6)
1444 ndev->stats.rx_missed_errors++;
1445 if (desc_status & RD_RFS10)
1446 ndev->stats.rx_over_errors++;
1448 dma_addr = le32_to_cpu(rxdesc->addr);
1449 if (!mdp->cd->hw_swap)
1451 phys_to_virt(ALIGN(dma_addr, 4)),
1453 mdp->rx_skbuff[entry] = NULL;
1454 if (mdp->cd->rpadir)
1455 skb_reserve(skb, NET_IP_ALIGN);
1456 dma_unmap_single(&ndev->dev, dma_addr,
1457 ALIGN(mdp->rx_buf_sz, 32),
1459 skb_put(skb, pkt_len);
1460 skb->protocol = eth_type_trans(skb, ndev);
1461 netif_receive_skb(skb);
1462 ndev->stats.rx_packets++;
1463 ndev->stats.rx_bytes += pkt_len;
1464 if (desc_status & RD_RFS8)
1465 ndev->stats.multicast++;
1467 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1468 rxdesc = &mdp->rx_ring[entry];
1471 /* Refill the Rx ring buffers. */
1472 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1473 entry = mdp->dirty_rx % mdp->num_rx_ring;
1474 rxdesc = &mdp->rx_ring[entry];
1475 /* The size of the buffer is 32 byte boundary. */
1476 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1477 rxdesc->len = cpu_to_le32(buf_len << 16);
1479 if (mdp->rx_skbuff[entry] == NULL) {
1480 skb = netdev_alloc_skb(ndev, skbuff_size);
1482 break; /* Better luck next round. */
1483 sh_eth_set_receive_align(skb);
1484 dma_addr = dma_map_single(&ndev->dev, skb->data,
1485 buf_len, DMA_FROM_DEVICE);
1486 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1490 mdp->rx_skbuff[entry] = skb;
1492 skb_checksum_none_assert(skb);
1493 rxdesc->addr = cpu_to_le32(dma_addr);
1495 dma_wmb(); /* RACT bit must be set after all the above writes */
1496 if (entry >= mdp->num_rx_ring - 1)
1498 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1500 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1503 /* Restart Rx engine if stopped. */
1504 /* If we don't need to check status, don't. -KDU */
1505 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1506 /* fix the values for the next receiving if RDE is set */
1507 if (intr_status & EESR_RDE &&
1508 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1509 u32 count = (sh_eth_read(ndev, RDFAR) -
1510 sh_eth_read(ndev, RDLAR)) >> 4;
1512 mdp->cur_rx = count;
1513 mdp->dirty_rx = count;
1515 sh_eth_write(ndev, EDRRR_R, EDRRR);
1518 *quota -= limit - boguscnt - 1;
1523 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1525 /* disable tx and rx */
1526 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1529 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1531 /* enable tx and rx */
1532 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1535 /* error control function */
1536 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1538 struct sh_eth_private *mdp = netdev_priv(ndev);
1543 if (intr_status & EESR_ECI) {
1544 felic_stat = sh_eth_read(ndev, ECSR);
1545 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1546 if (felic_stat & ECSR_ICD)
1547 ndev->stats.tx_carrier_errors++;
1548 if (felic_stat & ECSR_LCHNG) {
1550 if (mdp->cd->no_psr || mdp->no_ether_link) {
1553 link_stat = (sh_eth_read(ndev, PSR));
1554 if (mdp->ether_link_active_low)
1555 link_stat = ~link_stat;
1557 if (!(link_stat & PHY_ST_LINK)) {
1558 sh_eth_rcv_snd_disable(ndev);
1561 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
1563 sh_eth_modify(ndev, ECSR, 0, 0);
1564 sh_eth_modify(ndev, EESIPR, DMAC_M_ECI,
1566 /* enable tx and rx */
1567 sh_eth_rcv_snd_enable(ndev);
1573 if (intr_status & EESR_TWB) {
1574 /* Unused write back interrupt */
1575 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1576 ndev->stats.tx_aborted_errors++;
1577 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1581 if (intr_status & EESR_RABT) {
1582 /* Receive Abort int */
1583 if (intr_status & EESR_RFRMER) {
1584 /* Receive Frame Overflow int */
1585 ndev->stats.rx_frame_errors++;
1589 if (intr_status & EESR_TDE) {
1590 /* Transmit Descriptor Empty int */
1591 ndev->stats.tx_fifo_errors++;
1592 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1595 if (intr_status & EESR_TFE) {
1596 /* FIFO under flow */
1597 ndev->stats.tx_fifo_errors++;
1598 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1601 if (intr_status & EESR_RDE) {
1602 /* Receive Descriptor Empty int */
1603 ndev->stats.rx_over_errors++;
1606 if (intr_status & EESR_RFE) {
1607 /* Receive FIFO Overflow int */
1608 ndev->stats.rx_fifo_errors++;
1611 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1613 ndev->stats.tx_fifo_errors++;
1614 netif_err(mdp, tx_err, ndev, "Address Error\n");
1617 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1618 if (mdp->cd->no_ade)
1620 if (intr_status & mask) {
1622 u32 edtrr = sh_eth_read(ndev, EDTRR);
1625 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1626 intr_status, mdp->cur_tx, mdp->dirty_tx,
1627 (u32)ndev->state, edtrr);
1628 /* dirty buffer free */
1629 sh_eth_txfree(ndev);
1632 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1634 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1637 netif_wake_queue(ndev);
1641 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1643 struct net_device *ndev = netdev;
1644 struct sh_eth_private *mdp = netdev_priv(ndev);
1645 struct sh_eth_cpu_data *cd = mdp->cd;
1646 irqreturn_t ret = IRQ_NONE;
1647 u32 intr_status, intr_enable;
1649 spin_lock(&mdp->lock);
1651 /* Get interrupt status */
1652 intr_status = sh_eth_read(ndev, EESR);
1653 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1654 * enabled since it's the one that comes thru regardless of the mask,
1655 * and we need to fully handle it in sh_eth_error() in order to quench
1656 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1658 intr_enable = sh_eth_read(ndev, EESIPR);
1659 intr_status &= intr_enable | DMAC_M_ECI;
1660 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1665 if (!likely(mdp->irq_enabled)) {
1666 sh_eth_write(ndev, 0, EESIPR);
1670 if (intr_status & EESR_RX_CHECK) {
1671 if (napi_schedule_prep(&mdp->napi)) {
1672 /* Mask Rx interrupts */
1673 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1675 __napi_schedule(&mdp->napi);
1678 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1679 intr_status, intr_enable);
1684 if (intr_status & cd->tx_check) {
1685 /* Clear Tx interrupts */
1686 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1688 sh_eth_txfree(ndev);
1689 netif_wake_queue(ndev);
1692 if (intr_status & cd->eesr_err_check) {
1693 /* Clear error interrupts */
1694 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1696 sh_eth_error(ndev, intr_status);
1700 spin_unlock(&mdp->lock);
1705 static int sh_eth_poll(struct napi_struct *napi, int budget)
1707 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1709 struct net_device *ndev = napi->dev;
1714 intr_status = sh_eth_read(ndev, EESR);
1715 if (!(intr_status & EESR_RX_CHECK))
1717 /* Clear Rx interrupts */
1718 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1720 if (sh_eth_rx(ndev, intr_status, "a))
1724 napi_complete(napi);
1726 /* Reenable Rx interrupts */
1727 if (mdp->irq_enabled)
1728 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1730 return budget - quota;
1733 /* PHY state control function */
1734 static void sh_eth_adjust_link(struct net_device *ndev)
1736 struct sh_eth_private *mdp = netdev_priv(ndev);
1737 struct phy_device *phydev = mdp->phydev;
1741 if (phydev->duplex != mdp->duplex) {
1743 mdp->duplex = phydev->duplex;
1744 if (mdp->cd->set_duplex)
1745 mdp->cd->set_duplex(ndev);
1748 if (phydev->speed != mdp->speed) {
1750 mdp->speed = phydev->speed;
1751 if (mdp->cd->set_rate)
1752 mdp->cd->set_rate(ndev);
1755 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1757 mdp->link = phydev->link;
1758 if (mdp->cd->no_psr || mdp->no_ether_link)
1759 sh_eth_rcv_snd_enable(ndev);
1761 } else if (mdp->link) {
1766 if (mdp->cd->no_psr || mdp->no_ether_link)
1767 sh_eth_rcv_snd_disable(ndev);
1770 if (new_state && netif_msg_link(mdp))
1771 phy_print_status(phydev);
1774 /* PHY init function */
1775 static int sh_eth_phy_init(struct net_device *ndev)
1777 struct device_node *np = ndev->dev.parent->of_node;
1778 struct sh_eth_private *mdp = netdev_priv(ndev);
1779 struct phy_device *phydev;
1785 /* Try connect to PHY */
1787 struct device_node *pn;
1789 pn = of_parse_phandle(np, "phy-handle", 0);
1790 phydev = of_phy_connect(ndev, pn,
1791 sh_eth_adjust_link, 0,
1792 mdp->phy_interface);
1795 phydev = ERR_PTR(-ENOENT);
1797 char phy_id[MII_BUS_ID_SIZE + 3];
1799 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1800 mdp->mii_bus->id, mdp->phy_id);
1802 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1803 mdp->phy_interface);
1806 if (IS_ERR(phydev)) {
1807 netdev_err(ndev, "failed to connect PHY\n");
1808 return PTR_ERR(phydev);
1811 phy_attached_info(phydev);
1813 mdp->phydev = phydev;
1818 /* PHY control start function */
1819 static int sh_eth_phy_start(struct net_device *ndev)
1821 struct sh_eth_private *mdp = netdev_priv(ndev);
1824 ret = sh_eth_phy_init(ndev);
1828 phy_start(mdp->phydev);
1833 static int sh_eth_get_settings(struct net_device *ndev,
1834 struct ethtool_cmd *ecmd)
1836 struct sh_eth_private *mdp = netdev_priv(ndev);
1837 unsigned long flags;
1843 spin_lock_irqsave(&mdp->lock, flags);
1844 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1845 spin_unlock_irqrestore(&mdp->lock, flags);
1850 static int sh_eth_set_settings(struct net_device *ndev,
1851 struct ethtool_cmd *ecmd)
1853 struct sh_eth_private *mdp = netdev_priv(ndev);
1854 unsigned long flags;
1860 spin_lock_irqsave(&mdp->lock, flags);
1862 /* disable tx and rx */
1863 sh_eth_rcv_snd_disable(ndev);
1865 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1869 if (ecmd->duplex == DUPLEX_FULL)
1874 if (mdp->cd->set_duplex)
1875 mdp->cd->set_duplex(ndev);
1880 /* enable tx and rx */
1881 sh_eth_rcv_snd_enable(ndev);
1883 spin_unlock_irqrestore(&mdp->lock, flags);
1888 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1889 * version must be bumped as well. Just adding registers up to that
1890 * limit is fine, as long as the existing register indices don't
1893 #define SH_ETH_REG_DUMP_VERSION 1
1894 #define SH_ETH_REG_DUMP_MAX_REGS 256
1896 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1898 struct sh_eth_private *mdp = netdev_priv(ndev);
1899 struct sh_eth_cpu_data *cd = mdp->cd;
1903 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1905 /* Dump starts with a bitmap that tells ethtool which
1906 * registers are defined for this chip.
1908 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1916 /* Add a register to the dump, if it has a defined offset.
1917 * This automatically skips most undefined registers, but for
1918 * some it is also necessary to check a capability flag in
1919 * struct sh_eth_cpu_data.
1921 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1922 #define add_reg_from(reg, read_expr) do { \
1923 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1925 mark_reg_valid(reg); \
1926 *buf++ = read_expr; \
1931 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1932 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2004 add_tsu_reg(TSU_CTRST);
2005 add_tsu_reg(TSU_FWEN0);
2006 add_tsu_reg(TSU_FWEN1);
2007 add_tsu_reg(TSU_FCM);
2008 add_tsu_reg(TSU_BSYSL0);
2009 add_tsu_reg(TSU_BSYSL1);
2010 add_tsu_reg(TSU_PRISL0);
2011 add_tsu_reg(TSU_PRISL1);
2012 add_tsu_reg(TSU_FWSL0);
2013 add_tsu_reg(TSU_FWSL1);
2014 add_tsu_reg(TSU_FWSLC);
2015 add_tsu_reg(TSU_QTAG0);
2016 add_tsu_reg(TSU_QTAG1);
2017 add_tsu_reg(TSU_QTAGM0);
2018 add_tsu_reg(TSU_QTAGM1);
2019 add_tsu_reg(TSU_FWSR);
2020 add_tsu_reg(TSU_FWINMK);
2021 add_tsu_reg(TSU_ADQT0);
2022 add_tsu_reg(TSU_ADQT1);
2023 add_tsu_reg(TSU_VTAG0);
2024 add_tsu_reg(TSU_VTAG1);
2025 add_tsu_reg(TSU_ADSBSY);
2026 add_tsu_reg(TSU_TEN);
2027 add_tsu_reg(TSU_POST1);
2028 add_tsu_reg(TSU_POST2);
2029 add_tsu_reg(TSU_POST3);
2030 add_tsu_reg(TSU_POST4);
2031 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2032 /* This is the start of a table, not just a single
2038 mark_reg_valid(TSU_ADRH0);
2039 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2042 mdp->reg_offset[TSU_ADRH0] +
2045 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2049 #undef mark_reg_valid
2057 static int sh_eth_get_regs_len(struct net_device *ndev)
2059 return __sh_eth_get_regs(ndev, NULL);
2062 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2065 struct sh_eth_private *mdp = netdev_priv(ndev);
2067 regs->version = SH_ETH_REG_DUMP_VERSION;
2069 pm_runtime_get_sync(&mdp->pdev->dev);
2070 __sh_eth_get_regs(ndev, buf);
2071 pm_runtime_put_sync(&mdp->pdev->dev);
2074 static int sh_eth_nway_reset(struct net_device *ndev)
2076 struct sh_eth_private *mdp = netdev_priv(ndev);
2077 unsigned long flags;
2083 spin_lock_irqsave(&mdp->lock, flags);
2084 ret = phy_start_aneg(mdp->phydev);
2085 spin_unlock_irqrestore(&mdp->lock, flags);
2090 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2092 struct sh_eth_private *mdp = netdev_priv(ndev);
2093 return mdp->msg_enable;
2096 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2098 struct sh_eth_private *mdp = netdev_priv(ndev);
2099 mdp->msg_enable = value;
2102 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2103 "rx_current", "tx_current",
2104 "rx_dirty", "tx_dirty",
2106 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2108 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2112 return SH_ETH_STATS_LEN;
2118 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2119 struct ethtool_stats *stats, u64 *data)
2121 struct sh_eth_private *mdp = netdev_priv(ndev);
2124 /* device-specific stats */
2125 data[i++] = mdp->cur_rx;
2126 data[i++] = mdp->cur_tx;
2127 data[i++] = mdp->dirty_rx;
2128 data[i++] = mdp->dirty_tx;
2131 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2133 switch (stringset) {
2135 memcpy(data, *sh_eth_gstrings_stats,
2136 sizeof(sh_eth_gstrings_stats));
2141 static void sh_eth_get_ringparam(struct net_device *ndev,
2142 struct ethtool_ringparam *ring)
2144 struct sh_eth_private *mdp = netdev_priv(ndev);
2146 ring->rx_max_pending = RX_RING_MAX;
2147 ring->tx_max_pending = TX_RING_MAX;
2148 ring->rx_pending = mdp->num_rx_ring;
2149 ring->tx_pending = mdp->num_tx_ring;
2152 static int sh_eth_set_ringparam(struct net_device *ndev,
2153 struct ethtool_ringparam *ring)
2155 struct sh_eth_private *mdp = netdev_priv(ndev);
2158 if (ring->tx_pending > TX_RING_MAX ||
2159 ring->rx_pending > RX_RING_MAX ||
2160 ring->tx_pending < TX_RING_MIN ||
2161 ring->rx_pending < RX_RING_MIN)
2163 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2166 if (netif_running(ndev)) {
2167 netif_device_detach(ndev);
2168 netif_tx_disable(ndev);
2170 /* Serialise with the interrupt handler and NAPI, then
2171 * disable interrupts. We have to clear the
2172 * irq_enabled flag first to ensure that interrupts
2173 * won't be re-enabled.
2175 mdp->irq_enabled = false;
2176 synchronize_irq(ndev->irq);
2177 napi_synchronize(&mdp->napi);
2178 sh_eth_write(ndev, 0x0000, EESIPR);
2180 sh_eth_dev_exit(ndev);
2182 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2183 sh_eth_ring_free(ndev);
2186 /* Set new parameters */
2187 mdp->num_rx_ring = ring->rx_pending;
2188 mdp->num_tx_ring = ring->tx_pending;
2190 if (netif_running(ndev)) {
2191 ret = sh_eth_ring_init(ndev);
2193 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2197 ret = sh_eth_dev_init(ndev, true);
2199 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2204 netif_device_attach(ndev);
2210 static const struct ethtool_ops sh_eth_ethtool_ops = {
2211 .get_settings = sh_eth_get_settings,
2212 .set_settings = sh_eth_set_settings,
2213 .get_regs_len = sh_eth_get_regs_len,
2214 .get_regs = sh_eth_get_regs,
2215 .nway_reset = sh_eth_nway_reset,
2216 .get_msglevel = sh_eth_get_msglevel,
2217 .set_msglevel = sh_eth_set_msglevel,
2218 .get_link = ethtool_op_get_link,
2219 .get_strings = sh_eth_get_strings,
2220 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2221 .get_sset_count = sh_eth_get_sset_count,
2222 .get_ringparam = sh_eth_get_ringparam,
2223 .set_ringparam = sh_eth_set_ringparam,
2226 /* network device open function */
2227 static int sh_eth_open(struct net_device *ndev)
2229 struct sh_eth_private *mdp = netdev_priv(ndev);
2232 pm_runtime_get_sync(&mdp->pdev->dev);
2234 napi_enable(&mdp->napi);
2236 ret = request_irq(ndev->irq, sh_eth_interrupt,
2237 mdp->cd->irq_flags, ndev->name, ndev);
2239 netdev_err(ndev, "Can not assign IRQ number\n");
2243 /* Descriptor set */
2244 ret = sh_eth_ring_init(ndev);
2249 ret = sh_eth_dev_init(ndev, true);
2253 /* PHY control start*/
2254 ret = sh_eth_phy_start(ndev);
2258 netif_start_queue(ndev);
2265 free_irq(ndev->irq, ndev);
2267 napi_disable(&mdp->napi);
2268 pm_runtime_put_sync(&mdp->pdev->dev);
2272 /* Timeout function */
2273 static void sh_eth_tx_timeout(struct net_device *ndev)
2275 struct sh_eth_private *mdp = netdev_priv(ndev);
2276 struct sh_eth_rxdesc *rxdesc;
2279 netif_stop_queue(ndev);
2281 netif_err(mdp, timer, ndev,
2282 "transmit timed out, status %8.8x, resetting...\n",
2283 sh_eth_read(ndev, EESR));
2285 /* tx_errors count up */
2286 ndev->stats.tx_errors++;
2288 /* Free all the skbuffs in the Rx queue. */
2289 for (i = 0; i < mdp->num_rx_ring; i++) {
2290 rxdesc = &mdp->rx_ring[i];
2291 rxdesc->status = cpu_to_le32(0);
2292 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2293 dev_kfree_skb(mdp->rx_skbuff[i]);
2294 mdp->rx_skbuff[i] = NULL;
2296 for (i = 0; i < mdp->num_tx_ring; i++) {
2297 dev_kfree_skb(mdp->tx_skbuff[i]);
2298 mdp->tx_skbuff[i] = NULL;
2302 sh_eth_dev_init(ndev, true);
2304 netif_start_queue(ndev);
2307 /* Packet transmit function */
2308 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2310 struct sh_eth_private *mdp = netdev_priv(ndev);
2311 struct sh_eth_txdesc *txdesc;
2312 dma_addr_t dma_addr;
2314 unsigned long flags;
2316 spin_lock_irqsave(&mdp->lock, flags);
2317 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2318 if (!sh_eth_txfree(ndev)) {
2319 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2320 netif_stop_queue(ndev);
2321 spin_unlock_irqrestore(&mdp->lock, flags);
2322 return NETDEV_TX_BUSY;
2325 spin_unlock_irqrestore(&mdp->lock, flags);
2327 if (skb_put_padto(skb, ETH_ZLEN))
2328 return NETDEV_TX_OK;
2330 entry = mdp->cur_tx % mdp->num_tx_ring;
2331 mdp->tx_skbuff[entry] = skb;
2332 txdesc = &mdp->tx_ring[entry];
2334 if (!mdp->cd->hw_swap)
2335 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2336 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2338 if (dma_mapping_error(&ndev->dev, dma_addr)) {
2340 return NETDEV_TX_OK;
2342 txdesc->addr = cpu_to_le32(dma_addr);
2343 txdesc->len = cpu_to_le32(skb->len << 16);
2345 dma_wmb(); /* TACT bit must be set after all the above writes */
2346 if (entry >= mdp->num_tx_ring - 1)
2347 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2349 txdesc->status |= cpu_to_le32(TD_TACT);
2353 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2354 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2356 return NETDEV_TX_OK;
2359 /* The statistics registers have write-clear behaviour, which means we
2360 * will lose any increment between the read and write. We mitigate
2361 * this by only clearing when we read a non-zero value, so we will
2362 * never falsely report a total of zero.
2365 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2367 u32 delta = sh_eth_read(ndev, reg);
2371 sh_eth_write(ndev, 0, reg);
2375 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2377 struct sh_eth_private *mdp = netdev_priv(ndev);
2379 if (sh_eth_is_rz_fast_ether(mdp))
2380 return &ndev->stats;
2382 if (!mdp->is_opened)
2383 return &ndev->stats;
2385 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2386 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2387 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2389 if (sh_eth_is_gether(mdp)) {
2390 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2392 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2395 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2399 return &ndev->stats;
2402 /* device close function */
2403 static int sh_eth_close(struct net_device *ndev)
2405 struct sh_eth_private *mdp = netdev_priv(ndev);
2407 netif_stop_queue(ndev);
2409 /* Serialise with the interrupt handler and NAPI, then disable
2410 * interrupts. We have to clear the irq_enabled flag first to
2411 * ensure that interrupts won't be re-enabled.
2413 mdp->irq_enabled = false;
2414 synchronize_irq(ndev->irq);
2415 napi_disable(&mdp->napi);
2416 sh_eth_write(ndev, 0x0000, EESIPR);
2418 sh_eth_dev_exit(ndev);
2420 /* PHY Disconnect */
2422 phy_stop(mdp->phydev);
2423 phy_disconnect(mdp->phydev);
2427 free_irq(ndev->irq, ndev);
2429 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2430 sh_eth_ring_free(ndev);
2432 pm_runtime_put_sync(&mdp->pdev->dev);
2439 /* ioctl to device function */
2440 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2442 struct sh_eth_private *mdp = netdev_priv(ndev);
2443 struct phy_device *phydev = mdp->phydev;
2445 if (!netif_running(ndev))
2451 return phy_mii_ioctl(phydev, rq, cmd);
2454 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2455 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2458 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2461 static u32 sh_eth_tsu_get_post_mask(int entry)
2463 return 0x0f << (28 - ((entry % 8) * 4));
2466 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2468 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2471 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2474 struct sh_eth_private *mdp = netdev_priv(ndev);
2478 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2479 tmp = ioread32(reg_offset);
2480 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2483 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2486 struct sh_eth_private *mdp = netdev_priv(ndev);
2487 u32 post_mask, ref_mask, tmp;
2490 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2491 post_mask = sh_eth_tsu_get_post_mask(entry);
2492 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2494 tmp = ioread32(reg_offset);
2495 iowrite32(tmp & ~post_mask, reg_offset);
2497 /* If other port enables, the function returns "true" */
2498 return tmp & ref_mask;
2501 static int sh_eth_tsu_busy(struct net_device *ndev)
2503 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2504 struct sh_eth_private *mdp = netdev_priv(ndev);
2506 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2510 netdev_err(ndev, "%s: timeout\n", __func__);
2518 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2523 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2524 iowrite32(val, reg);
2525 if (sh_eth_tsu_busy(ndev) < 0)
2528 val = addr[4] << 8 | addr[5];
2529 iowrite32(val, reg + 4);
2530 if (sh_eth_tsu_busy(ndev) < 0)
2536 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2540 val = ioread32(reg);
2541 addr[0] = (val >> 24) & 0xff;
2542 addr[1] = (val >> 16) & 0xff;
2543 addr[2] = (val >> 8) & 0xff;
2544 addr[3] = val & 0xff;
2545 val = ioread32(reg + 4);
2546 addr[4] = (val >> 8) & 0xff;
2547 addr[5] = val & 0xff;
2551 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2553 struct sh_eth_private *mdp = netdev_priv(ndev);
2554 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2556 u8 c_addr[ETH_ALEN];
2558 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2559 sh_eth_tsu_read_entry(reg_offset, c_addr);
2560 if (ether_addr_equal(addr, c_addr))
2567 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2572 memset(blank, 0, sizeof(blank));
2573 entry = sh_eth_tsu_find_entry(ndev, blank);
2574 return (entry < 0) ? -ENOMEM : entry;
2577 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2580 struct sh_eth_private *mdp = netdev_priv(ndev);
2581 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2585 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2586 ~(1 << (31 - entry)), TSU_TEN);
2588 memset(blank, 0, sizeof(blank));
2589 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2595 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2597 struct sh_eth_private *mdp = netdev_priv(ndev);
2598 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2604 i = sh_eth_tsu_find_entry(ndev, addr);
2606 /* No entry found, create one */
2607 i = sh_eth_tsu_find_empty(ndev);
2610 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2614 /* Enable the entry */
2615 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2616 (1 << (31 - i)), TSU_TEN);
2619 /* Entry found or created, enable POST */
2620 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2625 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2627 struct sh_eth_private *mdp = netdev_priv(ndev);
2633 i = sh_eth_tsu_find_entry(ndev, addr);
2636 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2639 /* Disable the entry if both ports was disabled */
2640 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2648 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2650 struct sh_eth_private *mdp = netdev_priv(ndev);
2656 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2657 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2660 /* Disable the entry if both ports was disabled */
2661 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2669 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2671 struct sh_eth_private *mdp = netdev_priv(ndev);
2673 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2679 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2680 sh_eth_tsu_read_entry(reg_offset, addr);
2681 if (is_multicast_ether_addr(addr))
2682 sh_eth_tsu_del_entry(ndev, addr);
2686 /* Update promiscuous flag and multicast filter */
2687 static void sh_eth_set_rx_mode(struct net_device *ndev)
2689 struct sh_eth_private *mdp = netdev_priv(ndev);
2692 unsigned long flags;
2694 spin_lock_irqsave(&mdp->lock, flags);
2695 /* Initial condition is MCT = 1, PRM = 0.
2696 * Depending on ndev->flags, set PRM or clear MCT
2698 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2700 ecmr_bits |= ECMR_MCT;
2702 if (!(ndev->flags & IFF_MULTICAST)) {
2703 sh_eth_tsu_purge_mcast(ndev);
2706 if (ndev->flags & IFF_ALLMULTI) {
2707 sh_eth_tsu_purge_mcast(ndev);
2708 ecmr_bits &= ~ECMR_MCT;
2712 if (ndev->flags & IFF_PROMISC) {
2713 sh_eth_tsu_purge_all(ndev);
2714 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2715 } else if (mdp->cd->tsu) {
2716 struct netdev_hw_addr *ha;
2717 netdev_for_each_mc_addr(ha, ndev) {
2718 if (mcast_all && is_multicast_ether_addr(ha->addr))
2721 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2723 sh_eth_tsu_purge_mcast(ndev);
2724 ecmr_bits &= ~ECMR_MCT;
2731 /* update the ethernet mode */
2732 sh_eth_write(ndev, ecmr_bits, ECMR);
2734 spin_unlock_irqrestore(&mdp->lock, flags);
2737 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2745 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2746 __be16 proto, u16 vid)
2748 struct sh_eth_private *mdp = netdev_priv(ndev);
2749 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2751 if (unlikely(!mdp->cd->tsu))
2754 /* No filtering if vid = 0 */
2758 mdp->vlan_num_ids++;
2760 /* The controller has one VLAN tag HW filter. So, if the filter is
2761 * already enabled, the driver disables it and the filte
2763 if (mdp->vlan_num_ids > 1) {
2764 /* disable VLAN filter */
2765 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2769 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2775 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2776 __be16 proto, u16 vid)
2778 struct sh_eth_private *mdp = netdev_priv(ndev);
2779 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2781 if (unlikely(!mdp->cd->tsu))
2784 /* No filtering if vid = 0 */
2788 mdp->vlan_num_ids--;
2789 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2794 /* SuperH's TSU register init function */
2795 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2797 if (sh_eth_is_rz_fast_ether(mdp)) {
2798 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2802 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2803 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2804 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2805 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2806 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2807 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2808 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2809 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2810 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2811 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2812 if (sh_eth_is_gether(mdp)) {
2813 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2814 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2816 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2817 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2819 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2820 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2821 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2822 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2823 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2824 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2825 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2828 /* MDIO bus release function */
2829 static int sh_mdio_release(struct sh_eth_private *mdp)
2831 /* unregister mdio bus */
2832 mdiobus_unregister(mdp->mii_bus);
2834 /* free bitbang info */
2835 free_mdio_bitbang(mdp->mii_bus);
2840 /* MDIO bus init function */
2841 static int sh_mdio_init(struct sh_eth_private *mdp,
2842 struct sh_eth_plat_data *pd)
2845 struct bb_info *bitbang;
2846 struct platform_device *pdev = mdp->pdev;
2847 struct device *dev = &mdp->pdev->dev;
2849 /* create bit control struct for PHY */
2850 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2855 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2856 bitbang->set_gate = pd->set_mdio_gate;
2857 bitbang->ctrl.ops = &bb_ops;
2859 /* MII controller setting */
2860 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2864 /* Hook up MII support for ethtool */
2865 mdp->mii_bus->name = "sh_mii";
2866 mdp->mii_bus->parent = dev;
2867 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2868 pdev->name, pdev->id);
2870 /* register MDIO bus */
2872 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2874 if (pd->phy_irq > 0)
2875 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2877 ret = mdiobus_register(mdp->mii_bus);
2886 free_mdio_bitbang(mdp->mii_bus);
2890 static const u16 *sh_eth_get_register_offset(int register_type)
2892 const u16 *reg_offset = NULL;
2894 switch (register_type) {
2895 case SH_ETH_REG_GIGABIT:
2896 reg_offset = sh_eth_offset_gigabit;
2898 case SH_ETH_REG_FAST_RZ:
2899 reg_offset = sh_eth_offset_fast_rz;
2901 case SH_ETH_REG_FAST_RCAR:
2902 reg_offset = sh_eth_offset_fast_rcar;
2904 case SH_ETH_REG_FAST_SH4:
2905 reg_offset = sh_eth_offset_fast_sh4;
2907 case SH_ETH_REG_FAST_SH3_SH2:
2908 reg_offset = sh_eth_offset_fast_sh3_sh2;
2915 static const struct net_device_ops sh_eth_netdev_ops = {
2916 .ndo_open = sh_eth_open,
2917 .ndo_stop = sh_eth_close,
2918 .ndo_start_xmit = sh_eth_start_xmit,
2919 .ndo_get_stats = sh_eth_get_stats,
2920 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2921 .ndo_tx_timeout = sh_eth_tx_timeout,
2922 .ndo_do_ioctl = sh_eth_do_ioctl,
2923 .ndo_validate_addr = eth_validate_addr,
2924 .ndo_set_mac_address = eth_mac_addr,
2925 .ndo_change_mtu = eth_change_mtu,
2928 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2929 .ndo_open = sh_eth_open,
2930 .ndo_stop = sh_eth_close,
2931 .ndo_start_xmit = sh_eth_start_xmit,
2932 .ndo_get_stats = sh_eth_get_stats,
2933 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2934 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2935 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2936 .ndo_tx_timeout = sh_eth_tx_timeout,
2937 .ndo_do_ioctl = sh_eth_do_ioctl,
2938 .ndo_validate_addr = eth_validate_addr,
2939 .ndo_set_mac_address = eth_mac_addr,
2940 .ndo_change_mtu = eth_change_mtu,
2944 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2946 struct device_node *np = dev->of_node;
2947 struct sh_eth_plat_data *pdata;
2948 const char *mac_addr;
2950 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2954 pdata->phy_interface = of_get_phy_mode(np);
2956 mac_addr = of_get_mac_address(np);
2958 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2960 pdata->no_ether_link =
2961 of_property_read_bool(np, "renesas,no-ether-link");
2962 pdata->ether_link_active_low =
2963 of_property_read_bool(np, "renesas,ether-link-active-low");
2968 static const struct of_device_id sh_eth_match_table[] = {
2969 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2970 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2971 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2972 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2973 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2974 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2975 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2976 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2979 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2981 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2987 static int sh_eth_drv_probe(struct platform_device *pdev)
2989 struct resource *res;
2990 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2991 const struct platform_device_id *id = platform_get_device_id(pdev);
2992 struct sh_eth_private *mdp;
2993 struct net_device *ndev;
2997 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2999 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3003 pm_runtime_enable(&pdev->dev);
3004 pm_runtime_get_sync(&pdev->dev);
3011 ret = platform_get_irq(pdev, 0);
3016 SET_NETDEV_DEV(ndev, &pdev->dev);
3018 mdp = netdev_priv(ndev);
3019 mdp->num_tx_ring = TX_RING_SIZE;
3020 mdp->num_rx_ring = RX_RING_SIZE;
3021 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3022 if (IS_ERR(mdp->addr)) {
3023 ret = PTR_ERR(mdp->addr);
3027 ndev->base_addr = res->start;
3029 spin_lock_init(&mdp->lock);
3032 if (pdev->dev.of_node)
3033 pd = sh_eth_parse_dt(&pdev->dev);
3035 dev_err(&pdev->dev, "no platform data\n");
3041 mdp->phy_id = pd->phy;
3042 mdp->phy_interface = pd->phy_interface;
3043 mdp->no_ether_link = pd->no_ether_link;
3044 mdp->ether_link_active_low = pd->ether_link_active_low;
3048 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3050 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3052 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3053 if (!mdp->reg_offset) {
3054 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3055 mdp->cd->register_type);
3059 sh_eth_set_default_cpu_data(mdp->cd);
3063 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3065 ndev->netdev_ops = &sh_eth_netdev_ops;
3066 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3067 ndev->watchdog_timeo = TX_TIMEOUT;
3069 /* debug message level */
3070 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3072 /* read and set MAC address */
3073 read_mac_address(ndev, pd->mac_addr);
3074 if (!is_valid_ether_addr(ndev->dev_addr)) {
3075 dev_warn(&pdev->dev,
3076 "no valid MAC address supplied, using a random one.\n");
3077 eth_hw_addr_random(ndev);
3080 /* ioremap the TSU registers */
3082 struct resource *rtsu;
3083 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3084 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3085 if (IS_ERR(mdp->tsu_addr)) {
3086 ret = PTR_ERR(mdp->tsu_addr);
3089 mdp->port = devno % 2;
3090 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3093 /* initialize first or needed device */
3094 if (!devno || pd->needs_init) {
3095 if (mdp->cd->chip_reset)
3096 mdp->cd->chip_reset(ndev);
3099 /* TSU init (Init only)*/
3100 sh_eth_tsu_init(mdp);
3104 if (mdp->cd->rmiimode)
3105 sh_eth_write(ndev, 0x1, RMIIMODE);
3108 ret = sh_mdio_init(mdp, pd);
3110 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3114 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3116 /* network device register */
3117 ret = register_netdev(ndev);
3121 /* print device information */
3122 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3123 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3125 pm_runtime_put(&pdev->dev);
3126 platform_set_drvdata(pdev, ndev);
3131 netif_napi_del(&mdp->napi);
3132 sh_mdio_release(mdp);
3139 pm_runtime_put(&pdev->dev);
3140 pm_runtime_disable(&pdev->dev);
3144 static int sh_eth_drv_remove(struct platform_device *pdev)
3146 struct net_device *ndev = platform_get_drvdata(pdev);
3147 struct sh_eth_private *mdp = netdev_priv(ndev);
3149 unregister_netdev(ndev);
3150 netif_napi_del(&mdp->napi);
3151 sh_mdio_release(mdp);
3152 pm_runtime_disable(&pdev->dev);
3159 #ifdef CONFIG_PM_SLEEP
3160 static int sh_eth_suspend(struct device *dev)
3162 struct net_device *ndev = dev_get_drvdata(dev);
3165 if (netif_running(ndev)) {
3166 netif_device_detach(ndev);
3167 ret = sh_eth_close(ndev);
3173 static int sh_eth_resume(struct device *dev)
3175 struct net_device *ndev = dev_get_drvdata(dev);
3178 if (netif_running(ndev)) {
3179 ret = sh_eth_open(ndev);
3182 netif_device_attach(ndev);
3189 static int sh_eth_runtime_nop(struct device *dev)
3191 /* Runtime PM callback shared between ->runtime_suspend()
3192 * and ->runtime_resume(). Simply returns success.
3194 * This driver re-initializes all registers after
3195 * pm_runtime_get_sync() anyway so there is no need
3196 * to save and restore registers here.
3201 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3202 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3203 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3205 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3207 #define SH_ETH_PM_OPS NULL
3210 static struct platform_device_id sh_eth_id_table[] = {
3211 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3212 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3213 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3214 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3215 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3216 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3217 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3220 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3222 static struct platform_driver sh_eth_driver = {
3223 .probe = sh_eth_drv_probe,
3224 .remove = sh_eth_drv_remove,
3225 .id_table = sh_eth_id_table,
3228 .pm = SH_ETH_PM_OPS,
3229 .of_match_table = of_match_ptr(sh_eth_match_table),
3233 module_platform_driver(sh_eth_driver);
3235 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3236 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3237 MODULE_LICENSE("GPL v2");