drivers/net/ethernet/renesas/sh_eth.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*  SuperH Ethernet device driver
   3  *
   4  *  Copyright (C) 2014 Renesas Electronics Corporation
   5  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   6  *  Copyright (C) 2008-2014 Renesas Solutions Corp.
   7  *  Copyright (C) 2013-2017 Cogent Embedded, Inc.
   8  *  Copyright (C) 2014 Codethink Limited
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/delay.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/mdio-bitbang.h>
  20 #include <linux/netdevice.h>
  21 #include <linux/of.h>
  22 #include <linux/of_device.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_net.h>
  25 #include <linux/phy.h>
  26 #include <linux/cache.h>
  27 #include <linux/io.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/slab.h>
  30 #include <linux/ethtool.h>
  31 #include <linux/if_vlan.h>
  32 #include <linux/sh_eth.h>
  33 #include <linux/of_mdio.h>
  34
  35 #include "sh_eth.h"
  36
  37 #define SH_ETH_DEF_MSG_ENABLE \
  38                 (NETIF_MSG_LINK | \
  39                 NETIF_MSG_TIMER | \
  40                 NETIF_MSG_RX_ERR| \
  41                 NETIF_MSG_TX_ERR)
  42
  43 #define SH_ETH_OFFSET_INVALID   ((u16)~0)
  44
  45 #define SH_ETH_OFFSET_DEFAULTS                  \
  46         [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
  47
  48 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
  49         SH_ETH_OFFSET_DEFAULTS,
  50
  51         [EDSR]          = 0x0000,
  52         [EDMR]          = 0x0400,
  53         [EDTRR]         = 0x0408,
  54         [EDRRR]         = 0x0410,
  55         [EESR]          = 0x0428,
  56         [EESIPR]        = 0x0430,
  57         [TDLAR]         = 0x0010,
  58         [TDFAR]         = 0x0014,
  59         [TDFXR]         = 0x0018,
  60         [TDFFR]         = 0x001c,
  61         [RDLAR]         = 0x0030,
  62         [RDFAR]         = 0x0034,
  63         [RDFXR]         = 0x0038,
  64         [RDFFR]         = 0x003c,
  65         [TRSCER]        = 0x0438,
  66         [RMFCR]         = 0x0440,
  67         [TFTR]          = 0x0448,
  68         [FDR]           = 0x0450,
  69         [RMCR]          = 0x0458,
  70         [RPADIR]        = 0x0460,
  71         [FCFTR]         = 0x0468,
  72         [CSMR]          = 0x04E4,
  73
  74         [ECMR]          = 0x0500,
  75         [ECSR]          = 0x0510,
  76         [ECSIPR]        = 0x0518,
  77         [PIR]           = 0x0520,
  78         [PSR]           = 0x0528,
  79         [PIPR]          = 0x052c,
  80         [RFLR]          = 0x0508,
  81         [APR]           = 0x0554,
  82         [MPR]           = 0x0558,
  83         [PFTCR]         = 0x055c,
  84         [PFRCR]         = 0x0560,
  85         [TPAUSER]       = 0x0564,
  86         [GECMR]         = 0x05b0,
  87         [BCULR]         = 0x05b4,
  88         [MAHR]          = 0x05c0,
  89         [MALR]          = 0x05c8,
  90         [TROCR]         = 0x0700,
  91         [CDCR]          = 0x0708,
  92         [LCCR]          = 0x0710,
  93         [CEFCR]         = 0x0740,
  94         [FRECR]         = 0x0748,
  95         [TSFRCR]        = 0x0750,
  96         [TLFRCR]        = 0x0758,
  97         [RFCR]          = 0x0760,
  98         [CERCR]         = 0x0768,
  99         [CEECR]         = 0x0770,
 100         [MAFCR]         = 0x0778,
 101         [RMII_MII]      = 0x0790,
 102
 103         [ARSTR]         = 0x0000,
 104         [TSU_CTRST]     = 0x0004,
 105         [TSU_FWEN0]     = 0x0010,
 106         [TSU_FWEN1]     = 0x0014,
 107         [TSU_FCM]       = 0x0018,
 108         [TSU_BSYSL0]    = 0x0020,
 109         [TSU_BSYSL1]    = 0x0024,
 110         [TSU_PRISL0]    = 0x0028,
 111         [TSU_PRISL1]    = 0x002c,
 112         [TSU_FWSL0]     = 0x0030,
 113         [TSU_FWSL1]     = 0x0034,
 114         [TSU_FWSLC]     = 0x0038,
 115         [TSU_QTAGM0]    = 0x0040,
 116         [TSU_QTAGM1]    = 0x0044,
 117         [TSU_FWSR]      = 0x0050,
 118         [TSU_FWINMK]    = 0x0054,
 119         [TSU_ADQT0]     = 0x0048,
 120         [TSU_ADQT1]     = 0x004c,
 121         [TSU_VTAG0]     = 0x0058,
 122         [TSU_VTAG1]     = 0x005c,
 123         [TSU_ADSBSY]    = 0x0060,
 124         [TSU_TEN]       = 0x0064,
 125         [TSU_POST1]     = 0x0070,
 126         [TSU_POST2]     = 0x0074,
 127         [TSU_POST3]     = 0x0078,
 128         [TSU_POST4]     = 0x007c,
 129         [TSU_ADRH0]     = 0x0100,
 130
 131         [TXNLCR0]       = 0x0080,
 132         [TXALCR0]       = 0x0084,
 133         [RXNLCR0]       = 0x0088,
 134         [RXALCR0]       = 0x008c,
 135         [FWNLCR0]       = 0x0090,
 136         [FWALCR0]       = 0x0094,
 137         [TXNLCR1]       = 0x00a0,
 138         [TXALCR1]       = 0x00a4,
 139         [RXNLCR1]       = 0x00a8,
 140         [RXALCR1]       = 0x00ac,
 141         [FWNLCR1]       = 0x00b0,
 142         [FWALCR1]       = 0x00b4,
 143 };
 144
 145 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
 146         SH_ETH_OFFSET_DEFAULTS,
 147
 148         [EDSR]          = 0x0000,
 149         [EDMR]          = 0x0400,
 150         [EDTRR]         = 0x0408,
 151         [EDRRR]         = 0x0410,
 152         [EESR]          = 0x0428,
 153         [EESIPR]        = 0x0430,
 154         [TDLAR]         = 0x0010,
 155         [TDFAR]         = 0x0014,
 156         [TDFXR]         = 0x0018,
 157         [TDFFR]         = 0x001c,
 158         [RDLAR]         = 0x0030,
 159         [RDFAR]         = 0x0034,
 160         [RDFXR]         = 0x0038,
 161         [RDFFR]         = 0x003c,
 162         [TRSCER]        = 0x0438,
 163         [RMFCR]         = 0x0440,
 164         [TFTR]          = 0x0448,
 165         [FDR]           = 0x0450,
 166         [RMCR]          = 0x0458,
 167         [RPADIR]        = 0x0460,
 168         [FCFTR]         = 0x0468,
 169         [CSMR]          = 0x04E4,
 170
 171         [ECMR]          = 0x0500,
 172         [RFLR]          = 0x0508,
 173         [ECSR]          = 0x0510,
 174         [ECSIPR]        = 0x0518,
 175         [PIR]           = 0x0520,
 176         [APR]           = 0x0554,
 177         [MPR]           = 0x0558,
 178         [PFTCR]         = 0x055c,
 179         [PFRCR]         = 0x0560,
 180         [TPAUSER]       = 0x0564,
 181         [MAHR]          = 0x05c0,
 182         [MALR]          = 0x05c8,
 183         [CEFCR]         = 0x0740,
 184         [FRECR]         = 0x0748,
 185         [TSFRCR]        = 0x0750,
 186         [TLFRCR]        = 0x0758,
 187         [RFCR]          = 0x0760,
 188         [MAFCR]         = 0x0778,
 189
 190         [ARSTR]         = 0x0000,
 191         [TSU_CTRST]     = 0x0004,
 192         [TSU_FWSLC]     = 0x0038,
 193         [TSU_VTAG0]     = 0x0058,
 194         [TSU_ADSBSY]    = 0x0060,
 195         [TSU_TEN]       = 0x0064,
 196         [TSU_POST1]     = 0x0070,
 197         [TSU_POST2]     = 0x0074,
 198         [TSU_POST3]     = 0x0078,
 199         [TSU_POST4]     = 0x007c,
 200         [TSU_ADRH0]     = 0x0100,
 201
 202         [TXNLCR0]       = 0x0080,
 203         [TXALCR0]       = 0x0084,
 204         [RXNLCR0]       = 0x0088,
 205         [RXALCR0]       = 0x008C,
 206 };
 207
 208 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
 209         SH_ETH_OFFSET_DEFAULTS,
 210
 211         [ECMR]          = 0x0300,
 212         [RFLR]          = 0x0308,
 213         [ECSR]          = 0x0310,
 214         [ECSIPR]        = 0x0318,
 215         [PIR]           = 0x0320,
 216         [PSR]           = 0x0328,
 217         [RDMLR]         = 0x0340,
 218         [IPGR]          = 0x0350,
 219         [APR]           = 0x0354,
 220         [MPR]           = 0x0358,
 221         [RFCF]          = 0x0360,
 222         [TPAUSER]       = 0x0364,
 223         [TPAUSECR]      = 0x0368,
 224         [MAHR]          = 0x03c0,
 225         [MALR]          = 0x03c8,
 226         [TROCR]         = 0x03d0,
 227         [CDCR]          = 0x03d4,
 228         [LCCR]          = 0x03d8,
 229         [CNDCR]         = 0x03dc,
 230         [CEFCR]         = 0x03e4,
 231         [FRECR]         = 0x03e8,
 232         [TSFRCR]        = 0x03ec,
 233         [TLFRCR]        = 0x03f0,
 234         [RFCR]          = 0x03f4,
 235         [MAFCR]         = 0x03f8,
 236
 237         [EDMR]          = 0x0200,
 238         [EDTRR]         = 0x0208,
 239         [EDRRR]         = 0x0210,
 240         [TDLAR]         = 0x0218,
 241         [RDLAR]         = 0x0220,
 242         [EESR]          = 0x0228,
 243         [EESIPR]        = 0x0230,
 244         [TRSCER]        = 0x0238,
 245         [RMFCR]         = 0x0240,
 246         [TFTR]          = 0x0248,
 247         [FDR]           = 0x0250,
 248         [RMCR]          = 0x0258,
 249         [TFUCR]         = 0x0264,
 250         [RFOCR]         = 0x0268,
 251         [RMIIMODE]      = 0x026c,
 252         [FCFTR]         = 0x0270,
 253         [TRIMD]         = 0x027c,
 254 };
 255
 256 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 257         SH_ETH_OFFSET_DEFAULTS,
 258
 259         [ECMR]          = 0x0100,
 260         [RFLR]          = 0x0108,
 261         [ECSR]          = 0x0110,
 262         [ECSIPR]        = 0x0118,
 263         [PIR]           = 0x0120,
 264         [PSR]           = 0x0128,
 265         [RDMLR]         = 0x0140,
 266         [IPGR]          = 0x0150,
 267         [APR]           = 0x0154,
 268         [MPR]           = 0x0158,
 269         [TPAUSER]       = 0x0164,
 270         [RFCF]          = 0x0160,
 271         [TPAUSECR]      = 0x0168,
 272         [BCFRR]         = 0x016c,
 273         [MAHR]          = 0x01c0,
 274         [MALR]          = 0x01c8,
 275         [TROCR]         = 0x01d0,
 276         [CDCR]          = 0x01d4,
 277         [LCCR]          = 0x01d8,
 278         [CNDCR]         = 0x01dc,
 279         [CEFCR]         = 0x01e4,
 280         [FRECR]         = 0x01e8,
 281         [TSFRCR]        = 0x01ec,
 282         [TLFRCR]        = 0x01f0,
 283         [RFCR]          = 0x01f4,
 284         [MAFCR]         = 0x01f8,
 285         [RTRATE]        = 0x01fc,
 286
 287         [EDMR]          = 0x0000,
 288         [EDTRR]         = 0x0008,
 289         [EDRRR]         = 0x0010,
 290         [TDLAR]         = 0x0018,
 291         [RDLAR]         = 0x0020,
 292         [EESR]          = 0x0028,
 293         [EESIPR]        = 0x0030,
 294         [TRSCER]        = 0x0038,
 295         [RMFCR]         = 0x0040,
 296         [TFTR]          = 0x0048,
 297         [FDR]           = 0x0050,
 298         [RMCR]          = 0x0058,
 299         [TFUCR]         = 0x0064,
 300         [RFOCR]         = 0x0068,
 301         [FCFTR]         = 0x0070,
 302         [RPADIR]        = 0x0078,
 303         [TRIMD]         = 0x007c,
 304         [RBWAR]         = 0x00c8,
 305         [RDFAR]         = 0x00cc,
 306         [TBRAR]         = 0x00d4,
 307         [TDFAR]         = 0x00d8,
 308 };
 309
 310 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
 311         SH_ETH_OFFSET_DEFAULTS,
 312
 313         [EDMR]          = 0x0000,
 314         [EDTRR]         = 0x0004,
 315         [EDRRR]         = 0x0008,
 316         [TDLAR]         = 0x000c,
 317         [RDLAR]         = 0x0010,
 318         [EESR]          = 0x0014,
 319         [EESIPR]        = 0x0018,
 320         [TRSCER]        = 0x001c,
 321         [RMFCR]         = 0x0020,
 322         [TFTR]          = 0x0024,
 323         [FDR]           = 0x0028,
 324         [RMCR]          = 0x002c,
 325         [EDOCR]         = 0x0030,
 326         [FCFTR]         = 0x0034,
 327         [RPADIR]        = 0x0038,
 328         [TRIMD]         = 0x003c,
 329         [RBWAR]         = 0x0040,
 330         [RDFAR]         = 0x0044,
 331         [TBRAR]         = 0x004c,
 332         [TDFAR]         = 0x0050,
 333
 334         [ECMR]          = 0x0160,
 335         [ECSR]          = 0x0164,
 336         [ECSIPR]        = 0x0168,
 337         [PIR]           = 0x016c,
 338         [MAHR]          = 0x0170,
 339         [MALR]          = 0x0174,
 340         [RFLR]          = 0x0178,
 341         [PSR]           = 0x017c,
 342         [TROCR]         = 0x0180,
 343         [CDCR]          = 0x0184,
 344         [LCCR]          = 0x0188,
 345         [CNDCR]         = 0x018c,
 346         [CEFCR]         = 0x0194,
 347         [FRECR]         = 0x0198,
 348         [TSFRCR]        = 0x019c,
 349         [TLFRCR]        = 0x01a0,
 350         [RFCR]          = 0x01a4,
 351         [MAFCR]         = 0x01a8,
 352         [IPGR]          = 0x01b4,
 353         [APR]           = 0x01b8,
 354         [MPR]           = 0x01bc,
 355         [TPAUSER]       = 0x01c4,
 356         [BCFR]          = 0x01cc,
 357
 358         [ARSTR]         = 0x0000,
 359         [TSU_CTRST]     = 0x0004,
 360         [TSU_FWEN0]     = 0x0010,
 361         [TSU_FWEN1]     = 0x0014,
 362         [TSU_FCM]       = 0x0018,
 363         [TSU_BSYSL0]    = 0x0020,
 364         [TSU_BSYSL1]    = 0x0024,
 365         [TSU_PRISL0]    = 0x0028,
 366         [TSU_PRISL1]    = 0x002c,
 367         [TSU_FWSL0]     = 0x0030,
 368         [TSU_FWSL1]     = 0x0034,
 369         [TSU_FWSLC]     = 0x0038,
 370         [TSU_QTAGM0]    = 0x0040,
 371         [TSU_QTAGM1]    = 0x0044,
 372         [TSU_ADQT0]     = 0x0048,
 373         [TSU_ADQT1]     = 0x004c,
 374         [TSU_FWSR]      = 0x0050,
 375         [TSU_FWINMK]    = 0x0054,
 376         [TSU_ADSBSY]    = 0x0060,
 377         [TSU_TEN]       = 0x0064,
 378         [TSU_POST1]     = 0x0070,
 379         [TSU_POST2]     = 0x0074,
 380         [TSU_POST3]     = 0x0078,
 381         [TSU_POST4]     = 0x007c,
 382
 383         [TXNLCR0]       = 0x0080,
 384         [TXALCR0]       = 0x0084,
 385         [RXNLCR0]       = 0x0088,
 386         [RXALCR0]       = 0x008c,
 387         [FWNLCR0]       = 0x0090,
 388         [FWALCR0]       = 0x0094,
 389         [TXNLCR1]       = 0x00a0,
 390         [TXALCR1]       = 0x00a4,
 391         [RXNLCR1]       = 0x00a8,
 392         [RXALCR1]       = 0x00ac,
 393         [FWNLCR1]       = 0x00b0,
 394         [FWALCR1]       = 0x00b4,
 395
 396         [TSU_ADRH0]     = 0x0100,
 397 };
 398
 399 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
 400 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
 401
 402 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
 403 {
 404         struct sh_eth_private *mdp = netdev_priv(ndev);
 405         u16 offset = mdp->reg_offset[enum_index];
 406
 407         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 408                 return;
 409
 410         iowrite32(data, mdp->addr + offset);
 411 }
 412
 413 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
 414 {
 415         struct sh_eth_private *mdp = netdev_priv(ndev);
 416         u16 offset = mdp->reg_offset[enum_index];
 417
 418         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 419                 return ~0U;
 420
 421         return ioread32(mdp->addr + offset);
 422 }
 423
 424 static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
 425                           u32 set)
 426 {
 427         sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
 428                      enum_index);
 429 }
 430
 431 static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index)
 432 {
 433         return mdp->reg_offset[enum_index];
 434 }
 435
 436 static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
 437                              int enum_index)
 438 {
 439         u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
 440
 441         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 442                 return;
 443
 444         iowrite32(data, mdp->tsu_addr + offset);
 445 }
 446
 447 static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
 448 {
 449         u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
 450
 451         if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
 452                 return ~0U;
 453
 454         return ioread32(mdp->tsu_addr + offset);
 455 }
 456
 457 static void sh_eth_soft_swap(char *src, int len)
 458 {
 459 #ifdef __LITTLE_ENDIAN
 460         u32 *p = (u32 *)src;
 461         u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
 462
 463         for (; p < maxp; p++)
 464                 *p = swab32(*p);
 465 #endif
 466 }
 467
 468 static void sh_eth_select_mii(struct net_device *ndev)
 469 {
 470         struct sh_eth_private *mdp = netdev_priv(ndev);
 471         u32 value;
 472
 473         switch (mdp->phy_interface) {
 474         case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
 475                 value = 0x3;
 476                 break;
 477         case PHY_INTERFACE_MODE_GMII:
 478                 value = 0x2;
 479                 break;
 480         case PHY_INTERFACE_MODE_MII:
 481                 value = 0x1;
 482                 break;
 483         case PHY_INTERFACE_MODE_RMII:
 484                 value = 0x0;
 485                 break;
 486         default:
 487                 netdev_warn(ndev,
 488                             "PHY interface mode was not setup. Set to MII.\n");
 489                 value = 0x1;
 490                 break;
 491         }
 492
 493         sh_eth_write(ndev, value, RMII_MII);
 494 }
 495
 496 static void sh_eth_set_duplex(struct net_device *ndev)
 497 {
 498         struct sh_eth_private *mdp = netdev_priv(ndev);
 499
 500         sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
 501 }
 502
 503 static void sh_eth_chip_reset(struct net_device *ndev)
 504 {
 505         struct sh_eth_private *mdp = netdev_priv(ndev);
 506
 507         /* reset device */
 508         sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
 509         mdelay(1);
 510 }
 511
 512 static int sh_eth_soft_reset(struct net_device *ndev)
 513 {
 514         sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
 515         mdelay(3);
 516         sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
 517
 518         return 0;
 519 }
 520
 521 static int sh_eth_check_soft_reset(struct net_device *ndev)
 522 {
 523         int cnt;
 524
 525         for (cnt = 100; cnt > 0; cnt--) {
 526                 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
 527                         return 0;
 528                 mdelay(1);
 529         }
 530
 531         netdev_err(ndev, "Device reset failed\n");
 532         return -ETIMEDOUT;
 533 }
 534
 535 static int sh_eth_soft_reset_gether(struct net_device *ndev)
 536 {
 537         struct sh_eth_private *mdp = netdev_priv(ndev);
 538         int ret;
 539
 540         sh_eth_write(ndev, EDSR_ENALL, EDSR);
 541         sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
 542
 543         ret = sh_eth_check_soft_reset(ndev);
 544         if (ret)
 545                 return ret;
 546
 547         /* Table Init */
 548         sh_eth_write(ndev, 0, TDLAR);
 549         sh_eth_write(ndev, 0, TDFAR);
 550         sh_eth_write(ndev, 0, TDFXR);
 551         sh_eth_write(ndev, 0, TDFFR);
 552         sh_eth_write(ndev, 0, RDLAR);
 553         sh_eth_write(ndev, 0, RDFAR);
 554         sh_eth_write(ndev, 0, RDFXR);
 555         sh_eth_write(ndev, 0, RDFFR);
 556
 557         /* Reset HW CRC register */
 558         if (mdp->cd->hw_checksum)
 559                 sh_eth_write(ndev, 0, CSMR);
 560
 561         /* Select MII mode */
 562         if (mdp->cd->select_mii)
 563                 sh_eth_select_mii(ndev);
 564
 565         return ret;
 566 }
 567
 568 static void sh_eth_set_rate_gether(struct net_device *ndev)
 569 {
 570         struct sh_eth_private *mdp = netdev_priv(ndev);
 571
 572         switch (mdp->speed) {
 573         case 10: /* 10BASE */
 574                 sh_eth_write(ndev, GECMR_10, GECMR);
 575                 break;
 576         case 100:/* 100BASE */
 577                 sh_eth_write(ndev, GECMR_100, GECMR);
 578                 break;
 579         case 1000: /* 1000BASE */
 580                 sh_eth_write(ndev, GECMR_1000, GECMR);
 581                 break;
 582         }
 583 }
 584
 585 #ifdef CONFIG_OF
 586 /* R7S72100 */
 587 static struct sh_eth_cpu_data r7s72100_data = {
 588         .soft_reset     = sh_eth_soft_reset_gether,
 589
 590         .chip_reset     = sh_eth_chip_reset,
 591         .set_duplex     = sh_eth_set_duplex,
 592
 593         .register_type  = SH_ETH_REG_FAST_RZ,
 594
 595         .edtrr_trns     = EDTRR_TRNS_GETHER,
 596         .ecsr_value     = ECSR_ICD,
 597         .ecsipr_value   = ECSIPR_ICDIP,
 598         .eesipr_value   = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
 599                           EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
 600                           EESIPR_ECIIP |
 601                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 602                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 603                           EESIPR_RMAFIP | EESIPR_RRFIP |
 604                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 605                           EESIPR_PREIP | EESIPR_CERFIP,
 606
 607         .tx_check       = EESR_TC1 | EESR_FTC,
 608         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 609                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 610                           EESR_TDE,
 611         .fdr_value      = 0x0000070f,
 612
 613         .no_psr         = 1,
 614         .apr            = 1,
 615         .mpr            = 1,
 616         .tpauser        = 1,
 617         .hw_swap        = 1,
 618         .rpadir         = 1,
 619         .no_trimd       = 1,
 620         .no_ade         = 1,
 621         .xdfar_rw       = 1,
 622         .hw_checksum    = 1,
 623         .tsu            = 1,
 624         .no_tx_cntrs    = 1,
 625 };
 626
 627 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
 628 {
 629         sh_eth_chip_reset(ndev);
 630
 631         sh_eth_select_mii(ndev);
 632 }
 633
 634 /* R8A7740 */
 635 static struct sh_eth_cpu_data r8a7740_data = {
 636         .soft_reset     = sh_eth_soft_reset_gether,
 637
 638         .chip_reset     = sh_eth_chip_reset_r8a7740,
 639         .set_duplex     = sh_eth_set_duplex,
 640         .set_rate       = sh_eth_set_rate_gether,
 641
 642         .register_type  = SH_ETH_REG_GIGABIT,
 643
 644         .edtrr_trns     = EDTRR_TRNS_GETHER,
 645         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 646         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 647         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 648                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 649                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 650                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 651                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 652                           EESIPR_CEEFIP | EESIPR_CELFIP |
 653                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 654                           EESIPR_PREIP | EESIPR_CERFIP,
 655
 656         .tx_check       = EESR_TC1 | EESR_FTC,
 657         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 658                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 659                           EESR_TDE,
 660         .fdr_value      = 0x0000070f,
 661
 662         .apr            = 1,
 663         .mpr            = 1,
 664         .tpauser        = 1,
 665         .bculr          = 1,
 666         .hw_swap        = 1,
 667         .rpadir         = 1,
 668         .no_trimd       = 1,
 669         .no_ade         = 1,
 670         .xdfar_rw       = 1,
 671         .hw_checksum    = 1,
 672         .tsu            = 1,
 673         .select_mii     = 1,
 674         .magic          = 1,
 675         .cexcr          = 1,
 676 };
 677
 678 /* There is CPU dependent code */
 679 static void sh_eth_set_rate_rcar(struct net_device *ndev)
 680 {
 681         struct sh_eth_private *mdp = netdev_priv(ndev);
 682
 683         switch (mdp->speed) {
 684         case 10: /* 10BASE */
 685                 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
 686                 break;
 687         case 100:/* 100BASE */
 688                 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
 689                 break;
 690         }
 691 }
 692
 693 /* R-Car Gen1 */
 694 static struct sh_eth_cpu_data rcar_gen1_data = {
 695         .soft_reset     = sh_eth_soft_reset,
 696
 697         .set_duplex     = sh_eth_set_duplex,
 698         .set_rate       = sh_eth_set_rate_rcar,
 699
 700         .register_type  = SH_ETH_REG_FAST_RCAR,
 701
 702         .edtrr_trns     = EDTRR_TRNS_ETHER,
 703         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 704         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 705         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 706                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 707                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 708                           EESIPR_RMAFIP | EESIPR_RRFIP |
 709                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 710                           EESIPR_PREIP | EESIPR_CERFIP,
 711
 712         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 713         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 714                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 715         .fdr_value      = 0x00000f0f,
 716
 717         .apr            = 1,
 718         .mpr            = 1,
 719         .tpauser        = 1,
 720         .hw_swap        = 1,
 721         .no_xdfar       = 1,
 722 };
 723
 724 /* R-Car Gen2 and RZ/G1 */
 725 static struct sh_eth_cpu_data rcar_gen2_data = {
 726         .soft_reset     = sh_eth_soft_reset,
 727
 728         .set_duplex     = sh_eth_set_duplex,
 729         .set_rate       = sh_eth_set_rate_rcar,
 730
 731         .register_type  = SH_ETH_REG_FAST_RCAR,
 732
 733         .edtrr_trns     = EDTRR_TRNS_ETHER,
 734         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
 735         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
 736                           ECSIPR_MPDIP,
 737         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 738                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 739                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 740                           EESIPR_RMAFIP | EESIPR_RRFIP |
 741                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 742                           EESIPR_PREIP | EESIPR_CERFIP,
 743
 744         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 745         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 746                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 747         .fdr_value      = 0x00000f0f,
 748
 749         .trscer_err_mask = DESC_I_RINT8,
 750
 751         .apr            = 1,
 752         .mpr            = 1,
 753         .tpauser        = 1,
 754         .hw_swap        = 1,
 755         .no_xdfar       = 1,
 756         .rmiimode       = 1,
 757         .magic          = 1,
 758 };
 759
 760 /* R8A77980 */
 761 static struct sh_eth_cpu_data r8a77980_data = {
 762         .soft_reset     = sh_eth_soft_reset_gether,
 763
 764         .set_duplex     = sh_eth_set_duplex,
 765         .set_rate       = sh_eth_set_rate_gether,
 766
 767         .register_type  = SH_ETH_REG_GIGABIT,
 768
 769         .edtrr_trns     = EDTRR_TRNS_GETHER,
 770         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
 771         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
 772                           ECSIPR_MPDIP,
 773         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 774                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 775                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 776                           EESIPR_RMAFIP | EESIPR_RRFIP |
 777                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 778                           EESIPR_PREIP | EESIPR_CERFIP,
 779
 780         .tx_check       = EESR_FTC | EESR_CD | EESR_TRO,
 781         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 782                           EESR_RFE | EESR_RDE | EESR_RFRMER |
 783                           EESR_TFE | EESR_TDE | EESR_ECI,
 784         .fdr_value      = 0x0000070f,
 785
 786         .apr            = 1,
 787         .mpr            = 1,
 788         .tpauser        = 1,
 789         .bculr          = 1,
 790         .hw_swap        = 1,
 791         .nbst           = 1,
 792         .rpadir         = 1,
 793         .no_trimd       = 1,
 794         .no_ade         = 1,
 795         .xdfar_rw       = 1,
 796         .hw_checksum    = 1,
 797         .select_mii     = 1,
 798         .magic          = 1,
 799         .cexcr          = 1,
 800 };
 801 #endif /* CONFIG_OF */
 802
 803 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
 804 {
 805         struct sh_eth_private *mdp = netdev_priv(ndev);
 806
 807         switch (mdp->speed) {
 808         case 10: /* 10BASE */
 809                 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
 810                 break;
 811         case 100:/* 100BASE */
 812                 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
 813                 break;
 814         }
 815 }
 816
 817 /* SH7724 */
 818 static struct sh_eth_cpu_data sh7724_data = {
 819         .soft_reset     = sh_eth_soft_reset,
 820
 821         .set_duplex     = sh_eth_set_duplex,
 822         .set_rate       = sh_eth_set_rate_sh7724,
 823
 824         .register_type  = SH_ETH_REG_FAST_SH4,
 825
 826         .edtrr_trns     = EDTRR_TRNS_ETHER,
 827         .ecsr_value     = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 828         .ecsipr_value   = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
 829         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
 830                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 831                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 832                           EESIPR_RMAFIP | EESIPR_RRFIP |
 833                           EESIPR_RTLFIP | EESIPR_RTSFIP |
 834                           EESIPR_PREIP | EESIPR_CERFIP,
 835
 836         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 837         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 838                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 839
 840         .apr            = 1,
 841         .mpr            = 1,
 842         .tpauser        = 1,
 843         .hw_swap        = 1,
 844         .rpadir         = 1,
 845 };
 846
 847 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
 848 {
 849         struct sh_eth_private *mdp = netdev_priv(ndev);
 850
 851         switch (mdp->speed) {
 852         case 10: /* 10BASE */
 853                 sh_eth_write(ndev, 0, RTRATE);
 854                 break;
 855         case 100:/* 100BASE */
 856                 sh_eth_write(ndev, 1, RTRATE);
 857                 break;
 858         }
 859 }
 860
 861 /* SH7757 */
 862 static struct sh_eth_cpu_data sh7757_data = {
 863         .soft_reset     = sh_eth_soft_reset,
 864
 865         .set_duplex     = sh_eth_set_duplex,
 866         .set_rate       = sh_eth_set_rate_sh7757,
 867
 868         .register_type  = SH_ETH_REG_FAST_SH4,
 869
 870         .edtrr_trns     = EDTRR_TRNS_ETHER,
 871         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 872                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 873                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 874                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 875                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 876                           EESIPR_CEEFIP | EESIPR_CELFIP |
 877                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 878                           EESIPR_PREIP | EESIPR_CERFIP,
 879
 880         .tx_check       = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
 881         .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
 882                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
 883
 884         .irq_flags      = IRQF_SHARED,
 885         .apr            = 1,
 886         .mpr            = 1,
 887         .tpauser        = 1,
 888         .hw_swap        = 1,
 889         .no_ade         = 1,
 890         .rpadir         = 1,
 891         .rtrate         = 1,
 892         .dual_port      = 1,
 893 };
 894
 895 #define SH_GIGA_ETH_BASE        0xfee00000UL
 896 #define GIGA_MALR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
 897 #define GIGA_MAHR(port)         (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
 898 static void sh_eth_chip_reset_giga(struct net_device *ndev)
 899 {
 900         u32 mahr[2], malr[2];
 901         int i;
 902
 903         /* save MAHR and MALR */
 904         for (i = 0; i < 2; i++) {
 905                 malr[i] = ioread32((void *)GIGA_MALR(i));
 906                 mahr[i] = ioread32((void *)GIGA_MAHR(i));
 907         }
 908
 909         sh_eth_chip_reset(ndev);
 910
 911         /* restore MAHR and MALR */
 912         for (i = 0; i < 2; i++) {
 913                 iowrite32(malr[i], (void *)GIGA_MALR(i));
 914                 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
 915         }
 916 }
 917
 918 static void sh_eth_set_rate_giga(struct net_device *ndev)
 919 {
 920         struct sh_eth_private *mdp = netdev_priv(ndev);
 921
 922         switch (mdp->speed) {
 923         case 10: /* 10BASE */
 924                 sh_eth_write(ndev, 0x00000000, GECMR);
 925                 break;
 926         case 100:/* 100BASE */
 927                 sh_eth_write(ndev, 0x00000010, GECMR);
 928                 break;
 929         case 1000: /* 1000BASE */
 930                 sh_eth_write(ndev, 0x00000020, GECMR);
 931                 break;
 932         }
 933 }
 934
 935 /* SH7757(GETHERC) */
 936 static struct sh_eth_cpu_data sh7757_data_giga = {
 937         .soft_reset     = sh_eth_soft_reset_gether,
 938
 939         .chip_reset     = sh_eth_chip_reset_giga,
 940         .set_duplex     = sh_eth_set_duplex,
 941         .set_rate       = sh_eth_set_rate_giga,
 942
 943         .register_type  = SH_ETH_REG_GIGABIT,
 944
 945         .edtrr_trns     = EDTRR_TRNS_GETHER,
 946         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 947         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 948         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 949                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 950                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 951                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
 952                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
 953                           EESIPR_CEEFIP | EESIPR_CELFIP |
 954                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 955                           EESIPR_PREIP | EESIPR_CERFIP,
 956
 957         .tx_check       = EESR_TC1 | EESR_FTC,
 958         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
 959                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
 960                           EESR_TDE,
 961         .fdr_value      = 0x0000072f,
 962
 963         .irq_flags      = IRQF_SHARED,
 964         .apr            = 1,
 965         .mpr            = 1,
 966         .tpauser        = 1,
 967         .bculr          = 1,
 968         .hw_swap        = 1,
 969         .rpadir         = 1,
 970         .no_trimd       = 1,
 971         .no_ade         = 1,
 972         .xdfar_rw       = 1,
 973         .tsu            = 1,
 974         .cexcr          = 1,
 975         .dual_port      = 1,
 976 };
 977
 978 /* SH7734 */
 979 static struct sh_eth_cpu_data sh7734_data = {
 980         .soft_reset     = sh_eth_soft_reset_gether,
 981
 982         .chip_reset     = sh_eth_chip_reset,
 983         .set_duplex     = sh_eth_set_duplex,
 984         .set_rate       = sh_eth_set_rate_gether,
 985
 986         .register_type  = SH_ETH_REG_GIGABIT,
 987
 988         .edtrr_trns     = EDTRR_TRNS_GETHER,
 989         .ecsr_value     = ECSR_ICD | ECSR_MPD,
 990         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
 991         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
 992                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
 993                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
 994                           EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
 995                           EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
 996                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
 997                           EESIPR_PREIP | EESIPR_CERFIP,
 998
 999         .tx_check       = EESR_TC1 | EESR_FTC,
1000         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1001                           EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1002                           EESR_TDE,
1003
1004         .apr            = 1,
1005         .mpr            = 1,
1006         .tpauser        = 1,
1007         .bculr          = 1,
1008         .hw_swap        = 1,
1009         .no_trimd       = 1,
1010         .no_ade         = 1,
1011         .xdfar_rw       = 1,
1012         .tsu            = 1,
1013         .hw_checksum    = 1,
1014         .select_mii     = 1,
1015         .magic          = 1,
1016         .cexcr          = 1,
1017 };
1018
1019 /* SH7763 */
1020 static struct sh_eth_cpu_data sh7763_data = {
1021         .soft_reset     = sh_eth_soft_reset_gether,
1022
1023         .chip_reset     = sh_eth_chip_reset,
1024         .set_duplex     = sh_eth_set_duplex,
1025         .set_rate       = sh_eth_set_rate_gether,
1026
1027         .register_type  = SH_ETH_REG_GIGABIT,
1028
1029         .edtrr_trns     = EDTRR_TRNS_GETHER,
1030         .ecsr_value     = ECSR_ICD | ECSR_MPD,
1031         .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1032         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1033                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1034                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1035                           EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1036                           EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1037                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1038                           EESIPR_PREIP | EESIPR_CERFIP,
1039
1040         .tx_check       = EESR_TC1 | EESR_FTC,
1041         .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1042                           EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1043
1044         .apr            = 1,
1045         .mpr            = 1,
1046         .tpauser        = 1,
1047         .bculr          = 1,
1048         .hw_swap        = 1,
1049         .no_trimd       = 1,
1050         .no_ade         = 1,
1051         .xdfar_rw       = 1,
1052         .tsu            = 1,
1053         .irq_flags      = IRQF_SHARED,
1054         .magic          = 1,
1055         .cexcr          = 1,
1056         .dual_port      = 1,
1057 };
1058
1059 static struct sh_eth_cpu_data sh7619_data = {
1060         .soft_reset     = sh_eth_soft_reset,
1061
1062         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
1063
1064         .edtrr_trns     = EDTRR_TRNS_ETHER,
1065         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1066                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1067                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1068                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1069                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1070                           EESIPR_CEEFIP | EESIPR_CELFIP |
1071                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1072                           EESIPR_PREIP | EESIPR_CERFIP,
1073
1074         .apr            = 1,
1075         .mpr            = 1,
1076         .tpauser        = 1,
1077         .hw_swap        = 1,
1078 };
1079
1080 static struct sh_eth_cpu_data sh771x_data = {
1081         .soft_reset     = sh_eth_soft_reset,
1082
1083         .register_type  = SH_ETH_REG_FAST_SH3_SH2,
1084
1085         .edtrr_trns     = EDTRR_TRNS_ETHER,
1086         .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
1087                           EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1088                           EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1089                           0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1090                           EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1091                           EESIPR_CEEFIP | EESIPR_CELFIP |
1092                           EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1093                           EESIPR_PREIP | EESIPR_CERFIP,
1094         .tsu            = 1,
1095         .dual_port      = 1,
1096 };
1097
1098 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1099 {
1100         if (!cd->ecsr_value)
1101                 cd->ecsr_value = DEFAULT_ECSR_INIT;
1102
1103         if (!cd->ecsipr_value)
1104                 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1105
1106         if (!cd->fcftr_value)
1107                 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1108                                   DEFAULT_FIFO_F_D_RFD;
1109
1110         if (!cd->fdr_value)
1111                 cd->fdr_value = DEFAULT_FDR_INIT;
1112
1113         if (!cd->tx_check)
1114                 cd->tx_check = DEFAULT_TX_CHECK;
1115
1116         if (!cd->eesr_err_check)
1117                 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1118
1119         if (!cd->trscer_err_mask)
1120                 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1121 }
1122
1123 static void sh_eth_set_receive_align(struct sk_buff *skb)
1124 {
1125         uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1126
1127         if (reserve)
1128                 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1129 }
1130
1131 /* Program the hardware MAC address from dev->dev_addr. */
1132 static void update_mac_address(struct net_device *ndev)
1133 {
1134         sh_eth_write(ndev,
1135                      (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1136                      (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1137         sh_eth_write(ndev,
1138                      (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1139 }
1140
1141 /* Get MAC address from SuperH MAC address register
1142  *
1143  * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1144  * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1145  * When you want use this device, you must set MAC address in bootloader.
1146  *
1147  */
1148 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1149 {
1150         if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1151                 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1152         } else {
1153                 u32 mahr = sh_eth_read(ndev, MAHR);
1154                 u32 malr = sh_eth_read(ndev, MALR);
1155
1156                 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1157                 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1158                 ndev->dev_addr[2] = (mahr >>  8) & 0xFF;
1159                 ndev->dev_addr[3] = (mahr >>  0) & 0xFF;
1160                 ndev->dev_addr[4] = (malr >>  8) & 0xFF;
1161                 ndev->dev_addr[5] = (malr >>  0) & 0xFF;
1162         }
1163 }
1164
1165 struct bb_info {
1166         void (*set_gate)(void *addr);
1167         struct mdiobb_ctrl ctrl;
1168         void *addr;
1169 };
1170
1171 static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1172 {
1173         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1174         u32 pir;
1175
1176         if (bitbang->set_gate)
1177                 bitbang->set_gate(bitbang->addr);
1178
1179         pir = ioread32(bitbang->addr);
1180         if (set)
1181                 pir |=  mask;
1182         else
1183                 pir &= ~mask;
1184         iowrite32(pir, bitbang->addr);
1185 }
1186
1187 /* Data I/O pin control */
1188 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1189 {
1190         sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1191 }
1192
1193 /* Set bit data*/
1194 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1195 {
1196         sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1197 }
1198
1199 /* Get bit data*/
1200 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1201 {
1202         struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1203
1204         if (bitbang->set_gate)
1205                 bitbang->set_gate(bitbang->addr);
1206
1207         return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1208 }
1209
1210 /* MDC pin control */
1211 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1212 {
1213         sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1214 }
1215
1216 /* mdio bus control struct */
1217 static struct mdiobb_ops bb_ops = {
1218         .owner = THIS_MODULE,
1219         .set_mdc = sh_mdc_ctrl,
1220         .set_mdio_dir = sh_mmd_ctrl,
1221         .set_mdio_data = sh_set_mdio,
1222         .get_mdio_data = sh_get_mdio,
1223 };
1224
1225 /* free Tx skb function */
1226 static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1227 {
1228         struct sh_eth_private *mdp = netdev_priv(ndev);
1229         struct sh_eth_txdesc *txdesc;
1230         int free_num = 0;
1231         int entry;
1232         bool sent;
1233
1234         for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1235                 entry = mdp->dirty_tx % mdp->num_tx_ring;
1236                 txdesc = &mdp->tx_ring[entry];
1237                 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1238                 if (sent_only && !sent)
1239                         break;
1240                 /* TACT bit must be checked before all the following reads */
1241                 dma_rmb();
1242                 netif_info(mdp, tx_done, ndev,
1243                            "tx entry %d status 0x%08x\n",
1244                            entry, le32_to_cpu(txdesc->status));
1245                 /* Free the original skb. */
1246                 if (mdp->tx_skbuff[entry]) {
1247                         dma_unmap_single(&mdp->pdev->dev,
1248                                          le32_to_cpu(txdesc->addr),
1249                                          le32_to_cpu(txdesc->len) >> 16,
1250                                          DMA_TO_DEVICE);
1251                         dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1252                         mdp->tx_skbuff[entry] = NULL;
1253                         free_num++;
1254                 }
1255                 txdesc->status = cpu_to_le32(TD_TFP);
1256                 if (entry >= mdp->num_tx_ring - 1)
1257                         txdesc->status |= cpu_to_le32(TD_TDLE);
1258
1259                 if (sent) {
1260                         ndev->stats.tx_packets++;
1261                         ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1262                 }
1263         }
1264         return free_num;
1265 }
1266
1267 /* free skb and descriptor buffer */
1268 static void sh_eth_ring_free(struct net_device *ndev)
1269 {
1270         struct sh_eth_private *mdp = netdev_priv(ndev);
1271         int ringsize, i;
1272
1273         if (mdp->rx_ring) {
1274                 for (i = 0; i < mdp->num_rx_ring; i++) {
1275                         if (mdp->rx_skbuff[i]) {
1276                                 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1277
1278                                 dma_unmap_single(&mdp->pdev->dev,
1279                                                  le32_to_cpu(rxdesc->addr),
1280                                                  ALIGN(mdp->rx_buf_sz, 32),
1281                                                  DMA_FROM_DEVICE);
1282                         }
1283                 }
1284                 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1285                 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1286                                   mdp->rx_desc_dma);
1287                 mdp->rx_ring = NULL;
1288         }
1289
1290         /* Free Rx skb ringbuffer */
1291         if (mdp->rx_skbuff) {
1292                 for (i = 0; i < mdp->num_rx_ring; i++)
1293                         dev_kfree_skb(mdp->rx_skbuff[i]);
1294         }
1295         kfree(mdp->rx_skbuff);
1296         mdp->rx_skbuff = NULL;
1297
1298         if (mdp->tx_ring) {
1299                 sh_eth_tx_free(ndev, false);
1300
1301                 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1302                 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1303                                   mdp->tx_desc_dma);
1304                 mdp->tx_ring = NULL;
1305         }
1306
1307         /* Free Tx skb ringbuffer */
1308         kfree(mdp->tx_skbuff);
1309         mdp->tx_skbuff = NULL;
1310 }
1311
1312 /* format skb and descriptor buffer */
1313 static void sh_eth_ring_format(struct net_device *ndev)
1314 {
1315         struct sh_eth_private *mdp = netdev_priv(ndev);
1316         int i;
1317         struct sk_buff *skb;
1318         struct sh_eth_rxdesc *rxdesc = NULL;
1319         struct sh_eth_txdesc *txdesc = NULL;
1320         int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1321         int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1322         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1323         dma_addr_t dma_addr;
1324         u32 buf_len;
1325
1326         mdp->cur_rx = 0;
1327         mdp->cur_tx = 0;
1328         mdp->dirty_rx = 0;
1329         mdp->dirty_tx = 0;
1330
1331         memset(mdp->rx_ring, 0, rx_ringsize);
1332
1333         /* build Rx ring buffer */
1334         for (i = 0; i < mdp->num_rx_ring; i++) {
1335                 /* skb */
1336                 mdp->rx_skbuff[i] = NULL;
1337                 skb = netdev_alloc_skb(ndev, skbuff_size);
1338                 if (skb == NULL)
1339                         break;
1340                 sh_eth_set_receive_align(skb);
1341
1342                 /* The size of the buffer is a multiple of 32 bytes. */
1343                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1344                 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1345                                           DMA_FROM_DEVICE);
1346                 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1347                         kfree_skb(skb);
1348                         break;
1349                 }
1350                 mdp->rx_skbuff[i] = skb;
1351
1352                 /* RX descriptor */
1353                 rxdesc = &mdp->rx_ring[i];
1354                 rxdesc->len = cpu_to_le32(buf_len << 16);
1355                 rxdesc->addr = cpu_to_le32(dma_addr);
1356                 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1357
1358                 /* Rx descriptor address set */
1359                 if (i == 0) {
1360                         sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1361                         if (mdp->cd->xdfar_rw)
1362                                 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1363                 }
1364         }
1365
1366         mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1367
1368         /* Mark the last entry as wrapping the ring. */
1369         if (rxdesc)
1370                 rxdesc->status |= cpu_to_le32(RD_RDLE);
1371
1372         memset(mdp->tx_ring, 0, tx_ringsize);
1373
1374         /* build Tx ring buffer */
1375         for (i = 0; i < mdp->num_tx_ring; i++) {
1376                 mdp->tx_skbuff[i] = NULL;
1377                 txdesc = &mdp->tx_ring[i];
1378                 txdesc->status = cpu_to_le32(TD_TFP);
1379                 txdesc->len = cpu_to_le32(0);
1380                 if (i == 0) {
1381                         /* Tx descriptor address set */
1382                         sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1383                         if (mdp->cd->xdfar_rw)
1384                                 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1385                 }
1386         }
1387
1388         txdesc->status |= cpu_to_le32(TD_TDLE);
1389 }
1390
1391 /* Get skb and descriptor buffer */
1392 static int sh_eth_ring_init(struct net_device *ndev)
1393 {
1394         struct sh_eth_private *mdp = netdev_priv(ndev);
1395         int rx_ringsize, tx_ringsize;
1396
1397         /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1398          * card needs room to do 8 byte alignment, +2 so we can reserve
1399          * the first 2 bytes, and +16 gets room for the status word from the
1400          * card.
1401          */
1402         mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1403                           (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1404         if (mdp->cd->rpadir)
1405                 mdp->rx_buf_sz += NET_IP_ALIGN;
1406
1407         /* Allocate RX and TX skb rings */
1408         mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1409                                  GFP_KERNEL);
1410         if (!mdp->rx_skbuff)
1411                 return -ENOMEM;
1412
1413         mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1414                                  GFP_KERNEL);
1415         if (!mdp->tx_skbuff)
1416                 goto ring_free;
1417
1418         /* Allocate all Rx descriptors. */
1419         rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1420         mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1421                                           &mdp->rx_desc_dma, GFP_KERNEL);
1422         if (!mdp->rx_ring)
1423                 goto ring_free;
1424
1425         mdp->dirty_rx = 0;
1426
1427         /* Allocate all Tx descriptors. */
1428         tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1429         mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1430                                           &mdp->tx_desc_dma, GFP_KERNEL);
1431         if (!mdp->tx_ring)
1432                 goto ring_free;
1433         return 0;
1434
1435 ring_free:
1436         /* Free Rx and Tx skb ring buffer and DMA buffer */
1437         sh_eth_ring_free(ndev);
1438
1439         return -ENOMEM;
1440 }
1441
1442 static int sh_eth_dev_init(struct net_device *ndev)
1443 {
1444         struct sh_eth_private *mdp = netdev_priv(ndev);
1445         int ret;
1446
1447         /* Soft Reset */
1448         ret = mdp->cd->soft_reset(ndev);
1449         if (ret)
1450                 return ret;
1451
1452         if (mdp->cd->rmiimode)
1453                 sh_eth_write(ndev, 0x1, RMIIMODE);
1454
1455         /* Descriptor format */
1456         sh_eth_ring_format(ndev);
1457         if (mdp->cd->rpadir)
1458                 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR);
1459
1460         /* all sh_eth int mask */
1461         sh_eth_write(ndev, 0, EESIPR);
1462
1463 #if defined(__LITTLE_ENDIAN)
1464         if (mdp->cd->hw_swap)
1465                 sh_eth_write(ndev, EDMR_EL, EDMR);
1466         else
1467 #endif
1468                 sh_eth_write(ndev, 0, EDMR);
1469
1470         /* FIFO size set */
1471         sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1472         sh_eth_write(ndev, 0, TFTR);
1473
1474         /* Frame recv control (enable multiple-packets per rx irq) */
1475         sh_eth_write(ndev, RMCR_RNC, RMCR);
1476
1477         sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1478
1479         /* DMA transfer burst mode */
1480         if (mdp->cd->nbst)
1481                 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1482
1483         /* Burst cycle count upper-limit */
1484         if (mdp->cd->bculr)
1485                 sh_eth_write(ndev, 0x800, BCULR);
1486
1487         sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1488
1489         if (!mdp->cd->no_trimd)
1490                 sh_eth_write(ndev, 0, TRIMD);
1491
1492         /* Recv frame limit set register */
1493         sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1494                      RFLR);
1495
1496         sh_eth_modify(ndev, EESR, 0, 0);
1497         mdp->irq_enabled = true;
1498         sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1499
1500         /* PAUSE Prohibition */
1501         sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1502                      ECMR_TE | ECMR_RE, ECMR);
1503
1504         if (mdp->cd->set_rate)
1505                 mdp->cd->set_rate(ndev);
1506
1507         /* E-MAC Status Register clear */
1508         sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1509
1510         /* E-MAC Interrupt Enable register */
1511         sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1512
1513         /* Set MAC address */
1514         update_mac_address(ndev);
1515
1516         /* mask reset */
1517         if (mdp->cd->apr)
1518                 sh_eth_write(ndev, 1, APR);
1519         if (mdp->cd->mpr)
1520                 sh_eth_write(ndev, 1, MPR);
1521         if (mdp->cd->tpauser)
1522                 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1523
1524         /* Setting the Rx mode will start the Rx process. */
1525         sh_eth_write(ndev, EDRRR_R, EDRRR);
1526
1527         return ret;
1528 }
1529
1530 static void sh_eth_dev_exit(struct net_device *ndev)
1531 {
1532         struct sh_eth_private *mdp = netdev_priv(ndev);
1533         int i;
1534
1535         /* Deactivate all TX descriptors, so DMA should stop at next
1536          * packet boundary if it's currently running
1537          */
1538         for (i = 0; i < mdp->num_tx_ring; i++)
1539                 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1540
1541         /* Disable TX FIFO egress to MAC */
1542         sh_eth_rcv_snd_disable(ndev);
1543
1544         /* Stop RX DMA at next packet boundary */
1545         sh_eth_write(ndev, 0, EDRRR);
1546
1547         /* Aside from TX DMA, we can't tell when the hardware is
1548          * really stopped, so we need to reset to make sure.
1549          * Before doing that, wait for long enough to *probably*
1550          * finish transmitting the last packet and poll stats.
1551          */
1552         msleep(2); /* max frame time at 10 Mbps < 1250 us */
1553         sh_eth_get_stats(ndev);
1554         mdp->cd->soft_reset(ndev);
1555
1556         /* Set MAC address again */
1557         update_mac_address(ndev);
1558 }
1559
1560 /* Packet receive function */
1561 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1562 {
1563         struct sh_eth_private *mdp = netdev_priv(ndev);
1564         struct sh_eth_rxdesc *rxdesc;
1565
1566         int entry = mdp->cur_rx % mdp->num_rx_ring;
1567         int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1568         int limit;
1569         struct sk_buff *skb;
1570         u32 desc_status;
1571         int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1572         dma_addr_t dma_addr;
1573         u16 pkt_len;
1574         u32 buf_len;
1575
1576         boguscnt = min(boguscnt, *quota);
1577         limit = boguscnt;
1578         rxdesc = &mdp->rx_ring[entry];
1579         while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1580                 /* RACT bit must be checked before all the following reads */
1581                 dma_rmb();
1582                 desc_status = le32_to_cpu(rxdesc->status);
1583                 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1584
1585                 if (--boguscnt < 0)
1586                         break;
1587
1588                 netif_info(mdp, rx_status, ndev,
1589                            "rx entry %d status 0x%08x len %d\n",
1590                            entry, desc_status, pkt_len);
1591
1592                 if (!(desc_status & RDFEND))
1593                         ndev->stats.rx_length_errors++;
1594
1595                 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1596                  * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1597                  * bit 0. However, in case of the R8A7740 and R7S72100
1598                  * the RFS bits are from bit 25 to bit 16. So, the
1599                  * driver needs right shifting by 16.
1600                  */
1601                 if (mdp->cd->hw_checksum)
1602                         desc_status >>= 16;
1603
1604                 skb = mdp->rx_skbuff[entry];
1605                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1606                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1607                         ndev->stats.rx_errors++;
1608                         if (desc_status & RD_RFS1)
1609                                 ndev->stats.rx_crc_errors++;
1610                         if (desc_status & RD_RFS2)
1611                                 ndev->stats.rx_frame_errors++;
1612                         if (desc_status & RD_RFS3)
1613                                 ndev->stats.rx_length_errors++;
1614                         if (desc_status & RD_RFS4)
1615                                 ndev->stats.rx_length_errors++;
1616                         if (desc_status & RD_RFS6)
1617                                 ndev->stats.rx_missed_errors++;
1618                         if (desc_status & RD_RFS10)
1619                                 ndev->stats.rx_over_errors++;
1620                 } else  if (skb) {
1621                         dma_addr = le32_to_cpu(rxdesc->addr);
1622                         if (!mdp->cd->hw_swap)
1623                                 sh_eth_soft_swap(
1624                                         phys_to_virt(ALIGN(dma_addr, 4)),
1625                                         pkt_len + 2);
1626                         mdp->rx_skbuff[entry] = NULL;
1627                         if (mdp->cd->rpadir)
1628                                 skb_reserve(skb, NET_IP_ALIGN);
1629                         dma_unmap_single(&mdp->pdev->dev, dma_addr,
1630                                          ALIGN(mdp->rx_buf_sz, 32),
1631                                          DMA_FROM_DEVICE);
1632                         skb_put(skb, pkt_len);
1633                         skb->protocol = eth_type_trans(skb, ndev);
1634                         netif_receive_skb(skb);
1635                         ndev->stats.rx_packets++;
1636                         ndev->stats.rx_bytes += pkt_len;
1637                         if (desc_status & RD_RFS8)
1638                                 ndev->stats.multicast++;
1639                 }
1640                 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1641                 rxdesc = &mdp->rx_ring[entry];
1642         }
1643
1644         /* Refill the Rx ring buffers. */
1645         for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1646                 entry = mdp->dirty_rx % mdp->num_rx_ring;
1647                 rxdesc = &mdp->rx_ring[entry];
1648                 /* The size of the buffer is 32 byte boundary. */
1649                 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1650                 rxdesc->len = cpu_to_le32(buf_len << 16);
1651
1652                 if (mdp->rx_skbuff[entry] == NULL) {
1653                         skb = netdev_alloc_skb(ndev, skbuff_size);
1654                         if (skb == NULL)
1655                                 break;  /* Better luck next round. */
1656                         sh_eth_set_receive_align(skb);
1657                         dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1658                                                   buf_len, DMA_FROM_DEVICE);
1659                         if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1660                                 kfree_skb(skb);
1661                                 break;
1662                         }
1663                         mdp->rx_skbuff[entry] = skb;
1664
1665                         skb_checksum_none_assert(skb);
1666                         rxdesc->addr = cpu_to_le32(dma_addr);
1667                 }
1668                 dma_wmb(); /* RACT bit must be set after all the above writes */
1669                 if (entry >= mdp->num_rx_ring - 1)
1670                         rxdesc->status |=
1671                                 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1672                 else
1673                         rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1674         }
1675
1676         /* Restart Rx engine if stopped. */
1677         /* If we don't need to check status, don't. -KDU */
1678         if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1679                 /* fix the values for the next receiving if RDE is set */
1680                 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1681                         u32 count = (sh_eth_read(ndev, RDFAR) -
1682                                      sh_eth_read(ndev, RDLAR)) >> 4;
1683
1684                         mdp->cur_rx = count;
1685                         mdp->dirty_rx = count;
1686                 }
1687                 sh_eth_write(ndev, EDRRR_R, EDRRR);
1688         }
1689
1690         *quota -= limit - boguscnt - 1;
1691
1692         return *quota <= 0;
1693 }
1694
1695 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1696 {
1697         /* disable tx and rx */
1698         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1699 }
1700
1701 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1702 {
1703         /* enable tx and rx */
1704         sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1705 }
1706
1707 /* E-MAC interrupt handler */
1708 static void sh_eth_emac_interrupt(struct net_device *ndev)
1709 {
1710         struct sh_eth_private *mdp = netdev_priv(ndev);
1711         u32 felic_stat;
1712         u32 link_stat;
1713
1714         felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1715         sh_eth_write(ndev, felic_stat, ECSR);   /* clear int */
1716         if (felic_stat & ECSR_ICD)
1717                 ndev->stats.tx_carrier_errors++;
1718         if (felic_stat & ECSR_MPD)
1719                 pm_wakeup_event(&mdp->pdev->dev, 0);
1720         if (felic_stat & ECSR_LCHNG) {
1721                 /* Link Changed */
1722                 if (mdp->cd->no_psr || mdp->no_ether_link)
1723                         return;
1724                 link_stat = sh_eth_read(ndev, PSR);
1725                 if (mdp->ether_link_active_low)
1726                         link_stat = ~link_stat;
1727                 if (!(link_stat & PHY_ST_LINK)) {
1728                         sh_eth_rcv_snd_disable(ndev);
1729                 } else {
1730                         /* Link Up */
1731                         sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1732                         /* clear int */
1733                         sh_eth_modify(ndev, ECSR, 0, 0);
1734                         sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1735                         /* enable tx and rx */
1736                         sh_eth_rcv_snd_enable(ndev);
1737                 }
1738         }
1739 }
1740
1741 /* error control function */
1742 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1743 {
1744         struct sh_eth_private *mdp = netdev_priv(ndev);
1745         u32 mask;
1746
1747         if (intr_status & EESR_TWB) {
1748                 /* Unused write back interrupt */
1749                 if (intr_status & EESR_TABT) {  /* Transmit Abort int */
1750                         ndev->stats.tx_aborted_errors++;
1751                         netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1752                 }
1753         }
1754
1755         if (intr_status & EESR_RABT) {
1756                 /* Receive Abort int */
1757                 if (intr_status & EESR_RFRMER) {
1758                         /* Receive Frame Overflow int */
1759                         ndev->stats.rx_frame_errors++;
1760                 }
1761         }
1762
1763         if (intr_status & EESR_TDE) {
1764                 /* Transmit Descriptor Empty int */
1765                 ndev->stats.tx_fifo_errors++;
1766                 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1767         }
1768
1769         if (intr_status & EESR_TFE) {
1770                 /* FIFO under flow */
1771                 ndev->stats.tx_fifo_errors++;
1772                 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1773         }
1774
1775         if (intr_status & EESR_RDE) {
1776                 /* Receive Descriptor Empty int */
1777                 ndev->stats.rx_over_errors++;
1778         }
1779
1780         if (intr_status & EESR_RFE) {
1781                 /* Receive FIFO Overflow int */
1782                 ndev->stats.rx_fifo_errors++;
1783         }
1784
1785         if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1786                 /* Address Error */
1787                 ndev->stats.tx_fifo_errors++;
1788                 netif_err(mdp, tx_err, ndev, "Address Error\n");
1789         }
1790
1791         mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1792         if (mdp->cd->no_ade)
1793                 mask &= ~EESR_ADE;
1794         if (intr_status & mask) {
1795                 /* Tx error */
1796                 u32 edtrr = sh_eth_read(ndev, EDTRR);
1797
1798                 /* dmesg */
1799                 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1800                            intr_status, mdp->cur_tx, mdp->dirty_tx,
1801                            (u32)ndev->state, edtrr);
1802                 /* dirty buffer free */
1803                 sh_eth_tx_free(ndev, true);
1804
1805                 /* SH7712 BUG */
1806                 if (edtrr ^ mdp->cd->edtrr_trns) {
1807                         /* tx dma start */
1808                         sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1809                 }
1810                 /* wakeup */
1811                 netif_wake_queue(ndev);
1812         }
1813 }
1814
1815 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1816 {
1817         struct net_device *ndev = netdev;
1818         struct sh_eth_private *mdp = netdev_priv(ndev);
1819         struct sh_eth_cpu_data *cd = mdp->cd;
1820         irqreturn_t ret = IRQ_NONE;
1821         u32 intr_status, intr_enable;
1822
1823         spin_lock(&mdp->lock);
1824
1825         /* Get interrupt status */
1826         intr_status = sh_eth_read(ndev, EESR);
1827         /* Mask it with the interrupt mask, forcing ECI interrupt  to be always
1828          * enabled since it's the one that  comes  thru regardless of the mask,
1829          * and  we need to fully handle it  in sh_eth_emac_interrupt() in order
1830          * to quench it as it doesn't get cleared by just writing 1 to the  ECI
1831          * bit...
1832          */
1833         intr_enable = sh_eth_read(ndev, EESIPR);
1834         intr_status &= intr_enable | EESIPR_ECIIP;
1835         if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1836                            cd->eesr_err_check))
1837                 ret = IRQ_HANDLED;
1838         else
1839                 goto out;
1840
1841         if (unlikely(!mdp->irq_enabled)) {
1842                 sh_eth_write(ndev, 0, EESIPR);
1843                 goto out;
1844         }
1845
1846         if (intr_status & EESR_RX_CHECK) {
1847                 if (napi_schedule_prep(&mdp->napi)) {
1848                         /* Mask Rx interrupts */
1849                         sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1850                                      EESIPR);
1851                         __napi_schedule(&mdp->napi);
1852                 } else {
1853                         netdev_warn(ndev,
1854                                     "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1855                                     intr_status, intr_enable);
1856                 }
1857         }
1858
1859         /* Tx Check */
1860         if (intr_status & cd->tx_check) {
1861                 /* Clear Tx interrupts */
1862                 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1863
1864                 sh_eth_tx_free(ndev, true);
1865                 netif_wake_queue(ndev);
1866         }
1867
1868         /* E-MAC interrupt */
1869         if (intr_status & EESR_ECI)
1870                 sh_eth_emac_interrupt(ndev);
1871
1872         if (intr_status & cd->eesr_err_check) {
1873                 /* Clear error interrupts */
1874                 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1875
1876                 sh_eth_error(ndev, intr_status);
1877         }
1878
1879 out:
1880         spin_unlock(&mdp->lock);
1881
1882         return ret;
1883 }
1884
1885 static int sh_eth_poll(struct napi_struct *napi, int budget)
1886 {
1887         struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1888                                                   napi);
1889         struct net_device *ndev = napi->dev;
1890         int quota = budget;
1891         u32 intr_status;
1892
1893         for (;;) {
1894                 intr_status = sh_eth_read(ndev, EESR);
1895                 if (!(intr_status & EESR_RX_CHECK))
1896                         break;
1897                 /* Clear Rx interrupts */
1898                 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1899
1900                 if (sh_eth_rx(ndev, intr_status, &quota))
1901                         goto out;
1902         }
1903
1904         napi_complete(napi);
1905
1906         /* Reenable Rx interrupts */
1907         if (mdp->irq_enabled)
1908                 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1909 out:
1910         return budget - quota;
1911 }
1912
1913 /* PHY state control function */
1914 static void sh_eth_adjust_link(struct net_device *ndev)
1915 {
1916         struct sh_eth_private *mdp = netdev_priv(ndev);
1917         struct phy_device *phydev = ndev->phydev;
1918         unsigned long flags;
1919         int new_state = 0;
1920
1921         spin_lock_irqsave(&mdp->lock, flags);
1922
1923         /* Disable TX and RX right over here, if E-MAC change is ignored */
1924         if (mdp->cd->no_psr || mdp->no_ether_link)
1925                 sh_eth_rcv_snd_disable(ndev);
1926
1927         if (phydev->link) {
1928                 if (phydev->duplex != mdp->duplex) {
1929                         new_state = 1;
1930                         mdp->duplex = phydev->duplex;
1931                         if (mdp->cd->set_duplex)
1932                                 mdp->cd->set_duplex(ndev);
1933                 }
1934
1935                 if (phydev->speed != mdp->speed) {
1936                         new_state = 1;
1937                         mdp->speed = phydev->speed;
1938                         if (mdp->cd->set_rate)
1939                                 mdp->cd->set_rate(ndev);
1940                 }
1941                 if (!mdp->link) {
1942                         sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1943                         new_state = 1;
1944                         mdp->link = phydev->link;
1945                 }
1946         } else if (mdp->link) {
1947                 new_state = 1;
1948                 mdp->link = 0;
1949                 mdp->speed = 0;
1950                 mdp->duplex = -1;
1951         }
1952
1953         /* Enable TX and RX right over here, if E-MAC change is ignored */
1954         if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
1955                 sh_eth_rcv_snd_enable(ndev);
1956
1957         mmiowb();
1958         spin_unlock_irqrestore(&mdp->lock, flags);
1959
1960         if (new_state && netif_msg_link(mdp))
1961                 phy_print_status(phydev);
1962 }
1963
1964 /* PHY init function */
1965 static int sh_eth_phy_init(struct net_device *ndev)
1966 {
1967         struct device_node *np = ndev->dev.parent->of_node;
1968         struct sh_eth_private *mdp = netdev_priv(ndev);
1969         struct phy_device *phydev;
1970
1971         mdp->link = 0;
1972         mdp->speed = 0;
1973         mdp->duplex = -1;
1974
1975         /* Try connect to PHY */
1976         if (np) {
1977                 struct device_node *pn;
1978
1979                 pn = of_parse_phandle(np, "phy-handle", 0);
1980                 phydev = of_phy_connect(ndev, pn,
1981                                         sh_eth_adjust_link, 0,
1982                                         mdp->phy_interface);
1983
1984                 of_node_put(pn);
1985                 if (!phydev)
1986                         phydev = ERR_PTR(-ENOENT);
1987         } else {
1988                 char phy_id[MII_BUS_ID_SIZE + 3];
1989
1990                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1991                          mdp->mii_bus->id, mdp->phy_id);
1992
1993                 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1994                                      mdp->phy_interface);
1995         }
1996
1997         if (IS_ERR(phydev)) {
1998                 netdev_err(ndev, "failed to connect PHY\n");
1999                 return PTR_ERR(phydev);
2000         }
2001
2002         /* mask with MAC supported features */
2003         if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2004                 int err = phy_set_max_speed(phydev, SPEED_100);
2005                 if (err) {
2006                         netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2007                         phy_disconnect(phydev);
2008                         return err;
2009                 }
2010         }
2011
2012         phy_attached_info(phydev);
2013
2014         return 0;
2015 }
2016
2017 /* PHY control start function */
2018 static int sh_eth_phy_start(struct net_device *ndev)
2019 {
2020         int ret;
2021
2022         ret = sh_eth_phy_init(ndev);
2023         if (ret)
2024                 return ret;
2025
2026         phy_start(ndev->phydev);
2027
2028         return 0;
2029 }
2030
2031 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2032  * version must be bumped as well.  Just adding registers up to that
2033  * limit is fine, as long as the existing register indices don't
2034  * change.
2035  */
2036 #define SH_ETH_REG_DUMP_VERSION         1
2037 #define SH_ETH_REG_DUMP_MAX_REGS        256
2038
2039 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2040 {
2041         struct sh_eth_private *mdp = netdev_priv(ndev);
2042         struct sh_eth_cpu_data *cd = mdp->cd;
2043         u32 *valid_map;
2044         size_t len;
2045
2046         BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2047
2048         /* Dump starts with a bitmap that tells ethtool which
2049          * registers are defined for this chip.
2050          */
2051         len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2052         if (buf) {
2053                 valid_map = buf;
2054                 buf += len;
2055         } else {
2056                 valid_map = NULL;
2057         }
2058
2059         /* Add a register to the dump, if it has a defined offset.
2060          * This automatically skips most undefined registers, but for
2061          * some it is also necessary to check a capability flag in
2062          * struct sh_eth_cpu_data.
2063          */
2064 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2065 #define add_reg_from(reg, read_expr) do {                               \
2066                 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) {    \
2067                         if (buf) {                                      \
2068                                 mark_reg_valid(reg);                    \
2069                                 *buf++ = read_expr;                     \
2070                         }                                               \
2071                         ++len;                                          \
2072                 }                                                       \
2073         } while (0)
2074 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2075 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2076
2077         add_reg(EDSR);
2078         add_reg(EDMR);
2079         add_reg(EDTRR);
2080         add_reg(EDRRR);
2081         add_reg(EESR);
2082         add_reg(EESIPR);
2083         add_reg(TDLAR);
2084         add_reg(TDFAR);
2085         add_reg(TDFXR);
2086         add_reg(TDFFR);
2087         add_reg(RDLAR);
2088         add_reg(RDFAR);
2089         add_reg(RDFXR);
2090         add_reg(RDFFR);
2091         add_reg(TRSCER);
2092         add_reg(RMFCR);
2093         add_reg(TFTR);
2094         add_reg(FDR);
2095         add_reg(RMCR);
2096         add_reg(TFUCR);
2097         add_reg(RFOCR);
2098         if (cd->rmiimode)
2099                 add_reg(RMIIMODE);
2100         add_reg(FCFTR);
2101         if (cd->rpadir)
2102                 add_reg(RPADIR);
2103         if (!cd->no_trimd)
2104                 add_reg(TRIMD);
2105         add_reg(ECMR);
2106         add_reg(ECSR);
2107         add_reg(ECSIPR);
2108         add_reg(PIR);
2109         if (!cd->no_psr)
2110                 add_reg(PSR);
2111         add_reg(RDMLR);
2112         add_reg(RFLR);
2113         add_reg(IPGR);
2114         if (cd->apr)
2115                 add_reg(APR);
2116         if (cd->mpr)
2117                 add_reg(MPR);
2118         add_reg(RFCR);
2119         add_reg(RFCF);
2120         if (cd->tpauser)
2121                 add_reg(TPAUSER);
2122         add_reg(TPAUSECR);
2123         add_reg(GECMR);
2124         if (cd->bculr)
2125                 add_reg(BCULR);
2126         add_reg(MAHR);
2127         add_reg(MALR);
2128         add_reg(TROCR);
2129         add_reg(CDCR);
2130         add_reg(LCCR);
2131         add_reg(CNDCR);
2132         add_reg(CEFCR);
2133         add_reg(FRECR);
2134         add_reg(TSFRCR);
2135         add_reg(TLFRCR);
2136         add_reg(CERCR);
2137         add_reg(CEECR);
2138         add_reg(MAFCR);
2139         if (cd->rtrate)
2140                 add_reg(RTRATE);
2141         if (cd->hw_checksum)
2142                 add_reg(CSMR);
2143         if (cd->select_mii)
2144                 add_reg(RMII_MII);
2145         if (cd->tsu) {
2146                 add_tsu_reg(ARSTR);
2147                 add_tsu_reg(TSU_CTRST);
2148                 add_tsu_reg(TSU_FWEN0);
2149                 add_tsu_reg(TSU_FWEN1);
2150                 add_tsu_reg(TSU_FCM);
2151                 add_tsu_reg(TSU_BSYSL0);
2152                 add_tsu_reg(TSU_BSYSL1);
2153                 add_tsu_reg(TSU_PRISL0);
2154                 add_tsu_reg(TSU_PRISL1);
2155                 add_tsu_reg(TSU_FWSL0);
2156                 add_tsu_reg(TSU_FWSL1);
2157                 add_tsu_reg(TSU_FWSLC);
2158                 add_tsu_reg(TSU_QTAGM0);
2159                 add_tsu_reg(TSU_QTAGM1);
2160                 add_tsu_reg(TSU_FWSR);
2161                 add_tsu_reg(TSU_FWINMK);
2162                 add_tsu_reg(TSU_ADQT0);
2163                 add_tsu_reg(TSU_ADQT1);
2164                 add_tsu_reg(TSU_VTAG0);
2165                 add_tsu_reg(TSU_VTAG1);
2166                 add_tsu_reg(TSU_ADSBSY);
2167                 add_tsu_reg(TSU_TEN);
2168                 add_tsu_reg(TSU_POST1);
2169                 add_tsu_reg(TSU_POST2);
2170                 add_tsu_reg(TSU_POST3);
2171                 add_tsu_reg(TSU_POST4);
2172                 /* This is the start of a table, not just a single register. */
2173                 if (buf) {
2174                         unsigned int i;
2175
2176                         mark_reg_valid(TSU_ADRH0);
2177                         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2178                                 *buf++ = ioread32(mdp->tsu_addr +
2179                                                   mdp->reg_offset[TSU_ADRH0] +
2180                                                   i * 4);
2181                 }
2182                 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2183         }
2184
2185 #undef mark_reg_valid
2186 #undef add_reg_from
2187 #undef add_reg
2188 #undef add_tsu_reg
2189
2190         return len * 4;
2191 }
2192
2193 static int sh_eth_get_regs_len(struct net_device *ndev)
2194 {
2195         return __sh_eth_get_regs(ndev, NULL);
2196 }
2197
2198 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2199                             void *buf)
2200 {
2201         struct sh_eth_private *mdp = netdev_priv(ndev);
2202
2203         regs->version = SH_ETH_REG_DUMP_VERSION;
2204
2205         pm_runtime_get_sync(&mdp->pdev->dev);
2206         __sh_eth_get_regs(ndev, buf);
2207         pm_runtime_put_sync(&mdp->pdev->dev);
2208 }
2209
2210 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2211 {
2212         struct sh_eth_private *mdp = netdev_priv(ndev);
2213         return mdp->msg_enable;
2214 }
2215
2216 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2217 {
2218         struct sh_eth_private *mdp = netdev_priv(ndev);
2219         mdp->msg_enable = value;
2220 }
2221
2222 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2223         "rx_current", "tx_current",
2224         "rx_dirty", "tx_dirty",
2225 };
2226 #define SH_ETH_STATS_LEN  ARRAY_SIZE(sh_eth_gstrings_stats)
2227
2228 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2229 {
2230         switch (sset) {
2231         case ETH_SS_STATS:
2232                 return SH_ETH_STATS_LEN;
2233         default:
2234                 return -EOPNOTSUPP;
2235         }
2236 }
2237
2238 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2239                                      struct ethtool_stats *stats, u64 *data)
2240 {
2241         struct sh_eth_private *mdp = netdev_priv(ndev);
2242         int i = 0;
2243
2244         /* device-specific stats */
2245         data[i++] = mdp->cur_rx;
2246         data[i++] = mdp->cur_tx;
2247         data[i++] = mdp->dirty_rx;
2248         data[i++] = mdp->dirty_tx;
2249 }
2250
2251 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2252 {
2253         switch (stringset) {
2254         case ETH_SS_STATS:
2255                 memcpy(data, *sh_eth_gstrings_stats,
2256                        sizeof(sh_eth_gstrings_stats));
2257                 break;
2258         }
2259 }
2260
2261 static void sh_eth_get_ringparam(struct net_device *ndev,
2262                                  struct ethtool_ringparam *ring)
2263 {
2264         struct sh_eth_private *mdp = netdev_priv(ndev);
2265
2266         ring->rx_max_pending = RX_RING_MAX;
2267         ring->tx_max_pending = TX_RING_MAX;
2268         ring->rx_pending = mdp->num_rx_ring;
2269         ring->tx_pending = mdp->num_tx_ring;
2270 }
2271
2272 static int sh_eth_set_ringparam(struct net_device *ndev,
2273                                 struct ethtool_ringparam *ring)
2274 {
2275         struct sh_eth_private *mdp = netdev_priv(ndev);
2276         int ret;
2277
2278         if (ring->tx_pending > TX_RING_MAX ||
2279             ring->rx_pending > RX_RING_MAX ||
2280             ring->tx_pending < TX_RING_MIN ||
2281             ring->rx_pending < RX_RING_MIN)
2282                 return -EINVAL;
2283         if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2284                 return -EINVAL;
2285
2286         if (netif_running(ndev)) {
2287                 netif_device_detach(ndev);
2288                 netif_tx_disable(ndev);
2289
2290                 /* Serialise with the interrupt handler and NAPI, then
2291                  * disable interrupts.  We have to clear the
2292                  * irq_enabled flag first to ensure that interrupts
2293                  * won't be re-enabled.
2294                  */
2295                 mdp->irq_enabled = false;
2296                 synchronize_irq(ndev->irq);
2297                 napi_synchronize(&mdp->napi);
2298                 sh_eth_write(ndev, 0x0000, EESIPR);
2299
2300                 sh_eth_dev_exit(ndev);
2301
2302                 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2303                 sh_eth_ring_free(ndev);
2304         }
2305
2306         /* Set new parameters */
2307         mdp->num_rx_ring = ring->rx_pending;
2308         mdp->num_tx_ring = ring->tx_pending;
2309
2310         if (netif_running(ndev)) {
2311                 ret = sh_eth_ring_init(ndev);
2312                 if (ret < 0) {
2313                         netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2314                                    __func__);
2315                         return ret;
2316                 }
2317                 ret = sh_eth_dev_init(ndev);
2318                 if (ret < 0) {
2319                         netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2320                                    __func__);
2321                         return ret;
2322                 }
2323
2324                 netif_device_attach(ndev);
2325         }
2326
2327         return 0;
2328 }
2329
2330 static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2331 {
2332         struct sh_eth_private *mdp = netdev_priv(ndev);
2333
2334         wol->supported = 0;
2335         wol->wolopts = 0;
2336
2337         if (mdp->cd->magic) {
2338                 wol->supported = WAKE_MAGIC;
2339                 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2340         }
2341 }
2342
2343 static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2344 {
2345         struct sh_eth_private *mdp = netdev_priv(ndev);
2346
2347         if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2348                 return -EOPNOTSUPP;
2349
2350         mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2351
2352         device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2353
2354         return 0;
2355 }
2356
2357 static const struct ethtool_ops sh_eth_ethtool_ops = {
2358         .get_regs_len   = sh_eth_get_regs_len,
2359         .get_regs       = sh_eth_get_regs,
2360         .nway_reset     = phy_ethtool_nway_reset,
2361         .get_msglevel   = sh_eth_get_msglevel,
2362         .set_msglevel   = sh_eth_set_msglevel,
2363         .get_link       = ethtool_op_get_link,
2364         .get_strings    = sh_eth_get_strings,
2365         .get_ethtool_stats  = sh_eth_get_ethtool_stats,
2366         .get_sset_count     = sh_eth_get_sset_count,
2367         .get_ringparam  = sh_eth_get_ringparam,
2368         .set_ringparam  = sh_eth_set_ringparam,
2369         .get_link_ksettings = phy_ethtool_get_link_ksettings,
2370         .set_link_ksettings = phy_ethtool_set_link_ksettings,
2371         .get_wol        = sh_eth_get_wol,
2372         .set_wol        = sh_eth_set_wol,
2373 };
2374
2375 /* network device open function */
2376 static int sh_eth_open(struct net_device *ndev)
2377 {
2378         struct sh_eth_private *mdp = netdev_priv(ndev);
2379         int ret;
2380
2381         pm_runtime_get_sync(&mdp->pdev->dev);
2382
2383         napi_enable(&mdp->napi);
2384
2385         ret = request_irq(ndev->irq, sh_eth_interrupt,
2386                           mdp->cd->irq_flags, ndev->name, ndev);
2387         if (ret) {
2388                 netdev_err(ndev, "Can not assign IRQ number\n");
2389                 goto out_napi_off;
2390         }
2391
2392         /* Descriptor set */
2393         ret = sh_eth_ring_init(ndev);
2394         if (ret)
2395                 goto out_free_irq;
2396
2397         /* device init */
2398         ret = sh_eth_dev_init(ndev);
2399         if (ret)
2400                 goto out_free_irq;
2401
2402         /* PHY control start*/
2403         ret = sh_eth_phy_start(ndev);
2404         if (ret)
2405                 goto out_free_irq;
2406
2407         netif_start_queue(ndev);
2408
2409         mdp->is_opened = 1;
2410
2411         return ret;
2412
2413 out_free_irq:
2414         free_irq(ndev->irq, ndev);
2415 out_napi_off:
2416         napi_disable(&mdp->napi);
2417         pm_runtime_put_sync(&mdp->pdev->dev);
2418         return ret;
2419 }
2420
2421 /* Timeout function */
2422 static void sh_eth_tx_timeout(struct net_device *ndev)
2423 {
2424         struct sh_eth_private *mdp = netdev_priv(ndev);
2425         struct sh_eth_rxdesc *rxdesc;
2426         int i;
2427
2428         netif_stop_queue(ndev);
2429
2430         netif_err(mdp, timer, ndev,
2431                   "transmit timed out, status %8.8x, resetting...\n",
2432                   sh_eth_read(ndev, EESR));
2433
2434         /* tx_errors count up */
2435         ndev->stats.tx_errors++;
2436
2437         /* Free all the skbuffs in the Rx queue. */
2438         for (i = 0; i < mdp->num_rx_ring; i++) {
2439                 rxdesc = &mdp->rx_ring[i];
2440                 rxdesc->status = cpu_to_le32(0);
2441                 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2442                 dev_kfree_skb(mdp->rx_skbuff[i]);
2443                 mdp->rx_skbuff[i] = NULL;
2444         }
2445         for (i = 0; i < mdp->num_tx_ring; i++) {
2446                 dev_kfree_skb(mdp->tx_skbuff[i]);
2447                 mdp->tx_skbuff[i] = NULL;
2448         }
2449
2450         /* device init */
2451         sh_eth_dev_init(ndev);
2452
2453         netif_start_queue(ndev);
2454 }
2455
2456 /* Packet transmit function */
2457 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2458 {
2459         struct sh_eth_private *mdp = netdev_priv(ndev);
2460         struct sh_eth_txdesc *txdesc;
2461         dma_addr_t dma_addr;
2462         u32 entry;
2463         unsigned long flags;
2464
2465         spin_lock_irqsave(&mdp->lock, flags);
2466         if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2467                 if (!sh_eth_tx_free(ndev, true)) {
2468                         netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2469                         netif_stop_queue(ndev);
2470                         spin_unlock_irqrestore(&mdp->lock, flags);
2471                         return NETDEV_TX_BUSY;
2472                 }
2473         }
2474         spin_unlock_irqrestore(&mdp->lock, flags);
2475
2476         if (skb_put_padto(skb, ETH_ZLEN))
2477                 return NETDEV_TX_OK;
2478
2479         entry = mdp->cur_tx % mdp->num_tx_ring;
2480         mdp->tx_skbuff[entry] = skb;
2481         txdesc = &mdp->tx_ring[entry];
2482         /* soft swap. */
2483         if (!mdp->cd->hw_swap)
2484                 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2485         dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2486                                   DMA_TO_DEVICE);
2487         if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2488                 kfree_skb(skb);
2489                 return NETDEV_TX_OK;
2490         }
2491         txdesc->addr = cpu_to_le32(dma_addr);
2492         txdesc->len  = cpu_to_le32(skb->len << 16);
2493
2494         dma_wmb(); /* TACT bit must be set after all the above writes */
2495         if (entry >= mdp->num_tx_ring - 1)
2496                 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2497         else
2498                 txdesc->status |= cpu_to_le32(TD_TACT);
2499
2500         mdp->cur_tx++;
2501
2502         if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2503                 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2504
2505         return NETDEV_TX_OK;
2506 }
2507
2508 /* The statistics registers have write-clear behaviour, which means we
2509  * will lose any increment between the read and write.  We mitigate
2510  * this by only clearing when we read a non-zero value, so we will
2511  * never falsely report a total of zero.
2512  */
2513 static void
2514 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2515 {
2516         u32 delta = sh_eth_read(ndev, reg);
2517
2518         if (delta) {
2519                 *stat += delta;
2520                 sh_eth_write(ndev, 0, reg);
2521         }
2522 }
2523
2524 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2525 {
2526         struct sh_eth_private *mdp = netdev_priv(ndev);
2527
2528         if (mdp->cd->no_tx_cntrs)
2529                 return &ndev->stats;
2530
2531         if (!mdp->is_opened)
2532                 return &ndev->stats;
2533
2534         sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2535         sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2536         sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2537
2538         if (mdp->cd->cexcr) {
2539                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2540                                    CERCR);
2541                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2542                                    CEECR);
2543         } else {
2544                 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2545                                    CNDCR);
2546         }
2547
2548         return &ndev->stats;
2549 }
2550
2551 /* device close function */
2552 static int sh_eth_close(struct net_device *ndev)
2553 {
2554         struct sh_eth_private *mdp = netdev_priv(ndev);
2555
2556         netif_stop_queue(ndev);
2557
2558         /* Serialise with the interrupt handler and NAPI, then disable
2559          * interrupts.  We have to clear the irq_enabled flag first to
2560          * ensure that interrupts won't be re-enabled.
2561          */
2562         mdp->irq_enabled = false;
2563         synchronize_irq(ndev->irq);
2564         napi_disable(&mdp->napi);
2565         sh_eth_write(ndev, 0x0000, EESIPR);
2566
2567         sh_eth_dev_exit(ndev);
2568
2569         /* PHY Disconnect */
2570         if (ndev->phydev) {
2571                 phy_stop(ndev->phydev);
2572                 phy_disconnect(ndev->phydev);
2573         }
2574
2575         free_irq(ndev->irq, ndev);
2576
2577         /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2578         sh_eth_ring_free(ndev);
2579
2580         pm_runtime_put_sync(&mdp->pdev->dev);
2581
2582         mdp->is_opened = 0;
2583
2584         return 0;
2585 }
2586
2587 /* ioctl to device function */
2588 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2589 {
2590         struct phy_device *phydev = ndev->phydev;
2591
2592         if (!netif_running(ndev))
2593                 return -EINVAL;
2594
2595         if (!phydev)
2596                 return -ENODEV;
2597
2598         return phy_mii_ioctl(phydev, rq, cmd);
2599 }
2600
2601 static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2602 {
2603         if (netif_running(ndev))
2604                 return -EBUSY;
2605
2606         ndev->mtu = new_mtu;
2607         netdev_update_features(ndev);
2608
2609         return 0;
2610 }
2611
2612 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2613 static u32 sh_eth_tsu_get_post_mask(int entry)
2614 {
2615         return 0x0f << (28 - ((entry % 8) * 4));
2616 }
2617
2618 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2619 {
2620         return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2621 }
2622
2623 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2624                                              int entry)
2625 {
2626         struct sh_eth_private *mdp = netdev_priv(ndev);
2627         int reg = TSU_POST1 + entry / 8;
2628         u32 tmp;
2629
2630         tmp = sh_eth_tsu_read(mdp, reg);
2631         sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2632 }
2633
2634 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2635                                               int entry)
2636 {
2637         struct sh_eth_private *mdp = netdev_priv(ndev);
2638         int reg = TSU_POST1 + entry / 8;
2639         u32 post_mask, ref_mask, tmp;
2640
2641         post_mask = sh_eth_tsu_get_post_mask(entry);
2642         ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2643
2644         tmp = sh_eth_tsu_read(mdp, reg);
2645         sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2646
2647         /* If other port enables, the function returns "true" */
2648         return tmp & ref_mask;
2649 }
2650
2651 static int sh_eth_tsu_busy(struct net_device *ndev)
2652 {
2653         int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2654         struct sh_eth_private *mdp = netdev_priv(ndev);
2655
2656         while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2657                 udelay(10);
2658                 timeout--;
2659                 if (timeout <= 0) {
2660                         netdev_err(ndev, "%s: timeout\n", __func__);
2661                         return -ETIMEDOUT;
2662                 }
2663         }
2664
2665         return 0;
2666 }
2667
2668 static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset,
2669                                   const u8 *addr)
2670 {
2671         struct sh_eth_private *mdp = netdev_priv(ndev);
2672         u32 val;
2673
2674         val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2675         iowrite32(val, mdp->tsu_addr + offset);
2676         if (sh_eth_tsu_busy(ndev) < 0)
2677                 return -EBUSY;
2678
2679         val = addr[4] << 8 | addr[5];
2680         iowrite32(val, mdp->tsu_addr + offset + 4);
2681         if (sh_eth_tsu_busy(ndev) < 0)
2682                 return -EBUSY;
2683
2684         return 0;
2685 }
2686
2687 static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr)
2688 {
2689         struct sh_eth_private *mdp = netdev_priv(ndev);
2690         u32 val;
2691
2692         val = ioread32(mdp->tsu_addr + offset);
2693         addr[0] = (val >> 24) & 0xff;
2694         addr[1] = (val >> 16) & 0xff;
2695         addr[2] = (val >> 8) & 0xff;
2696         addr[3] = val & 0xff;
2697         val = ioread32(mdp->tsu_addr + offset + 4);
2698         addr[4] = (val >> 8) & 0xff;
2699         addr[5] = val & 0xff;
2700 }
2701
2702
2703 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2704 {
2705         struct sh_eth_private *mdp = netdev_priv(ndev);
2706         u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2707         int i;
2708         u8 c_addr[ETH_ALEN];
2709
2710         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2711                 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr);
2712                 if (ether_addr_equal(addr, c_addr))
2713                         return i;
2714         }
2715
2716         return -ENOENT;
2717 }
2718
2719 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2720 {
2721         u8 blank[ETH_ALEN];
2722         int entry;
2723
2724         memset(blank, 0, sizeof(blank));
2725         entry = sh_eth_tsu_find_entry(ndev, blank);
2726         return (entry < 0) ? -ENOMEM : entry;
2727 }
2728
2729 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2730                                               int entry)
2731 {
2732         struct sh_eth_private *mdp = netdev_priv(ndev);
2733         u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2734         int ret;
2735         u8 blank[ETH_ALEN];
2736
2737         sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2738                          ~(1 << (31 - entry)), TSU_TEN);
2739
2740         memset(blank, 0, sizeof(blank));
2741         ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2742         if (ret < 0)
2743                 return ret;
2744         return 0;
2745 }
2746
2747 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2748 {
2749         struct sh_eth_private *mdp = netdev_priv(ndev);
2750         u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2751         int i, ret;
2752
2753         if (!mdp->cd->tsu)
2754                 return 0;
2755
2756         i = sh_eth_tsu_find_entry(ndev, addr);
2757         if (i < 0) {
2758                 /* No entry found, create one */
2759                 i = sh_eth_tsu_find_empty(ndev);
2760                 if (i < 0)
2761                         return -ENOMEM;
2762                 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2763                 if (ret < 0)
2764                         return ret;
2765
2766                 /* Enable the entry */
2767                 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2768                                  (1 << (31 - i)), TSU_TEN);
2769         }
2770
2771         /* Entry found or created, enable POST */
2772         sh_eth_tsu_enable_cam_entry_post(ndev, i);
2773
2774         return 0;
2775 }
2776
2777 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2778 {
2779         struct sh_eth_private *mdp = netdev_priv(ndev);
2780         int i, ret;
2781
2782         if (!mdp->cd->tsu)
2783                 return 0;
2784
2785         i = sh_eth_tsu_find_entry(ndev, addr);
2786         if (i) {
2787                 /* Entry found */
2788                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2789                         goto done;
2790
2791                 /* Disable the entry if both ports was disabled */
2792                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2793                 if (ret < 0)
2794                         return ret;
2795         }
2796 done:
2797         return 0;
2798 }
2799
2800 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2801 {
2802         struct sh_eth_private *mdp = netdev_priv(ndev);
2803         int i, ret;
2804
2805         if (!mdp->cd->tsu)
2806                 return 0;
2807
2808         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2809                 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2810                         continue;
2811
2812                 /* Disable the entry if both ports was disabled */
2813                 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2814                 if (ret < 0)
2815                         return ret;
2816         }
2817
2818         return 0;
2819 }
2820
2821 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2822 {
2823         struct sh_eth_private *mdp = netdev_priv(ndev);
2824         u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2825         u8 addr[ETH_ALEN];
2826         int i;
2827
2828         if (!mdp->cd->tsu)
2829                 return;
2830
2831         for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2832                 sh_eth_tsu_read_entry(ndev, reg_offset, addr);
2833                 if (is_multicast_ether_addr(addr))
2834                         sh_eth_tsu_del_entry(ndev, addr);
2835         }
2836 }
2837
2838 /* Update promiscuous flag and multicast filter */
2839 static void sh_eth_set_rx_mode(struct net_device *ndev)
2840 {
2841         struct sh_eth_private *mdp = netdev_priv(ndev);
2842         u32 ecmr_bits;
2843         int mcast_all = 0;
2844         unsigned long flags;
2845
2846         spin_lock_irqsave(&mdp->lock, flags);
2847         /* Initial condition is MCT = 1, PRM = 0.
2848          * Depending on ndev->flags, set PRM or clear MCT
2849          */
2850         ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2851         if (mdp->cd->tsu)
2852                 ecmr_bits |= ECMR_MCT;
2853
2854         if (!(ndev->flags & IFF_MULTICAST)) {
2855                 sh_eth_tsu_purge_mcast(ndev);
2856                 mcast_all = 1;
2857         }
2858         if (ndev->flags & IFF_ALLMULTI) {
2859                 sh_eth_tsu_purge_mcast(ndev);
2860                 ecmr_bits &= ~ECMR_MCT;
2861                 mcast_all = 1;
2862         }
2863
2864         if (ndev->flags & IFF_PROMISC) {
2865                 sh_eth_tsu_purge_all(ndev);
2866                 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2867         } else if (mdp->cd->tsu) {
2868                 struct netdev_hw_addr *ha;
2869                 netdev_for_each_mc_addr(ha, ndev) {
2870                         if (mcast_all && is_multicast_ether_addr(ha->addr))
2871                                 continue;
2872
2873                         if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2874                                 if (!mcast_all) {
2875                                         sh_eth_tsu_purge_mcast(ndev);
2876                                         ecmr_bits &= ~ECMR_MCT;
2877                                         mcast_all = 1;
2878                                 }
2879                         }
2880                 }
2881         }
2882
2883         /* update the ethernet mode */
2884         sh_eth_write(ndev, ecmr_bits, ECMR);
2885
2886         spin_unlock_irqrestore(&mdp->lock, flags);
2887 }
2888
2889 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2890 {
2891         if (!mdp->port)
2892                 return TSU_VTAG0;
2893         else
2894                 return TSU_VTAG1;
2895 }
2896
2897 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2898                                   __be16 proto, u16 vid)
2899 {
2900         struct sh_eth_private *mdp = netdev_priv(ndev);
2901         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2902
2903         if (unlikely(!mdp->cd->tsu))
2904                 return -EPERM;
2905
2906         /* No filtering if vid = 0 */
2907         if (!vid)
2908                 return 0;
2909
2910         mdp->vlan_num_ids++;
2911
2912         /* The controller has one VLAN tag HW filter. So, if the filter is
2913          * already enabled, the driver disables it and the filte
2914          */
2915         if (mdp->vlan_num_ids > 1) {
2916                 /* disable VLAN filter */
2917                 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2918                 return 0;
2919         }
2920
2921         sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2922                          vtag_reg_index);
2923
2924         return 0;
2925 }
2926
2927 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2928                                    __be16 proto, u16 vid)
2929 {
2930         struct sh_eth_private *mdp = netdev_priv(ndev);
2931         int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2932
2933         if (unlikely(!mdp->cd->tsu))
2934                 return -EPERM;
2935
2936         /* No filtering if vid = 0 */
2937         if (!vid)
2938                 return 0;
2939
2940         mdp->vlan_num_ids--;
2941         sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2942
2943         return 0;
2944 }
2945
2946 /* SuperH's TSU register init function */
2947 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2948 {
2949         if (!mdp->cd->dual_port) {
2950                 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2951                 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2952                                  TSU_FWSLC);    /* Enable POST registers */
2953                 return;
2954         }
2955
2956         sh_eth_tsu_write(mdp, 0, TSU_FWEN0);    /* Disable forward(0->1) */
2957         sh_eth_tsu_write(mdp, 0, TSU_FWEN1);    /* Disable forward(1->0) */
2958         sh_eth_tsu_write(mdp, 0, TSU_FCM);      /* forward fifo 3k-3k */
2959         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2960         sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2961         sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2962         sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2963         sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2964         sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2965         sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2966         sh_eth_tsu_write(mdp, 0, TSU_QTAGM0);   /* Disable QTAG(0->1) */
2967         sh_eth_tsu_write(mdp, 0, TSU_QTAGM1);   /* Disable QTAG(1->0) */
2968         sh_eth_tsu_write(mdp, 0, TSU_FWSR);     /* all interrupt status clear */
2969         sh_eth_tsu_write(mdp, 0, TSU_FWINMK);   /* Disable all interrupt */
2970         sh_eth_tsu_write(mdp, 0, TSU_TEN);      /* Disable all CAM entry */
2971         sh_eth_tsu_write(mdp, 0, TSU_POST1);    /* Disable CAM entry [ 0- 7] */
2972         sh_eth_tsu_write(mdp, 0, TSU_POST2);    /* Disable CAM entry [ 8-15] */
2973         sh_eth_tsu_write(mdp, 0, TSU_POST3);    /* Disable CAM entry [16-23] */
2974         sh_eth_tsu_write(mdp, 0, TSU_POST4);    /* Disable CAM entry [24-31] */
2975 }
2976
2977 /* MDIO bus release function */
2978 static int sh_mdio_release(struct sh_eth_private *mdp)
2979 {
2980         /* unregister mdio bus */
2981         mdiobus_unregister(mdp->mii_bus);
2982
2983         /* free bitbang info */
2984         free_mdio_bitbang(mdp->mii_bus);
2985
2986         return 0;
2987 }
2988
2989 /* MDIO bus init function */
2990 static int sh_mdio_init(struct sh_eth_private *mdp,
2991                         struct sh_eth_plat_data *pd)
2992 {
2993         int ret;
2994         struct bb_info *bitbang;
2995         struct platform_device *pdev = mdp->pdev;
2996         struct device *dev = &mdp->pdev->dev;
2997
2998         /* create bit control struct for PHY */
2999         bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3000         if (!bitbang)
3001                 return -ENOMEM;
3002
3003         /* bitbang init */
3004         bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3005         bitbang->set_gate = pd->set_mdio_gate;
3006         bitbang->ctrl.ops = &bb_ops;
3007
3008         /* MII controller setting */
3009         mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3010         if (!mdp->mii_bus)
3011                 return -ENOMEM;
3012
3013         /* Hook up MII support for ethtool */
3014         mdp->mii_bus->name = "sh_mii";
3015         mdp->mii_bus->parent = dev;
3016         snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3017                  pdev->name, pdev->id);
3018
3019         /* register MDIO bus */
3020         if (pd->phy_irq > 0)
3021                 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3022
3023         ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3024         if (ret)
3025                 goto out_free_bus;
3026
3027         return 0;
3028
3029 out_free_bus:
3030         free_mdio_bitbang(mdp->mii_bus);
3031         return ret;
3032 }
3033
3034 static const u16 *sh_eth_get_register_offset(int register_type)
3035 {
3036         const u16 *reg_offset = NULL;
3037
3038         switch (register_type) {
3039         case SH_ETH_REG_GIGABIT:
3040                 reg_offset = sh_eth_offset_gigabit;
3041                 break;
3042         case SH_ETH_REG_FAST_RZ:
3043                 reg_offset = sh_eth_offset_fast_rz;
3044                 break;
3045         case SH_ETH_REG_FAST_RCAR:
3046                 reg_offset = sh_eth_offset_fast_rcar;
3047                 break;
3048         case SH_ETH_REG_FAST_SH4:
3049                 reg_offset = sh_eth_offset_fast_sh4;
3050                 break;
3051         case SH_ETH_REG_FAST_SH3_SH2:
3052                 reg_offset = sh_eth_offset_fast_sh3_sh2;
3053                 break;
3054         }
3055
3056         return reg_offset;
3057 }
3058
3059 static const struct net_device_ops sh_eth_netdev_ops = {
3060         .ndo_open               = sh_eth_open,
3061         .ndo_stop               = sh_eth_close,
3062         .ndo_start_xmit         = sh_eth_start_xmit,
3063         .ndo_get_stats          = sh_eth_get_stats,
3064         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3065         .ndo_tx_timeout         = sh_eth_tx_timeout,
3066         .ndo_do_ioctl           = sh_eth_do_ioctl,
3067         .ndo_change_mtu         = sh_eth_change_mtu,
3068         .ndo_validate_addr      = eth_validate_addr,
3069         .ndo_set_mac_address    = eth_mac_addr,
3070 };
3071
3072 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3073         .ndo_open               = sh_eth_open,
3074         .ndo_stop               = sh_eth_close,
3075         .ndo_start_xmit         = sh_eth_start_xmit,
3076         .ndo_get_stats          = sh_eth_get_stats,
3077         .ndo_set_rx_mode        = sh_eth_set_rx_mode,
3078         .ndo_vlan_rx_add_vid    = sh_eth_vlan_rx_add_vid,
3079         .ndo_vlan_rx_kill_vid   = sh_eth_vlan_rx_kill_vid,
3080         .ndo_tx_timeout         = sh_eth_tx_timeout,
3081         .ndo_do_ioctl           = sh_eth_do_ioctl,
3082         .ndo_change_mtu         = sh_eth_change_mtu,
3083         .ndo_validate_addr      = eth_validate_addr,
3084         .ndo_set_mac_address    = eth_mac_addr,
3085 };
3086
3087 #ifdef CONFIG_OF
3088 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3089 {
3090         struct device_node *np = dev->of_node;
3091         struct sh_eth_plat_data *pdata;
3092         const char *mac_addr;
3093
3094         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3095         if (!pdata)
3096                 return NULL;
3097
3098         pdata->phy_interface = of_get_phy_mode(np);
3099
3100         mac_addr = of_get_mac_address(np);
3101         if (mac_addr)
3102                 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3103
3104         pdata->no_ether_link =
3105                 of_property_read_bool(np, "renesas,no-ether-link");
3106         pdata->ether_link_active_low =
3107                 of_property_read_bool(np, "renesas,ether-link-active-low");
3108
3109         return pdata;
3110 }
3111
3112 static const struct of_device_id sh_eth_match_table[] = {
3113         { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3114         { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3115         { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3116         { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3117         { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3118         { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3119         { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3120         { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3121         { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3122         { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
3123         { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3124         { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3125         { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3126         { }
3127 };
3128 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3129 #else
3130 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3131 {
3132         return NULL;
3133 }
3134 #endif
3135
3136 static int sh_eth_drv_probe(struct platform_device *pdev)
3137 {
3138         struct resource *res;
3139         struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3140         const struct platform_device_id *id = platform_get_device_id(pdev);
3141         struct sh_eth_private *mdp;
3142         struct net_device *ndev;
3143         int ret;
3144
3145         /* get base addr */
3146         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3147
3148         ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3149         if (!ndev)
3150                 return -ENOMEM;
3151
3152         pm_runtime_enable(&pdev->dev);
3153         pm_runtime_get_sync(&pdev->dev);
3154
3155         ret = platform_get_irq(pdev, 0);
3156         if (ret < 0)
3157                 goto out_release;
3158         ndev->irq = ret;
3159
3160         SET_NETDEV_DEV(ndev, &pdev->dev);
3161
3162         mdp = netdev_priv(ndev);
3163         mdp->num_tx_ring = TX_RING_SIZE;
3164         mdp->num_rx_ring = RX_RING_SIZE;
3165         mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3166         if (IS_ERR(mdp->addr)) {
3167                 ret = PTR_ERR(mdp->addr);
3168                 goto out_release;
3169         }
3170
3171         ndev->base_addr = res->start;
3172
3173         spin_lock_init(&mdp->lock);
3174         mdp->pdev = pdev;
3175
3176         if (pdev->dev.of_node)
3177                 pd = sh_eth_parse_dt(&pdev->dev);
3178         if (!pd) {
3179                 dev_err(&pdev->dev, "no platform data\n");
3180                 ret = -EINVAL;
3181                 goto out_release;
3182         }
3183
3184         /* get PHY ID */
3185         mdp->phy_id = pd->phy;
3186         mdp->phy_interface = pd->phy_interface;
3187         mdp->no_ether_link = pd->no_ether_link;
3188         mdp->ether_link_active_low = pd->ether_link_active_low;
3189
3190         /* set cpu data */
3191         if (id)
3192                 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3193         else
3194                 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3195
3196         mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3197         if (!mdp->reg_offset) {
3198                 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3199                         mdp->cd->register_type);
3200                 ret = -EINVAL;
3201                 goto out_release;
3202         }
3203         sh_eth_set_default_cpu_data(mdp->cd);
3204
3205         /* User's manual states max MTU should be 2048 but due to the
3206          * alignment calculations in sh_eth_ring_init() the practical
3207          * MTU is a bit less. Maybe this can be optimized some more.
3208          */
3209         ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3210         ndev->min_mtu = ETH_MIN_MTU;
3211
3212         /* set function */
3213         if (mdp->cd->tsu)
3214                 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3215         else
3216                 ndev->netdev_ops = &sh_eth_netdev_ops;
3217         ndev->ethtool_ops = &sh_eth_ethtool_ops;
3218         ndev->watchdog_timeo = TX_TIMEOUT;
3219
3220         /* debug message level */
3221         mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3222
3223         /* read and set MAC address */
3224         read_mac_address(ndev, pd->mac_addr);
3225         if (!is_valid_ether_addr(ndev->dev_addr)) {
3226                 dev_warn(&pdev->dev,
3227                          "no valid MAC address supplied, using a random one.\n");
3228                 eth_hw_addr_random(ndev);
3229         }
3230
3231         if (mdp->cd->tsu) {
3232                 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3233                 struct resource *rtsu;
3234
3235                 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3236                 if (!rtsu) {
3237                         dev_err(&pdev->dev, "no TSU resource\n");
3238                         ret = -ENODEV;
3239                         goto out_release;
3240                 }
3241                 /* We can only request the  TSU region  for the first port
3242                  * of the two  sharing this TSU for the probe to succeed...
3243                  */
3244                 if (port == 0 &&
3245                     !devm_request_mem_region(&pdev->dev, rtsu->start,
3246                                              resource_size(rtsu),
3247                                              dev_name(&pdev->dev))) {
3248                         dev_err(&pdev->dev, "can't request TSU resource.\n");
3249                         ret = -EBUSY;
3250                         goto out_release;
3251                 }
3252                 /* ioremap the TSU registers */
3253                 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3254                                              resource_size(rtsu));
3255                 if (!mdp->tsu_addr) {
3256                         dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3257                         ret = -ENOMEM;
3258                         goto out_release;
3259                 }
3260                 mdp->port = port;
3261                 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3262
3263                 /* Need to init only the first port of the two sharing a TSU */
3264                 if (port == 0) {
3265                         if (mdp->cd->chip_reset)
3266                                 mdp->cd->chip_reset(ndev);
3267
3268                         /* TSU init (Init only)*/
3269                         sh_eth_tsu_init(mdp);
3270                 }
3271         }
3272
3273         if (mdp->cd->rmiimode)
3274                 sh_eth_write(ndev, 0x1, RMIIMODE);
3275
3276         /* MDIO bus init */
3277         ret = sh_mdio_init(mdp, pd);
3278         if (ret) {
3279                 if (ret != -EPROBE_DEFER)
3280                         dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3281                 goto out_release;
3282         }
3283
3284         netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3285
3286         /* network device register */
3287         ret = register_netdev(ndev);
3288         if (ret)
3289                 goto out_napi_del;
3290
3291         if (mdp->cd->magic)
3292                 device_set_wakeup_capable(&pdev->dev, 1);
3293
3294         /* print device information */
3295         netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3296                     (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3297
3298         pm_runtime_put(&pdev->dev);
3299         platform_set_drvdata(pdev, ndev);
3300
3301         return ret;
3302
3303 out_napi_del:
3304         netif_napi_del(&mdp->napi);
3305         sh_mdio_release(mdp);
3306
3307 out_release:
3308         /* net_dev free */
3309         free_netdev(ndev);
3310
3311         pm_runtime_put(&pdev->dev);
3312         pm_runtime_disable(&pdev->dev);
3313         return ret;
3314 }
3315
3316 static int sh_eth_drv_remove(struct platform_device *pdev)
3317 {
3318         struct net_device *ndev = platform_get_drvdata(pdev);
3319         struct sh_eth_private *mdp = netdev_priv(ndev);
3320
3321         unregister_netdev(ndev);
3322         netif_napi_del(&mdp->napi);
3323         sh_mdio_release(mdp);
3324         pm_runtime_disable(&pdev->dev);
3325         free_netdev(ndev);
3326
3327         return 0;
3328 }
3329
3330 #ifdef CONFIG_PM
3331 #ifdef CONFIG_PM_SLEEP
3332 static int sh_eth_wol_setup(struct net_device *ndev)
3333 {
3334         struct sh_eth_private *mdp = netdev_priv(ndev);
3335
3336         /* Only allow ECI interrupts */
3337         synchronize_irq(ndev->irq);
3338         napi_disable(&mdp->napi);
3339         sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3340
3341         /* Enable MagicPacket */
3342         sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3343
3344         return enable_irq_wake(ndev->irq);
3345 }
3346
3347 static int sh_eth_wol_restore(struct net_device *ndev)
3348 {
3349         struct sh_eth_private *mdp = netdev_priv(ndev);
3350         int ret;
3351
3352         napi_enable(&mdp->napi);
3353
3354         /* Disable MagicPacket */
3355         sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3356
3357         /* The device needs to be reset to restore MagicPacket logic
3358          * for next wakeup. If we close and open the device it will
3359          * both be reset and all registers restored. This is what
3360          * happens during suspend and resume without WoL enabled.
3361          */
3362         ret = sh_eth_close(ndev);
3363         if (ret < 0)
3364                 return ret;
3365         ret = sh_eth_open(ndev);
3366         if (ret < 0)
3367                 return ret;
3368
3369         return disable_irq_wake(ndev->irq);
3370 }
3371
3372 static int sh_eth_suspend(struct device *dev)
3373 {
3374         struct net_device *ndev = dev_get_drvdata(dev);
3375         struct sh_eth_private *mdp = netdev_priv(ndev);
3376         int ret = 0;
3377
3378         if (!netif_running(ndev))
3379                 return 0;
3380
3381         netif_device_detach(ndev);
3382
3383         if (mdp->wol_enabled)
3384                 ret = sh_eth_wol_setup(ndev);
3385         else
3386                 ret = sh_eth_close(ndev);
3387
3388         return ret;
3389 }
3390
3391 static int sh_eth_resume(struct device *dev)
3392 {
3393         struct net_device *ndev = dev_get_drvdata(dev);
3394         struct sh_eth_private *mdp = netdev_priv(ndev);
3395         int ret = 0;
3396
3397         if (!netif_running(ndev))
3398                 return 0;
3399
3400         if (mdp->wol_enabled)
3401                 ret = sh_eth_wol_restore(ndev);
3402         else
3403                 ret = sh_eth_open(ndev);
3404
3405         if (ret < 0)
3406                 return ret;
3407
3408         netif_device_attach(ndev);
3409
3410         return ret;
3411 }
3412 #endif
3413
3414 static int sh_eth_runtime_nop(struct device *dev)
3415 {
3416         /* Runtime PM callback shared between ->runtime_suspend()
3417          * and ->runtime_resume(). Simply returns success.
3418          *
3419          * This driver re-initializes all registers after
3420          * pm_runtime_get_sync() anyway so there is no need
3421          * to save and restore registers here.
3422          */
3423         return 0;
3424 }
3425
3426 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3427         SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3428         SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3429 };
3430 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3431 #else
3432 #define SH_ETH_PM_OPS NULL
3433 #endif
3434
3435 static const struct platform_device_id sh_eth_id_table[] = {
3436         { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3437         { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3438         { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3439         { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3440         { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3441         { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3442         { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3443         { }
3444 };
3445 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3446
3447 static struct platform_driver sh_eth_driver = {
3448         .probe = sh_eth_drv_probe,
3449         .remove = sh_eth_drv_remove,
3450         .id_table = sh_eth_id_table,
3451         .driver = {
3452                    .name = CARDNAME,
3453                    .pm = SH_ETH_PM_OPS,
3454                    .of_match_table = of_match_ptr(sh_eth_match_table),
3455         },
3456 };
3457
3458 module_platform_driver(sh_eth_driver);
3459
3460 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3461 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3462 MODULE_LICENSE("GPL v2");