1 /* SuperH Ethernet device driver
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
49 #define SH_ETH_DEF_MSG_ENABLE \
55 #define SH_ETH_OFFSET_INVALID ((u16)~0)
57 #define SH_ETH_OFFSET_DEFAULTS \
58 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
60 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
61 SH_ETH_OFFSET_DEFAULTS,
116 [TSU_CTRST] = 0x0004,
117 [TSU_FWEN0] = 0x0010,
118 [TSU_FWEN1] = 0x0014,
120 [TSU_BSYSL0] = 0x0020,
121 [TSU_BSYSL1] = 0x0024,
122 [TSU_PRISL0] = 0x0028,
123 [TSU_PRISL1] = 0x002c,
124 [TSU_FWSL0] = 0x0030,
125 [TSU_FWSL1] = 0x0034,
126 [TSU_FWSLC] = 0x0038,
127 [TSU_QTAG0] = 0x0040,
128 [TSU_QTAG1] = 0x0044,
130 [TSU_FWINMK] = 0x0054,
131 [TSU_ADQT0] = 0x0048,
132 [TSU_ADQT1] = 0x004c,
133 [TSU_VTAG0] = 0x0058,
134 [TSU_VTAG1] = 0x005c,
135 [TSU_ADSBSY] = 0x0060,
137 [TSU_POST1] = 0x0070,
138 [TSU_POST2] = 0x0074,
139 [TSU_POST3] = 0x0078,
140 [TSU_POST4] = 0x007c,
141 [TSU_ADRH0] = 0x0100,
157 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
158 SH_ETH_OFFSET_DEFAULTS,
203 [TSU_CTRST] = 0x0004,
204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
207 [TSU_ADRH0] = 0x0100,
215 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
216 SH_ETH_OFFSET_DEFAULTS,
263 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
264 SH_ETH_OFFSET_DEFAULTS,
317 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
318 SH_ETH_OFFSET_DEFAULTS,
366 [TSU_CTRST] = 0x0004,
367 [TSU_FWEN0] = 0x0010,
368 [TSU_FWEN1] = 0x0014,
370 [TSU_BSYSL0] = 0x0020,
371 [TSU_BSYSL1] = 0x0024,
372 [TSU_PRISL0] = 0x0028,
373 [TSU_PRISL1] = 0x002c,
374 [TSU_FWSL0] = 0x0030,
375 [TSU_FWSL1] = 0x0034,
376 [TSU_FWSLC] = 0x0038,
377 [TSU_QTAGM0] = 0x0040,
378 [TSU_QTAGM1] = 0x0044,
379 [TSU_ADQT0] = 0x0048,
380 [TSU_ADQT1] = 0x004c,
382 [TSU_FWINMK] = 0x0054,
383 [TSU_ADSBSY] = 0x0060,
385 [TSU_POST1] = 0x0070,
386 [TSU_POST2] = 0x0074,
387 [TSU_POST3] = 0x0078,
388 [TSU_POST4] = 0x007c,
403 [TSU_ADRH0] = 0x0100,
406 static void sh_eth_rcv_snd_disable(struct net_device *ndev);
407 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
409 static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
411 struct sh_eth_private *mdp = netdev_priv(ndev);
412 u16 offset = mdp->reg_offset[enum_index];
414 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
417 iowrite32(data, mdp->addr + offset);
420 static u32 sh_eth_read(struct net_device *ndev, int enum_index)
422 struct sh_eth_private *mdp = netdev_priv(ndev);
423 u16 offset = mdp->reg_offset[enum_index];
425 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
428 return ioread32(mdp->addr + offset);
431 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
433 return mdp->reg_offset == sh_eth_offset_gigabit;
436 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
438 return mdp->reg_offset == sh_eth_offset_fast_rz;
441 static void sh_eth_select_mii(struct net_device *ndev)
444 struct sh_eth_private *mdp = netdev_priv(ndev);
446 switch (mdp->phy_interface) {
447 case PHY_INTERFACE_MODE_GMII:
450 case PHY_INTERFACE_MODE_MII:
453 case PHY_INTERFACE_MODE_RMII:
458 "PHY interface mode was not setup. Set to MII.\n");
463 sh_eth_write(ndev, value, RMII_MII);
466 static void sh_eth_set_duplex(struct net_device *ndev)
468 struct sh_eth_private *mdp = netdev_priv(ndev);
470 if (mdp->duplex) /* Full */
471 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
473 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
476 /* There is CPU dependent code */
477 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
479 struct sh_eth_private *mdp = netdev_priv(ndev);
481 switch (mdp->speed) {
482 case 10: /* 10BASE */
483 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
485 case 100:/* 100BASE */
486 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
494 static struct sh_eth_cpu_data r8a777x_data = {
495 .set_duplex = sh_eth_set_duplex,
496 .set_rate = sh_eth_set_rate_r8a777x,
498 .register_type = SH_ETH_REG_FAST_RCAR,
500 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
501 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
502 .eesipr_value = 0x01ff009f,
504 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
505 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
506 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
508 .fdr_value = 0x00000f0f,
517 static struct sh_eth_cpu_data r8a779x_data = {
518 .set_duplex = sh_eth_set_duplex,
519 .set_rate = sh_eth_set_rate_r8a777x,
521 .register_type = SH_ETH_REG_FAST_RCAR,
523 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
524 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
525 .eesipr_value = 0x01ff009f,
527 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
528 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
529 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
531 .fdr_value = 0x00000f0f,
533 .trscer_err_mask = DESC_I_RINT8,
542 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
544 struct sh_eth_private *mdp = netdev_priv(ndev);
546 switch (mdp->speed) {
547 case 10: /* 10BASE */
548 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
550 case 100:/* 100BASE */
551 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
559 static struct sh_eth_cpu_data sh7724_data = {
560 .set_duplex = sh_eth_set_duplex,
561 .set_rate = sh_eth_set_rate_sh7724,
563 .register_type = SH_ETH_REG_FAST_SH4,
565 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
566 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
567 .eesipr_value = 0x01ff009f,
569 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
570 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
571 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
579 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
582 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
584 struct sh_eth_private *mdp = netdev_priv(ndev);
586 switch (mdp->speed) {
587 case 10: /* 10BASE */
588 sh_eth_write(ndev, 0, RTRATE);
590 case 100:/* 100BASE */
591 sh_eth_write(ndev, 1, RTRATE);
599 static struct sh_eth_cpu_data sh7757_data = {
600 .set_duplex = sh_eth_set_duplex,
601 .set_rate = sh_eth_set_rate_sh7757,
603 .register_type = SH_ETH_REG_FAST_SH4,
605 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
607 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
608 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
609 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
612 .irq_flags = IRQF_SHARED,
619 .rpadir_value = 2 << 16,
623 #define SH_GIGA_ETH_BASE 0xfee00000UL
624 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
625 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
626 static void sh_eth_chip_reset_giga(struct net_device *ndev)
629 u32 mahr[2], malr[2];
631 /* save MAHR and MALR */
632 for (i = 0; i < 2; i++) {
633 malr[i] = ioread32((void *)GIGA_MALR(i));
634 mahr[i] = ioread32((void *)GIGA_MAHR(i));
638 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
641 /* restore MAHR and MALR */
642 for (i = 0; i < 2; i++) {
643 iowrite32(malr[i], (void *)GIGA_MALR(i));
644 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
648 static void sh_eth_set_rate_giga(struct net_device *ndev)
650 struct sh_eth_private *mdp = netdev_priv(ndev);
652 switch (mdp->speed) {
653 case 10: /* 10BASE */
654 sh_eth_write(ndev, 0x00000000, GECMR);
656 case 100:/* 100BASE */
657 sh_eth_write(ndev, 0x00000010, GECMR);
659 case 1000: /* 1000BASE */
660 sh_eth_write(ndev, 0x00000020, GECMR);
667 /* SH7757(GETHERC) */
668 static struct sh_eth_cpu_data sh7757_data_giga = {
669 .chip_reset = sh_eth_chip_reset_giga,
670 .set_duplex = sh_eth_set_duplex,
671 .set_rate = sh_eth_set_rate_giga,
673 .register_type = SH_ETH_REG_GIGABIT,
675 .ecsr_value = ECSR_ICD | ECSR_MPD,
676 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
677 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
679 .tx_check = EESR_TC1 | EESR_FTC,
680 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
681 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
683 .fdr_value = 0x0000072f,
685 .irq_flags = IRQF_SHARED,
692 .rpadir_value = 2 << 16,
698 static void sh_eth_chip_reset(struct net_device *ndev)
700 struct sh_eth_private *mdp = netdev_priv(ndev);
703 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
707 static void sh_eth_set_rate_gether(struct net_device *ndev)
709 struct sh_eth_private *mdp = netdev_priv(ndev);
711 switch (mdp->speed) {
712 case 10: /* 10BASE */
713 sh_eth_write(ndev, GECMR_10, GECMR);
715 case 100:/* 100BASE */
716 sh_eth_write(ndev, GECMR_100, GECMR);
718 case 1000: /* 1000BASE */
719 sh_eth_write(ndev, GECMR_1000, GECMR);
727 static struct sh_eth_cpu_data sh7734_data = {
728 .chip_reset = sh_eth_chip_reset,
729 .set_duplex = sh_eth_set_duplex,
730 .set_rate = sh_eth_set_rate_gether,
732 .register_type = SH_ETH_REG_GIGABIT,
734 .ecsr_value = ECSR_ICD | ECSR_MPD,
735 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
736 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
738 .tx_check = EESR_TC1 | EESR_FTC,
739 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
740 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
756 static struct sh_eth_cpu_data sh7763_data = {
757 .chip_reset = sh_eth_chip_reset,
758 .set_duplex = sh_eth_set_duplex,
759 .set_rate = sh_eth_set_rate_gether,
761 .register_type = SH_ETH_REG_GIGABIT,
763 .ecsr_value = ECSR_ICD | ECSR_MPD,
764 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
765 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
767 .tx_check = EESR_TC1 | EESR_FTC,
768 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
769 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
780 .irq_flags = IRQF_SHARED,
783 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
785 struct sh_eth_private *mdp = netdev_priv(ndev);
788 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
791 sh_eth_select_mii(ndev);
795 static struct sh_eth_cpu_data r8a7740_data = {
796 .chip_reset = sh_eth_chip_reset_r8a7740,
797 .set_duplex = sh_eth_set_duplex,
798 .set_rate = sh_eth_set_rate_gether,
800 .register_type = SH_ETH_REG_GIGABIT,
802 .ecsr_value = ECSR_ICD | ECSR_MPD,
803 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
804 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
806 .tx_check = EESR_TC1 | EESR_FTC,
807 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
808 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
810 .fdr_value = 0x0000070f,
818 .rpadir_value = 2 << 16,
827 static struct sh_eth_cpu_data r7s72100_data = {
828 .chip_reset = sh_eth_chip_reset,
829 .set_duplex = sh_eth_set_duplex,
831 .register_type = SH_ETH_REG_FAST_RZ,
833 .ecsr_value = ECSR_ICD,
834 .ecsipr_value = ECSIPR_ICDIP,
835 .eesipr_value = 0xff7f009f,
837 .tx_check = EESR_TC1 | EESR_FTC,
838 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
839 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
841 .fdr_value = 0x0000070f,
849 .rpadir_value = 2 << 16,
857 static struct sh_eth_cpu_data sh7619_data = {
858 .register_type = SH_ETH_REG_FAST_SH3_SH2,
860 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
868 static struct sh_eth_cpu_data sh771x_data = {
869 .register_type = SH_ETH_REG_FAST_SH3_SH2,
871 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
875 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
878 cd->ecsr_value = DEFAULT_ECSR_INIT;
880 if (!cd->ecsipr_value)
881 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
883 if (!cd->fcftr_value)
884 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
885 DEFAULT_FIFO_F_D_RFD;
888 cd->fdr_value = DEFAULT_FDR_INIT;
891 cd->tx_check = DEFAULT_TX_CHECK;
893 if (!cd->eesr_err_check)
894 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
896 if (!cd->trscer_err_mask)
897 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
900 static int sh_eth_check_reset(struct net_device *ndev)
906 if (!(sh_eth_read(ndev, EDMR) & 0x3))
912 netdev_err(ndev, "Device reset failed\n");
918 static int sh_eth_reset(struct net_device *ndev)
920 struct sh_eth_private *mdp = netdev_priv(ndev);
923 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
924 sh_eth_write(ndev, EDSR_ENALL, EDSR);
925 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
928 ret = sh_eth_check_reset(ndev);
933 sh_eth_write(ndev, 0x0, TDLAR);
934 sh_eth_write(ndev, 0x0, TDFAR);
935 sh_eth_write(ndev, 0x0, TDFXR);
936 sh_eth_write(ndev, 0x0, TDFFR);
937 sh_eth_write(ndev, 0x0, RDLAR);
938 sh_eth_write(ndev, 0x0, RDFAR);
939 sh_eth_write(ndev, 0x0, RDFXR);
940 sh_eth_write(ndev, 0x0, RDFFR);
942 /* Reset HW CRC register */
944 sh_eth_write(ndev, 0x0, CSMR);
946 /* Select MII mode */
947 if (mdp->cd->select_mii)
948 sh_eth_select_mii(ndev);
950 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
953 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
960 static void sh_eth_set_receive_align(struct sk_buff *skb)
962 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
965 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
969 /* CPU <-> EDMAC endian convert */
970 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
972 switch (mdp->edmac_endian) {
973 case EDMAC_LITTLE_ENDIAN:
974 return cpu_to_le32(x);
975 case EDMAC_BIG_ENDIAN:
976 return cpu_to_be32(x);
981 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
983 switch (mdp->edmac_endian) {
984 case EDMAC_LITTLE_ENDIAN:
985 return le32_to_cpu(x);
986 case EDMAC_BIG_ENDIAN:
987 return be32_to_cpu(x);
992 /* Program the hardware MAC address from dev->dev_addr. */
993 static void update_mac_address(struct net_device *ndev)
996 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
997 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
999 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1002 /* Get MAC address from SuperH MAC address register
1004 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1005 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1006 * When you want use this device, you must set MAC address in bootloader.
1009 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1011 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1012 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1014 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
1015 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
1016 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
1017 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
1018 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
1019 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
1023 static u32 sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
1025 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
1026 return EDTRR_TRNS_GETHER;
1028 return EDTRR_TRNS_ETHER;
1032 void (*set_gate)(void *addr);
1033 struct mdiobb_ctrl ctrl;
1035 u32 mmd_msk;/* MMD */
1042 static void bb_set(void *addr, u32 msk)
1044 iowrite32(ioread32(addr) | msk, addr);
1048 static void bb_clr(void *addr, u32 msk)
1050 iowrite32((ioread32(addr) & ~msk), addr);
1054 static int bb_read(void *addr, u32 msk)
1056 return (ioread32(addr) & msk) != 0;
1059 /* Data I/O pin control */
1060 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1062 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1064 if (bitbang->set_gate)
1065 bitbang->set_gate(bitbang->addr);
1068 bb_set(bitbang->addr, bitbang->mmd_msk);
1070 bb_clr(bitbang->addr, bitbang->mmd_msk);
1074 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1076 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1078 if (bitbang->set_gate)
1079 bitbang->set_gate(bitbang->addr);
1082 bb_set(bitbang->addr, bitbang->mdo_msk);
1084 bb_clr(bitbang->addr, bitbang->mdo_msk);
1088 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1090 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1092 if (bitbang->set_gate)
1093 bitbang->set_gate(bitbang->addr);
1095 return bb_read(bitbang->addr, bitbang->mdi_msk);
1098 /* MDC pin control */
1099 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1101 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1103 if (bitbang->set_gate)
1104 bitbang->set_gate(bitbang->addr);
1107 bb_set(bitbang->addr, bitbang->mdc_msk);
1109 bb_clr(bitbang->addr, bitbang->mdc_msk);
1112 /* mdio bus control struct */
1113 static struct mdiobb_ops bb_ops = {
1114 .owner = THIS_MODULE,
1115 .set_mdc = sh_mdc_ctrl,
1116 .set_mdio_dir = sh_mmd_ctrl,
1117 .set_mdio_data = sh_set_mdio,
1118 .get_mdio_data = sh_get_mdio,
1121 /* free skb and descriptor buffer */
1122 static void sh_eth_ring_free(struct net_device *ndev)
1124 struct sh_eth_private *mdp = netdev_priv(ndev);
1127 /* Free Rx skb ringbuffer */
1128 if (mdp->rx_skbuff) {
1129 for (i = 0; i < mdp->num_rx_ring; i++)
1130 dev_kfree_skb(mdp->rx_skbuff[i]);
1132 kfree(mdp->rx_skbuff);
1133 mdp->rx_skbuff = NULL;
1135 /* Free Tx skb ringbuffer */
1136 if (mdp->tx_skbuff) {
1137 for (i = 0; i < mdp->num_tx_ring; i++)
1138 dev_kfree_skb(mdp->tx_skbuff[i]);
1140 kfree(mdp->tx_skbuff);
1141 mdp->tx_skbuff = NULL;
1144 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1145 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1147 mdp->rx_ring = NULL;
1151 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1152 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1154 mdp->tx_ring = NULL;
1158 /* format skb and descriptor buffer */
1159 static void sh_eth_ring_format(struct net_device *ndev)
1161 struct sh_eth_private *mdp = netdev_priv(ndev);
1163 struct sk_buff *skb;
1164 struct sh_eth_rxdesc *rxdesc = NULL;
1165 struct sh_eth_txdesc *txdesc = NULL;
1166 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1167 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1168 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1169 dma_addr_t dma_addr;
1176 memset(mdp->rx_ring, 0, rx_ringsize);
1178 /* build Rx ring buffer */
1179 for (i = 0; i < mdp->num_rx_ring; i++) {
1181 mdp->rx_skbuff[i] = NULL;
1182 skb = netdev_alloc_skb(ndev, skbuff_size);
1185 sh_eth_set_receive_align(skb);
1188 rxdesc = &mdp->rx_ring[i];
1189 /* The size of the buffer is a multiple of 32 bytes. */
1190 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
1191 dma_addr = dma_map_single(&ndev->dev, skb->data,
1192 rxdesc->buffer_length,
1194 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1198 mdp->rx_skbuff[i] = skb;
1199 rxdesc->addr = cpu_to_edmac(mdp, dma_addr);
1200 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1202 /* Rx descriptor address set */
1204 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1205 if (sh_eth_is_gether(mdp) ||
1206 sh_eth_is_rz_fast_ether(mdp))
1207 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1211 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1213 /* Mark the last entry as wrapping the ring. */
1214 rxdesc->status |= cpu_to_edmac(mdp, RD_RDLE);
1216 memset(mdp->tx_ring, 0, tx_ringsize);
1218 /* build Tx ring buffer */
1219 for (i = 0; i < mdp->num_tx_ring; i++) {
1220 mdp->tx_skbuff[i] = NULL;
1221 txdesc = &mdp->tx_ring[i];
1222 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1223 txdesc->buffer_length = 0;
1225 /* Tx descriptor address set */
1226 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1227 if (sh_eth_is_gether(mdp) ||
1228 sh_eth_is_rz_fast_ether(mdp))
1229 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1233 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1236 /* Get skb and descriptor buffer */
1237 static int sh_eth_ring_init(struct net_device *ndev)
1239 struct sh_eth_private *mdp = netdev_priv(ndev);
1240 int rx_ringsize, tx_ringsize;
1242 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1243 * card needs room to do 8 byte alignment, +2 so we can reserve
1244 * the first 2 bytes, and +16 gets room for the status word from the
1247 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1248 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1249 if (mdp->cd->rpadir)
1250 mdp->rx_buf_sz += NET_IP_ALIGN;
1252 /* Allocate RX and TX skb rings */
1253 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1255 if (!mdp->rx_skbuff)
1258 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1260 if (!mdp->tx_skbuff)
1263 /* Allocate all Rx descriptors. */
1264 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1265 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1272 /* Allocate all Tx descriptors. */
1273 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1274 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1281 /* Free Rx and Tx skb ring buffer and DMA buffer */
1282 sh_eth_ring_free(ndev);
1287 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1290 struct sh_eth_private *mdp = netdev_priv(ndev);
1294 ret = sh_eth_reset(ndev);
1298 if (mdp->cd->rmiimode)
1299 sh_eth_write(ndev, 0x1, RMIIMODE);
1301 /* Descriptor format */
1302 sh_eth_ring_format(ndev);
1303 if (mdp->cd->rpadir)
1304 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1306 /* all sh_eth int mask */
1307 sh_eth_write(ndev, 0, EESIPR);
1309 #if defined(__LITTLE_ENDIAN)
1310 if (mdp->cd->hw_swap)
1311 sh_eth_write(ndev, EDMR_EL, EDMR);
1314 sh_eth_write(ndev, 0, EDMR);
1317 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1318 sh_eth_write(ndev, 0, TFTR);
1320 /* Frame recv control (enable multiple-packets per rx irq) */
1321 sh_eth_write(ndev, RMCR_RNC, RMCR);
1323 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1326 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1328 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1330 if (!mdp->cd->no_trimd)
1331 sh_eth_write(ndev, 0, TRIMD);
1333 /* Recv frame limit set register */
1334 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1337 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1339 mdp->irq_enabled = true;
1340 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1343 /* PAUSE Prohibition */
1344 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1345 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1347 sh_eth_write(ndev, val, ECMR);
1349 if (mdp->cd->set_rate)
1350 mdp->cd->set_rate(ndev);
1352 /* E-MAC Status Register clear */
1353 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1355 /* E-MAC Interrupt Enable register */
1357 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1359 /* Set MAC address */
1360 update_mac_address(ndev);
1364 sh_eth_write(ndev, APR_AP, APR);
1366 sh_eth_write(ndev, MPR_MP, MPR);
1367 if (mdp->cd->tpauser)
1368 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1371 /* Setting the Rx mode will start the Rx process. */
1372 sh_eth_write(ndev, EDRRR_R, EDRRR);
1374 netif_start_queue(ndev);
1380 static void sh_eth_dev_exit(struct net_device *ndev)
1382 struct sh_eth_private *mdp = netdev_priv(ndev);
1385 /* Deactivate all TX descriptors, so DMA should stop at next
1386 * packet boundary if it's currently running
1388 for (i = 0; i < mdp->num_tx_ring; i++)
1389 mdp->tx_ring[i].status &= ~cpu_to_edmac(mdp, TD_TACT);
1391 /* Disable TX FIFO egress to MAC */
1392 sh_eth_rcv_snd_disable(ndev);
1394 /* Stop RX DMA at next packet boundary */
1395 sh_eth_write(ndev, 0, EDRRR);
1397 /* Aside from TX DMA, we can't tell when the hardware is
1398 * really stopped, so we need to reset to make sure.
1399 * Before doing that, wait for long enough to *probably*
1400 * finish transmitting the last packet and poll stats.
1402 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1403 sh_eth_get_stats(ndev);
1406 /* Set MAC address again */
1407 update_mac_address(ndev);
1410 /* free Tx skb function */
1411 static int sh_eth_txfree(struct net_device *ndev)
1413 struct sh_eth_private *mdp = netdev_priv(ndev);
1414 struct sh_eth_txdesc *txdesc;
1418 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1419 entry = mdp->dirty_tx % mdp->num_tx_ring;
1420 txdesc = &mdp->tx_ring[entry];
1421 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1423 /* TACT bit must be checked before all the following reads */
1425 netif_info(mdp, tx_done, ndev,
1426 "tx entry %d status 0x%08x\n",
1427 entry, edmac_to_cpu(mdp, txdesc->status));
1428 /* Free the original skb. */
1429 if (mdp->tx_skbuff[entry]) {
1430 dma_unmap_single(&ndev->dev,
1431 edmac_to_cpu(mdp, txdesc->addr),
1432 txdesc->buffer_length, DMA_TO_DEVICE);
1433 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1434 mdp->tx_skbuff[entry] = NULL;
1437 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1438 if (entry >= mdp->num_tx_ring - 1)
1439 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1441 ndev->stats.tx_packets++;
1442 ndev->stats.tx_bytes += txdesc->buffer_length;
1447 /* Packet receive function */
1448 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1450 struct sh_eth_private *mdp = netdev_priv(ndev);
1451 struct sh_eth_rxdesc *rxdesc;
1453 int entry = mdp->cur_rx % mdp->num_rx_ring;
1454 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1456 struct sk_buff *skb;
1459 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1460 dma_addr_t dma_addr;
1462 boguscnt = min(boguscnt, *quota);
1464 rxdesc = &mdp->rx_ring[entry];
1465 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1466 /* RACT bit must be checked before all the following reads */
1468 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1469 pkt_len = rxdesc->frame_length;
1474 netif_info(mdp, rx_status, ndev,
1475 "rx entry %d status 0x%08x len %d\n",
1476 entry, desc_status, pkt_len);
1478 if (!(desc_status & RDFEND))
1479 ndev->stats.rx_length_errors++;
1481 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1482 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1483 * bit 0. However, in case of the R8A7740 and R7S72100
1484 * the RFS bits are from bit 25 to bit 16. So, the
1485 * driver needs right shifting by 16.
1487 if (mdp->cd->shift_rd0)
1490 skb = mdp->rx_skbuff[entry];
1491 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1492 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1493 ndev->stats.rx_errors++;
1494 if (desc_status & RD_RFS1)
1495 ndev->stats.rx_crc_errors++;
1496 if (desc_status & RD_RFS2)
1497 ndev->stats.rx_frame_errors++;
1498 if (desc_status & RD_RFS3)
1499 ndev->stats.rx_length_errors++;
1500 if (desc_status & RD_RFS4)
1501 ndev->stats.rx_length_errors++;
1502 if (desc_status & RD_RFS6)
1503 ndev->stats.rx_missed_errors++;
1504 if (desc_status & RD_RFS10)
1505 ndev->stats.rx_over_errors++;
1507 dma_addr = edmac_to_cpu(mdp, rxdesc->addr);
1508 if (!mdp->cd->hw_swap)
1510 phys_to_virt(ALIGN(dma_addr, 4)),
1512 mdp->rx_skbuff[entry] = NULL;
1513 if (mdp->cd->rpadir)
1514 skb_reserve(skb, NET_IP_ALIGN);
1515 dma_unmap_single(&ndev->dev, dma_addr,
1516 ALIGN(mdp->rx_buf_sz, 32),
1518 skb_put(skb, pkt_len);
1519 skb->protocol = eth_type_trans(skb, ndev);
1520 netif_receive_skb(skb);
1521 ndev->stats.rx_packets++;
1522 ndev->stats.rx_bytes += pkt_len;
1523 if (desc_status & RD_RFS8)
1524 ndev->stats.multicast++;
1526 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1527 rxdesc = &mdp->rx_ring[entry];
1530 /* Refill the Rx ring buffers. */
1531 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1532 entry = mdp->dirty_rx % mdp->num_rx_ring;
1533 rxdesc = &mdp->rx_ring[entry];
1534 /* The size of the buffer is 32 byte boundary. */
1535 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 32);
1537 if (mdp->rx_skbuff[entry] == NULL) {
1538 skb = netdev_alloc_skb(ndev, skbuff_size);
1540 break; /* Better luck next round. */
1541 sh_eth_set_receive_align(skb);
1542 dma_addr = dma_map_single(&ndev->dev, skb->data,
1543 rxdesc->buffer_length,
1545 if (dma_mapping_error(&ndev->dev, dma_addr)) {
1549 mdp->rx_skbuff[entry] = skb;
1551 skb_checksum_none_assert(skb);
1552 rxdesc->addr = cpu_to_edmac(mdp, dma_addr);
1554 dma_wmb(); /* RACT bit must be set after all the above writes */
1555 if (entry >= mdp->num_rx_ring - 1)
1557 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDLE);
1560 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1563 /* Restart Rx engine if stopped. */
1564 /* If we don't need to check status, don't. -KDU */
1565 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1566 /* fix the values for the next receiving if RDE is set */
1567 if (intr_status & EESR_RDE &&
1568 mdp->reg_offset[RDFAR] != SH_ETH_OFFSET_INVALID) {
1569 u32 count = (sh_eth_read(ndev, RDFAR) -
1570 sh_eth_read(ndev, RDLAR)) >> 4;
1572 mdp->cur_rx = count;
1573 mdp->dirty_rx = count;
1575 sh_eth_write(ndev, EDRRR_R, EDRRR);
1578 *quota -= limit - boguscnt - 1;
1583 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1585 /* disable tx and rx */
1586 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1587 ~(ECMR_RE | ECMR_TE), ECMR);
1590 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1592 /* enable tx and rx */
1593 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1594 (ECMR_RE | ECMR_TE), ECMR);
1597 /* error control function */
1598 static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1600 struct sh_eth_private *mdp = netdev_priv(ndev);
1605 if (intr_status & EESR_ECI) {
1606 felic_stat = sh_eth_read(ndev, ECSR);
1607 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1608 if (felic_stat & ECSR_ICD)
1609 ndev->stats.tx_carrier_errors++;
1610 if (felic_stat & ECSR_LCHNG) {
1612 if (mdp->cd->no_psr || mdp->no_ether_link) {
1615 link_stat = (sh_eth_read(ndev, PSR));
1616 if (mdp->ether_link_active_low)
1617 link_stat = ~link_stat;
1619 if (!(link_stat & PHY_ST_LINK)) {
1620 sh_eth_rcv_snd_disable(ndev);
1623 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1624 ~DMAC_M_ECI, EESIPR);
1626 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1628 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1629 DMAC_M_ECI, EESIPR);
1630 /* enable tx and rx */
1631 sh_eth_rcv_snd_enable(ndev);
1637 if (intr_status & EESR_TWB) {
1638 /* Unused write back interrupt */
1639 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1640 ndev->stats.tx_aborted_errors++;
1641 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1645 if (intr_status & EESR_RABT) {
1646 /* Receive Abort int */
1647 if (intr_status & EESR_RFRMER) {
1648 /* Receive Frame Overflow int */
1649 ndev->stats.rx_frame_errors++;
1653 if (intr_status & EESR_TDE) {
1654 /* Transmit Descriptor Empty int */
1655 ndev->stats.tx_fifo_errors++;
1656 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1659 if (intr_status & EESR_TFE) {
1660 /* FIFO under flow */
1661 ndev->stats.tx_fifo_errors++;
1662 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1665 if (intr_status & EESR_RDE) {
1666 /* Receive Descriptor Empty int */
1667 ndev->stats.rx_over_errors++;
1670 if (intr_status & EESR_RFE) {
1671 /* Receive FIFO Overflow int */
1672 ndev->stats.rx_fifo_errors++;
1675 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1677 ndev->stats.tx_fifo_errors++;
1678 netif_err(mdp, tx_err, ndev, "Address Error\n");
1681 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1682 if (mdp->cd->no_ade)
1684 if (intr_status & mask) {
1686 u32 edtrr = sh_eth_read(ndev, EDTRR);
1689 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1690 intr_status, mdp->cur_tx, mdp->dirty_tx,
1691 (u32)ndev->state, edtrr);
1692 /* dirty buffer free */
1693 sh_eth_txfree(ndev);
1696 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1698 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1701 netif_wake_queue(ndev);
1705 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1707 struct net_device *ndev = netdev;
1708 struct sh_eth_private *mdp = netdev_priv(ndev);
1709 struct sh_eth_cpu_data *cd = mdp->cd;
1710 irqreturn_t ret = IRQ_NONE;
1711 u32 intr_status, intr_enable;
1713 spin_lock(&mdp->lock);
1715 /* Get interrupt status */
1716 intr_status = sh_eth_read(ndev, EESR);
1717 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1718 * enabled since it's the one that comes thru regardless of the mask,
1719 * and we need to fully handle it in sh_eth_error() in order to quench
1720 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1722 intr_enable = sh_eth_read(ndev, EESIPR);
1723 intr_status &= intr_enable | DMAC_M_ECI;
1724 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1729 if (!likely(mdp->irq_enabled)) {
1730 sh_eth_write(ndev, 0, EESIPR);
1734 if (intr_status & EESR_RX_CHECK) {
1735 if (napi_schedule_prep(&mdp->napi)) {
1736 /* Mask Rx interrupts */
1737 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1739 __napi_schedule(&mdp->napi);
1742 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1743 intr_status, intr_enable);
1748 if (intr_status & cd->tx_check) {
1749 /* Clear Tx interrupts */
1750 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1752 sh_eth_txfree(ndev);
1753 netif_wake_queue(ndev);
1756 if (intr_status & cd->eesr_err_check) {
1757 /* Clear error interrupts */
1758 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1760 sh_eth_error(ndev, intr_status);
1764 spin_unlock(&mdp->lock);
1769 static int sh_eth_poll(struct napi_struct *napi, int budget)
1771 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1773 struct net_device *ndev = napi->dev;
1778 intr_status = sh_eth_read(ndev, EESR);
1779 if (!(intr_status & EESR_RX_CHECK))
1781 /* Clear Rx interrupts */
1782 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1784 if (sh_eth_rx(ndev, intr_status, "a))
1788 napi_complete(napi);
1790 /* Reenable Rx interrupts */
1791 if (mdp->irq_enabled)
1792 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1794 return budget - quota;
1797 /* PHY state control function */
1798 static void sh_eth_adjust_link(struct net_device *ndev)
1800 struct sh_eth_private *mdp = netdev_priv(ndev);
1801 struct phy_device *phydev = mdp->phydev;
1805 if (phydev->duplex != mdp->duplex) {
1807 mdp->duplex = phydev->duplex;
1808 if (mdp->cd->set_duplex)
1809 mdp->cd->set_duplex(ndev);
1812 if (phydev->speed != mdp->speed) {
1814 mdp->speed = phydev->speed;
1815 if (mdp->cd->set_rate)
1816 mdp->cd->set_rate(ndev);
1820 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1823 mdp->link = phydev->link;
1824 if (mdp->cd->no_psr || mdp->no_ether_link)
1825 sh_eth_rcv_snd_enable(ndev);
1827 } else if (mdp->link) {
1832 if (mdp->cd->no_psr || mdp->no_ether_link)
1833 sh_eth_rcv_snd_disable(ndev);
1836 if (new_state && netif_msg_link(mdp))
1837 phy_print_status(phydev);
1840 /* PHY init function */
1841 static int sh_eth_phy_init(struct net_device *ndev)
1843 struct device_node *np = ndev->dev.parent->of_node;
1844 struct sh_eth_private *mdp = netdev_priv(ndev);
1845 struct phy_device *phydev = NULL;
1851 /* Try connect to PHY */
1853 struct device_node *pn;
1855 pn = of_parse_phandle(np, "phy-handle", 0);
1856 phydev = of_phy_connect(ndev, pn,
1857 sh_eth_adjust_link, 0,
1858 mdp->phy_interface);
1861 phydev = ERR_PTR(-ENOENT);
1863 char phy_id[MII_BUS_ID_SIZE + 3];
1865 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1866 mdp->mii_bus->id, mdp->phy_id);
1868 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1869 mdp->phy_interface);
1872 if (IS_ERR(phydev)) {
1873 netdev_err(ndev, "failed to connect PHY\n");
1874 return PTR_ERR(phydev);
1877 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1878 phydev->addr, phydev->irq, phydev->drv->name);
1880 mdp->phydev = phydev;
1885 /* PHY control start function */
1886 static int sh_eth_phy_start(struct net_device *ndev)
1888 struct sh_eth_private *mdp = netdev_priv(ndev);
1891 ret = sh_eth_phy_init(ndev);
1895 phy_start(mdp->phydev);
1900 static int sh_eth_get_settings(struct net_device *ndev,
1901 struct ethtool_cmd *ecmd)
1903 struct sh_eth_private *mdp = netdev_priv(ndev);
1904 unsigned long flags;
1910 spin_lock_irqsave(&mdp->lock, flags);
1911 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1912 spin_unlock_irqrestore(&mdp->lock, flags);
1917 static int sh_eth_set_settings(struct net_device *ndev,
1918 struct ethtool_cmd *ecmd)
1920 struct sh_eth_private *mdp = netdev_priv(ndev);
1921 unsigned long flags;
1927 spin_lock_irqsave(&mdp->lock, flags);
1929 /* disable tx and rx */
1930 sh_eth_rcv_snd_disable(ndev);
1932 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1936 if (ecmd->duplex == DUPLEX_FULL)
1941 if (mdp->cd->set_duplex)
1942 mdp->cd->set_duplex(ndev);
1947 /* enable tx and rx */
1948 sh_eth_rcv_snd_enable(ndev);
1950 spin_unlock_irqrestore(&mdp->lock, flags);
1955 /* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
1956 * version must be bumped as well. Just adding registers up to that
1957 * limit is fine, as long as the existing register indices don't
1960 #define SH_ETH_REG_DUMP_VERSION 1
1961 #define SH_ETH_REG_DUMP_MAX_REGS 256
1963 static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
1965 struct sh_eth_private *mdp = netdev_priv(ndev);
1966 struct sh_eth_cpu_data *cd = mdp->cd;
1970 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
1972 /* Dump starts with a bitmap that tells ethtool which
1973 * registers are defined for this chip.
1975 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
1983 /* Add a register to the dump, if it has a defined offset.
1984 * This automatically skips most undefined registers, but for
1985 * some it is also necessary to check a capability flag in
1986 * struct sh_eth_cpu_data.
1988 #define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
1989 #define add_reg_from(reg, read_expr) do { \
1990 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
1992 mark_reg_valid(reg); \
1993 *buf++ = read_expr; \
1998 #define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
1999 #define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2071 add_tsu_reg(TSU_CTRST);
2072 add_tsu_reg(TSU_FWEN0);
2073 add_tsu_reg(TSU_FWEN1);
2074 add_tsu_reg(TSU_FCM);
2075 add_tsu_reg(TSU_BSYSL0);
2076 add_tsu_reg(TSU_BSYSL1);
2077 add_tsu_reg(TSU_PRISL0);
2078 add_tsu_reg(TSU_PRISL1);
2079 add_tsu_reg(TSU_FWSL0);
2080 add_tsu_reg(TSU_FWSL1);
2081 add_tsu_reg(TSU_FWSLC);
2082 add_tsu_reg(TSU_QTAG0);
2083 add_tsu_reg(TSU_QTAG1);
2084 add_tsu_reg(TSU_QTAGM0);
2085 add_tsu_reg(TSU_QTAGM1);
2086 add_tsu_reg(TSU_FWSR);
2087 add_tsu_reg(TSU_FWINMK);
2088 add_tsu_reg(TSU_ADQT0);
2089 add_tsu_reg(TSU_ADQT1);
2090 add_tsu_reg(TSU_VTAG0);
2091 add_tsu_reg(TSU_VTAG1);
2092 add_tsu_reg(TSU_ADSBSY);
2093 add_tsu_reg(TSU_TEN);
2094 add_tsu_reg(TSU_POST1);
2095 add_tsu_reg(TSU_POST2);
2096 add_tsu_reg(TSU_POST3);
2097 add_tsu_reg(TSU_POST4);
2098 if (mdp->reg_offset[TSU_ADRH0] != SH_ETH_OFFSET_INVALID) {
2099 /* This is the start of a table, not just a single
2105 mark_reg_valid(TSU_ADRH0);
2106 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2109 mdp->reg_offset[TSU_ADRH0] +
2112 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2116 #undef mark_reg_valid
2124 static int sh_eth_get_regs_len(struct net_device *ndev)
2126 return __sh_eth_get_regs(ndev, NULL);
2129 static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2132 struct sh_eth_private *mdp = netdev_priv(ndev);
2134 regs->version = SH_ETH_REG_DUMP_VERSION;
2136 pm_runtime_get_sync(&mdp->pdev->dev);
2137 __sh_eth_get_regs(ndev, buf);
2138 pm_runtime_put_sync(&mdp->pdev->dev);
2141 static int sh_eth_nway_reset(struct net_device *ndev)
2143 struct sh_eth_private *mdp = netdev_priv(ndev);
2144 unsigned long flags;
2150 spin_lock_irqsave(&mdp->lock, flags);
2151 ret = phy_start_aneg(mdp->phydev);
2152 spin_unlock_irqrestore(&mdp->lock, flags);
2157 static u32 sh_eth_get_msglevel(struct net_device *ndev)
2159 struct sh_eth_private *mdp = netdev_priv(ndev);
2160 return mdp->msg_enable;
2163 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2165 struct sh_eth_private *mdp = netdev_priv(ndev);
2166 mdp->msg_enable = value;
2169 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2170 "rx_current", "tx_current",
2171 "rx_dirty", "tx_dirty",
2173 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2175 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2179 return SH_ETH_STATS_LEN;
2185 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2186 struct ethtool_stats *stats, u64 *data)
2188 struct sh_eth_private *mdp = netdev_priv(ndev);
2191 /* device-specific stats */
2192 data[i++] = mdp->cur_rx;
2193 data[i++] = mdp->cur_tx;
2194 data[i++] = mdp->dirty_rx;
2195 data[i++] = mdp->dirty_tx;
2198 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2200 switch (stringset) {
2202 memcpy(data, *sh_eth_gstrings_stats,
2203 sizeof(sh_eth_gstrings_stats));
2208 static void sh_eth_get_ringparam(struct net_device *ndev,
2209 struct ethtool_ringparam *ring)
2211 struct sh_eth_private *mdp = netdev_priv(ndev);
2213 ring->rx_max_pending = RX_RING_MAX;
2214 ring->tx_max_pending = TX_RING_MAX;
2215 ring->rx_pending = mdp->num_rx_ring;
2216 ring->tx_pending = mdp->num_tx_ring;
2219 static int sh_eth_set_ringparam(struct net_device *ndev,
2220 struct ethtool_ringparam *ring)
2222 struct sh_eth_private *mdp = netdev_priv(ndev);
2225 if (ring->tx_pending > TX_RING_MAX ||
2226 ring->rx_pending > RX_RING_MAX ||
2227 ring->tx_pending < TX_RING_MIN ||
2228 ring->rx_pending < RX_RING_MIN)
2230 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2233 if (netif_running(ndev)) {
2234 netif_device_detach(ndev);
2235 netif_tx_disable(ndev);
2237 /* Serialise with the interrupt handler and NAPI, then
2238 * disable interrupts. We have to clear the
2239 * irq_enabled flag first to ensure that interrupts
2240 * won't be re-enabled.
2242 mdp->irq_enabled = false;
2243 synchronize_irq(ndev->irq);
2244 napi_synchronize(&mdp->napi);
2245 sh_eth_write(ndev, 0x0000, EESIPR);
2247 sh_eth_dev_exit(ndev);
2249 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2250 sh_eth_ring_free(ndev);
2253 /* Set new parameters */
2254 mdp->num_rx_ring = ring->rx_pending;
2255 mdp->num_tx_ring = ring->tx_pending;
2257 if (netif_running(ndev)) {
2258 ret = sh_eth_ring_init(ndev);
2260 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2264 ret = sh_eth_dev_init(ndev, false);
2266 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2271 mdp->irq_enabled = true;
2272 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2273 /* Setting the Rx mode will start the Rx process. */
2274 sh_eth_write(ndev, EDRRR_R, EDRRR);
2275 netif_device_attach(ndev);
2281 static const struct ethtool_ops sh_eth_ethtool_ops = {
2282 .get_settings = sh_eth_get_settings,
2283 .set_settings = sh_eth_set_settings,
2284 .get_regs_len = sh_eth_get_regs_len,
2285 .get_regs = sh_eth_get_regs,
2286 .nway_reset = sh_eth_nway_reset,
2287 .get_msglevel = sh_eth_get_msglevel,
2288 .set_msglevel = sh_eth_set_msglevel,
2289 .get_link = ethtool_op_get_link,
2290 .get_strings = sh_eth_get_strings,
2291 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2292 .get_sset_count = sh_eth_get_sset_count,
2293 .get_ringparam = sh_eth_get_ringparam,
2294 .set_ringparam = sh_eth_set_ringparam,
2297 /* network device open function */
2298 static int sh_eth_open(struct net_device *ndev)
2301 struct sh_eth_private *mdp = netdev_priv(ndev);
2303 pm_runtime_get_sync(&mdp->pdev->dev);
2305 napi_enable(&mdp->napi);
2307 ret = request_irq(ndev->irq, sh_eth_interrupt,
2308 mdp->cd->irq_flags, ndev->name, ndev);
2310 netdev_err(ndev, "Can not assign IRQ number\n");
2314 /* Descriptor set */
2315 ret = sh_eth_ring_init(ndev);
2320 ret = sh_eth_dev_init(ndev, true);
2324 /* PHY control start*/
2325 ret = sh_eth_phy_start(ndev);
2334 free_irq(ndev->irq, ndev);
2336 napi_disable(&mdp->napi);
2337 pm_runtime_put_sync(&mdp->pdev->dev);
2341 /* Timeout function */
2342 static void sh_eth_tx_timeout(struct net_device *ndev)
2344 struct sh_eth_private *mdp = netdev_priv(ndev);
2345 struct sh_eth_rxdesc *rxdesc;
2348 netif_stop_queue(ndev);
2350 netif_err(mdp, timer, ndev,
2351 "transmit timed out, status %8.8x, resetting...\n",
2352 sh_eth_read(ndev, EESR));
2354 /* tx_errors count up */
2355 ndev->stats.tx_errors++;
2357 /* Free all the skbuffs in the Rx queue. */
2358 for (i = 0; i < mdp->num_rx_ring; i++) {
2359 rxdesc = &mdp->rx_ring[i];
2360 rxdesc->status = cpu_to_edmac(mdp, 0);
2361 rxdesc->addr = cpu_to_edmac(mdp, 0xBADF00D0);
2362 dev_kfree_skb(mdp->rx_skbuff[i]);
2363 mdp->rx_skbuff[i] = NULL;
2365 for (i = 0; i < mdp->num_tx_ring; i++) {
2366 dev_kfree_skb(mdp->tx_skbuff[i]);
2367 mdp->tx_skbuff[i] = NULL;
2371 sh_eth_dev_init(ndev, true);
2374 /* Packet transmit function */
2375 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2377 struct sh_eth_private *mdp = netdev_priv(ndev);
2378 struct sh_eth_txdesc *txdesc;
2379 dma_addr_t dma_addr;
2381 unsigned long flags;
2383 spin_lock_irqsave(&mdp->lock, flags);
2384 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2385 if (!sh_eth_txfree(ndev)) {
2386 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2387 netif_stop_queue(ndev);
2388 spin_unlock_irqrestore(&mdp->lock, flags);
2389 return NETDEV_TX_BUSY;
2392 spin_unlock_irqrestore(&mdp->lock, flags);
2394 if (skb_put_padto(skb, ETH_ZLEN))
2395 return NETDEV_TX_OK;
2397 entry = mdp->cur_tx % mdp->num_tx_ring;
2398 mdp->tx_skbuff[entry] = skb;
2399 txdesc = &mdp->tx_ring[entry];
2401 if (!mdp->cd->hw_swap)
2402 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2403 dma_addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2405 if (dma_mapping_error(&ndev->dev, dma_addr)) {
2407 return NETDEV_TX_OK;
2409 txdesc->addr = cpu_to_edmac(mdp, dma_addr);
2410 txdesc->buffer_length = skb->len;
2412 dma_wmb(); /* TACT bit must be set after all the above writes */
2413 if (entry >= mdp->num_tx_ring - 1)
2414 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2416 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2420 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2421 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2423 return NETDEV_TX_OK;
2426 /* The statistics registers have write-clear behaviour, which means we
2427 * will lose any increment between the read and write. We mitigate
2428 * this by only clearing when we read a non-zero value, so we will
2429 * never falsely report a total of zero.
2432 sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2434 u32 delta = sh_eth_read(ndev, reg);
2438 sh_eth_write(ndev, 0, reg);
2442 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2444 struct sh_eth_private *mdp = netdev_priv(ndev);
2446 if (sh_eth_is_rz_fast_ether(mdp))
2447 return &ndev->stats;
2449 if (!mdp->is_opened)
2450 return &ndev->stats;
2452 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2453 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2454 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2456 if (sh_eth_is_gether(mdp)) {
2457 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2459 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2462 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2466 return &ndev->stats;
2469 /* device close function */
2470 static int sh_eth_close(struct net_device *ndev)
2472 struct sh_eth_private *mdp = netdev_priv(ndev);
2474 netif_stop_queue(ndev);
2476 /* Serialise with the interrupt handler and NAPI, then disable
2477 * interrupts. We have to clear the irq_enabled flag first to
2478 * ensure that interrupts won't be re-enabled.
2480 mdp->irq_enabled = false;
2481 synchronize_irq(ndev->irq);
2482 napi_disable(&mdp->napi);
2483 sh_eth_write(ndev, 0x0000, EESIPR);
2485 sh_eth_dev_exit(ndev);
2487 /* PHY Disconnect */
2489 phy_stop(mdp->phydev);
2490 phy_disconnect(mdp->phydev);
2494 free_irq(ndev->irq, ndev);
2496 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2497 sh_eth_ring_free(ndev);
2499 pm_runtime_put_sync(&mdp->pdev->dev);
2506 /* ioctl to device function */
2507 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2509 struct sh_eth_private *mdp = netdev_priv(ndev);
2510 struct phy_device *phydev = mdp->phydev;
2512 if (!netif_running(ndev))
2518 return phy_mii_ioctl(phydev, rq, cmd);
2521 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2522 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2525 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2528 static u32 sh_eth_tsu_get_post_mask(int entry)
2530 return 0x0f << (28 - ((entry % 8) * 4));
2533 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2535 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2538 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2541 struct sh_eth_private *mdp = netdev_priv(ndev);
2545 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2546 tmp = ioread32(reg_offset);
2547 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2550 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2553 struct sh_eth_private *mdp = netdev_priv(ndev);
2554 u32 post_mask, ref_mask, tmp;
2557 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2558 post_mask = sh_eth_tsu_get_post_mask(entry);
2559 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2561 tmp = ioread32(reg_offset);
2562 iowrite32(tmp & ~post_mask, reg_offset);
2564 /* If other port enables, the function returns "true" */
2565 return tmp & ref_mask;
2568 static int sh_eth_tsu_busy(struct net_device *ndev)
2570 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2571 struct sh_eth_private *mdp = netdev_priv(ndev);
2573 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2577 netdev_err(ndev, "%s: timeout\n", __func__);
2585 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2590 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2591 iowrite32(val, reg);
2592 if (sh_eth_tsu_busy(ndev) < 0)
2595 val = addr[4] << 8 | addr[5];
2596 iowrite32(val, reg + 4);
2597 if (sh_eth_tsu_busy(ndev) < 0)
2603 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2607 val = ioread32(reg);
2608 addr[0] = (val >> 24) & 0xff;
2609 addr[1] = (val >> 16) & 0xff;
2610 addr[2] = (val >> 8) & 0xff;
2611 addr[3] = val & 0xff;
2612 val = ioread32(reg + 4);
2613 addr[4] = (val >> 8) & 0xff;
2614 addr[5] = val & 0xff;
2618 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2620 struct sh_eth_private *mdp = netdev_priv(ndev);
2621 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2623 u8 c_addr[ETH_ALEN];
2625 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2626 sh_eth_tsu_read_entry(reg_offset, c_addr);
2627 if (ether_addr_equal(addr, c_addr))
2634 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2639 memset(blank, 0, sizeof(blank));
2640 entry = sh_eth_tsu_find_entry(ndev, blank);
2641 return (entry < 0) ? -ENOMEM : entry;
2644 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2647 struct sh_eth_private *mdp = netdev_priv(ndev);
2648 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2652 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2653 ~(1 << (31 - entry)), TSU_TEN);
2655 memset(blank, 0, sizeof(blank));
2656 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2662 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2664 struct sh_eth_private *mdp = netdev_priv(ndev);
2665 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2671 i = sh_eth_tsu_find_entry(ndev, addr);
2673 /* No entry found, create one */
2674 i = sh_eth_tsu_find_empty(ndev);
2677 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2681 /* Enable the entry */
2682 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2683 (1 << (31 - i)), TSU_TEN);
2686 /* Entry found or created, enable POST */
2687 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2692 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2694 struct sh_eth_private *mdp = netdev_priv(ndev);
2700 i = sh_eth_tsu_find_entry(ndev, addr);
2703 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2706 /* Disable the entry if both ports was disabled */
2707 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2715 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2717 struct sh_eth_private *mdp = netdev_priv(ndev);
2723 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2724 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2727 /* Disable the entry if both ports was disabled */
2728 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2736 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2738 struct sh_eth_private *mdp = netdev_priv(ndev);
2740 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2746 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2747 sh_eth_tsu_read_entry(reg_offset, addr);
2748 if (is_multicast_ether_addr(addr))
2749 sh_eth_tsu_del_entry(ndev, addr);
2753 /* Update promiscuous flag and multicast filter */
2754 static void sh_eth_set_rx_mode(struct net_device *ndev)
2756 struct sh_eth_private *mdp = netdev_priv(ndev);
2759 unsigned long flags;
2761 spin_lock_irqsave(&mdp->lock, flags);
2762 /* Initial condition is MCT = 1, PRM = 0.
2763 * Depending on ndev->flags, set PRM or clear MCT
2765 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2767 ecmr_bits |= ECMR_MCT;
2769 if (!(ndev->flags & IFF_MULTICAST)) {
2770 sh_eth_tsu_purge_mcast(ndev);
2773 if (ndev->flags & IFF_ALLMULTI) {
2774 sh_eth_tsu_purge_mcast(ndev);
2775 ecmr_bits &= ~ECMR_MCT;
2779 if (ndev->flags & IFF_PROMISC) {
2780 sh_eth_tsu_purge_all(ndev);
2781 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2782 } else if (mdp->cd->tsu) {
2783 struct netdev_hw_addr *ha;
2784 netdev_for_each_mc_addr(ha, ndev) {
2785 if (mcast_all && is_multicast_ether_addr(ha->addr))
2788 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2790 sh_eth_tsu_purge_mcast(ndev);
2791 ecmr_bits &= ~ECMR_MCT;
2798 /* update the ethernet mode */
2799 sh_eth_write(ndev, ecmr_bits, ECMR);
2801 spin_unlock_irqrestore(&mdp->lock, flags);
2804 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2812 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2813 __be16 proto, u16 vid)
2815 struct sh_eth_private *mdp = netdev_priv(ndev);
2816 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2818 if (unlikely(!mdp->cd->tsu))
2821 /* No filtering if vid = 0 */
2825 mdp->vlan_num_ids++;
2827 /* The controller has one VLAN tag HW filter. So, if the filter is
2828 * already enabled, the driver disables it and the filte
2830 if (mdp->vlan_num_ids > 1) {
2831 /* disable VLAN filter */
2832 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2836 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2842 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2843 __be16 proto, u16 vid)
2845 struct sh_eth_private *mdp = netdev_priv(ndev);
2846 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2848 if (unlikely(!mdp->cd->tsu))
2851 /* No filtering if vid = 0 */
2855 mdp->vlan_num_ids--;
2856 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2861 /* SuperH's TSU register init function */
2862 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2864 if (sh_eth_is_rz_fast_ether(mdp)) {
2865 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2869 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2870 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2871 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2872 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2873 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2874 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2875 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2876 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2877 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2878 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2879 if (sh_eth_is_gether(mdp)) {
2880 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2881 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2883 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2884 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2886 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2887 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2888 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2889 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2890 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2891 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2892 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2895 /* MDIO bus release function */
2896 static int sh_mdio_release(struct sh_eth_private *mdp)
2898 /* unregister mdio bus */
2899 mdiobus_unregister(mdp->mii_bus);
2901 /* free bitbang info */
2902 free_mdio_bitbang(mdp->mii_bus);
2907 /* MDIO bus init function */
2908 static int sh_mdio_init(struct sh_eth_private *mdp,
2909 struct sh_eth_plat_data *pd)
2912 struct bb_info *bitbang;
2913 struct platform_device *pdev = mdp->pdev;
2914 struct device *dev = &mdp->pdev->dev;
2916 /* create bit control struct for PHY */
2917 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2922 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2923 bitbang->set_gate = pd->set_mdio_gate;
2924 bitbang->mdi_msk = PIR_MDI;
2925 bitbang->mdo_msk = PIR_MDO;
2926 bitbang->mmd_msk = PIR_MMD;
2927 bitbang->mdc_msk = PIR_MDC;
2928 bitbang->ctrl.ops = &bb_ops;
2930 /* MII controller setting */
2931 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2935 /* Hook up MII support for ethtool */
2936 mdp->mii_bus->name = "sh_mii";
2937 mdp->mii_bus->parent = dev;
2938 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2939 pdev->name, pdev->id);
2942 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2944 if (!mdp->mii_bus->irq) {
2949 /* register MDIO bus */
2951 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2953 for (i = 0; i < PHY_MAX_ADDR; i++)
2954 mdp->mii_bus->irq[i] = PHY_POLL;
2955 if (pd->phy_irq > 0)
2956 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2958 ret = mdiobus_register(mdp->mii_bus);
2967 free_mdio_bitbang(mdp->mii_bus);
2971 static const u16 *sh_eth_get_register_offset(int register_type)
2973 const u16 *reg_offset = NULL;
2975 switch (register_type) {
2976 case SH_ETH_REG_GIGABIT:
2977 reg_offset = sh_eth_offset_gigabit;
2979 case SH_ETH_REG_FAST_RZ:
2980 reg_offset = sh_eth_offset_fast_rz;
2982 case SH_ETH_REG_FAST_RCAR:
2983 reg_offset = sh_eth_offset_fast_rcar;
2985 case SH_ETH_REG_FAST_SH4:
2986 reg_offset = sh_eth_offset_fast_sh4;
2988 case SH_ETH_REG_FAST_SH3_SH2:
2989 reg_offset = sh_eth_offset_fast_sh3_sh2;
2998 static const struct net_device_ops sh_eth_netdev_ops = {
2999 .ndo_open = sh_eth_open,
3000 .ndo_stop = sh_eth_close,
3001 .ndo_start_xmit = sh_eth_start_xmit,
3002 .ndo_get_stats = sh_eth_get_stats,
3003 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3004 .ndo_tx_timeout = sh_eth_tx_timeout,
3005 .ndo_do_ioctl = sh_eth_do_ioctl,
3006 .ndo_validate_addr = eth_validate_addr,
3007 .ndo_set_mac_address = eth_mac_addr,
3008 .ndo_change_mtu = eth_change_mtu,
3011 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3012 .ndo_open = sh_eth_open,
3013 .ndo_stop = sh_eth_close,
3014 .ndo_start_xmit = sh_eth_start_xmit,
3015 .ndo_get_stats = sh_eth_get_stats,
3016 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3017 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3018 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3019 .ndo_tx_timeout = sh_eth_tx_timeout,
3020 .ndo_do_ioctl = sh_eth_do_ioctl,
3021 .ndo_validate_addr = eth_validate_addr,
3022 .ndo_set_mac_address = eth_mac_addr,
3023 .ndo_change_mtu = eth_change_mtu,
3027 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3029 struct device_node *np = dev->of_node;
3030 struct sh_eth_plat_data *pdata;
3031 const char *mac_addr;
3033 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3037 pdata->phy_interface = of_get_phy_mode(np);
3039 mac_addr = of_get_mac_address(np);
3041 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3043 pdata->no_ether_link =
3044 of_property_read_bool(np, "renesas,no-ether-link");
3045 pdata->ether_link_active_low =
3046 of_property_read_bool(np, "renesas,ether-link-active-low");
3051 static const struct of_device_id sh_eth_match_table[] = {
3052 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3053 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
3054 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
3055 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
3056 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
3057 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
3058 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
3059 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3062 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3064 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3070 static int sh_eth_drv_probe(struct platform_device *pdev)
3073 struct resource *res;
3074 struct net_device *ndev = NULL;
3075 struct sh_eth_private *mdp = NULL;
3076 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3077 const struct platform_device_id *id = platform_get_device_id(pdev);
3080 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3082 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3086 pm_runtime_enable(&pdev->dev);
3087 pm_runtime_get_sync(&pdev->dev);
3094 ret = platform_get_irq(pdev, 0);
3099 SET_NETDEV_DEV(ndev, &pdev->dev);
3101 mdp = netdev_priv(ndev);
3102 mdp->num_tx_ring = TX_RING_SIZE;
3103 mdp->num_rx_ring = RX_RING_SIZE;
3104 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3105 if (IS_ERR(mdp->addr)) {
3106 ret = PTR_ERR(mdp->addr);
3110 ndev->base_addr = res->start;
3112 spin_lock_init(&mdp->lock);
3115 if (pdev->dev.of_node)
3116 pd = sh_eth_parse_dt(&pdev->dev);
3118 dev_err(&pdev->dev, "no platform data\n");
3124 mdp->phy_id = pd->phy;
3125 mdp->phy_interface = pd->phy_interface;
3127 mdp->edmac_endian = pd->edmac_endian;
3128 mdp->no_ether_link = pd->no_ether_link;
3129 mdp->ether_link_active_low = pd->ether_link_active_low;
3133 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3135 const struct of_device_id *match;
3137 match = of_match_device(of_match_ptr(sh_eth_match_table),
3139 mdp->cd = (struct sh_eth_cpu_data *)match->data;
3141 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3142 if (!mdp->reg_offset) {
3143 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3144 mdp->cd->register_type);
3148 sh_eth_set_default_cpu_data(mdp->cd);
3152 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3154 ndev->netdev_ops = &sh_eth_netdev_ops;
3155 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3156 ndev->watchdog_timeo = TX_TIMEOUT;
3158 /* debug message level */
3159 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3161 /* read and set MAC address */
3162 read_mac_address(ndev, pd->mac_addr);
3163 if (!is_valid_ether_addr(ndev->dev_addr)) {
3164 dev_warn(&pdev->dev,
3165 "no valid MAC address supplied, using a random one.\n");
3166 eth_hw_addr_random(ndev);
3169 /* ioremap the TSU registers */
3171 struct resource *rtsu;
3172 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3173 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
3174 if (IS_ERR(mdp->tsu_addr)) {
3175 ret = PTR_ERR(mdp->tsu_addr);
3178 mdp->port = devno % 2;
3179 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3182 /* initialize first or needed device */
3183 if (!devno || pd->needs_init) {
3184 if (mdp->cd->chip_reset)
3185 mdp->cd->chip_reset(ndev);
3188 /* TSU init (Init only)*/
3189 sh_eth_tsu_init(mdp);
3193 if (mdp->cd->rmiimode)
3194 sh_eth_write(ndev, 0x1, RMIIMODE);
3197 ret = sh_mdio_init(mdp, pd);
3199 dev_err(&ndev->dev, "failed to initialise MDIO\n");
3203 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3205 /* network device register */
3206 ret = register_netdev(ndev);
3210 /* print device information */
3211 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3212 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3214 pm_runtime_put(&pdev->dev);
3215 platform_set_drvdata(pdev, ndev);
3220 netif_napi_del(&mdp->napi);
3221 sh_mdio_release(mdp);
3228 pm_runtime_put(&pdev->dev);
3229 pm_runtime_disable(&pdev->dev);
3233 static int sh_eth_drv_remove(struct platform_device *pdev)
3235 struct net_device *ndev = platform_get_drvdata(pdev);
3236 struct sh_eth_private *mdp = netdev_priv(ndev);
3238 unregister_netdev(ndev);
3239 netif_napi_del(&mdp->napi);
3240 sh_mdio_release(mdp);
3241 pm_runtime_disable(&pdev->dev);
3248 #ifdef CONFIG_PM_SLEEP
3249 static int sh_eth_suspend(struct device *dev)
3251 struct net_device *ndev = dev_get_drvdata(dev);
3254 if (netif_running(ndev)) {
3255 netif_device_detach(ndev);
3256 ret = sh_eth_close(ndev);
3262 static int sh_eth_resume(struct device *dev)
3264 struct net_device *ndev = dev_get_drvdata(dev);
3267 if (netif_running(ndev)) {
3268 ret = sh_eth_open(ndev);
3271 netif_device_attach(ndev);
3278 static int sh_eth_runtime_nop(struct device *dev)
3280 /* Runtime PM callback shared between ->runtime_suspend()
3281 * and ->runtime_resume(). Simply returns success.
3283 * This driver re-initializes all registers after
3284 * pm_runtime_get_sync() anyway so there is no need
3285 * to save and restore registers here.
3290 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3291 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3292 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3294 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3296 #define SH_ETH_PM_OPS NULL
3299 static struct platform_device_id sh_eth_id_table[] = {
3300 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3301 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3302 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3303 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3304 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3305 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3306 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3307 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
3308 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
3309 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
3310 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
3311 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
3312 { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
3313 { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
3316 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3318 static struct platform_driver sh_eth_driver = {
3319 .probe = sh_eth_drv_probe,
3320 .remove = sh_eth_drv_remove,
3321 .id_table = sh_eth_id_table,
3324 .pm = SH_ETH_PM_OPS,
3325 .of_match_table = of_match_ptr(sh_eth_match_table),
3329 module_platform_driver(sh_eth_driver);
3331 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3332 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3333 MODULE_LICENSE("GPL v2");