1 /* SuperH Ethernet device driver
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2014 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/etherdevice.h>
28 #include <linux/delay.h>
29 #include <linux/platform_device.h>
30 #include <linux/mdio-bitbang.h>
31 #include <linux/netdevice.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/of_net.h>
36 #include <linux/phy.h>
37 #include <linux/cache.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/slab.h>
41 #include <linux/ethtool.h>
42 #include <linux/if_vlan.h>
43 #include <linux/clk.h>
44 #include <linux/sh_eth.h>
45 #include <linux/of_mdio.h>
49 #define SH_ETH_DEF_MSG_ENABLE \
55 static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
109 [TSU_CTRST] = 0x0004,
110 [TSU_FWEN0] = 0x0010,
111 [TSU_FWEN1] = 0x0014,
113 [TSU_BSYSL0] = 0x0020,
114 [TSU_BSYSL1] = 0x0024,
115 [TSU_PRISL0] = 0x0028,
116 [TSU_PRISL1] = 0x002c,
117 [TSU_FWSL0] = 0x0030,
118 [TSU_FWSL1] = 0x0034,
119 [TSU_FWSLC] = 0x0038,
120 [TSU_QTAG0] = 0x0040,
121 [TSU_QTAG1] = 0x0044,
123 [TSU_FWINMK] = 0x0054,
124 [TSU_ADQT0] = 0x0048,
125 [TSU_ADQT1] = 0x004c,
126 [TSU_VTAG0] = 0x0058,
127 [TSU_VTAG1] = 0x005c,
128 [TSU_ADSBSY] = 0x0060,
130 [TSU_POST1] = 0x0070,
131 [TSU_POST2] = 0x0074,
132 [TSU_POST3] = 0x0078,
133 [TSU_POST4] = 0x007c,
134 [TSU_ADRH0] = 0x0100,
135 [TSU_ADRL0] = 0x0104,
136 [TSU_ADRH31] = 0x01f8,
137 [TSU_ADRL31] = 0x01fc,
153 static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
197 [TSU_CTRST] = 0x0004,
198 [TSU_VTAG0] = 0x0058,
199 [TSU_ADSBSY] = 0x0060,
201 [TSU_ADRH0] = 0x0100,
202 [TSU_ADRL0] = 0x0104,
203 [TSU_ADRH31] = 0x01f8,
204 [TSU_ADRL31] = 0x01fc,
212 static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
258 static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
310 static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
357 [TSU_CTRST] = 0x0004,
358 [TSU_FWEN0] = 0x0010,
359 [TSU_FWEN1] = 0x0014,
361 [TSU_BSYSL0] = 0x0020,
362 [TSU_BSYSL1] = 0x0024,
363 [TSU_PRISL0] = 0x0028,
364 [TSU_PRISL1] = 0x002c,
365 [TSU_FWSL0] = 0x0030,
366 [TSU_FWSL1] = 0x0034,
367 [TSU_FWSLC] = 0x0038,
368 [TSU_QTAGM0] = 0x0040,
369 [TSU_QTAGM1] = 0x0044,
370 [TSU_ADQT0] = 0x0048,
371 [TSU_ADQT1] = 0x004c,
373 [TSU_FWINMK] = 0x0054,
374 [TSU_ADSBSY] = 0x0060,
376 [TSU_POST1] = 0x0070,
377 [TSU_POST2] = 0x0074,
378 [TSU_POST3] = 0x0078,
379 [TSU_POST4] = 0x007c,
394 [TSU_ADRH0] = 0x0100,
395 [TSU_ADRL0] = 0x0104,
396 [TSU_ADRL31] = 0x01fc,
399 static bool sh_eth_is_gether(struct sh_eth_private *mdp)
401 return mdp->reg_offset == sh_eth_offset_gigabit;
404 static bool sh_eth_is_rz_fast_ether(struct sh_eth_private *mdp)
406 return mdp->reg_offset == sh_eth_offset_fast_rz;
409 static void sh_eth_select_mii(struct net_device *ndev)
412 struct sh_eth_private *mdp = netdev_priv(ndev);
414 switch (mdp->phy_interface) {
415 case PHY_INTERFACE_MODE_GMII:
418 case PHY_INTERFACE_MODE_MII:
421 case PHY_INTERFACE_MODE_RMII:
426 "PHY interface mode was not setup. Set to MII.\n");
431 sh_eth_write(ndev, value, RMII_MII);
434 static void sh_eth_set_duplex(struct net_device *ndev)
436 struct sh_eth_private *mdp = netdev_priv(ndev);
438 if (mdp->duplex) /* Full */
439 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
441 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
444 /* There is CPU dependent code */
445 static void sh_eth_set_rate_r8a777x(struct net_device *ndev)
447 struct sh_eth_private *mdp = netdev_priv(ndev);
449 switch (mdp->speed) {
450 case 10: /* 10BASE */
451 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR);
453 case 100:/* 100BASE */
454 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR);
462 static struct sh_eth_cpu_data r8a777x_data = {
463 .set_duplex = sh_eth_set_duplex,
464 .set_rate = sh_eth_set_rate_r8a777x,
466 .register_type = SH_ETH_REG_FAST_RCAR,
468 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
469 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
470 .eesipr_value = 0x01ff009f,
472 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
473 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
474 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
476 .fdr_value = 0x00000f0f,
485 static struct sh_eth_cpu_data r8a779x_data = {
486 .set_duplex = sh_eth_set_duplex,
487 .set_rate = sh_eth_set_rate_r8a777x,
489 .register_type = SH_ETH_REG_FAST_RCAR,
491 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
492 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
493 .eesipr_value = 0x01ff009f,
495 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
496 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
497 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
499 .fdr_value = 0x00000f0f,
501 .trscer_err_mask = DESC_I_RINT8,
511 static void sh_eth_set_rate_sh7724(struct net_device *ndev)
513 struct sh_eth_private *mdp = netdev_priv(ndev);
515 switch (mdp->speed) {
516 case 10: /* 10BASE */
517 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
519 case 100:/* 100BASE */
520 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
528 static struct sh_eth_cpu_data sh7724_data = {
529 .set_duplex = sh_eth_set_duplex,
530 .set_rate = sh_eth_set_rate_sh7724,
532 .register_type = SH_ETH_REG_FAST_SH4,
534 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
535 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
536 .eesipr_value = 0x01ff009f,
538 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
539 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
540 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
548 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
551 static void sh_eth_set_rate_sh7757(struct net_device *ndev)
553 struct sh_eth_private *mdp = netdev_priv(ndev);
555 switch (mdp->speed) {
556 case 10: /* 10BASE */
557 sh_eth_write(ndev, 0, RTRATE);
559 case 100:/* 100BASE */
560 sh_eth_write(ndev, 1, RTRATE);
568 static struct sh_eth_cpu_data sh7757_data = {
569 .set_duplex = sh_eth_set_duplex,
570 .set_rate = sh_eth_set_rate_sh7757,
572 .register_type = SH_ETH_REG_FAST_SH4,
574 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
576 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
577 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
578 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
581 .irq_flags = IRQF_SHARED,
588 .rpadir_value = 2 << 16,
591 #define SH_GIGA_ETH_BASE 0xfee00000UL
592 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
593 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
594 static void sh_eth_chip_reset_giga(struct net_device *ndev)
597 unsigned long mahr[2], malr[2];
599 /* save MAHR and MALR */
600 for (i = 0; i < 2; i++) {
601 malr[i] = ioread32((void *)GIGA_MALR(i));
602 mahr[i] = ioread32((void *)GIGA_MAHR(i));
606 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800));
609 /* restore MAHR and MALR */
610 for (i = 0; i < 2; i++) {
611 iowrite32(malr[i], (void *)GIGA_MALR(i));
612 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
616 static void sh_eth_set_rate_giga(struct net_device *ndev)
618 struct sh_eth_private *mdp = netdev_priv(ndev);
620 switch (mdp->speed) {
621 case 10: /* 10BASE */
622 sh_eth_write(ndev, 0x00000000, GECMR);
624 case 100:/* 100BASE */
625 sh_eth_write(ndev, 0x00000010, GECMR);
627 case 1000: /* 1000BASE */
628 sh_eth_write(ndev, 0x00000020, GECMR);
635 /* SH7757(GETHERC) */
636 static struct sh_eth_cpu_data sh7757_data_giga = {
637 .chip_reset = sh_eth_chip_reset_giga,
638 .set_duplex = sh_eth_set_duplex,
639 .set_rate = sh_eth_set_rate_giga,
641 .register_type = SH_ETH_REG_GIGABIT,
643 .ecsr_value = ECSR_ICD | ECSR_MPD,
644 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
645 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
647 .tx_check = EESR_TC1 | EESR_FTC,
648 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
649 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
651 .fdr_value = 0x0000072f,
653 .irq_flags = IRQF_SHARED,
660 .rpadir_value = 2 << 16,
666 static void sh_eth_chip_reset(struct net_device *ndev)
668 struct sh_eth_private *mdp = netdev_priv(ndev);
671 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
675 static void sh_eth_set_rate_gether(struct net_device *ndev)
677 struct sh_eth_private *mdp = netdev_priv(ndev);
679 switch (mdp->speed) {
680 case 10: /* 10BASE */
681 sh_eth_write(ndev, GECMR_10, GECMR);
683 case 100:/* 100BASE */
684 sh_eth_write(ndev, GECMR_100, GECMR);
686 case 1000: /* 1000BASE */
687 sh_eth_write(ndev, GECMR_1000, GECMR);
695 static struct sh_eth_cpu_data sh7734_data = {
696 .chip_reset = sh_eth_chip_reset,
697 .set_duplex = sh_eth_set_duplex,
698 .set_rate = sh_eth_set_rate_gether,
700 .register_type = SH_ETH_REG_GIGABIT,
702 .ecsr_value = ECSR_ICD | ECSR_MPD,
703 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
704 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
706 .tx_check = EESR_TC1 | EESR_FTC,
707 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
708 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
724 static struct sh_eth_cpu_data sh7763_data = {
725 .chip_reset = sh_eth_chip_reset,
726 .set_duplex = sh_eth_set_duplex,
727 .set_rate = sh_eth_set_rate_gether,
729 .register_type = SH_ETH_REG_GIGABIT,
731 .ecsr_value = ECSR_ICD | ECSR_MPD,
732 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
733 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
735 .tx_check = EESR_TC1 | EESR_FTC,
736 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
737 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE |
748 .irq_flags = IRQF_SHARED,
751 static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
753 struct sh_eth_private *mdp = netdev_priv(ndev);
756 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
759 sh_eth_select_mii(ndev);
763 static struct sh_eth_cpu_data r8a7740_data = {
764 .chip_reset = sh_eth_chip_reset_r8a7740,
765 .set_duplex = sh_eth_set_duplex,
766 .set_rate = sh_eth_set_rate_gether,
768 .register_type = SH_ETH_REG_GIGABIT,
770 .ecsr_value = ECSR_ICD | ECSR_MPD,
771 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
772 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
774 .tx_check = EESR_TC1 | EESR_FTC,
775 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
776 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
778 .fdr_value = 0x0000070f,
786 .rpadir_value = 2 << 16,
795 static struct sh_eth_cpu_data r7s72100_data = {
796 .chip_reset = sh_eth_chip_reset,
797 .set_duplex = sh_eth_set_duplex,
799 .register_type = SH_ETH_REG_FAST_RZ,
801 .ecsr_value = ECSR_ICD,
802 .ecsipr_value = ECSIPR_ICDIP,
803 .eesipr_value = 0xff7f009f,
805 .tx_check = EESR_TC1 | EESR_FTC,
806 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
807 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
809 .fdr_value = 0x0000070f,
817 .rpadir_value = 2 << 16,
825 static struct sh_eth_cpu_data sh7619_data = {
826 .register_type = SH_ETH_REG_FAST_SH3_SH2,
828 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
836 static struct sh_eth_cpu_data sh771x_data = {
837 .register_type = SH_ETH_REG_FAST_SH3_SH2,
839 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
843 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
846 cd->ecsr_value = DEFAULT_ECSR_INIT;
848 if (!cd->ecsipr_value)
849 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
851 if (!cd->fcftr_value)
852 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
853 DEFAULT_FIFO_F_D_RFD;
856 cd->fdr_value = DEFAULT_FDR_INIT;
859 cd->tx_check = DEFAULT_TX_CHECK;
861 if (!cd->eesr_err_check)
862 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
864 if (!cd->trscer_err_mask)
865 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
868 static int sh_eth_check_reset(struct net_device *ndev)
874 if (!(sh_eth_read(ndev, EDMR) & 0x3))
880 netdev_err(ndev, "Device reset failed\n");
886 static int sh_eth_reset(struct net_device *ndev)
888 struct sh_eth_private *mdp = netdev_priv(ndev);
891 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp)) {
892 sh_eth_write(ndev, EDSR_ENALL, EDSR);
893 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
896 ret = sh_eth_check_reset(ndev);
901 sh_eth_write(ndev, 0x0, TDLAR);
902 sh_eth_write(ndev, 0x0, TDFAR);
903 sh_eth_write(ndev, 0x0, TDFXR);
904 sh_eth_write(ndev, 0x0, TDFFR);
905 sh_eth_write(ndev, 0x0, RDLAR);
906 sh_eth_write(ndev, 0x0, RDFAR);
907 sh_eth_write(ndev, 0x0, RDFXR);
908 sh_eth_write(ndev, 0x0, RDFFR);
910 /* Reset HW CRC register */
912 sh_eth_write(ndev, 0x0, CSMR);
914 /* Select MII mode */
915 if (mdp->cd->select_mii)
916 sh_eth_select_mii(ndev);
918 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
921 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
928 static void sh_eth_set_receive_align(struct sk_buff *skb)
930 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
933 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
937 /* CPU <-> EDMAC endian convert */
938 static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
940 switch (mdp->edmac_endian) {
941 case EDMAC_LITTLE_ENDIAN:
942 return cpu_to_le32(x);
943 case EDMAC_BIG_ENDIAN:
944 return cpu_to_be32(x);
949 static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
951 switch (mdp->edmac_endian) {
952 case EDMAC_LITTLE_ENDIAN:
953 return le32_to_cpu(x);
954 case EDMAC_BIG_ENDIAN:
955 return be32_to_cpu(x);
960 /* Program the hardware MAC address from dev->dev_addr. */
961 static void update_mac_address(struct net_device *ndev)
964 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
965 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
967 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
970 /* Get MAC address from SuperH MAC address register
972 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
973 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
974 * When you want use this device, you must set MAC address in bootloader.
977 static void read_mac_address(struct net_device *ndev, unsigned char *mac)
979 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
980 memcpy(ndev->dev_addr, mac, ETH_ALEN);
982 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
983 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
984 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
985 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
986 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
987 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
991 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
993 if (sh_eth_is_gether(mdp) || sh_eth_is_rz_fast_ether(mdp))
994 return EDTRR_TRNS_GETHER;
996 return EDTRR_TRNS_ETHER;
1000 void (*set_gate)(void *addr);
1001 struct mdiobb_ctrl ctrl;
1003 u32 mmd_msk;/* MMD */
1010 static void bb_set(void *addr, u32 msk)
1012 iowrite32(ioread32(addr) | msk, addr);
1016 static void bb_clr(void *addr, u32 msk)
1018 iowrite32((ioread32(addr) & ~msk), addr);
1022 static int bb_read(void *addr, u32 msk)
1024 return (ioread32(addr) & msk) != 0;
1027 /* Data I/O pin control */
1028 static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1030 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1032 if (bitbang->set_gate)
1033 bitbang->set_gate(bitbang->addr);
1036 bb_set(bitbang->addr, bitbang->mmd_msk);
1038 bb_clr(bitbang->addr, bitbang->mmd_msk);
1042 static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1044 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1046 if (bitbang->set_gate)
1047 bitbang->set_gate(bitbang->addr);
1050 bb_set(bitbang->addr, bitbang->mdo_msk);
1052 bb_clr(bitbang->addr, bitbang->mdo_msk);
1056 static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1058 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1060 if (bitbang->set_gate)
1061 bitbang->set_gate(bitbang->addr);
1063 return bb_read(bitbang->addr, bitbang->mdi_msk);
1066 /* MDC pin control */
1067 static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1069 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1071 if (bitbang->set_gate)
1072 bitbang->set_gate(bitbang->addr);
1075 bb_set(bitbang->addr, bitbang->mdc_msk);
1077 bb_clr(bitbang->addr, bitbang->mdc_msk);
1080 /* mdio bus control struct */
1081 static struct mdiobb_ops bb_ops = {
1082 .owner = THIS_MODULE,
1083 .set_mdc = sh_mdc_ctrl,
1084 .set_mdio_dir = sh_mmd_ctrl,
1085 .set_mdio_data = sh_set_mdio,
1086 .get_mdio_data = sh_get_mdio,
1089 /* free skb and descriptor buffer */
1090 static void sh_eth_ring_free(struct net_device *ndev)
1092 struct sh_eth_private *mdp = netdev_priv(ndev);
1095 /* Free Rx skb ringbuffer */
1096 if (mdp->rx_skbuff) {
1097 for (i = 0; i < mdp->num_rx_ring; i++)
1098 dev_kfree_skb(mdp->rx_skbuff[i]);
1100 kfree(mdp->rx_skbuff);
1101 mdp->rx_skbuff = NULL;
1103 /* Free Tx skb ringbuffer */
1104 if (mdp->tx_skbuff) {
1105 for (i = 0; i < mdp->num_tx_ring; i++)
1106 dev_kfree_skb(mdp->tx_skbuff[i]);
1108 kfree(mdp->tx_skbuff);
1109 mdp->tx_skbuff = NULL;
1112 /* format skb and descriptor buffer */
1113 static void sh_eth_ring_format(struct net_device *ndev)
1115 struct sh_eth_private *mdp = netdev_priv(ndev);
1117 struct sk_buff *skb;
1118 struct sh_eth_rxdesc *rxdesc = NULL;
1119 struct sh_eth_txdesc *txdesc = NULL;
1120 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1121 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1122 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
1129 memset(mdp->rx_ring, 0, rx_ringsize);
1131 /* build Rx ring buffer */
1132 for (i = 0; i < mdp->num_rx_ring; i++) {
1134 mdp->rx_skbuff[i] = NULL;
1135 skb = netdev_alloc_skb(ndev, skbuff_size);
1136 mdp->rx_skbuff[i] = skb;
1139 sh_eth_set_receive_align(skb);
1142 rxdesc = &mdp->rx_ring[i];
1143 /* The size of the buffer is a multiple of 16 bytes. */
1144 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1145 dma_map_single(&ndev->dev, skb->data, rxdesc->buffer_length,
1147 rxdesc->addr = virt_to_phys(skb->data);
1148 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1150 /* Rx descriptor address set */
1152 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1153 if (sh_eth_is_gether(mdp) ||
1154 sh_eth_is_rz_fast_ether(mdp))
1155 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1159 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1161 /* Mark the last entry as wrapping the ring. */
1162 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
1164 memset(mdp->tx_ring, 0, tx_ringsize);
1166 /* build Tx ring buffer */
1167 for (i = 0; i < mdp->num_tx_ring; i++) {
1168 mdp->tx_skbuff[i] = NULL;
1169 txdesc = &mdp->tx_ring[i];
1170 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1171 txdesc->buffer_length = 0;
1173 /* Tx descriptor address set */
1174 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1175 if (sh_eth_is_gether(mdp) ||
1176 sh_eth_is_rz_fast_ether(mdp))
1177 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1181 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1184 /* Get skb and descriptor buffer */
1185 static int sh_eth_ring_init(struct net_device *ndev)
1187 struct sh_eth_private *mdp = netdev_priv(ndev);
1188 int rx_ringsize, tx_ringsize, ret = 0;
1190 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1191 * card needs room to do 8 byte alignment, +2 so we can reserve
1192 * the first 2 bytes, and +16 gets room for the status word from the
1195 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1196 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1197 if (mdp->cd->rpadir)
1198 mdp->rx_buf_sz += NET_IP_ALIGN;
1200 /* Allocate RX and TX skb rings */
1201 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring,
1202 sizeof(*mdp->rx_skbuff), GFP_KERNEL);
1203 if (!mdp->rx_skbuff) {
1208 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring,
1209 sizeof(*mdp->tx_skbuff), GFP_KERNEL);
1210 if (!mdp->tx_skbuff) {
1215 /* Allocate all Rx descriptors. */
1216 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1217 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
1219 if (!mdp->rx_ring) {
1221 goto desc_ring_free;
1226 /* Allocate all Tx descriptors. */
1227 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1228 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
1230 if (!mdp->tx_ring) {
1232 goto desc_ring_free;
1237 /* free DMA buffer */
1238 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1241 /* Free Rx and Tx skb ring buffer */
1242 sh_eth_ring_free(ndev);
1243 mdp->tx_ring = NULL;
1244 mdp->rx_ring = NULL;
1249 static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp)
1254 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1255 dma_free_coherent(NULL, ringsize, mdp->rx_ring,
1257 mdp->rx_ring = NULL;
1261 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1262 dma_free_coherent(NULL, ringsize, mdp->tx_ring,
1264 mdp->tx_ring = NULL;
1268 static int sh_eth_dev_init(struct net_device *ndev, bool start)
1271 struct sh_eth_private *mdp = netdev_priv(ndev);
1275 ret = sh_eth_reset(ndev);
1279 if (mdp->cd->rmiimode)
1280 sh_eth_write(ndev, 0x1, RMIIMODE);
1282 /* Descriptor format */
1283 sh_eth_ring_format(ndev);
1284 if (mdp->cd->rpadir)
1285 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1287 /* all sh_eth int mask */
1288 sh_eth_write(ndev, 0, EESIPR);
1290 #if defined(__LITTLE_ENDIAN)
1291 if (mdp->cd->hw_swap)
1292 sh_eth_write(ndev, EDMR_EL, EDMR);
1295 sh_eth_write(ndev, 0, EDMR);
1298 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1299 sh_eth_write(ndev, 0, TFTR);
1301 /* Frame recv control (enable multiple-packets per rx irq) */
1302 sh_eth_write(ndev, RMCR_RNC, RMCR);
1304 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1307 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1309 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1311 if (!mdp->cd->no_trimd)
1312 sh_eth_write(ndev, 0, TRIMD);
1314 /* Recv frame limit set register */
1315 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1318 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
1320 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1322 /* PAUSE Prohibition */
1323 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
1324 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
1326 sh_eth_write(ndev, val, ECMR);
1328 if (mdp->cd->set_rate)
1329 mdp->cd->set_rate(ndev);
1331 /* E-MAC Status Register clear */
1332 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1334 /* E-MAC Interrupt Enable register */
1336 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1338 /* Set MAC address */
1339 update_mac_address(ndev);
1343 sh_eth_write(ndev, APR_AP, APR);
1345 sh_eth_write(ndev, MPR_MP, MPR);
1346 if (mdp->cd->tpauser)
1347 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1350 /* Setting the Rx mode will start the Rx process. */
1351 sh_eth_write(ndev, EDRRR_R, EDRRR);
1353 netif_start_queue(ndev);
1359 /* free Tx skb function */
1360 static int sh_eth_txfree(struct net_device *ndev)
1362 struct sh_eth_private *mdp = netdev_priv(ndev);
1363 struct sh_eth_txdesc *txdesc;
1367 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1368 entry = mdp->dirty_tx % mdp->num_tx_ring;
1369 txdesc = &mdp->tx_ring[entry];
1370 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
1372 /* Free the original skb. */
1373 if (mdp->tx_skbuff[entry]) {
1374 dma_unmap_single(&ndev->dev, txdesc->addr,
1375 txdesc->buffer_length, DMA_TO_DEVICE);
1376 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1377 mdp->tx_skbuff[entry] = NULL;
1380 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
1381 if (entry >= mdp->num_tx_ring - 1)
1382 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
1384 ndev->stats.tx_packets++;
1385 ndev->stats.tx_bytes += txdesc->buffer_length;
1390 /* Packet receive function */
1391 static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1393 struct sh_eth_private *mdp = netdev_priv(ndev);
1394 struct sh_eth_rxdesc *rxdesc;
1396 int entry = mdp->cur_rx % mdp->num_rx_ring;
1397 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1399 struct sk_buff *skb;
1402 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN - 1;
1404 boguscnt = min(boguscnt, *quota);
1406 rxdesc = &mdp->rx_ring[entry];
1407 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
1408 desc_status = edmac_to_cpu(mdp, rxdesc->status);
1409 pkt_len = rxdesc->frame_length;
1414 if (!(desc_status & RDFEND))
1415 ndev->stats.rx_length_errors++;
1417 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1418 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1419 * bit 0. However, in case of the R8A7740, R8A779x, and
1420 * R7S72100 the RFS bits are from bit 25 to bit 16. So, the
1421 * driver needs right shifting by 16.
1423 if (mdp->cd->shift_rd0)
1426 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1427 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1428 ndev->stats.rx_errors++;
1429 if (desc_status & RD_RFS1)
1430 ndev->stats.rx_crc_errors++;
1431 if (desc_status & RD_RFS2)
1432 ndev->stats.rx_frame_errors++;
1433 if (desc_status & RD_RFS3)
1434 ndev->stats.rx_length_errors++;
1435 if (desc_status & RD_RFS4)
1436 ndev->stats.rx_length_errors++;
1437 if (desc_status & RD_RFS6)
1438 ndev->stats.rx_missed_errors++;
1439 if (desc_status & RD_RFS10)
1440 ndev->stats.rx_over_errors++;
1442 if (!mdp->cd->hw_swap)
1444 phys_to_virt(ALIGN(rxdesc->addr, 4)),
1446 skb = mdp->rx_skbuff[entry];
1447 mdp->rx_skbuff[entry] = NULL;
1448 if (mdp->cd->rpadir)
1449 skb_reserve(skb, NET_IP_ALIGN);
1450 dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr,
1451 ALIGN(mdp->rx_buf_sz, 16),
1453 skb_put(skb, pkt_len);
1454 skb->protocol = eth_type_trans(skb, ndev);
1455 netif_receive_skb(skb);
1456 ndev->stats.rx_packets++;
1457 ndev->stats.rx_bytes += pkt_len;
1459 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1460 rxdesc = &mdp->rx_ring[entry];
1463 /* Refill the Rx ring buffers. */
1464 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1465 entry = mdp->dirty_rx % mdp->num_rx_ring;
1466 rxdesc = &mdp->rx_ring[entry];
1467 /* The size of the buffer is 16 byte boundary. */
1468 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
1470 if (mdp->rx_skbuff[entry] == NULL) {
1471 skb = netdev_alloc_skb(ndev, skbuff_size);
1472 mdp->rx_skbuff[entry] = skb;
1474 break; /* Better luck next round. */
1475 sh_eth_set_receive_align(skb);
1476 dma_map_single(&ndev->dev, skb->data,
1477 rxdesc->buffer_length, DMA_FROM_DEVICE);
1479 skb_checksum_none_assert(skb);
1480 rxdesc->addr = virt_to_phys(skb->data);
1482 if (entry >= mdp->num_rx_ring - 1)
1484 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
1487 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
1490 /* Restart Rx engine if stopped. */
1491 /* If we don't need to check status, don't. -KDU */
1492 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1493 /* fix the values for the next receiving if RDE is set */
1494 if (intr_status & EESR_RDE) {
1495 u32 count = (sh_eth_read(ndev, RDFAR) -
1496 sh_eth_read(ndev, RDLAR)) >> 4;
1498 mdp->cur_rx = count;
1499 mdp->dirty_rx = count;
1501 sh_eth_write(ndev, EDRRR_R, EDRRR);
1504 *quota -= limit - boguscnt - 1;
1509 static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1511 /* disable tx and rx */
1512 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
1513 ~(ECMR_RE | ECMR_TE), ECMR);
1516 static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1518 /* enable tx and rx */
1519 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
1520 (ECMR_RE | ECMR_TE), ECMR);
1523 /* error control function */
1524 static void sh_eth_error(struct net_device *ndev, int intr_status)
1526 struct sh_eth_private *mdp = netdev_priv(ndev);
1531 if (intr_status & EESR_ECI) {
1532 felic_stat = sh_eth_read(ndev, ECSR);
1533 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1534 if (felic_stat & ECSR_ICD)
1535 ndev->stats.tx_carrier_errors++;
1536 if (felic_stat & ECSR_LCHNG) {
1538 if (mdp->cd->no_psr || mdp->no_ether_link) {
1541 link_stat = (sh_eth_read(ndev, PSR));
1542 if (mdp->ether_link_active_low)
1543 link_stat = ~link_stat;
1545 if (!(link_stat & PHY_ST_LINK)) {
1546 sh_eth_rcv_snd_disable(ndev);
1549 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1550 ~DMAC_M_ECI, EESIPR);
1552 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1554 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1555 DMAC_M_ECI, EESIPR);
1556 /* enable tx and rx */
1557 sh_eth_rcv_snd_enable(ndev);
1563 if (intr_status & EESR_TWB) {
1564 /* Unused write back interrupt */
1565 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1566 ndev->stats.tx_aborted_errors++;
1567 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1571 if (intr_status & EESR_RABT) {
1572 /* Receive Abort int */
1573 if (intr_status & EESR_RFRMER) {
1574 /* Receive Frame Overflow int */
1575 ndev->stats.rx_frame_errors++;
1576 netif_err(mdp, rx_err, ndev, "Receive Abort\n");
1580 if (intr_status & EESR_TDE) {
1581 /* Transmit Descriptor Empty int */
1582 ndev->stats.tx_fifo_errors++;
1583 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1586 if (intr_status & EESR_TFE) {
1587 /* FIFO under flow */
1588 ndev->stats.tx_fifo_errors++;
1589 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1592 if (intr_status & EESR_RDE) {
1593 /* Receive Descriptor Empty int */
1594 ndev->stats.rx_over_errors++;
1595 netif_err(mdp, rx_err, ndev, "Receive Descriptor Empty\n");
1598 if (intr_status & EESR_RFE) {
1599 /* Receive FIFO Overflow int */
1600 ndev->stats.rx_fifo_errors++;
1601 netif_err(mdp, rx_err, ndev, "Receive FIFO Overflow\n");
1604 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1606 ndev->stats.tx_fifo_errors++;
1607 netif_err(mdp, tx_err, ndev, "Address Error\n");
1610 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1611 if (mdp->cd->no_ade)
1613 if (intr_status & mask) {
1615 u32 edtrr = sh_eth_read(ndev, EDTRR);
1618 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1619 intr_status, mdp->cur_tx, mdp->dirty_tx,
1620 (u32)ndev->state, edtrr);
1621 /* dirty buffer free */
1622 sh_eth_txfree(ndev);
1625 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
1627 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
1630 netif_wake_queue(ndev);
1634 static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1636 struct net_device *ndev = netdev;
1637 struct sh_eth_private *mdp = netdev_priv(ndev);
1638 struct sh_eth_cpu_data *cd = mdp->cd;
1639 irqreturn_t ret = IRQ_NONE;
1640 unsigned long intr_status, intr_enable;
1642 spin_lock(&mdp->lock);
1644 /* Get interrupt status */
1645 intr_status = sh_eth_read(ndev, EESR);
1646 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1647 * enabled since it's the one that comes thru regardless of the mask,
1648 * and we need to fully handle it in sh_eth_error() in order to quench
1649 * it as it doesn't get cleared by just writing 1 to the ECI bit...
1651 intr_enable = sh_eth_read(ndev, EESIPR);
1652 intr_status &= intr_enable | DMAC_M_ECI;
1653 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check))
1658 if (intr_status & EESR_RX_CHECK) {
1659 if (napi_schedule_prep(&mdp->napi)) {
1660 /* Mask Rx interrupts */
1661 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1663 __napi_schedule(&mdp->napi);
1666 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n",
1667 intr_status, intr_enable);
1672 if (intr_status & cd->tx_check) {
1673 /* Clear Tx interrupts */
1674 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1676 sh_eth_txfree(ndev);
1677 netif_wake_queue(ndev);
1680 if (intr_status & cd->eesr_err_check) {
1681 /* Clear error interrupts */
1682 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1684 sh_eth_error(ndev, intr_status);
1688 spin_unlock(&mdp->lock);
1693 static int sh_eth_poll(struct napi_struct *napi, int budget)
1695 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1697 struct net_device *ndev = napi->dev;
1699 unsigned long intr_status;
1702 intr_status = sh_eth_read(ndev, EESR);
1703 if (!(intr_status & EESR_RX_CHECK))
1705 /* Clear Rx interrupts */
1706 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1708 if (sh_eth_rx(ndev, intr_status, "a))
1712 napi_complete(napi);
1714 /* Reenable Rx interrupts */
1715 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1717 return budget - quota;
1720 /* PHY state control function */
1721 static void sh_eth_adjust_link(struct net_device *ndev)
1723 struct sh_eth_private *mdp = netdev_priv(ndev);
1724 struct phy_device *phydev = mdp->phydev;
1728 if (phydev->duplex != mdp->duplex) {
1730 mdp->duplex = phydev->duplex;
1731 if (mdp->cd->set_duplex)
1732 mdp->cd->set_duplex(ndev);
1735 if (phydev->speed != mdp->speed) {
1737 mdp->speed = phydev->speed;
1738 if (mdp->cd->set_rate)
1739 mdp->cd->set_rate(ndev);
1743 sh_eth_read(ndev, ECMR) & ~ECMR_TXF,
1746 mdp->link = phydev->link;
1747 if (mdp->cd->no_psr || mdp->no_ether_link)
1748 sh_eth_rcv_snd_enable(ndev);
1750 } else if (mdp->link) {
1755 if (mdp->cd->no_psr || mdp->no_ether_link)
1756 sh_eth_rcv_snd_disable(ndev);
1759 if (new_state && netif_msg_link(mdp))
1760 phy_print_status(phydev);
1763 /* PHY init function */
1764 static int sh_eth_phy_init(struct net_device *ndev)
1766 struct device_node *np = ndev->dev.parent->of_node;
1767 struct sh_eth_private *mdp = netdev_priv(ndev);
1768 struct phy_device *phydev = NULL;
1774 /* Try connect to PHY */
1776 struct device_node *pn;
1778 pn = of_parse_phandle(np, "phy-handle", 0);
1779 phydev = of_phy_connect(ndev, pn,
1780 sh_eth_adjust_link, 0,
1781 mdp->phy_interface);
1784 phydev = ERR_PTR(-ENOENT);
1786 char phy_id[MII_BUS_ID_SIZE + 3];
1788 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1789 mdp->mii_bus->id, mdp->phy_id);
1791 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1792 mdp->phy_interface);
1795 if (IS_ERR(phydev)) {
1796 netdev_err(ndev, "failed to connect PHY\n");
1797 return PTR_ERR(phydev);
1800 netdev_info(ndev, "attached PHY %d (IRQ %d) to driver %s\n",
1801 phydev->addr, phydev->irq, phydev->drv->name);
1803 mdp->phydev = phydev;
1808 /* PHY control start function */
1809 static int sh_eth_phy_start(struct net_device *ndev)
1811 struct sh_eth_private *mdp = netdev_priv(ndev);
1814 ret = sh_eth_phy_init(ndev);
1818 phy_start(mdp->phydev);
1823 static int sh_eth_get_settings(struct net_device *ndev,
1824 struct ethtool_cmd *ecmd)
1826 struct sh_eth_private *mdp = netdev_priv(ndev);
1827 unsigned long flags;
1833 spin_lock_irqsave(&mdp->lock, flags);
1834 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1835 spin_unlock_irqrestore(&mdp->lock, flags);
1840 static int sh_eth_set_settings(struct net_device *ndev,
1841 struct ethtool_cmd *ecmd)
1843 struct sh_eth_private *mdp = netdev_priv(ndev);
1844 unsigned long flags;
1850 spin_lock_irqsave(&mdp->lock, flags);
1852 /* disable tx and rx */
1853 sh_eth_rcv_snd_disable(ndev);
1855 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1859 if (ecmd->duplex == DUPLEX_FULL)
1864 if (mdp->cd->set_duplex)
1865 mdp->cd->set_duplex(ndev);
1870 /* enable tx and rx */
1871 sh_eth_rcv_snd_enable(ndev);
1873 spin_unlock_irqrestore(&mdp->lock, flags);
1878 static int sh_eth_nway_reset(struct net_device *ndev)
1880 struct sh_eth_private *mdp = netdev_priv(ndev);
1881 unsigned long flags;
1887 spin_lock_irqsave(&mdp->lock, flags);
1888 ret = phy_start_aneg(mdp->phydev);
1889 spin_unlock_irqrestore(&mdp->lock, flags);
1894 static u32 sh_eth_get_msglevel(struct net_device *ndev)
1896 struct sh_eth_private *mdp = netdev_priv(ndev);
1897 return mdp->msg_enable;
1900 static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1902 struct sh_eth_private *mdp = netdev_priv(ndev);
1903 mdp->msg_enable = value;
1906 static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1907 "rx_current", "tx_current",
1908 "rx_dirty", "tx_dirty",
1910 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1912 static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1916 return SH_ETH_STATS_LEN;
1922 static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1923 struct ethtool_stats *stats, u64 *data)
1925 struct sh_eth_private *mdp = netdev_priv(ndev);
1928 /* device-specific stats */
1929 data[i++] = mdp->cur_rx;
1930 data[i++] = mdp->cur_tx;
1931 data[i++] = mdp->dirty_rx;
1932 data[i++] = mdp->dirty_tx;
1935 static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1937 switch (stringset) {
1939 memcpy(data, *sh_eth_gstrings_stats,
1940 sizeof(sh_eth_gstrings_stats));
1945 static void sh_eth_get_ringparam(struct net_device *ndev,
1946 struct ethtool_ringparam *ring)
1948 struct sh_eth_private *mdp = netdev_priv(ndev);
1950 ring->rx_max_pending = RX_RING_MAX;
1951 ring->tx_max_pending = TX_RING_MAX;
1952 ring->rx_pending = mdp->num_rx_ring;
1953 ring->tx_pending = mdp->num_tx_ring;
1956 static int sh_eth_set_ringparam(struct net_device *ndev,
1957 struct ethtool_ringparam *ring)
1959 struct sh_eth_private *mdp = netdev_priv(ndev);
1962 if (ring->tx_pending > TX_RING_MAX ||
1963 ring->rx_pending > RX_RING_MAX ||
1964 ring->tx_pending < TX_RING_MIN ||
1965 ring->rx_pending < RX_RING_MIN)
1967 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1970 if (netif_running(ndev)) {
1971 netif_tx_disable(ndev);
1972 /* Disable interrupts by clearing the interrupt mask. */
1973 sh_eth_write(ndev, 0x0000, EESIPR);
1974 /* Stop the chip's Tx and Rx processes. */
1975 sh_eth_write(ndev, 0, EDTRR);
1976 sh_eth_write(ndev, 0, EDRRR);
1977 synchronize_irq(ndev->irq);
1980 /* Free all the skbuffs in the Rx queue. */
1981 sh_eth_ring_free(ndev);
1982 /* Free DMA buffer */
1983 sh_eth_free_dma_buffer(mdp);
1985 /* Set new parameters */
1986 mdp->num_rx_ring = ring->rx_pending;
1987 mdp->num_tx_ring = ring->tx_pending;
1989 ret = sh_eth_ring_init(ndev);
1991 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n", __func__);
1994 ret = sh_eth_dev_init(ndev, false);
1996 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n", __func__);
2000 if (netif_running(ndev)) {
2001 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
2002 /* Setting the Rx mode will start the Rx process. */
2003 sh_eth_write(ndev, EDRRR_R, EDRRR);
2004 netif_wake_queue(ndev);
2010 static const struct ethtool_ops sh_eth_ethtool_ops = {
2011 .get_settings = sh_eth_get_settings,
2012 .set_settings = sh_eth_set_settings,
2013 .nway_reset = sh_eth_nway_reset,
2014 .get_msglevel = sh_eth_get_msglevel,
2015 .set_msglevel = sh_eth_set_msglevel,
2016 .get_link = ethtool_op_get_link,
2017 .get_strings = sh_eth_get_strings,
2018 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2019 .get_sset_count = sh_eth_get_sset_count,
2020 .get_ringparam = sh_eth_get_ringparam,
2021 .set_ringparam = sh_eth_set_ringparam,
2024 /* network device open function */
2025 static int sh_eth_open(struct net_device *ndev)
2028 struct sh_eth_private *mdp = netdev_priv(ndev);
2030 pm_runtime_get_sync(&mdp->pdev->dev);
2032 napi_enable(&mdp->napi);
2034 ret = request_irq(ndev->irq, sh_eth_interrupt,
2035 mdp->cd->irq_flags, ndev->name, ndev);
2037 netdev_err(ndev, "Can not assign IRQ number\n");
2041 /* Descriptor set */
2042 ret = sh_eth_ring_init(ndev);
2047 ret = sh_eth_dev_init(ndev, true);
2051 /* PHY control start*/
2052 ret = sh_eth_phy_start(ndev);
2061 free_irq(ndev->irq, ndev);
2063 napi_disable(&mdp->napi);
2064 pm_runtime_put_sync(&mdp->pdev->dev);
2068 /* Timeout function */
2069 static void sh_eth_tx_timeout(struct net_device *ndev)
2071 struct sh_eth_private *mdp = netdev_priv(ndev);
2072 struct sh_eth_rxdesc *rxdesc;
2075 netif_stop_queue(ndev);
2077 netif_err(mdp, timer, ndev,
2078 "transmit timed out, status %8.8x, resetting...\n",
2079 (int)sh_eth_read(ndev, EESR));
2081 /* tx_errors count up */
2082 ndev->stats.tx_errors++;
2084 /* Free all the skbuffs in the Rx queue. */
2085 for (i = 0; i < mdp->num_rx_ring; i++) {
2086 rxdesc = &mdp->rx_ring[i];
2088 rxdesc->addr = 0xBADF00D0;
2089 dev_kfree_skb(mdp->rx_skbuff[i]);
2090 mdp->rx_skbuff[i] = NULL;
2092 for (i = 0; i < mdp->num_tx_ring; i++) {
2093 dev_kfree_skb(mdp->tx_skbuff[i]);
2094 mdp->tx_skbuff[i] = NULL;
2098 sh_eth_dev_init(ndev, true);
2101 /* Packet transmit function */
2102 static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2104 struct sh_eth_private *mdp = netdev_priv(ndev);
2105 struct sh_eth_txdesc *txdesc;
2107 unsigned long flags;
2109 spin_lock_irqsave(&mdp->lock, flags);
2110 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2111 if (!sh_eth_txfree(ndev)) {
2112 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2113 netif_stop_queue(ndev);
2114 spin_unlock_irqrestore(&mdp->lock, flags);
2115 return NETDEV_TX_BUSY;
2118 spin_unlock_irqrestore(&mdp->lock, flags);
2120 entry = mdp->cur_tx % mdp->num_tx_ring;
2121 mdp->tx_skbuff[entry] = skb;
2122 txdesc = &mdp->tx_ring[entry];
2124 if (!mdp->cd->hw_swap)
2125 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
2127 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len,
2129 if (skb->len < ETH_ZLEN)
2130 txdesc->buffer_length = ETH_ZLEN;
2132 txdesc->buffer_length = skb->len;
2134 if (entry >= mdp->num_tx_ring - 1)
2135 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
2137 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
2141 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
2142 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
2144 return NETDEV_TX_OK;
2147 static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2149 struct sh_eth_private *mdp = netdev_priv(ndev);
2151 if (sh_eth_is_rz_fast_ether(mdp))
2152 return &ndev->stats;
2154 if (!mdp->is_opened)
2155 return &ndev->stats;
2157 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR);
2158 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
2159 ndev->stats.collisions += sh_eth_read(ndev, CDCR);
2160 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
2161 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
2162 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
2164 if (sh_eth_is_gether(mdp)) {
2165 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
2166 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
2167 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
2168 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
2170 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
2171 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
2174 return &ndev->stats;
2177 /* device close function */
2178 static int sh_eth_close(struct net_device *ndev)
2180 struct sh_eth_private *mdp = netdev_priv(ndev);
2182 netif_stop_queue(ndev);
2184 /* Disable interrupts by clearing the interrupt mask. */
2185 sh_eth_write(ndev, 0x0000, EESIPR);
2187 /* Stop the chip's Tx and Rx processes. */
2188 sh_eth_write(ndev, 0, EDTRR);
2189 sh_eth_write(ndev, 0, EDRRR);
2191 sh_eth_get_stats(ndev);
2192 /* PHY Disconnect */
2194 phy_stop(mdp->phydev);
2195 phy_disconnect(mdp->phydev);
2199 free_irq(ndev->irq, ndev);
2201 napi_disable(&mdp->napi);
2203 /* Free all the skbuffs in the Rx queue. */
2204 sh_eth_ring_free(ndev);
2206 /* free DMA buffer */
2207 sh_eth_free_dma_buffer(mdp);
2209 pm_runtime_put_sync(&mdp->pdev->dev);
2216 /* ioctl to device function */
2217 static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2219 struct sh_eth_private *mdp = netdev_priv(ndev);
2220 struct phy_device *phydev = mdp->phydev;
2222 if (!netif_running(ndev))
2228 return phy_mii_ioctl(phydev, rq, cmd);
2231 /* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2232 static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2235 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2238 static u32 sh_eth_tsu_get_post_mask(int entry)
2240 return 0x0f << (28 - ((entry % 8) * 4));
2243 static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2245 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2248 static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2251 struct sh_eth_private *mdp = netdev_priv(ndev);
2255 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2256 tmp = ioread32(reg_offset);
2257 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2260 static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2263 struct sh_eth_private *mdp = netdev_priv(ndev);
2264 u32 post_mask, ref_mask, tmp;
2267 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2268 post_mask = sh_eth_tsu_get_post_mask(entry);
2269 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2271 tmp = ioread32(reg_offset);
2272 iowrite32(tmp & ~post_mask, reg_offset);
2274 /* If other port enables, the function returns "true" */
2275 return tmp & ref_mask;
2278 static int sh_eth_tsu_busy(struct net_device *ndev)
2280 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2281 struct sh_eth_private *mdp = netdev_priv(ndev);
2283 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2287 netdev_err(ndev, "%s: timeout\n", __func__);
2295 static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2300 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2301 iowrite32(val, reg);
2302 if (sh_eth_tsu_busy(ndev) < 0)
2305 val = addr[4] << 8 | addr[5];
2306 iowrite32(val, reg + 4);
2307 if (sh_eth_tsu_busy(ndev) < 0)
2313 static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2317 val = ioread32(reg);
2318 addr[0] = (val >> 24) & 0xff;
2319 addr[1] = (val >> 16) & 0xff;
2320 addr[2] = (val >> 8) & 0xff;
2321 addr[3] = val & 0xff;
2322 val = ioread32(reg + 4);
2323 addr[4] = (val >> 8) & 0xff;
2324 addr[5] = val & 0xff;
2328 static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2330 struct sh_eth_private *mdp = netdev_priv(ndev);
2331 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2333 u8 c_addr[ETH_ALEN];
2335 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2336 sh_eth_tsu_read_entry(reg_offset, c_addr);
2337 if (ether_addr_equal(addr, c_addr))
2344 static int sh_eth_tsu_find_empty(struct net_device *ndev)
2349 memset(blank, 0, sizeof(blank));
2350 entry = sh_eth_tsu_find_entry(ndev, blank);
2351 return (entry < 0) ? -ENOMEM : entry;
2354 static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2357 struct sh_eth_private *mdp = netdev_priv(ndev);
2358 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2362 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2363 ~(1 << (31 - entry)), TSU_TEN);
2365 memset(blank, 0, sizeof(blank));
2366 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2372 static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2374 struct sh_eth_private *mdp = netdev_priv(ndev);
2375 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2381 i = sh_eth_tsu_find_entry(ndev, addr);
2383 /* No entry found, create one */
2384 i = sh_eth_tsu_find_empty(ndev);
2387 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2391 /* Enable the entry */
2392 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2393 (1 << (31 - i)), TSU_TEN);
2396 /* Entry found or created, enable POST */
2397 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2402 static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2404 struct sh_eth_private *mdp = netdev_priv(ndev);
2410 i = sh_eth_tsu_find_entry(ndev, addr);
2413 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2416 /* Disable the entry if both ports was disabled */
2417 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2425 static int sh_eth_tsu_purge_all(struct net_device *ndev)
2427 struct sh_eth_private *mdp = netdev_priv(ndev);
2433 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2434 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2437 /* Disable the entry if both ports was disabled */
2438 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2446 static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2448 struct sh_eth_private *mdp = netdev_priv(ndev);
2450 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2456 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2457 sh_eth_tsu_read_entry(reg_offset, addr);
2458 if (is_multicast_ether_addr(addr))
2459 sh_eth_tsu_del_entry(ndev, addr);
2463 /* Update promiscuous flag and multicast filter */
2464 static void sh_eth_set_rx_mode(struct net_device *ndev)
2466 struct sh_eth_private *mdp = netdev_priv(ndev);
2469 unsigned long flags;
2471 spin_lock_irqsave(&mdp->lock, flags);
2472 /* Initial condition is MCT = 1, PRM = 0.
2473 * Depending on ndev->flags, set PRM or clear MCT
2475 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2477 ecmr_bits |= ECMR_MCT;
2479 if (!(ndev->flags & IFF_MULTICAST)) {
2480 sh_eth_tsu_purge_mcast(ndev);
2483 if (ndev->flags & IFF_ALLMULTI) {
2484 sh_eth_tsu_purge_mcast(ndev);
2485 ecmr_bits &= ~ECMR_MCT;
2489 if (ndev->flags & IFF_PROMISC) {
2490 sh_eth_tsu_purge_all(ndev);
2491 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2492 } else if (mdp->cd->tsu) {
2493 struct netdev_hw_addr *ha;
2494 netdev_for_each_mc_addr(ha, ndev) {
2495 if (mcast_all && is_multicast_ether_addr(ha->addr))
2498 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2500 sh_eth_tsu_purge_mcast(ndev);
2501 ecmr_bits &= ~ECMR_MCT;
2508 /* update the ethernet mode */
2509 sh_eth_write(ndev, ecmr_bits, ECMR);
2511 spin_unlock_irqrestore(&mdp->lock, flags);
2514 static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2522 static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2523 __be16 proto, u16 vid)
2525 struct sh_eth_private *mdp = netdev_priv(ndev);
2526 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2528 if (unlikely(!mdp->cd->tsu))
2531 /* No filtering if vid = 0 */
2535 mdp->vlan_num_ids++;
2537 /* The controller has one VLAN tag HW filter. So, if the filter is
2538 * already enabled, the driver disables it and the filte
2540 if (mdp->vlan_num_ids > 1) {
2541 /* disable VLAN filter */
2542 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2546 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2552 static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2553 __be16 proto, u16 vid)
2555 struct sh_eth_private *mdp = netdev_priv(ndev);
2556 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2558 if (unlikely(!mdp->cd->tsu))
2561 /* No filtering if vid = 0 */
2565 mdp->vlan_num_ids--;
2566 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2571 /* SuperH's TSU register init function */
2572 static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2574 if (sh_eth_is_rz_fast_ether(mdp)) {
2575 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2579 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2580 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2581 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2582 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2583 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2584 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2585 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2586 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2587 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2588 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2589 if (sh_eth_is_gether(mdp)) {
2590 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
2591 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
2593 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2594 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2596 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2597 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2598 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2599 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2600 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2601 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2602 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2605 /* MDIO bus release function */
2606 static int sh_mdio_release(struct sh_eth_private *mdp)
2608 /* unregister mdio bus */
2609 mdiobus_unregister(mdp->mii_bus);
2611 /* free bitbang info */
2612 free_mdio_bitbang(mdp->mii_bus);
2617 /* MDIO bus init function */
2618 static int sh_mdio_init(struct sh_eth_private *mdp,
2619 struct sh_eth_plat_data *pd)
2622 struct bb_info *bitbang;
2623 struct platform_device *pdev = mdp->pdev;
2624 struct device *dev = &mdp->pdev->dev;
2626 /* create bit control struct for PHY */
2627 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
2632 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
2633 bitbang->set_gate = pd->set_mdio_gate;
2634 bitbang->mdi_msk = PIR_MDI;
2635 bitbang->mdo_msk = PIR_MDO;
2636 bitbang->mmd_msk = PIR_MMD;
2637 bitbang->mdc_msk = PIR_MDC;
2638 bitbang->ctrl.ops = &bb_ops;
2640 /* MII controller setting */
2641 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
2645 /* Hook up MII support for ethtool */
2646 mdp->mii_bus->name = "sh_mii";
2647 mdp->mii_bus->parent = dev;
2648 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
2649 pdev->name, pdev->id);
2652 mdp->mii_bus->irq = devm_kmalloc_array(dev, PHY_MAX_ADDR, sizeof(int),
2654 if (!mdp->mii_bus->irq) {
2659 /* register MDIO bus */
2661 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
2663 for (i = 0; i < PHY_MAX_ADDR; i++)
2664 mdp->mii_bus->irq[i] = PHY_POLL;
2665 if (pd->phy_irq > 0)
2666 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
2668 ret = mdiobus_register(mdp->mii_bus);
2677 free_mdio_bitbang(mdp->mii_bus);
2681 static const u16 *sh_eth_get_register_offset(int register_type)
2683 const u16 *reg_offset = NULL;
2685 switch (register_type) {
2686 case SH_ETH_REG_GIGABIT:
2687 reg_offset = sh_eth_offset_gigabit;
2689 case SH_ETH_REG_FAST_RZ:
2690 reg_offset = sh_eth_offset_fast_rz;
2692 case SH_ETH_REG_FAST_RCAR:
2693 reg_offset = sh_eth_offset_fast_rcar;
2695 case SH_ETH_REG_FAST_SH4:
2696 reg_offset = sh_eth_offset_fast_sh4;
2698 case SH_ETH_REG_FAST_SH3_SH2:
2699 reg_offset = sh_eth_offset_fast_sh3_sh2;
2708 static const struct net_device_ops sh_eth_netdev_ops = {
2709 .ndo_open = sh_eth_open,
2710 .ndo_stop = sh_eth_close,
2711 .ndo_start_xmit = sh_eth_start_xmit,
2712 .ndo_get_stats = sh_eth_get_stats,
2713 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2714 .ndo_tx_timeout = sh_eth_tx_timeout,
2715 .ndo_do_ioctl = sh_eth_do_ioctl,
2716 .ndo_validate_addr = eth_validate_addr,
2717 .ndo_set_mac_address = eth_mac_addr,
2718 .ndo_change_mtu = eth_change_mtu,
2721 static const struct net_device_ops sh_eth_netdev_ops_tsu = {
2722 .ndo_open = sh_eth_open,
2723 .ndo_stop = sh_eth_close,
2724 .ndo_start_xmit = sh_eth_start_xmit,
2725 .ndo_get_stats = sh_eth_get_stats,
2726 .ndo_set_rx_mode = sh_eth_set_rx_mode,
2727 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
2728 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
2729 .ndo_tx_timeout = sh_eth_tx_timeout,
2730 .ndo_do_ioctl = sh_eth_do_ioctl,
2731 .ndo_validate_addr = eth_validate_addr,
2732 .ndo_set_mac_address = eth_mac_addr,
2733 .ndo_change_mtu = eth_change_mtu,
2737 static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2739 struct device_node *np = dev->of_node;
2740 struct sh_eth_plat_data *pdata;
2741 const char *mac_addr;
2743 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2747 pdata->phy_interface = of_get_phy_mode(np);
2749 mac_addr = of_get_mac_address(np);
2751 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
2753 pdata->no_ether_link =
2754 of_property_read_bool(np, "renesas,no-ether-link");
2755 pdata->ether_link_active_low =
2756 of_property_read_bool(np, "renesas,ether-link-active-low");
2761 static const struct of_device_id sh_eth_match_table[] = {
2762 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
2763 { .compatible = "renesas,ether-r8a7778", .data = &r8a777x_data },
2764 { .compatible = "renesas,ether-r8a7779", .data = &r8a777x_data },
2765 { .compatible = "renesas,ether-r8a7790", .data = &r8a779x_data },
2766 { .compatible = "renesas,ether-r8a7791", .data = &r8a779x_data },
2767 { .compatible = "renesas,ether-r8a7793", .data = &r8a779x_data },
2768 { .compatible = "renesas,ether-r8a7794", .data = &r8a779x_data },
2769 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
2772 MODULE_DEVICE_TABLE(of, sh_eth_match_table);
2774 static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
2780 static int sh_eth_drv_probe(struct platform_device *pdev)
2783 struct resource *res;
2784 struct net_device *ndev = NULL;
2785 struct sh_eth_private *mdp = NULL;
2786 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
2787 const struct platform_device_id *id = platform_get_device_id(pdev);
2790 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2792 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
2796 pm_runtime_enable(&pdev->dev);
2797 pm_runtime_get_sync(&pdev->dev);
2804 ret = platform_get_irq(pdev, 0);
2811 SET_NETDEV_DEV(ndev, &pdev->dev);
2813 mdp = netdev_priv(ndev);
2814 mdp->num_tx_ring = TX_RING_SIZE;
2815 mdp->num_rx_ring = RX_RING_SIZE;
2816 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
2817 if (IS_ERR(mdp->addr)) {
2818 ret = PTR_ERR(mdp->addr);
2822 ndev->base_addr = res->start;
2824 spin_lock_init(&mdp->lock);
2827 if (pdev->dev.of_node)
2828 pd = sh_eth_parse_dt(&pdev->dev);
2830 dev_err(&pdev->dev, "no platform data\n");
2836 mdp->phy_id = pd->phy;
2837 mdp->phy_interface = pd->phy_interface;
2839 mdp->edmac_endian = pd->edmac_endian;
2840 mdp->no_ether_link = pd->no_ether_link;
2841 mdp->ether_link_active_low = pd->ether_link_active_low;
2845 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
2847 const struct of_device_id *match;
2849 match = of_match_device(of_match_ptr(sh_eth_match_table),
2851 mdp->cd = (struct sh_eth_cpu_data *)match->data;
2853 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
2854 if (!mdp->reg_offset) {
2855 dev_err(&pdev->dev, "Unknown register type (%d)\n",
2856 mdp->cd->register_type);
2860 sh_eth_set_default_cpu_data(mdp->cd);
2864 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
2866 ndev->netdev_ops = &sh_eth_netdev_ops;
2867 ndev->ethtool_ops = &sh_eth_ethtool_ops;
2868 ndev->watchdog_timeo = TX_TIMEOUT;
2870 /* debug message level */
2871 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
2873 /* read and set MAC address */
2874 read_mac_address(ndev, pd->mac_addr);
2875 if (!is_valid_ether_addr(ndev->dev_addr)) {
2876 dev_warn(&pdev->dev,
2877 "no valid MAC address supplied, using a random one.\n");
2878 eth_hw_addr_random(ndev);
2881 /* ioremap the TSU registers */
2883 struct resource *rtsu;
2884 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2885 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu);
2886 if (IS_ERR(mdp->tsu_addr)) {
2887 ret = PTR_ERR(mdp->tsu_addr);
2890 mdp->port = devno % 2;
2891 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
2894 /* initialize first or needed device */
2895 if (!devno || pd->needs_init) {
2896 if (mdp->cd->chip_reset)
2897 mdp->cd->chip_reset(ndev);
2900 /* TSU init (Init only)*/
2901 sh_eth_tsu_init(mdp);
2905 if (mdp->cd->rmiimode)
2906 sh_eth_write(ndev, 0x1, RMIIMODE);
2909 ret = sh_mdio_init(mdp, pd);
2911 dev_err(&ndev->dev, "failed to initialise MDIO\n");
2915 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
2917 /* network device register */
2918 ret = register_netdev(ndev);
2922 /* print device information */
2923 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
2924 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2926 pm_runtime_put(&pdev->dev);
2927 platform_set_drvdata(pdev, ndev);
2932 netif_napi_del(&mdp->napi);
2933 sh_mdio_release(mdp);
2940 pm_runtime_put(&pdev->dev);
2941 pm_runtime_disable(&pdev->dev);
2945 static int sh_eth_drv_remove(struct platform_device *pdev)
2947 struct net_device *ndev = platform_get_drvdata(pdev);
2948 struct sh_eth_private *mdp = netdev_priv(ndev);
2950 unregister_netdev(ndev);
2951 netif_napi_del(&mdp->napi);
2952 sh_mdio_release(mdp);
2953 pm_runtime_disable(&pdev->dev);
2960 static int sh_eth_runtime_nop(struct device *dev)
2962 /* Runtime PM callback shared between ->runtime_suspend()
2963 * and ->runtime_resume(). Simply returns success.
2965 * This driver re-initializes all registers after
2966 * pm_runtime_get_sync() anyway so there is no need
2967 * to save and restore registers here.
2972 static const struct dev_pm_ops sh_eth_dev_pm_ops = {
2973 .runtime_suspend = sh_eth_runtime_nop,
2974 .runtime_resume = sh_eth_runtime_nop,
2976 #define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
2978 #define SH_ETH_PM_OPS NULL
2981 static struct platform_device_id sh_eth_id_table[] = {
2982 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
2983 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
2984 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
2985 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
2986 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
2987 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
2988 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
2989 { "r7s72100-ether", (kernel_ulong_t)&r7s72100_data },
2990 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data },
2991 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data },
2992 { "r8a7790-ether", (kernel_ulong_t)&r8a779x_data },
2993 { "r8a7791-ether", (kernel_ulong_t)&r8a779x_data },
2994 { "r8a7793-ether", (kernel_ulong_t)&r8a779x_data },
2995 { "r8a7794-ether", (kernel_ulong_t)&r8a779x_data },
2998 MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3000 static struct platform_driver sh_eth_driver = {
3001 .probe = sh_eth_drv_probe,
3002 .remove = sh_eth_drv_remove,
3003 .id_table = sh_eth_id_table,
3006 .pm = SH_ETH_PM_OPS,
3007 .of_match_table = of_match_ptr(sh_eth_match_table),
3011 module_platform_driver(sh_eth_driver);
3013 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3014 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3015 MODULE_LICENSE("GPL v2");